sim/v850/interp.c

   1 #include "sim-main.h"
   2 #include "sim-options.h"
   3 #include "v850_sim.h"
   4 #include "sim-assert.h"
   5 #include "itable.h"
   6
   7 #include <stdlib.h>
   8 #include <string.h>
   9
  10 #include "bfd.h"
  11
  12 static const char * get_insn_name (sim_cpu *, int);
  13
  14 /* For compatibility.  */
  15 SIM_DESC simulator;
  16
  17 /* V850 interrupt model.  */
  18
  19 enum interrupt_type
  20 {
  21   int_reset,
  22   int_nmi,
  23   int_intov1,
  24   int_intp10,
  25   int_intp11,
  26   int_intp12,
  27   int_intp13,
  28   int_intcm4,
  29   num_int_types
  30 };
  31
  32 const char *interrupt_names[] =
  33 {
  34   "reset",
  35   "nmi",
  36   "intov1",
  37   "intp10",
  38   "intp11",
  39   "intp12",
  40   "intp13",
  41   "intcm4",
  42   NULL
  43 };
  44
  45 static void
  46 do_interrupt (SIM_DESC sd, void *data)
  47 {
  48   const char **interrupt_name = (const char**)data;
  49   enum interrupt_type inttype;
  50   inttype = (interrupt_name - STATE_WATCHPOINTS (sd)->interrupt_names);
  51
  52   /* For a hardware reset, drop everything and jump to the start
  53      address */
  54   if (inttype == int_reset)
  55     {
  56       PC = 0;
  57       PSW = 0x20;
  58       ECR = 0;
  59       sim_engine_restart (sd, NULL, NULL, NULL_CIA);
  60     }
  61
  62   /* Deliver an NMI when allowed */
  63   if (inttype == int_nmi)
  64     {
  65       if (PSW & PSW_NP)
  66         {
  67           /* We're already working on an NMI, so this one must wait
  68              around until the previous one is done.  The processor
  69              ignores subsequent NMIs, so we don't need to count them.
  70              Just keep re-scheduling a single NMI until it manages to
  71              be delivered */
  72           if (STATE_CPU (sd, 0)->pending_nmi != NULL)
  73             sim_events_deschedule (sd, STATE_CPU (sd, 0)->pending_nmi);
  74           STATE_CPU (sd, 0)->pending_nmi =
  75             sim_events_schedule (sd, 1, do_interrupt, data);
  76           return;
  77         }
  78       else
  79         {
  80           /* NMI can be delivered.  Do not deschedule pending_nmi as
  81              that, if still in the event queue, is a second NMI that
  82              needs to be delivered later. */
  83           FEPC = PC;
  84           FEPSW = PSW;
  85           /* Set the FECC part of the ECR. */
  86           ECR &= 0x0000ffff;
  87           ECR |= 0x10;
  88           PSW |= PSW_NP;
  89           PSW &= ~PSW_EP;
  90           PSW |= PSW_ID;
  91           PC = 0x10;
  92           sim_engine_restart (sd, NULL, NULL, NULL_CIA);
  93         }
  94     }
  95
  96   /* deliver maskable interrupt when allowed */
  97   if (inttype > int_nmi && inttype < num_int_types)
  98     {
  99       if ((PSW & PSW_NP) || (PSW & PSW_ID))
 100         {
 101           /* Can't deliver this interrupt, reschedule it for later */
 102           sim_events_schedule (sd, 1, do_interrupt, data);
 103           return;
 104         }
 105       else
 106         {
 107           /* save context */
 108           EIPC = PC;
 109           EIPSW = PSW;
 110           /* Disable further interrupts.  */
 111           PSW |= PSW_ID;
 112           /* Indicate that we're doing interrupt not exception processing.  */
 113           PSW &= ~PSW_EP;
 114           /* Clear the EICC part of the ECR, will set below. */
 115           ECR &= 0xffff0000;
 116           switch (inttype)
 117             {
 118             case int_intov1:
 119               PC = 0x80;
 120               ECR |= 0x80;
 121               break;
 122             case int_intp10:
 123               PC = 0x90;
 124               ECR |= 0x90;
 125               break;
 126             case int_intp11:
 127               PC = 0xa0;
 128               ECR |= 0xa0;
 129               break;
 130             case int_intp12:
 131               PC = 0xb0;
 132               ECR |= 0xb0;
 133               break;
 134             case int_intp13:
 135               PC = 0xc0;
 136               ECR |= 0xc0;
 137               break;
 138             case int_intcm4:
 139               PC = 0xd0;
 140               ECR |= 0xd0;
 141               break;
 142             default:
 143               /* Should never be possible.  */
 144               sim_engine_abort (sd, NULL, NULL_CIA,
 145                                 "do_interrupt - internal error - bad switch");
 146               break;
 147             }
 148         }
 149       sim_engine_restart (sd, NULL, NULL, NULL_CIA);
 150     }
 151
 152   /* some other interrupt? */
 153   sim_engine_abort (sd, NULL, NULL_CIA,
 154                     "do_interrupt - internal error - interrupt %d unknown",
 155                     inttype);
 156 }
 157
 158 /* Return name of an insn, used by insn profiling.  */
 159
 160 static const char *
 161 get_insn_name (sim_cpu *cpu, int i)
 162 {
 163   return itable[i].name;
 164 }
 165
 166 /* These default values correspond to expected usage for the chip.  */
 167
 168 uint32 OP[4];
 169
 170 static sim_cia
 171 v850_pc_get (sim_cpu *cpu)
 172 {
 173   return PC;
 174 }
 175
 176 static void
 177 v850_pc_set (sim_cpu *cpu, sim_cia pc)
 178 {
 179   PC = pc;
 180 }
 181
 182 static int v850_reg_fetch (SIM_CPU *, int, unsigned char *, int);
 183 static int v850_reg_store (SIM_CPU *, int, unsigned char *, int);
 184
 185 SIM_DESC
 186 sim_open (SIM_OPEN_KIND    kind,
 187           host_callback *  cb,
 188           struct bfd *     abfd,
 189           char * const *   argv)
 190 {
 191   int i;
 192   SIM_DESC sd = sim_state_alloc (kind, cb);
 193   int mach;
 194
 195   SIM_ASSERT (STATE_MAGIC (sd) == SIM_MAGIC_NUMBER);
 196
 197   /* The cpu data is kept in a separately allocated chunk of memory.  */
 198   if (sim_cpu_alloc_all (sd, 1, /*cgen_cpu_max_extra_bytes ()*/0) != SIM_RC_OK)
 199     return 0;
 200
 201   /* for compatibility */
 202   simulator = sd;
 203
 204   /* FIXME: should be better way of setting up interrupts */
 205   STATE_WATCHPOINTS (sd)->interrupt_handler = do_interrupt;
 206   STATE_WATCHPOINTS (sd)->interrupt_names = interrupt_names;
 207
 208   /* Initialize the mechanism for doing insn profiling.  */
 209   CPU_INSN_NAME (STATE_CPU (sd, 0)) = get_insn_name;
 210   CPU_MAX_INSNS (STATE_CPU (sd, 0)) = nr_itable_entries;
 211
 212   if (sim_pre_argv_init (sd, argv[0]) != SIM_RC_OK)
 213     return 0;
 214
 215   /* Allocate core managed memory */
 216
 217   /* "Mirror" the ROM addresses below 1MB. */
 218   sim_do_commandf (sd, "memory region 0,0x100000,0x%lx", V850_ROM_SIZE);
 219   /* Chunk of ram adjacent to rom */
 220   sim_do_commandf (sd, "memory region 0x100000,0x%lx", V850_LOW_END-0x100000);
 221   /* peripheral I/O region - mirror 1K across 4k (0x1000) */
 222   sim_do_command (sd, "memory region 0xfff000,0x1000,1024");
 223   /* similarly if in the internal RAM region */
 224   sim_do_command (sd, "memory region 0xffe000,0x1000,1024");
 225
 226   /* The parser will print an error message for us, so we silently return.  */
 227   if (sim_parse_args (sd, argv) != SIM_RC_OK)
 228     {
 229       /* Uninstall the modules to avoid memory leaks,
 230          file descriptor leaks, etc.  */
 231       sim_module_uninstall (sd);
 232       return 0;
 233     }
 234
 235   /* check for/establish the a reference program image */
 236   if (sim_analyze_program (sd,
 237                            (STATE_PROG_ARGV (sd) != NULL
 238                             ? *STATE_PROG_ARGV (sd)
 239                             : NULL),
 240                            abfd) != SIM_RC_OK)
 241     {
 242       sim_module_uninstall (sd);
 243       return 0;
 244     }
 245
 246   /* establish any remaining configuration options */
 247   if (sim_config (sd) != SIM_RC_OK)
 248     {
 249       sim_module_uninstall (sd);
 250       return 0;
 251     }
 252
 253   if (sim_post_argv_init (sd) != SIM_RC_OK)
 254     {
 255       /* Uninstall the modules to avoid memory leaks,
 256          file descriptor leaks, etc.  */
 257       sim_module_uninstall (sd);
 258       return 0;
 259     }
 260
 261
 262   /* determine the machine type */
 263   if (STATE_ARCHITECTURE (sd) != NULL
 264       && (STATE_ARCHITECTURE (sd)->arch == bfd_arch_v850
 265           || STATE_ARCHITECTURE (sd)->arch == bfd_arch_v850_rh850))
 266     mach = STATE_ARCHITECTURE (sd)->mach;
 267   else
 268     mach = bfd_mach_v850; /* default */
 269
 270   /* set machine specific configuration */
 271   switch (mach)
 272     {
 273     case bfd_mach_v850:
 274     case bfd_mach_v850e:
 275     case bfd_mach_v850e1:
 276     case bfd_mach_v850e2:
 277     case bfd_mach_v850e2v3:
 278     case bfd_mach_v850e3v5:
 279       STATE_CPU (sd, 0)->psw_mask = (PSW_NP | PSW_EP | PSW_ID | PSW_SAT
 280                                      | PSW_CY | PSW_OV | PSW_S | PSW_Z);
 281       break;
 282     }
 283
 284   /* CPU specific initialization.  */
 285   for (i = 0; i < MAX_NR_PROCESSORS; ++i)
 286     {
 287       SIM_CPU *cpu = STATE_CPU (sd, i);
 288
 289       CPU_REG_FETCH (cpu) = v850_reg_fetch;
 290       CPU_REG_STORE (cpu) = v850_reg_store;
 291       CPU_PC_FETCH (cpu) = v850_pc_get;
 292       CPU_PC_STORE (cpu) = v850_pc_set;
 293     }
 294
 295   return sd;
 296 }
 297
 298 SIM_RC
 299 sim_create_inferior (SIM_DESC      sd,
 300                      struct bfd *  prog_bfd,
 301                      char * const *argv,
 302                      char * const *env)
 303 {
 304   memset (&State, 0, sizeof (State));
 305   if (prog_bfd != NULL)
 306     PC = bfd_get_start_address (prog_bfd);
 307   return SIM_RC_OK;
 308 }
 309
 310 static int
 311 v850_reg_fetch (SIM_CPU *cpu, int rn, unsigned char *memory, int length)
 312 {
 313   *(unsigned32*)memory = H2T_4 (State.regs[rn]);
 314   return -1;
 315 }
 316
 317 static int
 318 v850_reg_store (SIM_CPU *cpu, int rn, unsigned char *memory, int length)
 319 {
 320   State.regs[rn] = T2H_4 (*(unsigned32 *) memory);
 321   return length;
 322 }