sim/v850/sim-main.h

   1 #ifndef SIM_MAIN_H
   2 #define SIM_MAIN_H
   3
   4 /* The v850 has 32bit words, numbered 31 (MSB) to 0 (LSB) */
   5
   6 #define WITH_TARGET_WORD_MSB 31
   7
   8 #include "sim-basics.h"
   9 #include "sim-signal.h"
  10 #include "sim-fpu.h"
  11 #include "sim-base.h"
  12
  13 #include "simops.h"
  14
  15 typedef uint32_t reg_t;
  16 typedef uint64_t reg64_t;
  17
  18
  19 /* The current state of the processor; registers, memory, etc.  */
  20
  21 typedef struct _v850_regs {
  22   reg_t regs[32];               /* general-purpose registers */
  23   reg_t sregs[32];              /* system registers, including psw */
  24   reg_t pc;
  25   int dummy_mem;                /* where invalid accesses go */
  26   reg_t mpu0_sregs[28];         /* mpu0 system registers */
  27   reg_t mpu1_sregs[28];         /* mpu1 system registers */
  28   reg_t fpu_sregs[28];          /* fpu system registers */
  29   reg_t selID_sregs[7][32];     /* system registers, selID 1 thru selID 7 */
  30   reg64_t vregs[32];            /* vector registers.  */
  31 } v850_regs;
  32
  33 struct v850_sim_cpu {
  34   v850_regs reg;
  35   reg_t psw_mask;               /* only allow non-reserved bits to be set */
  36   sim_event *pending_nmi;
  37 };
  38
  39 #define V850_SIM_CPU(cpu) ((struct v850_sim_cpu *) CPU_ARCH_DATA (cpu))
  40
  41 /* For compatibility, until all functions converted to passing
  42    SIM_DESC as an argument */
  43 extern SIM_DESC simulator;
  44
  45
  46 #define V850_ROM_SIZE 0x8000
  47 #define V850_LOW_END 0x200000
  48 #define V850_HIGH_START 0xffe000
  49
  50
  51 /* Because we are still using the old semantic table, provide compat
  52    macro's that store the instruction where the old simops expects
  53    it. */
  54
  55 extern uint32_t OP[4];
  56 #if 0
  57 OP[0] = inst & 0x1f;           /* RRRRR -> reg1 */
  58 OP[1] = (inst >> 11) & 0x1f;   /* rrrrr -> reg2 */
  59 OP[2] = (inst >> 16) & 0xffff; /* wwwww -> reg3 OR imm16 */
  60 OP[3] = inst;
  61 #endif
  62
  63 #define SAVE_1 \
  64 PC = cia; \
  65 OP[0] = instruction_0 & 0x1f; \
  66 OP[1] = (instruction_0 >> 11) & 0x1f; \
  67 OP[2] = 0; \
  68 OP[3] = instruction_0
  69
  70 #define COMPAT_1(CALL) \
  71 SAVE_1; \
  72 PC += (CALL); \
  73 nia = PC
  74
  75 #define SAVE_2 \
  76 PC = cia; \
  77 OP[0] = instruction_0 & 0x1f; \
  78 OP[1] = (instruction_0 >> 11) & 0x1f; \
  79 OP[2] = instruction_1; \
  80 OP[3] = (instruction_1 << 16) | instruction_0
  81
  82 #define COMPAT_2(CALL) \
  83 SAVE_2; \
  84 PC += (CALL); \
  85 nia = PC
  86
  87
  88 /* new */
  89 #define GR  (V850_SIM_CPU (CPU)->reg.regs)
  90 #define SR  (V850_SIM_CPU (CPU)->reg.sregs)
  91 #define VR  (V850_SIM_CPU (CPU)->reg.vregs)
  92 #define MPU0_SR  (V850_SIM_CPU (STATE_CPU (sd, 0))->reg.mpu0_sregs)
  93 #define MPU1_SR  (V850_SIM_CPU (STATE_CPU (sd, 0))->reg.mpu1_sregs)
  94 #define FPU_SR   (V850_SIM_CPU (STATE_CPU (sd, 0))->reg.fpu_sregs)
  95
  96 /* old */
  97 #define State    (V850_SIM_CPU (STATE_CPU (simulator, 0))->reg)
  98 #define PC      (State.pc)
  99 #define SP_REGNO        3
 100 #define SP      (State.regs[SP_REGNO])
 101 #define EP      (State.regs[30])
 102
 103 #define EIPC  (State.sregs[0])
 104 #define EIPSW (State.sregs[1])
 105 #define FEPC  (State.sregs[2])
 106 #define FEPSW (State.sregs[3])
 107 #define ECR   (State.sregs[4])
 108 #define PSW   (State.sregs[5])
 109 #define PSW_REGNO   5
 110 #define EIIC  (State.sregs[13])
 111 #define FEIC  (State.sregs[14])
 112 #define DBIC  (SR[15])
 113 #define CTPC  (SR[16])
 114 #define CTPSW (SR[17])
 115 #define DBPC  (State.sregs[18])
 116 #define DBPSW (State.sregs[19])
 117 #define CTBP  (State.sregs[20])
 118 #define DIR   (SR[21])
 119 #define EIWR  (SR[28])
 120 #define FEWR  (SR[29])
 121 #define DBWR  (SR[30])
 122 #define BSEL  (SR[31])
 123
 124 #define PSW_US BIT32 (8)
 125 #define PSW_NP 0x80
 126 #define PSW_EP 0x40
 127 #define PSW_ID 0x20
 128 #define PSW_SAT 0x10
 129 #define PSW_CY 0x8
 130 #define PSW_OV 0x4
 131 #define PSW_S 0x2
 132 #define PSW_Z 0x1
 133
 134 #define PSW_NPV (1<<18)
 135 #define PSW_DMP (1<<17)
 136 #define PSW_IMP (1<<16)
 137
 138 #define ECR_EICC 0x0000ffff
 139 #define ECR_FECC 0xffff0000
 140
 141 /* FPU */
 142
 143 #define FPSR  (FPU_SR[6])
 144 #define FPSR_REGNO 6
 145 #define FPEPC (FPU_SR[7])
 146 #define FPST  (FPU_SR[8])
 147 #define FPST_REGNO 8
 148 #define FPCC  (FPU_SR[9])
 149 #define FPCFG (FPU_SR[10])
 150 #define FPCFG_REGNO 10
 151
 152 #define FPSR_DEM  0x00200000
 153 #define FPSR_SEM  0x00100000
 154 #define FPSR_RM   0x000c0000
 155 #define FPSR_RN   0x00000000
 156 #define FPSR_FS   0x00020000
 157 #define FPSR_PR   0x00010000
 158
 159 #define FPSR_XC   0x0000fc00
 160 #define FPSR_XCE  0x00008000
 161 #define FPSR_XCV  0x00004000
 162 #define FPSR_XCZ  0x00002000
 163 #define FPSR_XCO  0x00001000
 164 #define FPSR_XCU  0x00000800
 165 #define FPSR_XCI  0x00000400
 166
 167 #define FPSR_XE   0x000003e0
 168 #define FPSR_XEV  0x00000200
 169 #define FPSR_XEZ  0x00000100
 170 #define FPSR_XEO  0x00000080
 171 #define FPSR_XEU  0x00000040
 172 #define FPSR_XEI  0x00000020
 173
 174 #define FPSR_XP   0x0000001f
 175 #define FPSR_XPV  0x00000010
 176 #define FPSR_XPZ  0x00000008
 177 #define FPSR_XPO  0x00000004
 178 #define FPSR_XPU  0x00000002
 179 #define FPSR_XPI  0x00000001
 180
 181 #define FPST_PR   0x00008000
 182 #define FPST_XCE  0x00002000
 183 #define FPST_XCV  0x00001000
 184 #define FPST_XCZ  0x00000800
 185 #define FPST_XCO  0x00000400
 186 #define FPST_XCU  0x00000200
 187 #define FPST_XCI  0x00000100
 188
 189 #define FPST_XPV  0x00000010
 190 #define FPST_XPZ  0x00000008
 191 #define FPST_XPO  0x00000004
 192 #define FPST_XPU  0x00000002
 193 #define FPST_XPI  0x00000001
 194
 195 #define FPCFG_RM   0x00000180
 196 #define FPCFG_XEV  0x00000010
 197 #define FPCFG_XEZ  0x00000008
 198 #define FPCFG_XEO  0x00000004
 199 #define FPCFG_XEU  0x00000002
 200 #define FPCFG_XEI  0x00000001
 201
 202 #define GET_FPCC()\
 203  ((FPSR >> 24) &0xf)
 204
 205 #define CLEAR_FPCC(bbb)\
 206   (FPSR &= ~(1 << (bbb+24)))
 207
 208 #define SET_FPCC(bbb)\
 209  (FPSR |= 1 << (bbb+24))
 210
 211 #define TEST_FPCC(bbb)\
 212   ((FPSR & (1 << (bbb+24))) != 0)
 213
 214 #define FPSR_GET_ROUND()                                        \
 215   (((FPSR & FPSR_RM) == FPSR_RN) ? sim_fpu_round_near           \
 216    : ((FPSR & FPSR_RM) == 0x00040000) ? sim_fpu_round_up        \
 217    : ((FPSR & FPSR_RM) == 0x00080000) ? sim_fpu_round_down      \
 218    : sim_fpu_round_zero)
 219
 220
 221 enum FPU_COMPARE {
 222   FPU_CMP_F = 0,
 223   FPU_CMP_UN,
 224   FPU_CMP_EQ,
 225   FPU_CMP_UEQ,
 226   FPU_CMP_OLT,
 227   FPU_CMP_ULT,
 228   FPU_CMP_OLE,
 229   FPU_CMP_ULE,
 230   FPU_CMP_SF,
 231   FPU_CMP_NGLE,
 232   FPU_CMP_SEQ,
 233   FPU_CMP_NGL,
 234   FPU_CMP_LT,
 235   FPU_CMP_NGE,
 236   FPU_CMP_LE,
 237   FPU_CMP_NGT
 238 };
 239
 240
 241 /* MPU */
 242 #define MPM     (MPU1_SR[0])
 243 #define MPC     (MPU1_SR[1])
 244 #define MPC_REGNO 1
 245 #define TID     (MPU1_SR[2])
 246 #define PPA     (MPU1_SR[3])
 247 #define PPM     (MPU1_SR[4])
 248 #define PPC     (MPU1_SR[5])
 249 #define DCC     (MPU1_SR[6])
 250 #define DCV0    (MPU1_SR[7])
 251 #define DCV1    (MPU1_SR[8])
 252 #define SPAL    (MPU1_SR[10])
 253 #define SPAU    (MPU1_SR[11])
 254 #define IPA0L   (MPU1_SR[12])
 255 #define IPA0U   (MPU1_SR[13])
 256 #define IPA1L   (MPU1_SR[14])
 257 #define IPA1U   (MPU1_SR[15])
 258 #define IPA2L   (MPU1_SR[16])
 259 #define IPA2U   (MPU1_SR[17])
 260 #define IPA3L   (MPU1_SR[18])
 261 #define IPA3U   (MPU1_SR[19])
 262 #define DPA0L   (MPU1_SR[20])
 263 #define DPA0U   (MPU1_SR[21])
 264 #define DPA1L   (MPU1_SR[22])
 265 #define DPA1U   (MPU1_SR[23])
 266 #define DPA2L   (MPU1_SR[24])
 267 #define DPA2U   (MPU1_SR[25])
 268 #define DPA3L   (MPU1_SR[26])
 269 #define DPA3U   (MPU1_SR[27])
 270
 271 #define PPC_PPE 0x1
 272 #define SPAL_SPE 0x1
 273 #define SPAL_SPS 0x10
 274
 275 #define VIP     (MPU0_SR[0])
 276 #define VMECR   (MPU0_SR[4])
 277 #define VMTID   (MPU0_SR[5])
 278 #define VMADR   (MPU0_SR[6])
 279 #define VPECR   (MPU0_SR[8])
 280 #define VPTID   (MPU0_SR[9])
 281 #define VPADR   (MPU0_SR[10])
 282 #define VDECR   (MPU0_SR[12])
 283 #define VDTID   (MPU0_SR[13])
 284
 285 #define MPM_AUE 0x2
 286 #define MPM_MPE 0x1
 287
 288 #define VMECR_VMX   0x2
 289 #define VMECR_VMR   0x4
 290 #define VMECR_VMW   0x8
 291 #define VMECR_VMS   0x10
 292 #define VMECR_VMRMW 0x20
 293 #define VMECR_VMMS  0x40
 294
 295 #define IPA2ADDR(IPA)   ((IPA) & 0x1fffff80)
 296 #define IPA_IPE 0x1
 297 #define IPA_IPX 0x2
 298 #define IPA_IPR 0x4
 299 #define IPE0    (IPA0L & IPA_IPE)
 300 #define IPE1    (IPA1L & IPA_IPE)
 301 #define IPE2    (IPA2L & IPA_IPE)
 302 #define IPE3    (IPA3L & IPA_IPE)
 303 #define IPX0    (IPA0L & IPA_IPX)
 304 #define IPX1    (IPA1L & IPA_IPX)
 305 #define IPX2    (IPA2L & IPA_IPX)
 306 #define IPX3    (IPA3L & IPA_IPX)
 307 #define IPR0    (IPA0L & IPA_IPR)
 308 #define IPR1    (IPA1L & IPA_IPR)
 309 #define IPR2    (IPA2L & IPA_IPR)
 310 #define IPR3    (IPA3L & IPA_IPR)
 311
 312 #define DPA2ADDR(DPA)   ((DPA) & 0x1fffff80)
 313 #define DPA_DPE 0x1
 314 #define DPA_DPR 0x4
 315 #define DPA_DPW 0x8
 316 #define DPE0    (DPA0L & DPA_DPE)
 317 #define DPE1    (DPA1L & DPA_DPE)
 318 #define DPE2    (DPA2L & DPA_DPE)
 319 #define DPE3    (DPA3L & DPA_DPE)
 320 #define DPR0    (DPA0L & DPA_DPR)
 321 #define DPR1    (DPA1L & DPA_DPR)
 322 #define DPR2    (DPA2L & DPA_DPR)
 323 #define DPR3    (DPA3L & DPA_DPR)
 324 #define DPW0    (DPA0L & DPA_DPW)
 325 #define DPW1    (DPA1L & DPA_DPW)
 326 #define DPW2    (DPA2L & DPA_DPW)
 327 #define DPW3    (DPA3L & DPA_DPW)
 328
 329 #define DCC_DCE0 0x1
 330 #define DCC_DCE1 0x10000
 331
 332 #define PPA2ADDR(PPA)   ((PPA) & 0x1fffff80)
 333 #define PPC_PPC 0xfffffffe
 334 #define PPC_PPE 0x1
 335 #define PPC_PPM 0x0000fff8
 336
 337
 338 #define SEXT3(x)        ((((x)&0x7)^(~0x3))+0x4)
 339
 340 /* sign-extend a 4-bit number */
 341 #define SEXT4(x)        ((((x)&0xf)^(~0x7))+0x8)
 342
 343 /* sign-extend a 5-bit number */
 344 #define SEXT5(x)        ((((x)&0x1f)^(~0xf))+0x10)
 345
 346 /* sign-extend a 9-bit number */
 347 #define SEXT9(x)        ((((x)&0x1ff)^(~0xff))+0x100)
 348
 349 /* sign-extend a 22-bit number */
 350 #define SEXT22(x)       ((((x)&0x3fffff)^(~0x1fffff))+0x200000)
 351
 352 /* sign extend a 40 bit number */
 353 #define SEXT40(x)       ((((x) & UNSIGNED64 (0xffffffffff)) \
 354                           ^ (~UNSIGNED64 (0x7fffffffff))) \
 355                          + UNSIGNED64 (0x8000000000))
 356
 357 /* sign extend a 44 bit number */
 358 #define SEXT44(x)       ((((x) & UNSIGNED64 (0xfffffffffff)) \
 359                           ^ (~ UNSIGNED64 (0x7ffffffffff))) \
 360                          + UNSIGNED64 (0x80000000000))
 361
 362 /* sign extend a 60 bit number */
 363 #define SEXT60(x)       ((((x) & UNSIGNED64 (0xfffffffffffffff)) \
 364                           ^ (~ UNSIGNED64 (0x7ffffffffffffff))) \
 365                          + UNSIGNED64 (0x800000000000000))
 366
 367 /* No sign extension */
 368 #define NOP(x)          (x)
 369
 370 #define INC_ADDR(x,i)   x = ((State.MD && x == MOD_E) ? MOD_S : (x)+(i))
 371
 372 #define RLW(x) load_mem (x, 4)
 373
 374 /* Function declarations.  */
 375
 376 #define IMEM16(EA) \
 377 sim_core_read_aligned_2 (CPU, PC, exec_map, (EA))
 378
 379 #define IMEM16_IMMED(EA,N) \
 380 sim_core_read_aligned_2 (STATE_CPU (sd, 0), \
 381                          PC, exec_map, (EA) + (N) * 2)
 382
 383 #define load_mem(ADDR,LEN) \
 384 sim_core_read_unaligned_##LEN (STATE_CPU (simulator, 0), \
 385                                PC, read_map, (ADDR))
 386
 387 #define store_mem(ADDR,LEN,DATA) \
 388 sim_core_write_unaligned_##LEN (STATE_CPU (simulator, 0), \
 389                                 PC, write_map, (ADDR), (DATA))
 390
 391
 392 /* compare cccc field against PSW */
 393 int condition_met (unsigned code);
 394
 395
 396 /* Debug/tracing calls */
 397
 398 enum op_types
 399 {
 400   OP_UNKNOWN,
 401   OP_NONE,
 402   OP_TRAP,
 403   OP_REG,
 404   OP_REG_REG,
 405   OP_REG_REG_CMP,
 406   OP_REG_REG_MOVE,
 407   OP_IMM_REG,
 408   OP_IMM_REG_CMP,
 409   OP_IMM_REG_MOVE,
 410   OP_COND_BR,
 411   OP_LOAD16,
 412   OP_STORE16,
 413   OP_LOAD32,
 414   OP_STORE32,
 415   OP_JUMP,
 416   OP_IMM_REG_REG,
 417   OP_UIMM_REG_REG,
 418   OP_IMM16_REG_REG,
 419   OP_UIMM16_REG_REG,
 420   OP_BIT,
 421   OP_EX1,
 422   OP_EX2,
 423   OP_LDSR,
 424   OP_STSR,
 425   OP_BIT_CHANGE,
 426   OP_REG_REG_REG,
 427   OP_REG_REG3,
 428   OP_IMM_REG_REG_REG,
 429   OP_PUSHPOP1,
 430   OP_PUSHPOP2,
 431   OP_PUSHPOP3,
 432 };
 433
 434 #if WITH_TRACE_ANY_P
 435 void trace_input (char *name, enum op_types type, int size);
 436 void trace_output (enum op_types result);
 437 void trace_result (int has_result, uint32_t result);
 438
 439 extern int trace_num_values;
 440 extern uint32_t trace_values[];
 441 extern uint32_t trace_pc;
 442 extern const char *trace_name;
 443 extern int trace_module;
 444
 445 #define TRACE_BRANCH0() \
 446 do { \
 447   if (TRACE_BRANCH_P (CPU)) { \
 448     trace_module = TRACE_BRANCH_IDX; \
 449     trace_pc = cia; \
 450     trace_name = itable[MY_INDEX].name; \
 451     trace_num_values = 0; \
 452     trace_result (1, (nia)); \
 453   } \
 454 } while (0)
 455
 456 #define TRACE_BRANCH1(IN1) \
 457 do { \
 458   if (TRACE_BRANCH_P (CPU)) { \
 459     trace_module = TRACE_BRANCH_IDX; \
 460     trace_pc = cia; \
 461     trace_name = itable[MY_INDEX].name; \
 462     trace_values[0] = (IN1); \
 463     trace_num_values = 1; \
 464     trace_result (1, (nia)); \
 465   } \
 466 } while (0)
 467
 468 #define TRACE_BRANCH2(IN1, IN2) \
 469 do { \
 470   if (TRACE_BRANCH_P (CPU)) { \
 471     trace_module = TRACE_BRANCH_IDX; \
 472     trace_pc = cia; \
 473     trace_name = itable[MY_INDEX].name; \
 474     trace_values[0] = (IN1); \
 475     trace_values[1] = (IN2); \
 476     trace_num_values = 2; \
 477     trace_result (1, (nia)); \
 478   } \
 479 } while (0)
 480
 481 #define TRACE_BRANCH3(IN1, IN2, IN3) \
 482 do { \
 483   if (TRACE_BRANCH_P (CPU)) { \
 484     trace_module = TRACE_BRANCH_IDX; \
 485     trace_pc = cia; \
 486     trace_name = itable[MY_INDEX].name; \
 487     trace_values[0] = (IN1); \
 488     trace_values[1] = (IN2); \
 489     trace_values[2] = (IN3); \
 490     trace_num_values = 3; \
 491     trace_result (1, (nia)); \
 492   } \
 493 } while (0)
 494
 495 #define TRACE_LD(ADDR,RESULT) \
 496 do { \
 497   if (TRACE_MEMORY_P (CPU)) { \
 498     trace_module = TRACE_MEMORY_IDX; \
 499     trace_pc = cia; \
 500     trace_name = itable[MY_INDEX].name; \
 501     trace_values[0] = (ADDR); \
 502     trace_num_values = 1; \
 503     trace_result (1, (RESULT)); \
 504   } \
 505 } while (0)
 506
 507 #define TRACE_LD_NAME(NAME, ADDR,RESULT) \
 508 do { \
 509   if (TRACE_MEMORY_P (CPU)) { \
 510     trace_module = TRACE_MEMORY_IDX; \
 511     trace_pc = cia; \
 512     trace_name = (NAME); \
 513     trace_values[0] = (ADDR); \
 514     trace_num_values = 1; \
 515     trace_result (1, (RESULT)); \
 516   } \
 517 } while (0)
 518
 519 #define TRACE_ST(ADDR,RESULT) \
 520 do { \
 521   if (TRACE_MEMORY_P (CPU)) { \
 522     trace_module = TRACE_MEMORY_IDX; \
 523     trace_pc = cia; \
 524     trace_name = itable[MY_INDEX].name; \
 525     trace_values[0] = (ADDR); \
 526     trace_num_values = 1; \
 527     trace_result (1, (RESULT)); \
 528   } \
 529 } while (0)
 530
 531 #define TRACE_FP_INPUT_FPU1(V0) \
 532 do { \
 533   if (TRACE_FPU_P (CPU)) \
 534     { \
 535       uint64_t f0; \
 536       sim_fpu_to64 (&f0, (V0)); \
 537       trace_input_fp1 (SD, CPU, TRACE_FPU_IDX, f0); \
 538     } \
 539 } while (0)
 540
 541 #define TRACE_FP_INPUT_FPU2(V0, V1) \
 542 do { \
 543   if (TRACE_FPU_P (CPU)) \
 544     { \
 545       uint64_t f0, f1; \
 546       sim_fpu_to64 (&f0, (V0)); \
 547       sim_fpu_to64 (&f1, (V1)); \
 548       trace_input_fp2 (SD, CPU, TRACE_FPU_IDX, f0, f1); \
 549     } \
 550 } while (0)
 551
 552 #define TRACE_FP_INPUT_FPU3(V0, V1, V2) \
 553 do { \
 554   if (TRACE_FPU_P (CPU)) \
 555     { \
 556       uint64_t f0, f1, f2; \
 557       sim_fpu_to64 (&f0, (V0)); \
 558       sim_fpu_to64 (&f1, (V1)); \
 559       sim_fpu_to64 (&f2, (V2)); \
 560       trace_input_fp3 (SD, CPU, TRACE_FPU_IDX, f0, f1, f2); \
 561     } \
 562 } while (0)
 563
 564 #define TRACE_FP_INPUT_BOOL1_FPU2(V0, V1, V2) \
 565 do { \
 566   if (TRACE_FPU_P (CPU)) \
 567     { \
 568       int d0 = (V0); \
 569       uint64_t f1, f2; \
 570       TRACE_DATA *data = CPU_TRACE_DATA (CPU); \
 571       TRACE_IDX (data) = TRACE_FPU_IDX; \
 572       sim_fpu_to64 (&f1, (V1)); \
 573       sim_fpu_to64 (&f2, (V2)); \
 574       save_data (SD, data, trace_fmt_bool, sizeof (d0), &d0); \
 575       save_data (SD, data, trace_fmt_fp, sizeof (fp_word), &f1); \
 576       save_data (SD, data, trace_fmt_fp, sizeof (fp_word), &f2); \
 577     } \
 578 } while (0)
 579
 580 #define TRACE_FP_INPUT_WORD2(V0, V1) \
 581 do { \
 582   if (TRACE_FPU_P (CPU)) \
 583     trace_input_word2 (SD, CPU, TRACE_FPU_IDX, (V0), (V1)); \
 584 } while (0)
 585
 586 #define TRACE_FP_RESULT_FPU1(R0) \
 587 do { \
 588   if (TRACE_FPU_P (CPU)) \
 589     { \
 590       uint64_t f0; \
 591       sim_fpu_to64 (&f0, (R0)); \
 592       trace_result_fp1 (SD, CPU, TRACE_FPU_IDX, f0); \
 593     } \
 594 } while (0)
 595
 596 #define TRACE_FP_RESULT_WORD1(R0) TRACE_FP_RESULT_WORD(R0)
 597
 598 #define TRACE_FP_RESULT_WORD2(R0, R1) \
 599 do { \
 600   if (TRACE_FPU_P (CPU)) \
 601     trace_result_word2 (SD, CPU, TRACE_FPU_IDX, (R0), (R1)); \
 602 } while (0)
 603
 604 #else
 605 #define trace_input(NAME, IN1, IN2)
 606 #define trace_output(RESULT)
 607 #define trace_result(HAS_RESULT, RESULT)
 608
 609 #define TRACE_ALU_INPUT0()
 610 #define TRACE_ALU_INPUT1(IN0)
 611 #define TRACE_ALU_INPUT2(IN0, IN1)
 612 #define TRACE_ALU_INPUT2(IN0, IN1)
 613 #define TRACE_ALU_INPUT2(IN0, IN1 INS2)
 614 #define TRACE_ALU_RESULT(RESULT)
 615
 616 #define TRACE_BRANCH0()
 617 #define TRACE_BRANCH1(IN1)
 618 #define TRACE_BRANCH2(IN1, IN2)
 619 #define TRACE_BRANCH2(IN1, IN2, IN3)
 620
 621 #define TRACE_LD(ADDR,RESULT)
 622 #define TRACE_ST(ADDR,RESULT)
 623
 624 #endif
 625
 626 #define GPR_SET(N, VAL) (State.regs[(N)] = (VAL))
 627 #define GPR_CLEAR(N)    (State.regs[(N)] = 0)
 628
 629 extern void divun ( unsigned int       N,
 630                     unsigned long int  als,
 631                     unsigned long int  sfi,
 632                     uint32_t /*unsigned long int*/ *  quotient_ptr,
 633                     uint32_t /*unsigned long int*/ *  remainder_ptr,
 634                     int *overflow_ptr
 635                     );
 636 extern void divn ( unsigned int       N,
 637                    unsigned long int  als,
 638                    unsigned long int  sfi,
 639                    int32_t /*signed long int*/ *  quotient_ptr,
 640                    int32_t /*signed long int*/ *  remainder_ptr,
 641                    int *overflow_ptr
 642                    );
 643 extern int type1_regs[];
 644 extern int type2_regs[];
 645 extern int type3_regs[];
 646
 647 #define SESR_OV   (1 << 0)
 648 #define SESR_SOV  (1 << 1)
 649
 650 #define SESR      (State.sregs[12])
 651
 652 #define ROUND_Q62_Q31(X) ((((X) + (1 << 30)) >> 31) & 0xffffffff)
 653 #define ROUND_Q62_Q15(X) ((((X) + (1 << 30)) >> 47) & 0xffff)
 654 #define ROUND_Q31_Q15(X) ((((X) + (1 << 15)) >> 15) & 0xffff)
 655 #define ROUND_Q30_Q15(X) ((((X) + (1 << 14)) >> 15) & 0xffff)
 656
 657 #define SAT16(X)                        \
 658   do                                    \
 659     {                                   \
 660       int64_t z = (X);                  \
 661       if (z > 0x7fff)                   \
 662         {                               \
 663           SESR |= SESR_OV | SESR_SOV;   \
 664           z = 0x7fff;                   \
 665         }                               \
 666       else if (z < -0x8000)             \
 667         {                               \
 668           SESR |= SESR_OV | SESR_SOV;   \
 669           z = - 0x8000;                 \
 670         }                               \
 671       (X) = z;                          \
 672     }                                   \
 673   while (0)
 674
 675 #define SAT32(X)                        \
 676   do                                    \
 677     {                                   \
 678       int64_t z = (X);                  \
 679       if (z > 0x7fffffff)               \
 680         {                               \
 681           SESR |= SESR_OV | SESR_SOV;   \
 682           z = 0x7fffffff;               \
 683         }                               \
 684       else if (z < -0x80000000)         \
 685         {                               \
 686           SESR |= SESR_OV | SESR_SOV;   \
 687           z = - 0x80000000;             \
 688         }                               \
 689       (X) = z;                          \
 690     }                                   \
 691   while (0)
 692
 693 #define ABS16(X)                        \
 694   do                                    \
 695     {                                   \
 696       int64_t z = (X) & 0xffff; \
 697       if (z == 0x8000)                  \
 698         {                               \
 699           SESR |= SESR_OV | SESR_SOV;   \
 700           z = 0x7fff;                   \
 701         }                               \
 702       else if (z & 0x8000)              \
 703         {                               \
 704           z = (- z) & 0xffff;           \
 705         }                               \
 706       (X) = z;                          \
 707     }                                   \
 708   while (0)
 709
 710 #define ABS32(X)                        \
 711   do                                    \
 712     {                                   \
 713       int64_t z = (X) & 0xffffffff;     \
 714       if (z == 0x80000000)              \
 715         {                               \
 716           SESR |= SESR_OV | SESR_SOV;   \
 717           z = 0x7fffffff;               \
 718         }                               \
 719       else if (z & 0x80000000)          \
 720         {                               \
 721           z = (- z) & 0xffffffff;       \
 722         }                               \
 723       (X) = z;                          \
 724     }                                   \
 725   while (0)
 726
 727 #endif