sim/v850/sim-main.h

   1 #define SIM_HAVE_FLATMEM 1
   2
   3 #include "sim-basics.h"
   4
   5 typedef address_word sim_cia;
   6
   7 /* This simulator doesn't cache state */
   8 #define SIM_ENGINE_HALT_HOOK(sd,last_cpu,cia) while (0)
   9 #define SIM_ENGINE_RESTART_HOOK(sd,last_cpu,cia) while (0)
  10
  11 #include "sim-base.h"
  12
  13 typedef signed8 int8;
  14 typedef unsigned8 uint8;
  15 typedef signed16 int16;
  16 typedef unsigned16 uint16;
  17 typedef signed32 int32;
  18 typedef unsigned32 uint32;
  19 typedef unsigned32 reg_t;
  20
  21
  22 /* The current state of the processor; registers, memory, etc.  */
  23
  24 typedef struct _v850_regs {
  25   reg_t regs[32];               /* general-purpose registers */
  26   reg_t sregs[32];              /* system registers, including psw */
  27   reg_t pc;
  28   int dummy_mem;                /* where invalid accesses go */
  29   int exception;
  30   int pending_nmi;
  31 } v850_regs;
  32
  33 struct _sim_cpu
  34 {
  35   /* ... simulator specific members ... */
  36   v850_regs reg;
  37   /* ... base type ... */
  38   sim_cpu_base base;
  39 };
  40
  41 struct sim_state {
  42   sim_cpu cpu[MAX_NR_PROCESSORS];
  43 #if (WITH_SMP)
  44 #define STATE_CPU(sd,n) (&(sd)->cpu[n])
  45 #else
  46 #define STATE_CPU(sd,n) (&(sd)->cpu[0])
  47 #endif
  48   SIM_ADDR rom_size;
  49   SIM_ADDR low_end;
  50   SIM_ADDR high_start;
  51   SIM_ADDR high_base;
  52   sim_state_base base;
  53 };
  54
  55 /* For compatibility, until all functions converted to passing
  56    SIM_DESC as an argument */
  57 extern SIM_DESC simulator;
  58
  59
  60 #define V850_ROM_SIZE 0x8000
  61 #define V850_LOW_END 0x200000
  62 #define V850_HIGH_START 0xffe000
  63
  64
  65 #define DEBUG_TRACE             0x00000001
  66 #define DEBUG_VALUES            0x00000002
  67
  68 extern int v850_debug;
  69
  70 #define SIG_V850_EXIT   -1      /* indication of a normal exit */
  71
  72 extern uint32 OP[4];
  73 extern struct simops Simops[];
  74
  75 #define State    (STATE_CPU (simulator, 0)->reg)
  76 #define PC      (State.pc)
  77 #define SP      (State.regs[3])
  78 #define EP      (State.regs[30])
  79
  80 #define EIPC  (State.sregs[0])
  81 #define EIPSW (State.sregs[1])
  82 #define FEPC  (State.sregs[2])
  83 #define FEPSW (State.sregs[3])
  84 #define ECR   (State.sregs[4])
  85 #define PSW   (State.sregs[5])
  86 /* start-sanitize-v850e */
  87 #define CTPC  (State.sregs[16])
  88 #define CTPSW (State.sregs[17])
  89 /* end-sanitize-v850e */
  90 #define DBPC  (State.sregs[18])
  91 #define DBPSW (State.sregs[19])
  92 /* start-sanitize-v850e */
  93 #define CTBP  (State.sregs[20])
  94 /* end-sanitize-v850e */
  95
  96 #define PSW_NP 0x80
  97 #define PSW_EP 0x40
  98 #define PSW_ID 0x20
  99 #define PSW_SAT 0x10
 100 #define PSW_CY 0x8
 101 #define PSW_OV 0x4
 102 #define PSW_S 0x2
 103 #define PSW_Z 0x1
 104
 105 #define SEXT3(x)        ((((x)&0x7)^(~0x3))+0x4)
 106
 107 /* sign-extend a 4-bit number */
 108 #define SEXT4(x)        ((((x)&0xf)^(~0x7))+0x8)
 109
 110 /* sign-extend a 5-bit number */
 111 #define SEXT5(x)        ((((x)&0x1f)^(~0xf))+0x10)
 112
 113 /* sign-extend an 8-bit number */
 114 #define SEXT8(x)        ((((x)&0xff)^(~0x7f))+0x80)
 115
 116 /* sign-extend a 9-bit number */
 117 #define SEXT9(x)        ((((x)&0x1ff)^(~0xff))+0x100)
 118
 119 /* sign-extend a 16-bit number */
 120 #define SEXT16(x)       ((((x)&0xffff)^(~0x7fff))+0x8000)
 121
 122 /* sign-extend a 22-bit number */
 123 #define SEXT22(x)       ((((x)&0x3fffff)^(~0x1fffff))+0x200000)
 124
 125 /* sign-extend a 32-bit number */
 126 #define SEXT32(x)       ((((x)&0xffffffffLL)^(~0x7fffffffLL))+0x80000000LL)
 127
 128 /* sign extend a 40 bit number */
 129 #define SEXT40(x)       ((((x)&0xffffffffffLL)^(~0x7fffffffffLL))+0x8000000000LL)
 130
 131 /* sign extend a 44 bit number */
 132 #define SEXT44(x)       ((((x)&0xfffffffffffLL)^(~0x7ffffffffffLL))+0x80000000000LL)
 133
 134 /* sign extend a 60 bit number */
 135 #define SEXT60(x)       ((((x)&0xfffffffffffffffLL)^(~0x7ffffffffffffffLL))+0x800000000000000LL)
 136
 137 /* No sign extension */
 138 #define NOP(x)          (x)
 139
 140 #if 0
 141 #define MAX32   0x7fffffffLL
 142 #define MIN32   0xff80000000LL
 143 #define MASK32  0xffffffffLL
 144 #define MASK40  0xffffffffffLL
 145 #endif
 146
 147 #define INC_ADDR(x,i)   x = ((State.MD && x == MOD_E) ? MOD_S : (x)+(i))
 148
 149 #define RLW(x) load_mem (x, 4)
 150
 151 #ifdef _WIN32
 152 #ifndef SIGTRAP
 153 #define SIGTRAP 5
 154 #endif
 155 #ifndef SIGQUIT
 156 #define SIGQUIT 3
 157 #endif
 158 #endif
 159
 160 /* Function declarations.  */
 161
 162 uint32 get_word PARAMS ((uint8 *));
 163 uint16 get_half PARAMS ((uint8 *));
 164 uint8 get_byte PARAMS ((uint8 *));
 165 void put_word PARAMS ((uint8 *, uint32));
 166 void put_half PARAMS ((uint8 *, uint16));
 167 void put_byte PARAMS ((uint8 *, uint8));
 168
 169 extern uint32 load_mem PARAMS ((SIM_ADDR addr, int len));
 170 extern void store_mem PARAMS ((SIM_ADDR addr, int len, uint32 data));
 171
 172 extern uint8 *map PARAMS ((SIM_ADDR addr));