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[thirdparty/binutils-gdb.git] / sim / v850 / simops.c
1 /* This must come before any other includes. */
2 #include "defs.h"
3
4 #include "sim-main.h"
5 #include "sim-signal.h"
6 #include "v850_sim.h"
7 #include "simops.h"
8
9 #include <sys/types.h>
10
11 #ifdef HAVE_UTIME_H
12 #include <utime.h>
13 #endif
14 #include <time.h>
15 #ifdef HAVE_UNISTD_H
16 #include <unistd.h>
17 #endif
18 #include <stdlib.h>
19 #include <string.h>
20
21 #include "targ-vals.h"
22
23 #include "libiberty.h"
24
25 #include <errno.h>
26 #if !defined(__GO32__) && !defined(_WIN32)
27 #include <sys/stat.h>
28 #include <sys/times.h>
29 #include <sys/time.h>
30 #endif
31
32 /* This is an array of the bit positions of registers r20 .. r31 in
33 that order in a prepare/dispose instruction. */
34 int type1_regs[12] = { 27, 26, 25, 24, 31, 30, 29, 28, 23, 22, 0, 21 };
35 /* This is an array of the bit positions of registers r16 .. r31 in
36 that order in a push/pop instruction. */
37 int type2_regs[16] = { 3, 2, 1, 0, 27, 26, 25, 24, 31, 30, 29, 28, 23, 22, 20, 21};
38 /* This is an array of the bit positions of registers r1 .. r15 in
39 that order in a push/pop instruction. */
40 int type3_regs[15] = { 2, 1, 0, 27, 26, 25, 24, 31, 30, 29, 28, 23, 22, 20, 21};
41
42 #ifdef DEBUG
43 #ifndef SIZE_INSTRUCTION
44 #define SIZE_INSTRUCTION 18
45 #endif
46
47 #ifndef SIZE_VALUES
48 #define SIZE_VALUES 11
49 #endif
50
51
52 unsigned32 trace_values[3];
53 int trace_num_values;
54 unsigned32 trace_pc;
55 const char * trace_name;
56 int trace_module;
57
58
59 void
60 trace_input (char *name, enum op_types type, int size)
61 {
62 if (!TRACE_ALU_P (STATE_CPU (simulator, 0)))
63 return;
64
65 trace_pc = PC;
66 trace_name = name;
67 trace_module = TRACE_ALU_IDX;
68
69 switch (type)
70 {
71 default:
72 case OP_UNKNOWN:
73 case OP_NONE:
74 case OP_TRAP:
75 trace_num_values = 0;
76 break;
77
78 case OP_REG:
79 case OP_REG_REG_MOVE:
80 trace_values[0] = State.regs[OP[0]];
81 trace_num_values = 1;
82 break;
83
84 case OP_BIT_CHANGE:
85 case OP_REG_REG:
86 case OP_REG_REG_CMP:
87 trace_values[0] = State.regs[OP[1]];
88 trace_values[1] = State.regs[OP[0]];
89 trace_num_values = 2;
90 break;
91
92 case OP_IMM_REG:
93 case OP_IMM_REG_CMP:
94 trace_values[0] = SEXT5 (OP[0]);
95 trace_values[1] = OP[1];
96 trace_num_values = 2;
97 break;
98
99 case OP_IMM_REG_MOVE:
100 trace_values[0] = SEXT5 (OP[0]);
101 trace_num_values = 1;
102 break;
103
104 case OP_COND_BR:
105 trace_values[0] = State.pc;
106 trace_values[1] = SEXT9 (OP[0]);
107 trace_values[2] = PSW;
108 trace_num_values = 3;
109 break;
110
111 case OP_LOAD16:
112 trace_values[0] = OP[1] * size;
113 trace_values[1] = State.regs[30];
114 trace_num_values = 2;
115 break;
116
117 case OP_STORE16:
118 trace_values[0] = State.regs[OP[0]];
119 trace_values[1] = OP[1] * size;
120 trace_values[2] = State.regs[30];
121 trace_num_values = 3;
122 break;
123
124 case OP_LOAD32:
125 trace_values[0] = EXTEND16 (OP[2]);
126 trace_values[1] = State.regs[OP[0]];
127 trace_num_values = 2;
128 break;
129
130 case OP_STORE32:
131 trace_values[0] = State.regs[OP[1]];
132 trace_values[1] = EXTEND16 (OP[2]);
133 trace_values[2] = State.regs[OP[0]];
134 trace_num_values = 3;
135 break;
136
137 case OP_JUMP:
138 trace_values[0] = SEXT22 (OP[0]);
139 trace_values[1] = State.pc;
140 trace_num_values = 2;
141 break;
142
143 case OP_IMM_REG_REG:
144 trace_values[0] = EXTEND16 (OP[0]) << size;
145 trace_values[1] = State.regs[OP[1]];
146 trace_num_values = 2;
147 break;
148
149 case OP_IMM16_REG_REG:
150 trace_values[0] = EXTEND16 (OP[2]) << size;
151 trace_values[1] = State.regs[OP[1]];
152 trace_num_values = 2;
153 break;
154
155 case OP_UIMM_REG_REG:
156 trace_values[0] = (OP[0] & 0xffff) << size;
157 trace_values[1] = State.regs[OP[1]];
158 trace_num_values = 2;
159 break;
160
161 case OP_UIMM16_REG_REG:
162 trace_values[0] = (OP[2]) << size;
163 trace_values[1] = State.regs[OP[1]];
164 trace_num_values = 2;
165 break;
166
167 case OP_BIT:
168 trace_num_values = 0;
169 break;
170
171 case OP_EX1:
172 trace_values[0] = PSW;
173 trace_num_values = 1;
174 break;
175
176 case OP_EX2:
177 trace_num_values = 0;
178 break;
179
180 case OP_LDSR:
181 trace_values[0] = State.regs[OP[0]];
182 trace_num_values = 1;
183 break;
184
185 case OP_STSR:
186 trace_values[0] = State.sregs[OP[1]];
187 trace_num_values = 1;
188 }
189
190 }
191
192 void
193 trace_result (int has_result, unsigned32 result)
194 {
195 char buf[1000];
196 char *chp;
197
198 buf[0] = '\0';
199 chp = buf;
200
201 /* write out the values saved during the trace_input call */
202 {
203 int i;
204 for (i = 0; i < trace_num_values; i++)
205 {
206 sprintf (chp, "%*s0x%.8lx", SIZE_VALUES - 10, "",
207 (long) trace_values[i]);
208 chp = strchr (chp, '\0');
209 }
210 while (i++ < 3)
211 {
212 sprintf (chp, "%*s", SIZE_VALUES, "");
213 chp = strchr (chp, '\0');
214 }
215 }
216
217 /* append any result to the end of the buffer */
218 if (has_result)
219 sprintf (chp, " :: 0x%.8lx", (unsigned long) result);
220
221 trace_generic (simulator, STATE_CPU (simulator, 0), trace_module, "%s", buf);
222 }
223
224 void
225 trace_output (enum op_types result)
226 {
227 if (!TRACE_ALU_P (STATE_CPU (simulator, 0)))
228 return;
229
230 switch (result)
231 {
232 default:
233 case OP_UNKNOWN:
234 case OP_NONE:
235 case OP_TRAP:
236 case OP_REG:
237 case OP_REG_REG_CMP:
238 case OP_IMM_REG_CMP:
239 case OP_COND_BR:
240 case OP_STORE16:
241 case OP_STORE32:
242 case OP_BIT:
243 case OP_EX2:
244 trace_result (0, 0);
245 break;
246
247 case OP_LOAD16:
248 case OP_STSR:
249 trace_result (1, State.regs[OP[0]]);
250 break;
251
252 case OP_REG_REG:
253 case OP_REG_REG_MOVE:
254 case OP_IMM_REG:
255 case OP_IMM_REG_MOVE:
256 case OP_LOAD32:
257 case OP_EX1:
258 trace_result (1, State.regs[OP[1]]);
259 break;
260
261 case OP_IMM_REG_REG:
262 case OP_UIMM_REG_REG:
263 case OP_IMM16_REG_REG:
264 case OP_UIMM16_REG_REG:
265 trace_result (1, State.regs[OP[1]]);
266 break;
267
268 case OP_JUMP:
269 if (OP[1] != 0)
270 trace_result (1, State.regs[OP[1]]);
271 else
272 trace_result (0, 0);
273 break;
274
275 case OP_LDSR:
276 trace_result (1, State.sregs[OP[1]]);
277 break;
278 }
279 }
280 #endif
281
282 \f
283 /* Returns 1 if the specific condition is met, returns 0 otherwise. */
284 int
285 condition_met (unsigned code)
286 {
287 unsigned int psw = PSW;
288
289 switch (code & 0xf)
290 {
291 case 0x0: return ((psw & PSW_OV) != 0);
292 case 0x1: return ((psw & PSW_CY) != 0);
293 case 0x2: return ((psw & PSW_Z) != 0);
294 case 0x3: return ((((psw & PSW_CY) != 0) | ((psw & PSW_Z) != 0)) != 0);
295 case 0x4: return ((psw & PSW_S) != 0);
296 /*case 0x5: return 1;*/
297 case 0x6: return ((((psw & PSW_S) != 0) ^ ((psw & PSW_OV) != 0)) != 0);
298 case 0x7: return (((((psw & PSW_S) != 0) ^ ((psw & PSW_OV) != 0)) || ((psw & PSW_Z) != 0)) != 0);
299 case 0x8: return ((psw & PSW_OV) == 0);
300 case 0x9: return ((psw & PSW_CY) == 0);
301 case 0xa: return ((psw & PSW_Z) == 0);
302 case 0xb: return ((((psw & PSW_CY) != 0) | ((psw & PSW_Z) != 0)) == 0);
303 case 0xc: return ((psw & PSW_S) == 0);
304 case 0xd: return ((psw & PSW_SAT) != 0);
305 case 0xe: return ((((psw & PSW_S) != 0) ^ ((psw & PSW_OV) != 0)) == 0);
306 case 0xf: return (((((psw & PSW_S) != 0) ^ ((psw & PSW_OV) != 0)) || ((psw & PSW_Z) != 0)) == 0);
307 }
308
309 return 1;
310 }
311
312 unsigned long
313 Add32 (unsigned long a1, unsigned long a2, int * carry)
314 {
315 unsigned long result = (a1 + a2);
316
317 * carry = (result < a1);
318
319 return result;
320 }
321
322 static void
323 Multiply64 (int sign, unsigned long op0)
324 {
325 unsigned long op1;
326 unsigned long lo;
327 unsigned long mid1;
328 unsigned long mid2;
329 unsigned long hi;
330 unsigned long RdLo;
331 unsigned long RdHi;
332 int carry;
333
334 op1 = State.regs[ OP[1] ];
335
336 if (sign)
337 {
338 /* Compute sign of result and adjust operands if necessary. */
339
340 sign = (op0 ^ op1) & 0x80000000;
341
342 if (((signed long) op0) < 0)
343 op0 = - op0;
344
345 if (((signed long) op1) < 0)
346 op1 = - op1;
347 }
348
349 /* We can split the 32x32 into four 16x16 operations. This ensures
350 that we do not lose precision on 32bit only hosts: */
351 lo = ( (op0 & 0xFFFF) * (op1 & 0xFFFF));
352 mid1 = ( (op0 & 0xFFFF) * ((op1 >> 16) & 0xFFFF));
353 mid2 = (((op0 >> 16) & 0xFFFF) * (op1 & 0xFFFF));
354 hi = (((op0 >> 16) & 0xFFFF) * ((op1 >> 16) & 0xFFFF));
355
356 /* We now need to add all of these results together, taking care
357 to propogate the carries from the additions: */
358 RdLo = Add32 (lo, (mid1 << 16), & carry);
359 RdHi = carry;
360 RdLo = Add32 (RdLo, (mid2 << 16), & carry);
361 RdHi += (carry + ((mid1 >> 16) & 0xFFFF) + ((mid2 >> 16) & 0xFFFF) + hi);
362
363 if (sign)
364 {
365 /* Negate result if necessary. */
366
367 RdLo = ~ RdLo;
368 RdHi = ~ RdHi;
369 if (RdLo == 0xFFFFFFFF)
370 {
371 RdLo = 0;
372 RdHi += 1;
373 }
374 else
375 RdLo += 1;
376 }
377
378 /* Don't store into register 0. */
379 if (OP[1])
380 State.regs[ OP[1] ] = RdLo;
381 if (OP[2] >> 11)
382 State.regs[ OP[2] >> 11 ] = RdHi;
383
384 return;
385 }
386
387 \f
388 /* Read a null terminated string from memory, return in a buffer. */
389
390 static char *
391 fetch_str (SIM_DESC sd, address_word addr)
392 {
393 char *buf;
394 int nr = 0;
395
396 while (sim_core_read_1 (STATE_CPU (sd, 0),
397 PC, read_map, addr + nr) != 0)
398 nr++;
399
400 buf = NZALLOC (char, nr + 1);
401 sim_read (simulator, addr, (unsigned char *) buf, nr);
402
403 return buf;
404 }
405
406 /* Read a null terminated argument vector from memory, return in a
407 buffer. */
408
409 static char **
410 fetch_argv (SIM_DESC sd, address_word addr)
411 {
412 int max_nr = 64;
413 int nr = 0;
414 char **buf = xmalloc (max_nr * sizeof (char*));
415
416 while (1)
417 {
418 unsigned32 a = sim_core_read_4 (STATE_CPU (sd, 0),
419 PC, read_map, addr + nr * 4);
420 if (a == 0) break;
421 buf[nr] = fetch_str (sd, a);
422 nr ++;
423 if (nr == max_nr - 1)
424 {
425 max_nr += 50;
426 buf = xrealloc (buf, max_nr * sizeof (char*));
427 }
428 }
429 buf[nr] = 0;
430 return buf;
431 }
432
433 \f
434 /* sst.b */
435 int
436 OP_380 (void)
437 {
438 trace_input ("sst.b", OP_STORE16, 1);
439
440 store_mem (State.regs[30] + (OP[3] & 0x7f), 1, State.regs[ OP[1] ]);
441
442 trace_output (OP_STORE16);
443
444 return 2;
445 }
446
447 /* sst.h */
448 int
449 OP_480 (void)
450 {
451 trace_input ("sst.h", OP_STORE16, 2);
452
453 store_mem (State.regs[30] + ((OP[3] & 0x7f) << 1), 2, State.regs[ OP[1] ]);
454
455 trace_output (OP_STORE16);
456
457 return 2;
458 }
459
460 /* sst.w */
461 int
462 OP_501 (void)
463 {
464 trace_input ("sst.w", OP_STORE16, 4);
465
466 store_mem (State.regs[30] + ((OP[3] & 0x7e) << 1), 4, State.regs[ OP[1] ]);
467
468 trace_output (OP_STORE16);
469
470 return 2;
471 }
472
473 /* ld.b */
474 int
475 OP_700 (void)
476 {
477 int adr;
478
479 trace_input ("ld.b", OP_LOAD32, 1);
480
481 adr = State.regs[ OP[0] ] + EXTEND16 (OP[2]);
482
483 State.regs[ OP[1] ] = EXTEND8 (load_mem (adr, 1));
484
485 trace_output (OP_LOAD32);
486
487 return 4;
488 }
489
490 /* ld.h */
491 int
492 OP_720 (void)
493 {
494 int adr;
495
496 trace_input ("ld.h", OP_LOAD32, 2);
497
498 adr = State.regs[ OP[0] ] + EXTEND16 (OP[2]);
499 adr &= ~0x1;
500
501 State.regs[ OP[1] ] = EXTEND16 (load_mem (adr, 2));
502
503 trace_output (OP_LOAD32);
504
505 return 4;
506 }
507
508 /* ld.w */
509 int
510 OP_10720 (void)
511 {
512 int adr;
513
514 trace_input ("ld.w", OP_LOAD32, 4);
515
516 adr = State.regs[ OP[0] ] + EXTEND16 (OP[2] & ~1);
517 adr &= ~0x3;
518
519 State.regs[ OP[1] ] = load_mem (adr, 4);
520
521 trace_output (OP_LOAD32);
522
523 return 4;
524 }
525
526 /* st.b */
527 int
528 OP_740 (void)
529 {
530 trace_input ("st.b", OP_STORE32, 1);
531
532 store_mem (State.regs[ OP[0] ] + EXTEND16 (OP[2]), 1, State.regs[ OP[1] ]);
533
534 trace_output (OP_STORE32);
535
536 return 4;
537 }
538
539 /* st.h */
540 int
541 OP_760 (void)
542 {
543 int adr;
544
545 trace_input ("st.h", OP_STORE32, 2);
546
547 adr = State.regs[ OP[0] ] + EXTEND16 (OP[2]);
548 adr &= ~1;
549
550 store_mem (adr, 2, State.regs[ OP[1] ]);
551
552 trace_output (OP_STORE32);
553
554 return 4;
555 }
556
557 /* st.w */
558 int
559 OP_10760 (void)
560 {
561 int adr;
562
563 trace_input ("st.w", OP_STORE32, 4);
564
565 adr = State.regs[ OP[0] ] + EXTEND16 (OP[2] & ~1);
566 adr &= ~3;
567
568 store_mem (adr, 4, State.regs[ OP[1] ]);
569
570 trace_output (OP_STORE32);
571
572 return 4;
573 }
574
575 /* add reg, reg */
576 int
577 OP_1C0 (void)
578 {
579 unsigned int op0, op1, result, z, s, cy, ov;
580
581 trace_input ("add", OP_REG_REG, 0);
582
583 /* Compute the result. */
584
585 op0 = State.regs[ OP[0] ];
586 op1 = State.regs[ OP[1] ];
587
588 result = op0 + op1;
589
590 /* Compute the condition codes. */
591 z = (result == 0);
592 s = (result & 0x80000000);
593 cy = (result < op0 || result < op1);
594 ov = ((op0 & 0x80000000) == (op1 & 0x80000000)
595 && (op0 & 0x80000000) != (result & 0x80000000));
596
597 /* Store the result and condition codes. */
598 State.regs[OP[1]] = result;
599 PSW &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
600 PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
601 | (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0));
602 trace_output (OP_REG_REG);
603
604 return 2;
605 }
606
607 /* add sign_extend(imm5), reg */
608 int
609 OP_240 (void)
610 {
611 unsigned int op0, op1, result, z, s, cy, ov;
612 int temp;
613
614 trace_input ("add", OP_IMM_REG, 0);
615
616 /* Compute the result. */
617 temp = SEXT5 (OP[0]);
618 op0 = temp;
619 op1 = State.regs[OP[1]];
620 result = op0 + op1;
621
622 /* Compute the condition codes. */
623 z = (result == 0);
624 s = (result & 0x80000000);
625 cy = (result < op0 || result < op1);
626 ov = ((op0 & 0x80000000) == (op1 & 0x80000000)
627 && (op0 & 0x80000000) != (result & 0x80000000));
628
629 /* Store the result and condition codes. */
630 State.regs[OP[1]] = result;
631 PSW &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
632 PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
633 | (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0));
634 trace_output (OP_IMM_REG);
635
636 return 2;
637 }
638
639 /* addi sign_extend(imm16), reg, reg */
640 int
641 OP_600 (void)
642 {
643 unsigned int op0, op1, result, z, s, cy, ov;
644
645 trace_input ("addi", OP_IMM16_REG_REG, 0);
646
647 /* Compute the result. */
648
649 op0 = EXTEND16 (OP[2]);
650 op1 = State.regs[ OP[0] ];
651 result = op0 + op1;
652
653 /* Compute the condition codes. */
654 z = (result == 0);
655 s = (result & 0x80000000);
656 cy = (result < op0 || result < op1);
657 ov = ((op0 & 0x80000000) == (op1 & 0x80000000)
658 && (op0 & 0x80000000) != (result & 0x80000000));
659
660 /* Store the result and condition codes. */
661 State.regs[OP[1]] = result;
662 PSW &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
663 PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
664 | (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0));
665 trace_output (OP_IMM16_REG_REG);
666
667 return 4;
668 }
669
670 /* sub reg1, reg2 */
671 int
672 OP_1A0 (void)
673 {
674 unsigned int op0, op1, result, z, s, cy, ov;
675
676 trace_input ("sub", OP_REG_REG, 0);
677 /* Compute the result. */
678 op0 = State.regs[ OP[0] ];
679 op1 = State.regs[ OP[1] ];
680 result = op1 - op0;
681
682 /* Compute the condition codes. */
683 z = (result == 0);
684 s = (result & 0x80000000);
685 cy = (op1 < op0);
686 ov = ((op1 & 0x80000000) != (op0 & 0x80000000)
687 && (op1 & 0x80000000) != (result & 0x80000000));
688
689 /* Store the result and condition codes. */
690 State.regs[OP[1]] = result;
691 PSW &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
692 PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
693 | (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0));
694 trace_output (OP_REG_REG);
695
696 return 2;
697 }
698
699 /* subr reg1, reg2 */
700 int
701 OP_180 (void)
702 {
703 unsigned int op0, op1, result, z, s, cy, ov;
704
705 trace_input ("subr", OP_REG_REG, 0);
706 /* Compute the result. */
707 op0 = State.regs[ OP[0] ];
708 op1 = State.regs[ OP[1] ];
709 result = op0 - op1;
710
711 /* Compute the condition codes. */
712 z = (result == 0);
713 s = (result & 0x80000000);
714 cy = (op0 < op1);
715 ov = ((op0 & 0x80000000) != (op1 & 0x80000000)
716 && (op0 & 0x80000000) != (result & 0x80000000));
717
718 /* Store the result and condition codes. */
719 State.regs[OP[1]] = result;
720 PSW &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
721 PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
722 | (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0));
723 trace_output (OP_REG_REG);
724
725 return 2;
726 }
727
728 /* sxh reg1 */
729 int
730 OP_E0 (void)
731 {
732 trace_input ("mulh", OP_REG_REG, 0);
733
734 State.regs[ OP[1] ] = (EXTEND16 (State.regs[ OP[1] ]) * EXTEND16 (State.regs[ OP[0] ]));
735
736 trace_output (OP_REG_REG);
737
738 return 2;
739 }
740
741 /* mulh sign_extend(imm5), reg2 */
742 int
743 OP_2E0 (void)
744 {
745 trace_input ("mulh", OP_IMM_REG, 0);
746
747 State.regs[ OP[1] ] = EXTEND16 (State.regs[ OP[1] ]) * SEXT5 (OP[0]);
748
749 trace_output (OP_IMM_REG);
750
751 return 2;
752 }
753
754 /* mulhi imm16, reg1, reg2 */
755 int
756 OP_6E0 (void)
757 {
758 trace_input ("mulhi", OP_IMM16_REG_REG, 0);
759
760 State.regs[ OP[1] ] = EXTEND16 (State.regs[ OP[0] ]) * EXTEND16 (OP[2]);
761
762 trace_output (OP_IMM16_REG_REG);
763
764 return 4;
765 }
766
767 /* cmp reg, reg */
768 int
769 OP_1E0 (void)
770 {
771 unsigned int op0, op1, result, z, s, cy, ov;
772
773 trace_input ("cmp", OP_REG_REG_CMP, 0);
774 /* Compute the result. */
775 op0 = State.regs[ OP[0] ];
776 op1 = State.regs[ OP[1] ];
777 result = op1 - op0;
778
779 /* Compute the condition codes. */
780 z = (result == 0);
781 s = (result & 0x80000000);
782 cy = (op1 < op0);
783 ov = ((op1 & 0x80000000) != (op0 & 0x80000000)
784 && (op1 & 0x80000000) != (result & 0x80000000));
785
786 /* Set condition codes. */
787 PSW &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
788 PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
789 | (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0));
790 trace_output (OP_REG_REG_CMP);
791
792 return 2;
793 }
794
795 /* cmp sign_extend(imm5), reg */
796 int
797 OP_260 (void)
798 {
799 unsigned int op0, op1, result, z, s, cy, ov;
800 int temp;
801
802 /* Compute the result. */
803 trace_input ("cmp", OP_IMM_REG_CMP, 0);
804 temp = SEXT5 (OP[0]);
805 op0 = temp;
806 op1 = State.regs[OP[1]];
807 result = op1 - op0;
808
809 /* Compute the condition codes. */
810 z = (result == 0);
811 s = (result & 0x80000000);
812 cy = (op1 < op0);
813 ov = ((op1 & 0x80000000) != (op0 & 0x80000000)
814 && (op1 & 0x80000000) != (result & 0x80000000));
815
816 /* Set condition codes. */
817 PSW &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
818 PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
819 | (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0));
820 trace_output (OP_IMM_REG_CMP);
821
822 return 2;
823 }
824
825 /* setf cccc,reg2 */
826 int
827 OP_7E0 (void)
828 {
829 trace_input ("setf", OP_EX1, 0);
830
831 State.regs[ OP[1] ] = condition_met (OP[0]);
832
833 trace_output (OP_EX1);
834
835 return 4;
836 }
837
838 /* satadd reg,reg */
839 int
840 OP_C0 (void)
841 {
842 unsigned int op0, op1, result, z, s, cy, ov, sat;
843
844 trace_input ("satadd", OP_REG_REG, 0);
845 /* Compute the result. */
846 op0 = State.regs[ OP[0] ];
847 op1 = State.regs[ OP[1] ];
848 result = op0 + op1;
849
850 /* Compute the condition codes. */
851 z = (result == 0);
852 s = (result & 0x80000000);
853 cy = (result < op0 || result < op1);
854 ov = ((op0 & 0x80000000) == (op1 & 0x80000000)
855 && (op0 & 0x80000000) != (result & 0x80000000));
856 sat = ov;
857
858 /* Handle saturated results. */
859 if (sat && s)
860 {
861 /* An overflow that results in a negative result implies that we
862 became too positive. */
863 result = 0x7fffffff;
864 s = 0;
865 }
866 else if (sat)
867 {
868 /* Any other overflow must have thus been too negative. */
869 result = 0x80000000;
870 s = 1;
871 z = 0;
872 }
873
874 /* Store the result and condition codes. */
875 State.regs[OP[1]] = result;
876 PSW &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
877 PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
878 | (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0)
879 | (sat ? PSW_SAT : 0));
880
881 trace_output (OP_REG_REG);
882
883 return 2;
884 }
885
886 /* satadd sign_extend(imm5), reg */
887 int
888 OP_220 (void)
889 {
890 unsigned int op0, op1, result, z, s, cy, ov, sat;
891
892 int temp;
893
894 trace_input ("satadd", OP_IMM_REG, 0);
895
896 /* Compute the result. */
897 temp = SEXT5 (OP[0]);
898 op0 = temp;
899 op1 = State.regs[OP[1]];
900 result = op0 + op1;
901
902 /* Compute the condition codes. */
903 z = (result == 0);
904 s = (result & 0x80000000);
905 cy = (result < op0 || result < op1);
906 ov = ((op0 & 0x80000000) == (op1 & 0x80000000)
907 && (op0 & 0x80000000) != (result & 0x80000000));
908 sat = ov;
909
910 /* Handle saturated results. */
911 if (sat && s)
912 {
913 /* An overflow that results in a negative result implies that we
914 became too positive. */
915 result = 0x7fffffff;
916 s = 0;
917 }
918 else if (sat)
919 {
920 /* Any other overflow must have thus been too negative. */
921 result = 0x80000000;
922 s = 1;
923 z = 0;
924 }
925
926 /* Store the result and condition codes. */
927 State.regs[OP[1]] = result;
928 PSW &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
929 PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
930 | (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0)
931 | (sat ? PSW_SAT : 0));
932 trace_output (OP_IMM_REG);
933
934 return 2;
935 }
936
937 /* satsub reg1, reg2 */
938 int
939 OP_A0 (void)
940 {
941 unsigned int op0, op1, result, z, s, cy, ov, sat;
942
943 trace_input ("satsub", OP_REG_REG, 0);
944
945 /* Compute the result. */
946 op0 = State.regs[ OP[0] ];
947 op1 = State.regs[ OP[1] ];
948 result = op1 - op0;
949
950 /* Compute the condition codes. */
951 z = (result == 0);
952 s = (result & 0x80000000);
953 cy = (op1 < op0);
954 ov = ((op1 & 0x80000000) != (op0 & 0x80000000)
955 && (op1 & 0x80000000) != (result & 0x80000000));
956 sat = ov;
957
958 /* Handle saturated results. */
959 if (sat && s)
960 {
961 /* An overflow that results in a negative result implies that we
962 became too positive. */
963 result = 0x7fffffff;
964 s = 0;
965 }
966 else if (sat)
967 {
968 /* Any other overflow must have thus been too negative. */
969 result = 0x80000000;
970 s = 1;
971 z = 0;
972 }
973
974 /* Store the result and condition codes. */
975 State.regs[OP[1]] = result;
976 PSW &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
977 PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
978 | (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0)
979 | (sat ? PSW_SAT : 0));
980
981 trace_output (OP_REG_REG);
982 return 2;
983 }
984
985 /* satsubi sign_extend(imm16), reg */
986 int
987 OP_660 (void)
988 {
989 unsigned int op0, op1, result, z, s, cy, ov, sat;
990 int temp;
991
992 trace_input ("satsubi", OP_IMM_REG, 0);
993
994 /* Compute the result. */
995 temp = EXTEND16 (OP[2]);
996 op0 = temp;
997 op1 = State.regs[ OP[0] ];
998 result = op1 - op0;
999
1000 /* Compute the condition codes. */
1001 z = (result == 0);
1002 s = (result & 0x80000000);
1003 cy = (op1 < op0);
1004 ov = ((op1 & 0x80000000) != (op0 & 0x80000000)
1005 && (op1 & 0x80000000) != (result & 0x80000000));
1006 sat = ov;
1007
1008 /* Handle saturated results. */
1009 if (sat && s)
1010 {
1011 /* An overflow that results in a negative result implies that we
1012 became too positive. */
1013 result = 0x7fffffff;
1014 s = 0;
1015 }
1016 else if (sat)
1017 {
1018 /* Any other overflow must have thus been too negative. */
1019 result = 0x80000000;
1020 s = 1;
1021 z = 0;
1022 }
1023
1024 /* Store the result and condition codes. */
1025 State.regs[OP[1]] = result;
1026 PSW &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
1027 PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
1028 | (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0)
1029 | (sat ? PSW_SAT : 0));
1030
1031 trace_output (OP_IMM_REG);
1032
1033 return 4;
1034 }
1035
1036 /* satsubr reg,reg */
1037 int
1038 OP_80 (void)
1039 {
1040 unsigned int op0, op1, result, z, s, cy, ov, sat;
1041
1042 trace_input ("satsubr", OP_REG_REG, 0);
1043
1044 /* Compute the result. */
1045 op0 = State.regs[ OP[0] ];
1046 op1 = State.regs[ OP[1] ];
1047 result = op0 - op1;
1048
1049 /* Compute the condition codes. */
1050 z = (result == 0);
1051 s = (result & 0x80000000);
1052 cy = (op0 < op1);
1053 ov = ((op0 & 0x80000000) != (op1 & 0x80000000)
1054 && (op0 & 0x80000000) != (result & 0x80000000));
1055 sat = ov;
1056
1057 /* Handle saturated results. */
1058 if (sat && s)
1059 {
1060 /* An overflow that results in a negative result implies that we
1061 became too positive. */
1062 result = 0x7fffffff;
1063 s = 0;
1064 }
1065 else if (sat)
1066 {
1067 /* Any other overflow must have thus been too negative. */
1068 result = 0x80000000;
1069 s = 1;
1070 z = 0;
1071 }
1072
1073 /* Store the result and condition codes. */
1074 State.regs[OP[1]] = result;
1075 PSW &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
1076 PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
1077 | (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0)
1078 | (sat ? PSW_SAT : 0));
1079
1080 trace_output (OP_REG_REG);
1081
1082 return 2;
1083 }
1084
1085 /* tst reg,reg */
1086 int
1087 OP_160 (void)
1088 {
1089 unsigned int op0, op1, result, z, s;
1090
1091 trace_input ("tst", OP_REG_REG_CMP, 0);
1092
1093 /* Compute the result. */
1094 op0 = State.regs[ OP[0] ];
1095 op1 = State.regs[ OP[1] ];
1096 result = op0 & op1;
1097
1098 /* Compute the condition codes. */
1099 z = (result == 0);
1100 s = (result & 0x80000000);
1101
1102 /* Store the condition codes. */
1103 PSW &= ~(PSW_Z | PSW_S | PSW_OV);
1104 PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0));
1105 trace_output (OP_REG_REG_CMP);
1106
1107 return 2;
1108 }
1109
1110 /* mov sign_extend(imm5), reg */
1111 int
1112 OP_200 (void)
1113 {
1114 int value = SEXT5 (OP[0]);
1115
1116 trace_input ("mov", OP_IMM_REG_MOVE, 0);
1117
1118 State.regs[ OP[1] ] = value;
1119
1120 trace_output (OP_IMM_REG_MOVE);
1121
1122 return 2;
1123 }
1124
1125 /* movhi imm16, reg, reg */
1126 int
1127 OP_640 (void)
1128 {
1129 trace_input ("movhi", OP_UIMM16_REG_REG, 16);
1130
1131 State.regs[ OP[1] ] = State.regs[ OP[0] ] + (OP[2] << 16);
1132
1133 trace_output (OP_UIMM16_REG_REG);
1134
1135 return 4;
1136 }
1137
1138 /* sar zero_extend(imm5),reg1 */
1139 int
1140 OP_2A0 (void)
1141 {
1142 unsigned int op0, op1, result, z, s, cy;
1143
1144 trace_input ("sar", OP_IMM_REG, 0);
1145 op0 = OP[0];
1146 op1 = State.regs[ OP[1] ];
1147 result = (signed)op1 >> op0;
1148
1149 /* Compute the condition codes. */
1150 z = (result == 0);
1151 s = (result & 0x80000000);
1152 cy = op0 ? (op1 & (1 << (op0 - 1))) : 0;
1153
1154 /* Store the result and condition codes. */
1155 State.regs[ OP[1] ] = result;
1156 PSW &= ~(PSW_Z | PSW_S | PSW_OV | PSW_CY);
1157 PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
1158 | (cy ? PSW_CY : 0));
1159 trace_output (OP_IMM_REG);
1160
1161 return 2;
1162 }
1163
1164 /* sar reg1, reg2 */
1165 int
1166 OP_A007E0 (void)
1167 {
1168 unsigned int op0, op1, result, z, s, cy;
1169
1170 trace_input ("sar", OP_REG_REG, 0);
1171
1172 op0 = State.regs[ OP[0] ] & 0x1f;
1173 op1 = State.regs[ OP[1] ];
1174 result = (signed)op1 >> op0;
1175
1176 /* Compute the condition codes. */
1177 z = (result == 0);
1178 s = (result & 0x80000000);
1179 cy = op0 ? (op1 & (1 << (op0 - 1))) : 0;
1180
1181 /* Store the result and condition codes. */
1182 State.regs[OP[1]] = result;
1183 PSW &= ~(PSW_Z | PSW_S | PSW_OV | PSW_CY);
1184 PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
1185 | (cy ? PSW_CY : 0));
1186 trace_output (OP_REG_REG);
1187
1188 return 4;
1189 }
1190
1191 /* shl zero_extend(imm5),reg1 */
1192 int
1193 OP_2C0 (void)
1194 {
1195 unsigned int op0, op1, result, z, s, cy;
1196
1197 trace_input ("shl", OP_IMM_REG, 0);
1198 op0 = OP[0];
1199 op1 = State.regs[ OP[1] ];
1200 result = op1 << op0;
1201
1202 /* Compute the condition codes. */
1203 z = (result == 0);
1204 s = (result & 0x80000000);
1205 cy = op0 ? (op1 & (1 << (32 - op0))) : 0;
1206
1207 /* Store the result and condition codes. */
1208 State.regs[OP[1]] = result;
1209 PSW &= ~(PSW_Z | PSW_S | PSW_OV | PSW_CY);
1210 PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
1211 | (cy ? PSW_CY : 0));
1212 trace_output (OP_IMM_REG);
1213
1214 return 2;
1215 }
1216
1217 /* shl reg1, reg2 */
1218 int
1219 OP_C007E0 (void)
1220 {
1221 unsigned int op0, op1, result, z, s, cy;
1222
1223 trace_input ("shl", OP_REG_REG, 0);
1224 op0 = State.regs[ OP[0] ] & 0x1f;
1225 op1 = State.regs[ OP[1] ];
1226 result = op1 << op0;
1227
1228 /* Compute the condition codes. */
1229 z = (result == 0);
1230 s = (result & 0x80000000);
1231 cy = op0 ? (op1 & (1 << (32 - op0))) : 0;
1232
1233 /* Store the result and condition codes. */
1234 State.regs[OP[1]] = result;
1235 PSW &= ~(PSW_Z | PSW_S | PSW_OV | PSW_CY);
1236 PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
1237 | (cy ? PSW_CY : 0));
1238 trace_output (OP_REG_REG);
1239
1240 return 4;
1241 }
1242
1243 /* shr zero_extend(imm5),reg1 */
1244 int
1245 OP_280 (void)
1246 {
1247 unsigned int op0, op1, result, z, s, cy;
1248
1249 trace_input ("shr", OP_IMM_REG, 0);
1250 op0 = OP[0];
1251 op1 = State.regs[ OP[1] ];
1252 result = op1 >> op0;
1253
1254 /* Compute the condition codes. */
1255 z = (result == 0);
1256 s = (result & 0x80000000);
1257 cy = op0 ? (op1 & (1 << (op0 - 1))) : 0;
1258
1259 /* Store the result and condition codes. */
1260 State.regs[OP[1]] = result;
1261 PSW &= ~(PSW_Z | PSW_S | PSW_OV | PSW_CY);
1262 PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
1263 | (cy ? PSW_CY : 0));
1264 trace_output (OP_IMM_REG);
1265
1266 return 2;
1267 }
1268
1269 /* shr reg1, reg2 */
1270 int
1271 OP_8007E0 (void)
1272 {
1273 unsigned int op0, op1, result, z, s, cy;
1274
1275 trace_input ("shr", OP_REG_REG, 0);
1276 op0 = State.regs[ OP[0] ] & 0x1f;
1277 op1 = State.regs[ OP[1] ];
1278 result = op1 >> op0;
1279
1280 /* Compute the condition codes. */
1281 z = (result == 0);
1282 s = (result & 0x80000000);
1283 cy = op0 ? (op1 & (1 << (op0 - 1))) : 0;
1284
1285 /* Store the result and condition codes. */
1286 State.regs[OP[1]] = result;
1287 PSW &= ~(PSW_Z | PSW_S | PSW_OV | PSW_CY);
1288 PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
1289 | (cy ? PSW_CY : 0));
1290 trace_output (OP_REG_REG);
1291
1292 return 4;
1293 }
1294
1295 /* or reg, reg */
1296 int
1297 OP_100 (void)
1298 {
1299 unsigned int op0, op1, result, z, s;
1300
1301 trace_input ("or", OP_REG_REG, 0);
1302
1303 /* Compute the result. */
1304 op0 = State.regs[ OP[0] ];
1305 op1 = State.regs[ OP[1] ];
1306 result = op0 | op1;
1307
1308 /* Compute the condition codes. */
1309 z = (result == 0);
1310 s = (result & 0x80000000);
1311
1312 /* Store the result and condition codes. */
1313 State.regs[OP[1]] = result;
1314 PSW &= ~(PSW_Z | PSW_S | PSW_OV);
1315 PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0));
1316 trace_output (OP_REG_REG);
1317
1318 return 2;
1319 }
1320
1321 /* ori zero_extend(imm16), reg, reg */
1322 int
1323 OP_680 (void)
1324 {
1325 unsigned int op0, op1, result, z, s;
1326
1327 trace_input ("ori", OP_UIMM16_REG_REG, 0);
1328 op0 = OP[2];
1329 op1 = State.regs[ OP[0] ];
1330 result = op0 | op1;
1331
1332 /* Compute the condition codes. */
1333 z = (result == 0);
1334 s = (result & 0x80000000);
1335
1336 /* Store the result and condition codes. */
1337 State.regs[OP[1]] = result;
1338 PSW &= ~(PSW_Z | PSW_S | PSW_OV);
1339 PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0));
1340 trace_output (OP_UIMM16_REG_REG);
1341
1342 return 4;
1343 }
1344
1345 /* and reg, reg */
1346 int
1347 OP_140 (void)
1348 {
1349 unsigned int op0, op1, result, z, s;
1350
1351 trace_input ("and", OP_REG_REG, 0);
1352
1353 /* Compute the result. */
1354 op0 = State.regs[ OP[0] ];
1355 op1 = State.regs[ OP[1] ];
1356 result = op0 & op1;
1357
1358 /* Compute the condition codes. */
1359 z = (result == 0);
1360 s = (result & 0x80000000);
1361
1362 /* Store the result and condition codes. */
1363 State.regs[OP[1]] = result;
1364 PSW &= ~(PSW_Z | PSW_S | PSW_OV);
1365 PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0));
1366 trace_output (OP_REG_REG);
1367
1368 return 2;
1369 }
1370
1371 /* andi zero_extend(imm16), reg, reg */
1372 int
1373 OP_6C0 (void)
1374 {
1375 unsigned int result, z;
1376
1377 trace_input ("andi", OP_UIMM16_REG_REG, 0);
1378
1379 result = OP[2] & State.regs[ OP[0] ];
1380
1381 /* Compute the condition codes. */
1382 z = (result == 0);
1383
1384 /* Store the result and condition codes. */
1385 State.regs[ OP[1] ] = result;
1386
1387 PSW &= ~(PSW_Z | PSW_S | PSW_OV);
1388 PSW |= (z ? PSW_Z : 0);
1389
1390 trace_output (OP_UIMM16_REG_REG);
1391
1392 return 4;
1393 }
1394
1395 /* xor reg, reg */
1396 int
1397 OP_120 (void)
1398 {
1399 unsigned int op0, op1, result, z, s;
1400
1401 trace_input ("xor", OP_REG_REG, 0);
1402
1403 /* Compute the result. */
1404 op0 = State.regs[ OP[0] ];
1405 op1 = State.regs[ OP[1] ];
1406 result = op0 ^ op1;
1407
1408 /* Compute the condition codes. */
1409 z = (result == 0);
1410 s = (result & 0x80000000);
1411
1412 /* Store the result and condition codes. */
1413 State.regs[OP[1]] = result;
1414 PSW &= ~(PSW_Z | PSW_S | PSW_OV);
1415 PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0));
1416 trace_output (OP_REG_REG);
1417
1418 return 2;
1419 }
1420
1421 /* xori zero_extend(imm16), reg, reg */
1422 int
1423 OP_6A0 (void)
1424 {
1425 unsigned int op0, op1, result, z, s;
1426
1427 trace_input ("xori", OP_UIMM16_REG_REG, 0);
1428 op0 = OP[2];
1429 op1 = State.regs[ OP[0] ];
1430 result = op0 ^ op1;
1431
1432 /* Compute the condition codes. */
1433 z = (result == 0);
1434 s = (result & 0x80000000);
1435
1436 /* Store the result and condition codes. */
1437 State.regs[OP[1]] = result;
1438 PSW &= ~(PSW_Z | PSW_S | PSW_OV);
1439 PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0));
1440 trace_output (OP_UIMM16_REG_REG);
1441
1442 return 4;
1443 }
1444
1445 /* not reg1, reg2 */
1446 int
1447 OP_20 (void)
1448 {
1449 unsigned int op0, result, z, s;
1450
1451 trace_input ("not", OP_REG_REG_MOVE, 0);
1452 /* Compute the result. */
1453 op0 = State.regs[ OP[0] ];
1454 result = ~op0;
1455
1456 /* Compute the condition codes. */
1457 z = (result == 0);
1458 s = (result & 0x80000000);
1459
1460 /* Store the result and condition codes. */
1461 State.regs[OP[1]] = result;
1462 PSW &= ~(PSW_Z | PSW_S | PSW_OV);
1463 PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0));
1464 trace_output (OP_REG_REG_MOVE);
1465
1466 return 2;
1467 }
1468
1469 /* set1 */
1470 int
1471 OP_7C0 (void)
1472 {
1473 unsigned int op0, op1, op2;
1474 int temp;
1475
1476 trace_input ("set1", OP_BIT, 0);
1477 op0 = State.regs[ OP[0] ];
1478 op1 = OP[1] & 0x7;
1479 temp = EXTEND16 (OP[2]);
1480 op2 = temp;
1481 temp = load_mem (op0 + op2, 1);
1482 PSW &= ~PSW_Z;
1483 if ((temp & (1 << op1)) == 0)
1484 PSW |= PSW_Z;
1485 temp |= (1 << op1);
1486 store_mem (op0 + op2, 1, temp);
1487 trace_output (OP_BIT);
1488
1489 return 4;
1490 }
1491
1492 /* not1 */
1493 int
1494 OP_47C0 (void)
1495 {
1496 unsigned int op0, op1, op2;
1497 int temp;
1498
1499 trace_input ("not1", OP_BIT, 0);
1500 op0 = State.regs[ OP[0] ];
1501 op1 = OP[1] & 0x7;
1502 temp = EXTEND16 (OP[2]);
1503 op2 = temp;
1504 temp = load_mem (op0 + op2, 1);
1505 PSW &= ~PSW_Z;
1506 if ((temp & (1 << op1)) == 0)
1507 PSW |= PSW_Z;
1508 temp ^= (1 << op1);
1509 store_mem (op0 + op2, 1, temp);
1510 trace_output (OP_BIT);
1511
1512 return 4;
1513 }
1514
1515 /* clr1 */
1516 int
1517 OP_87C0 (void)
1518 {
1519 unsigned int op0, op1, op2;
1520 int temp;
1521
1522 trace_input ("clr1", OP_BIT, 0);
1523 op0 = State.regs[ OP[0] ];
1524 op1 = OP[1] & 0x7;
1525 temp = EXTEND16 (OP[2]);
1526 op2 = temp;
1527 temp = load_mem (op0 + op2, 1);
1528 PSW &= ~PSW_Z;
1529 if ((temp & (1 << op1)) == 0)
1530 PSW |= PSW_Z;
1531 temp &= ~(1 << op1);
1532 store_mem (op0 + op2, 1, temp);
1533 trace_output (OP_BIT);
1534
1535 return 4;
1536 }
1537
1538 /* tst1 */
1539 int
1540 OP_C7C0 (void)
1541 {
1542 unsigned int op0, op1, op2;
1543 int temp;
1544
1545 trace_input ("tst1", OP_BIT, 0);
1546 op0 = State.regs[ OP[0] ];
1547 op1 = OP[1] & 0x7;
1548 temp = EXTEND16 (OP[2]);
1549 op2 = temp;
1550 temp = load_mem (op0 + op2, 1);
1551 PSW &= ~PSW_Z;
1552 if ((temp & (1 << op1)) == 0)
1553 PSW |= PSW_Z;
1554 trace_output (OP_BIT);
1555
1556 return 4;
1557 }
1558
1559 /* di */
1560 int
1561 OP_16007E0 (void)
1562 {
1563 trace_input ("di", OP_NONE, 0);
1564 PSW |= PSW_ID;
1565 trace_output (OP_NONE);
1566
1567 return 4;
1568 }
1569
1570 /* ei */
1571 int
1572 OP_16087E0 (void)
1573 {
1574 trace_input ("ei", OP_NONE, 0);
1575 PSW &= ~PSW_ID;
1576 trace_output (OP_NONE);
1577
1578 return 4;
1579 }
1580
1581 /* halt */
1582 int
1583 OP_12007E0 (void)
1584 {
1585 trace_input ("halt", OP_NONE, 0);
1586 /* FIXME this should put processor into a mode where NMI still handled */
1587 trace_output (OP_NONE);
1588 sim_engine_halt (simulator, STATE_CPU (simulator, 0), NULL, PC,
1589 sim_stopped, SIM_SIGTRAP);
1590 return 0;
1591 }
1592
1593 /* trap */
1594 int
1595 OP_10007E0 (void)
1596 {
1597 trace_input ("trap", OP_TRAP, 0);
1598 trace_output (OP_TRAP);
1599
1600 /* Trap 31 is used for simulating OS I/O functions */
1601
1602 if (OP[0] == 31)
1603 {
1604 int save_errno = errno;
1605 errno = 0;
1606
1607 /* Registers passed to trap 0 */
1608
1609 #define FUNC State.regs[6] /* function number, return value */
1610 #define PARM1 State.regs[7] /* optional parm 1 */
1611 #define PARM2 State.regs[8] /* optional parm 2 */
1612 #define PARM3 State.regs[9] /* optional parm 3 */
1613
1614 /* Registers set by trap 0 */
1615
1616 #define RETVAL State.regs[10] /* return value */
1617 #define RETERR State.regs[11] /* return error code */
1618
1619 /* Turn a pointer in a register into a pointer into real memory. */
1620
1621 #define MEMPTR(x) (map (x))
1622
1623 RETERR = 0;
1624
1625 switch (FUNC)
1626 {
1627
1628 #ifdef HAVE_FORK
1629 #ifdef TARGET_SYS_fork
1630 case TARGET_SYS_fork:
1631 RETVAL = fork ();
1632 RETERR = errno;
1633 break;
1634 #endif
1635 #endif
1636
1637 #ifdef HAVE_EXECVE
1638 #ifdef TARGET_SYS_execv
1639 case TARGET_SYS_execve:
1640 {
1641 char *path = fetch_str (simulator, PARM1);
1642 char **argv = fetch_argv (simulator, PARM2);
1643 char **envp = fetch_argv (simulator, PARM3);
1644 RETVAL = execve (path, (void *)argv, (void *)envp);
1645 free (path);
1646 freeargv (argv);
1647 freeargv (envp);
1648 RETERR = errno;
1649 break;
1650 }
1651 #endif
1652 #endif
1653
1654 #if HAVE_EXECV
1655 #ifdef TARGET_SYS_execv
1656 case TARGET_SYS_execv:
1657 {
1658 char *path = fetch_str (simulator, PARM1);
1659 char **argv = fetch_argv (simulator, PARM2);
1660 RETVAL = execv (path, (void *)argv);
1661 free (path);
1662 freeargv (argv);
1663 RETERR = errno;
1664 break;
1665 }
1666 #endif
1667 #endif
1668
1669 #if 0
1670 #ifdef TARGET_SYS_pipe
1671 case TARGET_SYS_pipe:
1672 {
1673 reg_t buf;
1674 int host_fd[2];
1675
1676 buf = PARM1;
1677 RETVAL = pipe (host_fd);
1678 SW (buf, host_fd[0]);
1679 buf += sizeof (uint16);
1680 SW (buf, host_fd[1]);
1681 RETERR = errno;
1682 }
1683 break;
1684 #endif
1685 #endif
1686
1687 #if 0
1688 #ifdef TARGET_SYS_wait
1689 case TARGET_SYS_wait:
1690 {
1691 int status;
1692
1693 RETVAL = wait (&status);
1694 SW (PARM1, status);
1695 RETERR = errno;
1696 }
1697 break;
1698 #endif
1699 #endif
1700
1701 #ifdef TARGET_SYS_read
1702 case TARGET_SYS_read:
1703 {
1704 char *buf = zalloc (PARM3);
1705 RETVAL = sim_io_read (simulator, PARM1, buf, PARM3);
1706 sim_write (simulator, PARM2, (unsigned char *) buf, PARM3);
1707 free (buf);
1708 if ((int) RETVAL < 0)
1709 RETERR = sim_io_get_errno (simulator);
1710 break;
1711 }
1712 #endif
1713
1714 #ifdef TARGET_SYS_write
1715 case TARGET_SYS_write:
1716 {
1717 char *buf = zalloc (PARM3);
1718 sim_read (simulator, PARM2, (unsigned char *) buf, PARM3);
1719 if (PARM1 == 1)
1720 RETVAL = sim_io_write_stdout (simulator, buf, PARM3);
1721 else
1722 RETVAL = sim_io_write (simulator, PARM1, buf, PARM3);
1723 free (buf);
1724 if ((int) RETVAL < 0)
1725 RETERR = sim_io_get_errno (simulator);
1726 break;
1727 }
1728 #endif
1729
1730 #ifdef TARGET_SYS_lseek
1731 case TARGET_SYS_lseek:
1732 RETVAL = sim_io_lseek (simulator, PARM1, PARM2, PARM3);
1733 if ((int) RETVAL < 0)
1734 RETERR = sim_io_get_errno (simulator);
1735 break;
1736 #endif
1737
1738 #ifdef TARGET_SYS_close
1739 case TARGET_SYS_close:
1740 RETVAL = sim_io_close (simulator, PARM1);
1741 if ((int) RETVAL < 0)
1742 RETERR = sim_io_get_errno (simulator);
1743 break;
1744 #endif
1745
1746 #ifdef TARGET_SYS_open
1747 case TARGET_SYS_open:
1748 {
1749 char *buf = fetch_str (simulator, PARM1);
1750 RETVAL = sim_io_open (simulator, buf, PARM2);
1751 free (buf);
1752 if ((int) RETVAL < 0)
1753 RETERR = sim_io_get_errno (simulator);
1754 break;
1755 }
1756 #endif
1757
1758 #ifdef TARGET_SYS_exit
1759 case TARGET_SYS_exit:
1760 if ((PARM1 & 0xffff0000) == 0xdead0000 && (PARM1 & 0xffff) != 0)
1761 /* get signal encoded by kill */
1762 sim_engine_halt (simulator, STATE_CPU (simulator, 0), NULL, PC,
1763 sim_signalled, PARM1 & 0xffff);
1764 else if (PARM1 == 0xdead)
1765 /* old libraries */
1766 sim_engine_halt (simulator, STATE_CPU (simulator, 0), NULL, PC,
1767 sim_stopped, SIM_SIGABRT);
1768 else
1769 /* PARM1 has exit status */
1770 sim_engine_halt (simulator, STATE_CPU (simulator, 0), NULL, PC,
1771 sim_exited, PARM1);
1772 break;
1773 #endif
1774
1775 #ifdef TARGET_SYS_stat
1776 case TARGET_SYS_stat: /* added at hmsi */
1777 /* stat system call */
1778 {
1779 struct stat host_stat;
1780 reg_t buf;
1781 char *path = fetch_str (simulator, PARM1);
1782
1783 RETVAL = sim_io_stat (simulator, path, &host_stat);
1784
1785 free (path);
1786 buf = PARM2;
1787
1788 /* Just wild-assed guesses. */
1789 store_mem (buf, 2, host_stat.st_dev);
1790 store_mem (buf + 2, 2, host_stat.st_ino);
1791 store_mem (buf + 4, 4, host_stat.st_mode);
1792 store_mem (buf + 8, 2, host_stat.st_nlink);
1793 store_mem (buf + 10, 2, host_stat.st_uid);
1794 store_mem (buf + 12, 2, host_stat.st_gid);
1795 store_mem (buf + 14, 2, host_stat.st_rdev);
1796 store_mem (buf + 16, 4, host_stat.st_size);
1797 store_mem (buf + 20, 4, host_stat.st_atime);
1798 store_mem (buf + 28, 4, host_stat.st_mtime);
1799 store_mem (buf + 36, 4, host_stat.st_ctime);
1800
1801 if ((int) RETVAL < 0)
1802 RETERR = sim_io_get_errno (simulator);
1803 }
1804 break;
1805 #endif
1806
1807 #ifdef TARGET_SYS_fstat
1808 case TARGET_SYS_fstat:
1809 /* fstat system call */
1810 {
1811 struct stat host_stat;
1812 reg_t buf;
1813
1814 RETVAL = sim_io_fstat (simulator, PARM1, &host_stat);
1815
1816 buf = PARM2;
1817
1818 /* Just wild-assed guesses. */
1819 store_mem (buf, 2, host_stat.st_dev);
1820 store_mem (buf + 2, 2, host_stat.st_ino);
1821 store_mem (buf + 4, 4, host_stat.st_mode);
1822 store_mem (buf + 8, 2, host_stat.st_nlink);
1823 store_mem (buf + 10, 2, host_stat.st_uid);
1824 store_mem (buf + 12, 2, host_stat.st_gid);
1825 store_mem (buf + 14, 2, host_stat.st_rdev);
1826 store_mem (buf + 16, 4, host_stat.st_size);
1827 store_mem (buf + 20, 4, host_stat.st_atime);
1828 store_mem (buf + 28, 4, host_stat.st_mtime);
1829 store_mem (buf + 36, 4, host_stat.st_ctime);
1830
1831 if ((int) RETVAL < 0)
1832 RETERR = sim_io_get_errno (simulator);
1833 }
1834 break;
1835 #endif
1836
1837 #ifdef TARGET_SYS_rename
1838 case TARGET_SYS_rename:
1839 {
1840 char *oldpath = fetch_str (simulator, PARM1);
1841 char *newpath = fetch_str (simulator, PARM2);
1842 RETVAL = sim_io_rename (simulator, oldpath, newpath);
1843 free (oldpath);
1844 free (newpath);
1845 if ((int) RETVAL < 0)
1846 RETERR = sim_io_get_errno (simulator);
1847 }
1848 break;
1849 #endif
1850
1851 #ifdef TARGET_SYS_unlink
1852 case TARGET_SYS_unlink:
1853 {
1854 char *path = fetch_str (simulator, PARM1);
1855 RETVAL = sim_io_unlink (simulator, path);
1856 free (path);
1857 if ((int) RETVAL < 0)
1858 RETERR = sim_io_get_errno (simulator);
1859 }
1860 break;
1861 #endif
1862
1863 #ifdef TARGET_SYS_chown
1864 case TARGET_SYS_chown:
1865 {
1866 char *path = fetch_str (simulator, PARM1);
1867 RETVAL = chown (path, PARM2, PARM3);
1868 free (path);
1869 RETERR = errno;
1870 }
1871 break;
1872 #endif
1873
1874 #if HAVE_CHMOD
1875 #ifdef TARGET_SYS_chmod
1876 case TARGET_SYS_chmod:
1877 {
1878 char *path = fetch_str (simulator, PARM1);
1879 RETVAL = chmod (path, PARM2);
1880 free (path);
1881 RETERR = errno;
1882 }
1883 break;
1884 #endif
1885 #endif
1886
1887 #ifdef TARGET_SYS_time
1888 #if HAVE_TIME
1889 case TARGET_SYS_time:
1890 {
1891 time_t now;
1892 RETVAL = time (&now);
1893 store_mem (PARM1, 4, now);
1894 RETERR = errno;
1895 }
1896 break;
1897 #endif
1898 #endif
1899
1900 #if !defined(__GO32__) && !defined(_WIN32)
1901 #ifdef TARGET_SYS_times
1902 case TARGET_SYS_times:
1903 {
1904 struct tms tms;
1905 RETVAL = times (&tms);
1906 store_mem (PARM1, 4, tms.tms_utime);
1907 store_mem (PARM1 + 4, 4, tms.tms_stime);
1908 store_mem (PARM1 + 8, 4, tms.tms_cutime);
1909 store_mem (PARM1 + 12, 4, tms.tms_cstime);
1910 RETERR = errno;
1911 break;
1912 }
1913 #endif
1914 #endif
1915
1916 #ifdef TARGET_SYS_gettimeofday
1917 #if !defined(__GO32__) && !defined(_WIN32)
1918 case TARGET_SYS_gettimeofday:
1919 {
1920 struct timeval t;
1921 struct timezone tz;
1922 RETVAL = gettimeofday (&t, &tz);
1923 store_mem (PARM1, 4, t.tv_sec);
1924 store_mem (PARM1 + 4, 4, t.tv_usec);
1925 store_mem (PARM2, 4, tz.tz_minuteswest);
1926 store_mem (PARM2 + 4, 4, tz.tz_dsttime);
1927 RETERR = errno;
1928 break;
1929 }
1930 #endif
1931 #endif
1932
1933 #ifdef TARGET_SYS_utime
1934 #if HAVE_UTIME
1935 case TARGET_SYS_utime:
1936 {
1937 /* Cast the second argument to void *, to avoid type mismatch
1938 if a prototype is present. */
1939 sim_io_error (simulator, "Utime not supported");
1940 /* RETVAL = utime (path, (void *) MEMPTR (PARM2)); */
1941 }
1942 break;
1943 #endif
1944 #endif
1945
1946 default:
1947 abort ();
1948 }
1949 errno = save_errno;
1950
1951 return 4;
1952 }
1953 else
1954 { /* Trap 0 -> 30 */
1955 EIPC = PC + 4;
1956 EIPSW = PSW;
1957 /* Mask out EICC */
1958 ECR &= 0xffff0000;
1959 ECR |= 0x40 + OP[0];
1960 /* Flag that we are now doing exception processing. */
1961 PSW |= PSW_EP | PSW_ID;
1962 PC = (OP[0] < 0x10) ? 0x40 : 0x50;
1963
1964 return 0;
1965 }
1966 }
1967
1968 /* tst1 reg2, [reg1] */
1969 int
1970 OP_E607E0 (void)
1971 {
1972 int temp;
1973
1974 trace_input ("tst1", OP_BIT, 1);
1975
1976 temp = load_mem (State.regs[ OP[0] ], 1);
1977
1978 PSW &= ~PSW_Z;
1979 if ((temp & (1 << (State.regs[ OP[1] ] & 0x7))) == 0)
1980 PSW |= PSW_Z;
1981
1982 trace_output (OP_BIT);
1983
1984 return 4;
1985 }
1986
1987 /* mulu reg1, reg2, reg3 */
1988 int
1989 OP_22207E0 (void)
1990 {
1991 trace_input ("mulu", OP_REG_REG_REG, 0);
1992
1993 Multiply64 (0, State.regs[ OP[0] ]);
1994
1995 trace_output (OP_REG_REG_REG);
1996
1997 return 4;
1998 }
1999
2000 #define BIT_CHANGE_OP( name, binop ) \
2001 unsigned int bit; \
2002 unsigned int temp; \
2003 \
2004 trace_input (name, OP_BIT_CHANGE, 0); \
2005 \
2006 bit = 1 << (State.regs[ OP[1] ] & 0x7); \
2007 temp = load_mem (State.regs[ OP[0] ], 1); \
2008 \
2009 PSW &= ~PSW_Z; \
2010 if ((temp & bit) == 0) \
2011 PSW |= PSW_Z; \
2012 temp binop bit; \
2013 \
2014 store_mem (State.regs[ OP[0] ], 1, temp); \
2015 \
2016 trace_output (OP_BIT_CHANGE); \
2017 \
2018 return 4;
2019
2020 /* clr1 reg2, [reg1] */
2021 int
2022 OP_E407E0 (void)
2023 {
2024 BIT_CHANGE_OP ("clr1", &= ~ );
2025 }
2026
2027 /* not1 reg2, [reg1] */
2028 int
2029 OP_E207E0 (void)
2030 {
2031 BIT_CHANGE_OP ("not1", ^= );
2032 }
2033
2034 /* set1 */
2035 int
2036 OP_E007E0 (void)
2037 {
2038 BIT_CHANGE_OP ("set1", |= );
2039 }
2040
2041 /* sasf */
2042 int
2043 OP_20007E0 (void)
2044 {
2045 trace_input ("sasf", OP_EX1, 0);
2046
2047 State.regs[ OP[1] ] = (State.regs[ OP[1] ] << 1) | condition_met (OP[0]);
2048
2049 trace_output (OP_EX1);
2050
2051 return 4;
2052 }
2053
2054 /* This function is courtesy of Sugimoto at NEC, via Seow Tan
2055 (Soew_Tan@el.nec.com) */
2056 void
2057 divun
2058 (
2059 unsigned int N,
2060 unsigned long int als,
2061 unsigned long int sfi,
2062 unsigned32 /*unsigned long int*/ * quotient_ptr,
2063 unsigned32 /*unsigned long int*/ * remainder_ptr,
2064 int * overflow_ptr
2065 )
2066 {
2067 unsigned long ald = sfi >> (N - 1);
2068 unsigned long alo = als;
2069 unsigned int Q = 1;
2070 unsigned int C;
2071 unsigned int S = 0;
2072 unsigned int i;
2073 unsigned int R1 = 1;
2074 unsigned int DBZ = (als == 0) ? 1 : 0;
2075 unsigned long alt = Q ? ~als : als;
2076
2077 /* 1st Loop */
2078 alo = ald + alt + Q;
2079 C = (((alt >> 31) & (ald >> 31))
2080 | (((alt >> 31) ^ (ald >> 31)) & (~alo >> 31)));
2081 C = C ^ Q;
2082 Q = ~(C ^ S) & 1;
2083 R1 = (alo == 0) ? 0 : (R1 & Q);
2084 if ((S ^ (alo>>31)) && !C)
2085 {
2086 DBZ = 1;
2087 }
2088 S = alo >> 31;
2089 sfi = (sfi << (32-N+1)) | Q;
2090 ald = (alo << 1) | (sfi >> 31);
2091
2092 /* 2nd - N-1th Loop */
2093 for (i = 2; i < N; i++)
2094 {
2095 alt = Q ? ~als : als;
2096 alo = ald + alt + Q;
2097 C = (((alt >> 31) & (ald >> 31))
2098 | (((alt >> 31) ^ (ald >> 31)) & (~alo >> 31)));
2099 C = C ^ Q;
2100 Q = ~(C ^ S) & 1;
2101 R1 = (alo == 0) ? 0 : (R1 & Q);
2102 if ((S ^ (alo>>31)) && !C && !DBZ)
2103 {
2104 DBZ = 1;
2105 }
2106 S = alo >> 31;
2107 sfi = (sfi << 1) | Q;
2108 ald = (alo << 1) | (sfi >> 31);
2109 }
2110
2111 /* Nth Loop */
2112 alt = Q ? ~als : als;
2113 alo = ald + alt + Q;
2114 C = (((alt >> 31) & (ald >> 31))
2115 | (((alt >> 31) ^ (ald >> 31)) & (~alo >> 31)));
2116 C = C ^ Q;
2117 Q = ~(C ^ S) & 1;
2118 R1 = (alo == 0) ? 0 : (R1 & Q);
2119 if ((S ^ (alo>>31)) && !C)
2120 {
2121 DBZ = 1;
2122 }
2123
2124 * quotient_ptr = (sfi << 1) | Q;
2125 * remainder_ptr = Q ? alo : (alo + als);
2126 * overflow_ptr = DBZ | R1;
2127 }
2128
2129 /* This function is courtesy of Sugimoto at NEC, via Seow Tan (Soew_Tan@el.nec.com) */
2130 void
2131 divn
2132 (
2133 unsigned int N,
2134 unsigned long int als,
2135 unsigned long int sfi,
2136 signed32 /*signed long int*/ * quotient_ptr,
2137 signed32 /*signed long int*/ * remainder_ptr,
2138 int * overflow_ptr
2139 )
2140 {
2141 unsigned long ald = (signed long) sfi >> (N - 1);
2142 unsigned long alo = als;
2143 unsigned int SS = als >> 31;
2144 unsigned int SD = sfi >> 31;
2145 unsigned int R1 = 1;
2146 unsigned int OV;
2147 unsigned int DBZ = als == 0 ? 1 : 0;
2148 unsigned int Q = ~(SS ^ SD) & 1;
2149 unsigned int C;
2150 unsigned int S;
2151 unsigned int i;
2152 unsigned long alt = Q ? ~als : als;
2153
2154
2155 /* 1st Loop */
2156
2157 alo = ald + alt + Q;
2158 C = (((alt >> 31) & (ald >> 31))
2159 | (((alt >> 31) ^ (ald >> 31)) & (~alo >> 31)));
2160 Q = C ^ SS;
2161 R1 = (alo == 0) ? 0 : (R1 & (Q ^ (SS ^ SD)));
2162 S = alo >> 31;
2163 sfi = (sfi << (32-N+1)) | Q;
2164 ald = (alo << 1) | (sfi >> 31);
2165 if ((alo >> 31) ^ (ald >> 31))
2166 {
2167 DBZ = 1;
2168 }
2169
2170 /* 2nd - N-1th Loop */
2171
2172 for (i = 2; i < N; i++)
2173 {
2174 alt = Q ? ~als : als;
2175 alo = ald + alt + Q;
2176 C = (((alt >> 31) & (ald >> 31))
2177 | (((alt >> 31) ^ (ald >> 31)) & (~alo >> 31)));
2178 Q = C ^ SS;
2179 R1 = (alo == 0) ? 0 : (R1 & (Q ^ (SS ^ SD)));
2180 S = alo >> 31;
2181 sfi = (sfi << 1) | Q;
2182 ald = (alo << 1) | (sfi >> 31);
2183 if ((alo >> 31) ^ (ald >> 31))
2184 {
2185 DBZ = 1;
2186 }
2187 }
2188
2189 /* Nth Loop */
2190 alt = Q ? ~als : als;
2191 alo = ald + alt + Q;
2192 C = (((alt >> 31) & (ald >> 31))
2193 | (((alt >> 31) ^ (ald >> 31)) & (~alo >> 31)));
2194 Q = C ^ SS;
2195 R1 = (alo == 0) ? 0 : (R1 & (Q ^ (SS ^ SD)));
2196 sfi = (sfi << (32-N+1));
2197 ald = alo;
2198
2199 /* End */
2200 if (alo != 0)
2201 {
2202 alt = Q ? ~als : als;
2203 alo = ald + alt + Q;
2204 }
2205 R1 = R1 & ((~alo >> 31) ^ SD);
2206 if ((alo != 0) && ((Q ^ (SS ^ SD)) ^ R1)) alo = ald;
2207 if (N != 32)
2208 ald = sfi = (long) ((sfi >> 1) | (SS ^ SD) << 31) >> (32-N-1) | Q;
2209 else
2210 ald = sfi = sfi | Q;
2211
2212 OV = DBZ | ((alo == 0) ? 0 : R1);
2213
2214 * remainder_ptr = alo;
2215
2216 /* Adj */
2217 if (((alo != 0) && ((SS ^ SD) ^ R1))
2218 || ((alo == 0) && (SS ^ R1)))
2219 alo = ald + 1;
2220 else
2221 alo = ald;
2222
2223 OV = (DBZ | R1) ? OV : ((alo >> 31) & (~ald >> 31));
2224
2225 * quotient_ptr = alo;
2226 * overflow_ptr = OV;
2227 }
2228
2229 /* sdivun imm5, reg1, reg2, reg3 */
2230 int
2231 OP_1C207E0 (void)
2232 {
2233 unsigned32 /*unsigned long int*/ quotient;
2234 unsigned32 /*unsigned long int*/ remainder;
2235 unsigned long int divide_by;
2236 unsigned long int divide_this;
2237 int overflow = 0;
2238 unsigned int imm5;
2239
2240 trace_input ("sdivun", OP_IMM_REG_REG_REG, 0);
2241
2242 imm5 = 32 - ((OP[3] & 0x3c0000) >> 17);
2243
2244 divide_by = State.regs[ OP[0] ];
2245 divide_this = State.regs[ OP[1] ] << imm5;
2246
2247 divun (imm5, divide_by, divide_this, & quotient, & remainder, & overflow);
2248
2249 State.regs[ OP[1] ] = quotient;
2250 State.regs[ OP[2] >> 11 ] = remainder;
2251
2252 /* Set condition codes. */
2253 PSW &= ~(PSW_Z | PSW_S | PSW_OV);
2254
2255 if (overflow) PSW |= PSW_OV;
2256 if (quotient == 0) PSW |= PSW_Z;
2257 if (quotient & 0x80000000) PSW |= PSW_S;
2258
2259 trace_output (OP_IMM_REG_REG_REG);
2260
2261 return 4;
2262 }
2263
2264 /* sdivn imm5, reg1, reg2, reg3 */
2265 int
2266 OP_1C007E0 (void)
2267 {
2268 signed32 /*signed long int*/ quotient;
2269 signed32 /*signed long int*/ remainder;
2270 signed long int divide_by;
2271 signed long int divide_this;
2272 int overflow = 0;
2273 unsigned int imm5;
2274
2275 trace_input ("sdivn", OP_IMM_REG_REG_REG, 0);
2276
2277 imm5 = 32 - ((OP[3] & 0x3c0000) >> 17);
2278
2279 divide_by = (signed32) State.regs[ OP[0] ];
2280 divide_this = (signed32) (State.regs[ OP[1] ] << imm5);
2281
2282 divn (imm5, divide_by, divide_this, & quotient, & remainder, & overflow);
2283
2284 State.regs[ OP[1] ] = quotient;
2285 State.regs[ OP[2] >> 11 ] = remainder;
2286
2287 /* Set condition codes. */
2288 PSW &= ~(PSW_Z | PSW_S | PSW_OV);
2289
2290 if (overflow) PSW |= PSW_OV;
2291 if (quotient == 0) PSW |= PSW_Z;
2292 if (quotient < 0) PSW |= PSW_S;
2293
2294 trace_output (OP_IMM_REG_REG_REG);
2295
2296 return 4;
2297 }
2298
2299 /* sdivhun imm5, reg1, reg2, reg3 */
2300 int
2301 OP_18207E0 (void)
2302 {
2303 unsigned32 /*unsigned long int*/ quotient;
2304 unsigned32 /*unsigned long int*/ remainder;
2305 unsigned long int divide_by;
2306 unsigned long int divide_this;
2307 int overflow = 0;
2308 unsigned int imm5;
2309
2310 trace_input ("sdivhun", OP_IMM_REG_REG_REG, 0);
2311
2312 imm5 = 32 - ((OP[3] & 0x3c0000) >> 17);
2313
2314 divide_by = State.regs[ OP[0] ] & 0xffff;
2315 divide_this = State.regs[ OP[1] ] << imm5;
2316
2317 divun (imm5, divide_by, divide_this, & quotient, & remainder, & overflow);
2318
2319 State.regs[ OP[1] ] = quotient;
2320 State.regs[ OP[2] >> 11 ] = remainder;
2321
2322 /* Set condition codes. */
2323 PSW &= ~(PSW_Z | PSW_S | PSW_OV);
2324
2325 if (overflow) PSW |= PSW_OV;
2326 if (quotient == 0) PSW |= PSW_Z;
2327 if (quotient & 0x80000000) PSW |= PSW_S;
2328
2329 trace_output (OP_IMM_REG_REG_REG);
2330
2331 return 4;
2332 }
2333
2334 /* sdivhn imm5, reg1, reg2, reg3 */
2335 int
2336 OP_18007E0 (void)
2337 {
2338 signed32 /*signed long int*/ quotient;
2339 signed32 /*signed long int*/ remainder;
2340 signed long int divide_by;
2341 signed long int divide_this;
2342 int overflow = 0;
2343 unsigned int imm5;
2344
2345 trace_input ("sdivhn", OP_IMM_REG_REG_REG, 0);
2346
2347 imm5 = 32 - ((OP[3] & 0x3c0000) >> 17);
2348
2349 divide_by = EXTEND16 (State.regs[ OP[0] ]);
2350 divide_this = (signed32) (State.regs[ OP[1] ] << imm5);
2351
2352 divn (imm5, divide_by, divide_this, & quotient, & remainder, & overflow);
2353
2354 State.regs[ OP[1] ] = quotient;
2355 State.regs[ OP[2] >> 11 ] = remainder;
2356
2357 /* Set condition codes. */
2358 PSW &= ~(PSW_Z | PSW_S | PSW_OV);
2359
2360 if (overflow) PSW |= PSW_OV;
2361 if (quotient == 0) PSW |= PSW_Z;
2362 if (quotient < 0) PSW |= PSW_S;
2363
2364 trace_output (OP_IMM_REG_REG_REG);
2365
2366 return 4;
2367 }
2368
2369 /* divu reg1, reg2, reg3 */
2370 int
2371 OP_2C207E0 (void)
2372 {
2373 unsigned long int quotient;
2374 unsigned long int remainder;
2375 unsigned long int divide_by;
2376 unsigned long int divide_this;
2377 int overflow = 0;
2378
2379 trace_input ("divu", OP_REG_REG_REG, 0);
2380
2381 /* Compute the result. */
2382
2383 divide_by = State.regs[ OP[0] ];
2384 divide_this = State.regs[ OP[1] ];
2385
2386 if (divide_by == 0)
2387 {
2388 PSW |= PSW_OV;
2389 }
2390 else
2391 {
2392 State.regs[ OP[1] ] = quotient = divide_this / divide_by;
2393 State.regs[ OP[2] >> 11 ] = remainder = divide_this % divide_by;
2394
2395 /* Set condition codes. */
2396 PSW &= ~(PSW_Z | PSW_S | PSW_OV);
2397
2398 if (overflow) PSW |= PSW_OV;
2399 if (quotient == 0) PSW |= PSW_Z;
2400 if (quotient & 0x80000000) PSW |= PSW_S;
2401 }
2402
2403 trace_output (OP_REG_REG_REG);
2404
2405 return 4;
2406 }
2407
2408 /* div reg1, reg2, reg3 */
2409 int
2410 OP_2C007E0 (void)
2411 {
2412 signed long int quotient;
2413 signed long int remainder;
2414 signed long int divide_by;
2415 signed long int divide_this;
2416
2417 trace_input ("div", OP_REG_REG_REG, 0);
2418
2419 /* Compute the result. */
2420
2421 divide_by = (signed32) State.regs[ OP[0] ];
2422 divide_this = State.regs[ OP[1] ];
2423
2424 if (divide_by == 0)
2425 {
2426 PSW |= PSW_OV;
2427 }
2428 else if (divide_by == -1 && divide_this == (1L << 31))
2429 {
2430 PSW &= ~PSW_Z;
2431 PSW |= PSW_OV | PSW_S;
2432 State.regs[ OP[1] ] = (1 << 31);
2433 State.regs[ OP[2] >> 11 ] = 0;
2434 }
2435 else
2436 {
2437 divide_this = (signed32) divide_this;
2438 State.regs[ OP[1] ] = quotient = divide_this / divide_by;
2439 State.regs[ OP[2] >> 11 ] = remainder = divide_this % divide_by;
2440
2441 /* Set condition codes. */
2442 PSW &= ~(PSW_Z | PSW_S | PSW_OV);
2443
2444 if (quotient == 0) PSW |= PSW_Z;
2445 if (quotient < 0) PSW |= PSW_S;
2446 }
2447
2448 trace_output (OP_REG_REG_REG);
2449
2450 return 4;
2451 }
2452
2453 /* divhu reg1, reg2, reg3 */
2454 int
2455 OP_28207E0 (void)
2456 {
2457 unsigned long int quotient;
2458 unsigned long int remainder;
2459 unsigned long int divide_by;
2460 unsigned long int divide_this;
2461 int overflow = 0;
2462
2463 trace_input ("divhu", OP_REG_REG_REG, 0);
2464
2465 /* Compute the result. */
2466
2467 divide_by = State.regs[ OP[0] ] & 0xffff;
2468 divide_this = State.regs[ OP[1] ];
2469
2470 if (divide_by == 0)
2471 {
2472 PSW |= PSW_OV;
2473 }
2474 else
2475 {
2476 State.regs[ OP[1] ] = quotient = divide_this / divide_by;
2477 State.regs[ OP[2] >> 11 ] = remainder = divide_this % divide_by;
2478
2479 /* Set condition codes. */
2480 PSW &= ~(PSW_Z | PSW_S | PSW_OV);
2481
2482 if (overflow) PSW |= PSW_OV;
2483 if (quotient == 0) PSW |= PSW_Z;
2484 if (quotient & 0x80000000) PSW |= PSW_S;
2485 }
2486
2487 trace_output (OP_REG_REG_REG);
2488
2489 return 4;
2490 }
2491
2492 /* divh reg1, reg2, reg3 */
2493 int
2494 OP_28007E0 (void)
2495 {
2496 signed long int quotient;
2497 signed long int remainder;
2498 signed long int divide_by;
2499 signed long int divide_this;
2500 int overflow = 0;
2501
2502 trace_input ("divh", OP_REG_REG_REG, 0);
2503
2504 /* Compute the result. */
2505
2506 divide_by = EXTEND16 (State.regs[ OP[0] ]);
2507 divide_this = State.regs[ OP[1] ];
2508
2509 if (divide_by == 0)
2510 {
2511 PSW |= PSW_OV;
2512 }
2513 else if (divide_by == -1 && divide_this == (1L << 31))
2514 {
2515 PSW &= ~PSW_Z;
2516 PSW |= PSW_OV | PSW_S;
2517 State.regs[ OP[1] ] = (1 << 31);
2518 State.regs[ OP[2] >> 11 ] = 0;
2519 }
2520 else
2521 {
2522 divide_this = (signed32) divide_this;
2523 State.regs[ OP[1] ] = quotient = divide_this / divide_by;
2524 State.regs[ OP[2] >> 11 ] = remainder = divide_this % divide_by;
2525
2526 /* Set condition codes. */
2527 PSW &= ~(PSW_Z | PSW_S | PSW_OV);
2528
2529 if (quotient == 0) PSW |= PSW_Z;
2530 if (quotient < 0) PSW |= PSW_S;
2531 }
2532
2533 trace_output (OP_REG_REG_REG);
2534
2535 return 4;
2536 }
2537
2538 /* mulu imm9, reg2, reg3 */
2539 int
2540 OP_24207E0 (void)
2541 {
2542 trace_input ("mulu", OP_IMM_REG_REG, 0);
2543
2544 Multiply64 (0, (OP[3] & 0x1f) | ((OP[3] >> 13) & 0x1e0));
2545
2546 trace_output (OP_IMM_REG_REG);
2547
2548 return 4;
2549 }
2550
2551 /* mul imm9, reg2, reg3 */
2552 int
2553 OP_24007E0 (void)
2554 {
2555 trace_input ("mul", OP_IMM_REG_REG, 0);
2556
2557 Multiply64 (1, SEXT9 ((OP[3] & 0x1f) | ((OP[3] >> 13) & 0x1e0)));
2558
2559 trace_output (OP_IMM_REG_REG);
2560
2561 return 4;
2562 }
2563
2564 /* ld.hu */
2565 int
2566 OP_107E0 (void)
2567 {
2568 int adr;
2569
2570 trace_input ("ld.hu", OP_LOAD32, 2);
2571
2572 adr = State.regs[ OP[0] ] + EXTEND16 (OP[2] & ~1);
2573 adr &= ~0x1;
2574
2575 State.regs[ OP[1] ] = load_mem (adr, 2);
2576
2577 trace_output (OP_LOAD32);
2578
2579 return 4;
2580 }
2581
2582
2583 /* ld.bu */
2584 int
2585 OP_10780 (void)
2586 {
2587 int adr;
2588
2589 trace_input ("ld.bu", OP_LOAD32, 1);
2590
2591 adr = (State.regs[ OP[0] ]
2592 + (EXTEND16 (OP[2] & ~1) | ((OP[3] >> 5) & 1)));
2593
2594 State.regs[ OP[1] ] = load_mem (adr, 1);
2595
2596 trace_output (OP_LOAD32);
2597
2598 return 4;
2599 }
2600
2601 /* prepare list12, imm5, imm32 */
2602 int
2603 OP_1B0780 (void)
2604 {
2605 int i;
2606
2607 trace_input ("prepare", OP_PUSHPOP1, 0);
2608
2609 /* Store the registers with lower number registers being placed at higher addresses. */
2610 for (i = 0; i < 12; i++)
2611 if ((OP[3] & (1 << type1_regs[ i ])))
2612 {
2613 SP -= 4;
2614 store_mem (SP, 4, State.regs[ 20 + i ]);
2615 }
2616
2617 SP -= (OP[3] & 0x3e) << 1;
2618
2619 EP = load_mem (PC + 4, 4);
2620
2621 trace_output (OP_PUSHPOP1);
2622
2623 return 8;
2624 }
2625
2626 /* prepare list12, imm5, imm16-32 */
2627 int
2628 OP_130780 (void)
2629 {
2630 int i;
2631
2632 trace_input ("prepare", OP_PUSHPOP1, 0);
2633
2634 /* Store the registers with lower number registers being placed at higher addresses. */
2635 for (i = 0; i < 12; i++)
2636 if ((OP[3] & (1 << type1_regs[ i ])))
2637 {
2638 SP -= 4;
2639 store_mem (SP, 4, State.regs[ 20 + i ]);
2640 }
2641
2642 SP -= (OP[3] & 0x3e) << 1;
2643
2644 EP = load_mem (PC + 4, 2) << 16;
2645
2646 trace_output (OP_PUSHPOP1);
2647
2648 return 6;
2649 }
2650
2651 /* prepare list12, imm5, imm16 */
2652 int
2653 OP_B0780 (void)
2654 {
2655 int i;
2656
2657 trace_input ("prepare", OP_PUSHPOP1, 0);
2658
2659 /* Store the registers with lower number registers being placed at higher addresses. */
2660 for (i = 0; i < 12; i++)
2661 if ((OP[3] & (1 << type1_regs[ i ])))
2662 {
2663 SP -= 4;
2664 store_mem (SP, 4, State.regs[ 20 + i ]);
2665 }
2666
2667 SP -= (OP[3] & 0x3e) << 1;
2668
2669 EP = EXTEND16 (load_mem (PC + 4, 2));
2670
2671 trace_output (OP_PUSHPOP1);
2672
2673 return 6;
2674 }
2675
2676 /* prepare list12, imm5, sp */
2677 int
2678 OP_30780 (void)
2679 {
2680 int i;
2681
2682 trace_input ("prepare", OP_PUSHPOP1, 0);
2683
2684 /* Store the registers with lower number registers being placed at higher addresses. */
2685 for (i = 0; i < 12; i++)
2686 if ((OP[3] & (1 << type1_regs[ i ])))
2687 {
2688 SP -= 4;
2689 store_mem (SP, 4, State.regs[ 20 + i ]);
2690 }
2691
2692 SP -= (OP[3] & 0x3e) << 1;
2693
2694 EP = SP;
2695
2696 trace_output (OP_PUSHPOP1);
2697
2698 return 4;
2699 }
2700
2701 /* mul reg1, reg2, reg3 */
2702 int
2703 OP_22007E0 (void)
2704 {
2705 trace_input ("mul", OP_REG_REG_REG, 0);
2706
2707 Multiply64 (1, State.regs[ OP[0] ]);
2708
2709 trace_output (OP_REG_REG_REG);
2710
2711 return 4;
2712 }
2713
2714 /* popmh list18 */
2715 int
2716 OP_307F0 (void)
2717 {
2718 int i;
2719
2720 trace_input ("popmh", OP_PUSHPOP2, 0);
2721
2722 if (OP[3] & (1 << 19))
2723 {
2724 if ((PSW & PSW_NP) && ((PSW & PSW_EP) == 0))
2725 {
2726 FEPSW = load_mem ( SP & ~ 3, 4);
2727 FEPC = load_mem ((SP + 4) & ~ 3, 4);
2728 }
2729 else
2730 {
2731 EIPSW = load_mem ( SP & ~ 3, 4);
2732 EIPC = load_mem ((SP + 4) & ~ 3, 4);
2733 }
2734
2735 SP += 8;
2736 }
2737
2738 /* Load the registers with lower number registers being retrieved from higher addresses. */
2739 for (i = 16; i--;)
2740 if ((OP[3] & (1 << type2_regs[ i ])))
2741 {
2742 State.regs[ i + 16 ] = load_mem (SP & ~ 3, 4);
2743 SP += 4;
2744 }
2745
2746 trace_output (OP_PUSHPOP2);
2747
2748 return 4;
2749 }
2750
2751 /* popml lsit18 */
2752 int
2753 OP_107F0 (void)
2754 {
2755 int i;
2756
2757 trace_input ("popml", OP_PUSHPOP3, 0);
2758
2759 if (OP[3] & (1 << 19))
2760 {
2761 if ((PSW & PSW_NP) && ((PSW & PSW_EP) == 0))
2762 {
2763 FEPSW = load_mem ( SP & ~ 3, 4);
2764 FEPC = load_mem ((SP + 4) & ~ 3, 4);
2765 }
2766 else
2767 {
2768 EIPSW = load_mem ( SP & ~ 3, 4);
2769 EIPC = load_mem ((SP + 4) & ~ 3, 4);
2770 }
2771
2772 SP += 8;
2773 }
2774
2775 if (OP[3] & (1 << 3))
2776 {
2777 PSW = load_mem (SP & ~ 3, 4);
2778 SP += 4;
2779 }
2780
2781 /* Load the registers with lower number registers being retrieved from higher addresses. */
2782 for (i = 15; i--;)
2783 if ((OP[3] & (1 << type3_regs[ i ])))
2784 {
2785 State.regs[ i + 1 ] = load_mem (SP & ~ 3, 4);
2786 SP += 4;
2787 }
2788
2789 trace_output (OP_PUSHPOP2);
2790
2791 return 4;
2792 }
2793
2794 /* pushmh list18 */
2795 int
2796 OP_307E0 (void)
2797 {
2798 int i;
2799
2800 trace_input ("pushmh", OP_PUSHPOP2, 0);
2801
2802 /* Store the registers with lower number registers being placed at higher addresses. */
2803 for (i = 0; i < 16; i++)
2804 if ((OP[3] & (1 << type2_regs[ i ])))
2805 {
2806 SP -= 4;
2807 store_mem (SP & ~ 3, 4, State.regs[ i + 16 ]);
2808 }
2809
2810 if (OP[3] & (1 << 19))
2811 {
2812 SP -= 8;
2813
2814 if ((PSW & PSW_NP) && ((PSW & PSW_EP) == 0))
2815 {
2816 store_mem ((SP + 4) & ~ 3, 4, FEPC);
2817 store_mem ( SP & ~ 3, 4, FEPSW);
2818 }
2819 else
2820 {
2821 store_mem ((SP + 4) & ~ 3, 4, EIPC);
2822 store_mem ( SP & ~ 3, 4, EIPSW);
2823 }
2824 }
2825
2826 trace_output (OP_PUSHPOP2);
2827
2828 return 4;
2829 }
2830
2831 /* V850E2R FPU functions */
2832 /*
2833 sim_fpu_status_invalid_snan = 1, -V--- (sim spec.)
2834 sim_fpu_status_invalid_qnan = 2, ----- (sim spec.)
2835 sim_fpu_status_invalid_isi = 4, (inf - inf) -V---
2836 sim_fpu_status_invalid_idi = 8, (inf / inf) -V---
2837 sim_fpu_status_invalid_zdz = 16, (0 / 0) -V---
2838 sim_fpu_status_invalid_imz = 32, (inf * 0) -V---
2839 sim_fpu_status_invalid_cvi = 64, convert to integer -V---
2840 sim_fpu_status_invalid_div0 = 128, (X / 0) --Z--
2841 sim_fpu_status_invalid_cmp = 256, compare ----- (sim spec.)
2842 sim_fpu_status_invalid_sqrt = 512, -V---
2843 sim_fpu_status_rounded = 1024, I----
2844 sim_fpu_status_inexact = 2048, I---- (sim spec.)
2845 sim_fpu_status_overflow = 4096, I--O-
2846 sim_fpu_status_underflow = 8192, I---U
2847 sim_fpu_status_denorm = 16384, ----U (sim spec.)
2848 */
2849
2850 void
2851 update_fpsr (SIM_DESC sd, sim_fpu_status status, unsigned int mask, unsigned int double_op_p)
2852 {
2853 unsigned int fpsr = FPSR & mask;
2854
2855 unsigned int flags = 0;
2856
2857 if (fpsr & FPSR_XEI
2858 && ((status & (sim_fpu_status_rounded
2859 | sim_fpu_status_overflow
2860 | sim_fpu_status_inexact))
2861 || (status & sim_fpu_status_underflow
2862 && (fpsr & (FPSR_XEU | FPSR_XEI)) == 0
2863 && fpsr & FPSR_FS)))
2864 {
2865 flags |= FPSR_XCI | FPSR_XPI;
2866 }
2867
2868 if (fpsr & FPSR_XEV
2869 && (status & (sim_fpu_status_invalid_isi
2870 | sim_fpu_status_invalid_imz
2871 | sim_fpu_status_invalid_zdz
2872 | sim_fpu_status_invalid_idi
2873 | sim_fpu_status_invalid_cvi
2874 | sim_fpu_status_invalid_sqrt
2875 | sim_fpu_status_invalid_snan)))
2876 {
2877 flags |= FPSR_XCV | FPSR_XPV;
2878 }
2879
2880 if (fpsr & FPSR_XEZ
2881 && (status & sim_fpu_status_invalid_div0))
2882 {
2883 flags |= FPSR_XCV | FPSR_XPV;
2884 }
2885
2886 if (fpsr & FPSR_XEO
2887 && (status & sim_fpu_status_overflow))
2888 {
2889 flags |= FPSR_XCO | FPSR_XPO;
2890 }
2891
2892 if (((fpsr & FPSR_XEU) || (fpsr & FPSR_FS) == 0)
2893 && (status & (sim_fpu_status_underflow
2894 | sim_fpu_status_denorm)))
2895 {
2896 flags |= FPSR_XCU | FPSR_XPU;
2897 }
2898
2899 if (flags)
2900 {
2901 FPSR &= ~FPSR_XC;
2902 FPSR |= flags;
2903
2904 SignalExceptionFPE (sd, double_op_p);
2905 }
2906 }
2907
2908 /* Exception. */
2909
2910 void
2911 SignalException (SIM_DESC sd)
2912 {
2913 if (MPM & MPM_AUE)
2914 {
2915 PSW = PSW & ~(PSW_NPV | PSW_DMP | PSW_IMP);
2916 }
2917 }
2918
2919 void
2920 SignalExceptionFPE (SIM_DESC sd, unsigned int double_op_p)
2921 {
2922 if (((PSW & (PSW_NP|PSW_ID)) == 0)
2923 || !(FPSR & (double_op_p ? FPSR_DEM : FPSR_SEM)))
2924 {
2925 EIPC = PC;
2926 EIPSW = PSW;
2927 EIIC = (FPSR & (double_op_p ? FPSR_DEM : FPSR_SEM))
2928 ? 0x71 : 0x72;
2929 PSW |= (PSW_EP | PSW_ID);
2930 PC = 0x70;
2931
2932 SignalException (sd);
2933 }
2934 }
2935
2936 void
2937 check_invalid_snan (SIM_DESC sd, sim_fpu_status status, unsigned int double_op_p)
2938 {
2939 if ((FPSR & FPSR_XEI)
2940 && (status & sim_fpu_status_invalid_snan))
2941 {
2942 FPSR &= ~FPSR_XC;
2943 FPSR |= FPSR_XCV;
2944 FPSR |= FPSR_XPV;
2945 SignalExceptionFPE (sd, double_op_p);
2946 }
2947 }
2948
2949 int
2950 v850_float_compare (SIM_DESC sd, int cmp, sim_fpu wop1, sim_fpu wop2, int double_op_p)
2951 {
2952 int result = -1;
2953
2954 if (sim_fpu_is_nan (&wop1) || sim_fpu_is_nan (&wop2))
2955 {
2956 if (cmp & 0x8)
2957 {
2958 if (FPSR & FPSR_XEV)
2959 {
2960 FPSR |= FPSR_XCV | FPSR_XPV;
2961 SignalExceptionFPE (sd, double_op_p);
2962 }
2963 }
2964
2965 switch (cmp)
2966 {
2967 case FPU_CMP_F:
2968 result = 0;
2969 break;
2970 case FPU_CMP_UN:
2971 result = 1;
2972 break;
2973 case FPU_CMP_EQ:
2974 result = 0;
2975 break;
2976 case FPU_CMP_UEQ:
2977 result = 1;
2978 break;
2979 case FPU_CMP_OLT:
2980 result = 0;
2981 break;
2982 case FPU_CMP_ULT:
2983 result = 1;
2984 break;
2985 case FPU_CMP_OLE:
2986 result = 0;
2987 break;
2988 case FPU_CMP_ULE:
2989 result = 1;
2990 break;
2991 case FPU_CMP_SF:
2992 result = 0;
2993 break;
2994 case FPU_CMP_NGLE:
2995 result = 1;
2996 break;
2997 case FPU_CMP_SEQ:
2998 result = 0;
2999 break;
3000 case FPU_CMP_NGL:
3001 result = 1;
3002 break;
3003 case FPU_CMP_LT:
3004 result = 0;
3005 break;
3006 case FPU_CMP_NGE:
3007 result = 1;
3008 break;
3009 case FPU_CMP_LE:
3010 result = 0;
3011 break;
3012 case FPU_CMP_NGT:
3013 result = 1;
3014 break;
3015 default:
3016 abort ();
3017 }
3018 }
3019 else if (sim_fpu_is_infinity (&wop1) && sim_fpu_is_infinity (&wop2)
3020 && sim_fpu_sign (&wop1) == sim_fpu_sign (&wop2))
3021 {
3022 switch (cmp)
3023 {
3024 case FPU_CMP_F:
3025 result = 0;
3026 break;
3027 case FPU_CMP_UN:
3028 result = 0;
3029 break;
3030 case FPU_CMP_EQ:
3031 result = 1;
3032 break;
3033 case FPU_CMP_UEQ:
3034 result = 1;
3035 break;
3036 case FPU_CMP_OLT:
3037 result = 0;
3038 break;
3039 case FPU_CMP_ULT:
3040 result = 0;
3041 break;
3042 case FPU_CMP_OLE:
3043 result = 1;
3044 break;
3045 case FPU_CMP_ULE:
3046 result = 1;
3047 break;
3048 case FPU_CMP_SF:
3049 result = 0;
3050 break;
3051 case FPU_CMP_NGLE:
3052 result = 0;
3053 break;
3054 case FPU_CMP_SEQ:
3055 result = 1;
3056 break;
3057 case FPU_CMP_NGL:
3058 result = 1;
3059 break;
3060 case FPU_CMP_LT:
3061 result = 0;
3062 break;
3063 case FPU_CMP_NGE:
3064 result = 0;
3065 break;
3066 case FPU_CMP_LE:
3067 result = 1;
3068 break;
3069 case FPU_CMP_NGT:
3070 result = 1;
3071 break;
3072 default:
3073 abort ();
3074 }
3075 }
3076 else
3077 {
3078 int gt = 0,lt = 0,eq = 0, status;
3079
3080 status = sim_fpu_cmp (&wop1, &wop2);
3081
3082 switch (status)
3083 {
3084 case SIM_FPU_IS_SNAN:
3085 case SIM_FPU_IS_QNAN:
3086 abort ();
3087 break;
3088
3089 case SIM_FPU_IS_NINF:
3090 lt = 1;
3091 break;
3092 case SIM_FPU_IS_PINF:
3093 gt = 1;
3094 break;
3095 case SIM_FPU_IS_NNUMBER:
3096 lt = 1;
3097 break;
3098 case SIM_FPU_IS_PNUMBER:
3099 gt = 1;
3100 break;
3101 case SIM_FPU_IS_NDENORM:
3102 lt = 1;
3103 break;
3104 case SIM_FPU_IS_PDENORM:
3105 gt = 1;
3106 break;
3107 case SIM_FPU_IS_NZERO:
3108 case SIM_FPU_IS_PZERO:
3109 eq = 1;
3110 break;
3111 }
3112
3113 switch (cmp)
3114 {
3115 case FPU_CMP_F:
3116 result = 0;
3117 break;
3118 case FPU_CMP_UN:
3119 result = 0;
3120 break;
3121 case FPU_CMP_EQ:
3122 result = eq;
3123 break;
3124 case FPU_CMP_UEQ:
3125 result = eq;
3126 break;
3127 case FPU_CMP_OLT:
3128 result = lt;
3129 break;
3130 case FPU_CMP_ULT:
3131 result = lt;
3132 break;
3133 case FPU_CMP_OLE:
3134 result = lt || eq;
3135 break;
3136 case FPU_CMP_ULE:
3137 result = lt || eq;
3138 break;
3139 case FPU_CMP_SF:
3140 result = 0;
3141 break;
3142 case FPU_CMP_NGLE:
3143 result = 0;
3144 break;
3145 case FPU_CMP_SEQ:
3146 result = eq;
3147 break;
3148 case FPU_CMP_NGL:
3149 result = eq;
3150 break;
3151 case FPU_CMP_LT:
3152 result = lt;
3153 break;
3154 case FPU_CMP_NGE:
3155 result = lt;
3156 break;
3157 case FPU_CMP_LE:
3158 result = lt || eq;
3159 break;
3160 case FPU_CMP_NGT:
3161 result = lt || eq;
3162 break;
3163 }
3164 }
3165
3166 ASSERT (result != -1);
3167 return result;
3168 }
3169
3170 void
3171 v850_div (SIM_DESC sd, unsigned int op0, unsigned int op1, unsigned int *op2p, unsigned int *op3p)
3172 {
3173 signed long int quotient;
3174 signed long int remainder;
3175 signed long int divide_by;
3176 signed long int divide_this;
3177 bfd_boolean overflow = FALSE;
3178
3179 /* Compute the result. */
3180 divide_by = op0;
3181 divide_this = op1;
3182
3183 if (divide_by == 0 || (divide_by == -1 && divide_this == (1 << 31)))
3184 {
3185 overflow = TRUE;
3186 divide_by = 1;
3187 }
3188
3189 quotient = divide_this / divide_by;
3190 remainder = divide_this % divide_by;
3191
3192 /* Set condition codes. */
3193 PSW &= ~(PSW_Z | PSW_S | PSW_OV);
3194
3195 if (overflow) PSW |= PSW_OV;
3196 if (quotient == 0) PSW |= PSW_Z;
3197 if (quotient < 0) PSW |= PSW_S;
3198
3199 *op2p = quotient;
3200 *op3p = remainder;
3201 }
3202
3203 void
3204 v850_divu (SIM_DESC sd, unsigned int op0, unsigned int op1, unsigned int *op2p, unsigned int *op3p)
3205 {
3206 unsigned long int quotient;
3207 unsigned long int remainder;
3208 unsigned long int divide_by;
3209 unsigned long int divide_this;
3210 bfd_boolean overflow = FALSE;
3211
3212 /* Compute the result. */
3213
3214 divide_by = op0;
3215 divide_this = op1;
3216
3217 if (divide_by == 0)
3218 {
3219 overflow = TRUE;
3220 divide_by = 1;
3221 }
3222
3223 quotient = divide_this / divide_by;
3224 remainder = divide_this % divide_by;
3225
3226 /* Set condition codes. */
3227 PSW &= ~(PSW_Z | PSW_S | PSW_OV);
3228
3229 if (overflow) PSW |= PSW_OV;
3230 if (quotient == 0) PSW |= PSW_Z;
3231 if (quotient & 0x80000000) PSW |= PSW_S;
3232
3233 *op2p = quotient;
3234 *op3p = remainder;
3235 }
3236
3237 void
3238 v850_sar (SIM_DESC sd, unsigned int op0, unsigned int op1, unsigned int *op2p)
3239 {
3240 unsigned int result, z, s, cy;
3241
3242 op0 &= 0x1f;
3243 result = (signed)op1 >> op0;
3244
3245 /* Compute the condition codes. */
3246 z = (result == 0);
3247 s = (result & 0x80000000);
3248 cy = (op1 & (1 << (op0 - 1)));
3249
3250 /* Store the result and condition codes. */
3251 PSW &= ~(PSW_Z | PSW_S | PSW_OV | PSW_CY);
3252 PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
3253 | (cy ? PSW_CY : 0));
3254
3255 *op2p = result;
3256 }
3257
3258 void
3259 v850_shl (SIM_DESC sd, unsigned int op0, unsigned int op1, unsigned int *op2p)
3260 {
3261 unsigned int result, z, s, cy;
3262
3263 op0 &= 0x1f;
3264 result = op1 << op0;
3265
3266 /* Compute the condition codes. */
3267 z = (result == 0);
3268 s = (result & 0x80000000);
3269 cy = (op1 & (1 << (32 - op0)));
3270
3271 /* Store the result and condition codes. */
3272 PSW &= ~(PSW_Z | PSW_S | PSW_OV | PSW_CY);
3273 PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
3274 | (cy ? PSW_CY : 0));
3275
3276 *op2p = result;
3277 }
3278
3279 void
3280 v850_rotl (SIM_DESC sd, unsigned int amount, unsigned int src, unsigned int * dest)
3281 {
3282 unsigned int result, z, s, cy;
3283
3284 amount &= 0x1f;
3285 result = src << amount;
3286 result |= src >> (32 - amount);
3287
3288 /* Compute the condition codes. */
3289 z = (result == 0);
3290 s = (result & 0x80000000);
3291 cy = ! (result & 1);
3292
3293 /* Store the result and condition codes. */
3294 PSW &= ~(PSW_Z | PSW_S | PSW_OV | PSW_CY);
3295 PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
3296 | (cy ? PSW_CY : 0));
3297
3298 * dest = result;
3299 }
3300
3301 void
3302 v850_bins (SIM_DESC sd, unsigned int source, unsigned int lsb, unsigned int msb,
3303 unsigned int * dest)
3304 {
3305 unsigned int mask;
3306 unsigned int result, pos, width;
3307 unsigned int z, s;
3308
3309 pos = lsb;
3310 width = (msb - lsb) + 1;
3311
3312 mask = ~ (-(1 << width));
3313 source &= mask;
3314 mask <<= pos;
3315 result = (* dest) & ~ mask;
3316 result |= source << pos;
3317
3318 /* Compute the condition codes. */
3319 z = (result == 0);
3320 s = result & 0x80000000;
3321
3322 /* Store the result and condition codes. */
3323 PSW &= ~(PSW_Z | PSW_S | PSW_OV );
3324 PSW |= (z ? PSW_Z : 0) | (s ? PSW_S : 0);
3325
3326 * dest = result;
3327 }
3328
3329 void
3330 v850_shr (SIM_DESC sd, unsigned int op0, unsigned int op1, unsigned int *op2p)
3331 {
3332 unsigned int result, z, s, cy;
3333
3334 op0 &= 0x1f;
3335 result = op1 >> op0;
3336
3337 /* Compute the condition codes. */
3338 z = (result == 0);
3339 s = (result & 0x80000000);
3340 cy = (op1 & (1 << (op0 - 1)));
3341
3342 /* Store the result and condition codes. */
3343 PSW &= ~(PSW_Z | PSW_S | PSW_OV | PSW_CY);
3344 PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
3345 | (cy ? PSW_CY : 0));
3346
3347 *op2p = result;
3348 }
3349
3350 void
3351 v850_satadd (SIM_DESC sd, unsigned int op0, unsigned int op1, unsigned int *op2p)
3352 {
3353 unsigned int result, z, s, cy, ov, sat;
3354
3355 result = op0 + op1;
3356
3357 /* Compute the condition codes. */
3358 z = (result == 0);
3359 s = (result & 0x80000000);
3360 cy = (result < op0 || result < op1);
3361 ov = ((op0 & 0x80000000) == (op1 & 0x80000000)
3362 && (op0 & 0x80000000) != (result & 0x80000000));
3363 sat = ov;
3364
3365 /* Store the result and condition codes. */
3366 PSW &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
3367 PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
3368 | (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0)
3369 | (sat ? PSW_SAT : 0));
3370
3371 /* Handle saturated results. */
3372 if (sat && s)
3373 {
3374 result = 0x7fffffff;
3375 PSW &= ~PSW_S;
3376 }
3377 else if (sat)
3378 {
3379 result = 0x80000000;
3380 PSW |= PSW_S;
3381 }
3382
3383 *op2p = result;
3384 }
3385
3386 void
3387 v850_satsub (SIM_DESC sd, unsigned int op0, unsigned int op1, unsigned int *op2p)
3388 {
3389 unsigned int result, z, s, cy, ov, sat;
3390
3391 /* Compute the result. */
3392 result = op1 - op0;
3393
3394 /* Compute the condition codes. */
3395 z = (result == 0);
3396 s = (result & 0x80000000);
3397 cy = (op1 < op0);
3398 ov = ((op1 & 0x80000000) != (op0 & 0x80000000)
3399 && (op1 & 0x80000000) != (result & 0x80000000));
3400 sat = ov;
3401
3402 /* Store the result and condition codes. */
3403 PSW &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
3404 PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
3405 | (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0)
3406 | (sat ? PSW_SAT : 0));
3407
3408 /* Handle saturated results. */
3409 if (sat && s)
3410 {
3411 result = 0x7fffffff;
3412 PSW &= ~PSW_S;
3413 }
3414 else if (sat)
3415 {
3416 result = 0x80000000;
3417 PSW |= PSW_S;
3418 }
3419
3420 *op2p = result;
3421 }
3422
3423 unsigned32
3424 load_data_mem (SIM_DESC sd,
3425 SIM_ADDR addr,
3426 int len)
3427 {
3428 uint32 data;
3429
3430 switch (len)
3431 {
3432 case 1:
3433 data = sim_core_read_unaligned_1 (STATE_CPU (sd, 0),
3434 PC, read_map, addr);
3435 break;
3436 case 2:
3437 data = sim_core_read_unaligned_2 (STATE_CPU (sd, 0),
3438 PC, read_map, addr);
3439 break;
3440 case 4:
3441 data = sim_core_read_unaligned_4 (STATE_CPU (sd, 0),
3442 PC, read_map, addr);
3443 break;
3444 default:
3445 abort ();
3446 }
3447 return data;
3448 }
3449
3450 void
3451 store_data_mem (SIM_DESC sd,
3452 SIM_ADDR addr,
3453 int len,
3454 unsigned32 data)
3455 {
3456 switch (len)
3457 {
3458 case 1:
3459 store_mem (addr, 1, data);
3460 break;
3461 case 2:
3462 store_mem (addr, 2, data);
3463 break;
3464 case 4:
3465 store_mem (addr, 4, data);
3466 break;
3467 default:
3468 abort ();
3469 }
3470 }
3471
3472 int
3473 mpu_load_mem_test (SIM_DESC sd, unsigned int addr, int size, int base_reg)
3474 {
3475 int result = 1;
3476
3477 if (PSW & PSW_DMP)
3478 {
3479 if (IPE0 && addr >= IPA2ADDR (IPA0L) && addr <= IPA2ADDR (IPA0L) && IPR0)
3480 {
3481 /* text area */
3482 }
3483 else if (IPE1 && addr >= IPA2ADDR (IPA1L) && addr <= IPA2ADDR (IPA1L) && IPR1)
3484 {
3485 /* text area */
3486 }
3487 else if (IPE2 && addr >= IPA2ADDR (IPA2L) && addr <= IPA2ADDR (IPA2L) && IPR2)
3488 {
3489 /* text area */
3490 }
3491 else if (IPE3 && addr >= IPA2ADDR (IPA3L) && addr <= IPA2ADDR (IPA3L) && IPR3)
3492 {
3493 /* text area */
3494 }
3495 else if (addr >= PPA2ADDR (PPA & ~PPM) && addr <= DPA2ADDR (PPA | PPM))
3496 {
3497 /* preifarallel area */
3498 }
3499 else if (addr >= PPA2ADDR (SPAL) && addr <= DPA2ADDR (SPAU))
3500 {
3501 /* stack area */
3502 }
3503 else if (DPE0 && addr >= DPA2ADDR (DPA0L) && addr <= DPA2ADDR (DPA0L) && DPR0
3504 && ((SPAL & SPAL_SPS) ? base_reg == SP_REGNO : 1))
3505 {
3506 /* data area */
3507 }
3508 else if (DPE1 && addr >= DPA2ADDR (DPA1L) && addr <= DPA2ADDR (DPA1L) && DPR1
3509 && ((SPAL & SPAL_SPS) ? base_reg == SP_REGNO : 1))
3510 {
3511 /* data area */
3512 }
3513 else if (DPE2 && addr >= DPA2ADDR (DPA2L) && addr <= DPA2ADDR (DPA2L) && DPR2
3514 && ((SPAL & SPAL_SPS) ? base_reg == SP_REGNO : 1))
3515 {
3516 /* data area */
3517 }
3518 else if (DPE3 && addr >= DPA2ADDR (DPA3L) && addr <= DPA2ADDR (DPA3L) && DPR3
3519 && ((SPAL & SPAL_SPS) ? base_reg == SP_REGNO : 1))
3520 {
3521 /* data area */
3522 }
3523 else
3524 {
3525 VMECR &= ~(VMECR_VMW | VMECR_VMX);
3526 VMECR |= VMECR_VMR;
3527 VMADR = addr;
3528 VMTID = TID;
3529 FEIC = 0x431;
3530
3531 PC = 0x30;
3532
3533 SignalException (sd);
3534 result = 0;
3535 }
3536 }
3537
3538 return result;
3539 }
3540
3541 int
3542 mpu_store_mem_test (SIM_DESC sd, unsigned int addr, int size, int base_reg)
3543 {
3544 int result = 1;
3545
3546 if (PSW & PSW_DMP)
3547 {
3548 if (addr >= PPA2ADDR (PPA & ~PPM) && addr <= DPA2ADDR (PPA | PPM))
3549 {
3550 /* preifarallel area */
3551 }
3552 else if (addr >= PPA2ADDR (SPAL) && addr <= DPA2ADDR (SPAU))
3553 {
3554 /* stack area */
3555 }
3556 else if (DPE0 && addr >= DPA2ADDR (DPA0L) && addr <= DPA2ADDR (DPA0L) && DPW0
3557 && ((SPAL & SPAL_SPS) ? base_reg == SP_REGNO : 1))
3558 {
3559 /* data area */
3560 }
3561 else if (DPE1 && addr >= DPA2ADDR (DPA1L) && addr <= DPA2ADDR (DPA1L) && DPW1
3562 && ((SPAL & SPAL_SPS) ? base_reg == SP_REGNO : 1))
3563 {
3564 /* data area */
3565 }
3566 else if (DPE2 && addr >= DPA2ADDR (DPA2L) && addr <= DPA2ADDR (DPA2L) && DPW2
3567 && ((SPAL & SPAL_SPS) ? base_reg == SP_REGNO : 1))
3568 {
3569 /* data area */
3570 }
3571 else if (DPE3 && addr >= DPA2ADDR (DPA3L) && addr <= DPA2ADDR (DPA3L) && DPW3
3572 && ((SPAL & SPAL_SPS) ? base_reg == SP_REGNO : 1))
3573 {
3574 /* data area */
3575 }
3576 else
3577 {
3578 if (addr >= PPA2ADDR (PPA & ~PPM) && addr <= DPA2ADDR (PPA | PPM))
3579 {
3580 FEIC = 0x432;
3581 VPTID = TID;
3582 VPADR = PC;
3583 #ifdef NOT_YET
3584 VIP_PP;
3585 VPECR;
3586 #endif
3587 }
3588 else
3589 {
3590 FEIC = 0x431;
3591 VMTID = TID;
3592 VMADR = VMECR;
3593 VMECR &= ~(VMECR_VMW | VMECR_VMX);
3594 VMECR |= VMECR_VMR;
3595 PC = 0x30;
3596 }
3597 result = 0;
3598 }
3599 }
3600
3601 return result;
3602 }
3603
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