1 /* This must come before any other includes. */
20 #include "targ-vals.h"
22 #include "libiberty.h"
25 #if !defined(__GO32__) && !defined(_WIN32)
27 #include <sys/times.h>
31 /* This is an array of the bit positions of registers r20 .. r31 in
32 that order in a prepare/dispose instruction. */
33 int type1_regs
[12] = { 27, 26, 25, 24, 31, 30, 29, 28, 23, 22, 0, 21 };
34 /* This is an array of the bit positions of registers r16 .. r31 in
35 that order in a push/pop instruction. */
36 int type2_regs
[16] = { 3, 2, 1, 0, 27, 26, 25, 24, 31, 30, 29, 28, 23, 22, 20, 21};
37 /* This is an array of the bit positions of registers r1 .. r15 in
38 that order in a push/pop instruction. */
39 int type3_regs
[15] = { 2, 1, 0, 27, 26, 25, 24, 31, 30, 29, 28, 23, 22, 20, 21};
42 #ifndef SIZE_INSTRUCTION
43 #define SIZE_INSTRUCTION 18
47 #define SIZE_VALUES 11
51 unsigned32 trace_values
[3];
54 const char * trace_name
;
59 trace_input (char *name
, enum op_types type
, int size
)
61 if (!TRACE_ALU_P (STATE_CPU (simulator
, 0)))
66 trace_module
= TRACE_ALU_IDX
;
79 trace_values
[0] = State
.regs
[OP
[0]];
86 trace_values
[0] = State
.regs
[OP
[1]];
87 trace_values
[1] = State
.regs
[OP
[0]];
93 trace_values
[0] = SEXT5 (OP
[0]);
94 trace_values
[1] = OP
[1];
99 trace_values
[0] = SEXT5 (OP
[0]);
100 trace_num_values
= 1;
104 trace_values
[0] = State
.pc
;
105 trace_values
[1] = SEXT9 (OP
[0]);
106 trace_values
[2] = PSW
;
107 trace_num_values
= 3;
111 trace_values
[0] = OP
[1] * size
;
112 trace_values
[1] = State
.regs
[30];
113 trace_num_values
= 2;
117 trace_values
[0] = State
.regs
[OP
[0]];
118 trace_values
[1] = OP
[1] * size
;
119 trace_values
[2] = State
.regs
[30];
120 trace_num_values
= 3;
124 trace_values
[0] = EXTEND16 (OP
[2]);
125 trace_values
[1] = State
.regs
[OP
[0]];
126 trace_num_values
= 2;
130 trace_values
[0] = State
.regs
[OP
[1]];
131 trace_values
[1] = EXTEND16 (OP
[2]);
132 trace_values
[2] = State
.regs
[OP
[0]];
133 trace_num_values
= 3;
137 trace_values
[0] = SEXT22 (OP
[0]);
138 trace_values
[1] = State
.pc
;
139 trace_num_values
= 2;
143 trace_values
[0] = EXTEND16 (OP
[0]) << size
;
144 trace_values
[1] = State
.regs
[OP
[1]];
145 trace_num_values
= 2;
148 case OP_IMM16_REG_REG
:
149 trace_values
[0] = EXTEND16 (OP
[2]) << size
;
150 trace_values
[1] = State
.regs
[OP
[1]];
151 trace_num_values
= 2;
154 case OP_UIMM_REG_REG
:
155 trace_values
[0] = (OP
[0] & 0xffff) << size
;
156 trace_values
[1] = State
.regs
[OP
[1]];
157 trace_num_values
= 2;
160 case OP_UIMM16_REG_REG
:
161 trace_values
[0] = (OP
[2]) << size
;
162 trace_values
[1] = State
.regs
[OP
[1]];
163 trace_num_values
= 2;
167 trace_num_values
= 0;
171 trace_values
[0] = PSW
;
172 trace_num_values
= 1;
176 trace_num_values
= 0;
180 trace_values
[0] = State
.regs
[OP
[0]];
181 trace_num_values
= 1;
185 trace_values
[0] = State
.sregs
[OP
[1]];
186 trace_num_values
= 1;
192 trace_result (int has_result
, unsigned32 result
)
200 /* write out the values saved during the trace_input call */
203 for (i
= 0; i
< trace_num_values
; i
++)
205 sprintf (chp
, "%*s0x%.8lx", SIZE_VALUES
- 10, "",
206 (long) trace_values
[i
]);
207 chp
= strchr (chp
, '\0');
211 sprintf (chp
, "%*s", SIZE_VALUES
, "");
212 chp
= strchr (chp
, '\0');
216 /* append any result to the end of the buffer */
218 sprintf (chp
, " :: 0x%.8lx", (unsigned long) result
);
220 trace_generic (simulator
, STATE_CPU (simulator
, 0), trace_module
, "%s", buf
);
224 trace_output (enum op_types result
)
226 if (!TRACE_ALU_P (STATE_CPU (simulator
, 0)))
248 trace_result (1, State
.regs
[OP
[0]]);
252 case OP_REG_REG_MOVE
:
254 case OP_IMM_REG_MOVE
:
257 trace_result (1, State
.regs
[OP
[1]]);
261 case OP_UIMM_REG_REG
:
262 case OP_IMM16_REG_REG
:
263 case OP_UIMM16_REG_REG
:
264 trace_result (1, State
.regs
[OP
[1]]);
269 trace_result (1, State
.regs
[OP
[1]]);
275 trace_result (1, State
.sregs
[OP
[1]]);
282 /* Returns 1 if the specific condition is met, returns 0 otherwise. */
284 condition_met (unsigned code
)
286 unsigned int psw
= PSW
;
290 case 0x0: return ((psw
& PSW_OV
) != 0);
291 case 0x1: return ((psw
& PSW_CY
) != 0);
292 case 0x2: return ((psw
& PSW_Z
) != 0);
293 case 0x3: return ((((psw
& PSW_CY
) != 0) | ((psw
& PSW_Z
) != 0)) != 0);
294 case 0x4: return ((psw
& PSW_S
) != 0);
295 /*case 0x5: return 1;*/
296 case 0x6: return ((((psw
& PSW_S
) != 0) ^ ((psw
& PSW_OV
) != 0)) != 0);
297 case 0x7: return (((((psw
& PSW_S
) != 0) ^ ((psw
& PSW_OV
) != 0)) || ((psw
& PSW_Z
) != 0)) != 0);
298 case 0x8: return ((psw
& PSW_OV
) == 0);
299 case 0x9: return ((psw
& PSW_CY
) == 0);
300 case 0xa: return ((psw
& PSW_Z
) == 0);
301 case 0xb: return ((((psw
& PSW_CY
) != 0) | ((psw
& PSW_Z
) != 0)) == 0);
302 case 0xc: return ((psw
& PSW_S
) == 0);
303 case 0xd: return ((psw
& PSW_SAT
) != 0);
304 case 0xe: return ((((psw
& PSW_S
) != 0) ^ ((psw
& PSW_OV
) != 0)) == 0);
305 case 0xf: return (((((psw
& PSW_S
) != 0) ^ ((psw
& PSW_OV
) != 0)) || ((psw
& PSW_Z
) != 0)) == 0);
312 Add32 (unsigned long a1
, unsigned long a2
, int * carry
)
314 unsigned long result
= (a1
+ a2
);
316 * carry
= (result
< a1
);
322 Multiply64 (int sign
, unsigned long op0
)
333 op1
= State
.regs
[ OP
[1] ];
337 /* Compute sign of result and adjust operands if necessary. */
339 sign
= (op0
^ op1
) & 0x80000000;
341 if (((signed long) op0
) < 0)
344 if (((signed long) op1
) < 0)
348 /* We can split the 32x32 into four 16x16 operations. This ensures
349 that we do not lose precision on 32bit only hosts: */
350 lo
= ( (op0
& 0xFFFF) * (op1
& 0xFFFF));
351 mid1
= ( (op0
& 0xFFFF) * ((op1
>> 16) & 0xFFFF));
352 mid2
= (((op0
>> 16) & 0xFFFF) * (op1
& 0xFFFF));
353 hi
= (((op0
>> 16) & 0xFFFF) * ((op1
>> 16) & 0xFFFF));
355 /* We now need to add all of these results together, taking care
356 to propogate the carries from the additions: */
357 RdLo
= Add32 (lo
, (mid1
<< 16), & carry
);
359 RdLo
= Add32 (RdLo
, (mid2
<< 16), & carry
);
360 RdHi
+= (carry
+ ((mid1
>> 16) & 0xFFFF) + ((mid2
>> 16) & 0xFFFF) + hi
);
364 /* Negate result if necessary. */
368 if (RdLo
== 0xFFFFFFFF)
377 /* Don't store into register 0. */
379 State
.regs
[ OP
[1] ] = RdLo
;
381 State
.regs
[ OP
[2] >> 11 ] = RdHi
;
387 /* Read a null terminated string from memory, return in a buffer. */
390 fetch_str (SIM_DESC sd
, address_word addr
)
395 while (sim_core_read_1 (STATE_CPU (sd
, 0),
396 PC
, read_map
, addr
+ nr
) != 0)
399 buf
= NZALLOC (char, nr
+ 1);
400 sim_read (simulator
, addr
, (unsigned char *) buf
, nr
);
405 /* Read a null terminated argument vector from memory, return in a
409 fetch_argv (SIM_DESC sd
, address_word addr
)
413 char **buf
= xmalloc (max_nr
* sizeof (char*));
417 unsigned32 a
= sim_core_read_4 (STATE_CPU (sd
, 0),
418 PC
, read_map
, addr
+ nr
* 4);
420 buf
[nr
] = fetch_str (sd
, a
);
422 if (nr
== max_nr
- 1)
425 buf
= xrealloc (buf
, max_nr
* sizeof (char*));
437 trace_input ("sst.b", OP_STORE16
, 1);
439 store_mem (State
.regs
[30] + (OP
[3] & 0x7f), 1, State
.regs
[ OP
[1] ]);
441 trace_output (OP_STORE16
);
450 trace_input ("sst.h", OP_STORE16
, 2);
452 store_mem (State
.regs
[30] + ((OP
[3] & 0x7f) << 1), 2, State
.regs
[ OP
[1] ]);
454 trace_output (OP_STORE16
);
463 trace_input ("sst.w", OP_STORE16
, 4);
465 store_mem (State
.regs
[30] + ((OP
[3] & 0x7e) << 1), 4, State
.regs
[ OP
[1] ]);
467 trace_output (OP_STORE16
);
478 trace_input ("ld.b", OP_LOAD32
, 1);
480 adr
= State
.regs
[ OP
[0] ] + EXTEND16 (OP
[2]);
482 State
.regs
[ OP
[1] ] = EXTEND8 (load_mem (adr
, 1));
484 trace_output (OP_LOAD32
);
495 trace_input ("ld.h", OP_LOAD32
, 2);
497 adr
= State
.regs
[ OP
[0] ] + EXTEND16 (OP
[2]);
500 State
.regs
[ OP
[1] ] = EXTEND16 (load_mem (adr
, 2));
502 trace_output (OP_LOAD32
);
513 trace_input ("ld.w", OP_LOAD32
, 4);
515 adr
= State
.regs
[ OP
[0] ] + EXTEND16 (OP
[2] & ~1);
518 State
.regs
[ OP
[1] ] = load_mem (adr
, 4);
520 trace_output (OP_LOAD32
);
529 trace_input ("st.b", OP_STORE32
, 1);
531 store_mem (State
.regs
[ OP
[0] ] + EXTEND16 (OP
[2]), 1, State
.regs
[ OP
[1] ]);
533 trace_output (OP_STORE32
);
544 trace_input ("st.h", OP_STORE32
, 2);
546 adr
= State
.regs
[ OP
[0] ] + EXTEND16 (OP
[2]);
549 store_mem (adr
, 2, State
.regs
[ OP
[1] ]);
551 trace_output (OP_STORE32
);
562 trace_input ("st.w", OP_STORE32
, 4);
564 adr
= State
.regs
[ OP
[0] ] + EXTEND16 (OP
[2] & ~1);
567 store_mem (adr
, 4, State
.regs
[ OP
[1] ]);
569 trace_output (OP_STORE32
);
578 unsigned int op0
, op1
, result
, z
, s
, cy
, ov
;
580 trace_input ("add", OP_REG_REG
, 0);
582 /* Compute the result. */
584 op0
= State
.regs
[ OP
[0] ];
585 op1
= State
.regs
[ OP
[1] ];
589 /* Compute the condition codes. */
591 s
= (result
& 0x80000000);
592 cy
= (result
< op0
|| result
< op1
);
593 ov
= ((op0
& 0x80000000) == (op1
& 0x80000000)
594 && (op0
& 0x80000000) != (result
& 0x80000000));
596 /* Store the result and condition codes. */
597 State
.regs
[OP
[1]] = result
;
598 PSW
&= ~(PSW_Z
| PSW_S
| PSW_CY
| PSW_OV
);
599 PSW
|= ((z
? PSW_Z
: 0) | (s
? PSW_S
: 0)
600 | (cy
? PSW_CY
: 0) | (ov
? PSW_OV
: 0));
601 trace_output (OP_REG_REG
);
606 /* add sign_extend(imm5), reg */
610 unsigned int op0
, op1
, result
, z
, s
, cy
, ov
;
613 trace_input ("add", OP_IMM_REG
, 0);
615 /* Compute the result. */
616 temp
= SEXT5 (OP
[0]);
618 op1
= State
.regs
[OP
[1]];
621 /* Compute the condition codes. */
623 s
= (result
& 0x80000000);
624 cy
= (result
< op0
|| result
< op1
);
625 ov
= ((op0
& 0x80000000) == (op1
& 0x80000000)
626 && (op0
& 0x80000000) != (result
& 0x80000000));
628 /* Store the result and condition codes. */
629 State
.regs
[OP
[1]] = result
;
630 PSW
&= ~(PSW_Z
| PSW_S
| PSW_CY
| PSW_OV
);
631 PSW
|= ((z
? PSW_Z
: 0) | (s
? PSW_S
: 0)
632 | (cy
? PSW_CY
: 0) | (ov
? PSW_OV
: 0));
633 trace_output (OP_IMM_REG
);
638 /* addi sign_extend(imm16), reg, reg */
642 unsigned int op0
, op1
, result
, z
, s
, cy
, ov
;
644 trace_input ("addi", OP_IMM16_REG_REG
, 0);
646 /* Compute the result. */
648 op0
= EXTEND16 (OP
[2]);
649 op1
= State
.regs
[ OP
[0] ];
652 /* Compute the condition codes. */
654 s
= (result
& 0x80000000);
655 cy
= (result
< op0
|| result
< op1
);
656 ov
= ((op0
& 0x80000000) == (op1
& 0x80000000)
657 && (op0
& 0x80000000) != (result
& 0x80000000));
659 /* Store the result and condition codes. */
660 State
.regs
[OP
[1]] = result
;
661 PSW
&= ~(PSW_Z
| PSW_S
| PSW_CY
| PSW_OV
);
662 PSW
|= ((z
? PSW_Z
: 0) | (s
? PSW_S
: 0)
663 | (cy
? PSW_CY
: 0) | (ov
? PSW_OV
: 0));
664 trace_output (OP_IMM16_REG_REG
);
673 unsigned int op0
, op1
, result
, z
, s
, cy
, ov
;
675 trace_input ("sub", OP_REG_REG
, 0);
676 /* Compute the result. */
677 op0
= State
.regs
[ OP
[0] ];
678 op1
= State
.regs
[ OP
[1] ];
681 /* Compute the condition codes. */
683 s
= (result
& 0x80000000);
685 ov
= ((op1
& 0x80000000) != (op0
& 0x80000000)
686 && (op1
& 0x80000000) != (result
& 0x80000000));
688 /* Store the result and condition codes. */
689 State
.regs
[OP
[1]] = result
;
690 PSW
&= ~(PSW_Z
| PSW_S
| PSW_CY
| PSW_OV
);
691 PSW
|= ((z
? PSW_Z
: 0) | (s
? PSW_S
: 0)
692 | (cy
? PSW_CY
: 0) | (ov
? PSW_OV
: 0));
693 trace_output (OP_REG_REG
);
698 /* subr reg1, reg2 */
702 unsigned int op0
, op1
, result
, z
, s
, cy
, ov
;
704 trace_input ("subr", OP_REG_REG
, 0);
705 /* Compute the result. */
706 op0
= State
.regs
[ OP
[0] ];
707 op1
= State
.regs
[ OP
[1] ];
710 /* Compute the condition codes. */
712 s
= (result
& 0x80000000);
714 ov
= ((op0
& 0x80000000) != (op1
& 0x80000000)
715 && (op0
& 0x80000000) != (result
& 0x80000000));
717 /* Store the result and condition codes. */
718 State
.regs
[OP
[1]] = result
;
719 PSW
&= ~(PSW_Z
| PSW_S
| PSW_CY
| PSW_OV
);
720 PSW
|= ((z
? PSW_Z
: 0) | (s
? PSW_S
: 0)
721 | (cy
? PSW_CY
: 0) | (ov
? PSW_OV
: 0));
722 trace_output (OP_REG_REG
);
731 trace_input ("mulh", OP_REG_REG
, 0);
733 State
.regs
[ OP
[1] ] = (EXTEND16 (State
.regs
[ OP
[1] ]) * EXTEND16 (State
.regs
[ OP
[0] ]));
735 trace_output (OP_REG_REG
);
740 /* mulh sign_extend(imm5), reg2 */
744 trace_input ("mulh", OP_IMM_REG
, 0);
746 State
.regs
[ OP
[1] ] = EXTEND16 (State
.regs
[ OP
[1] ]) * SEXT5 (OP
[0]);
748 trace_output (OP_IMM_REG
);
753 /* mulhi imm16, reg1, reg2 */
757 trace_input ("mulhi", OP_IMM16_REG_REG
, 0);
759 State
.regs
[ OP
[1] ] = EXTEND16 (State
.regs
[ OP
[0] ]) * EXTEND16 (OP
[2]);
761 trace_output (OP_IMM16_REG_REG
);
770 unsigned int op0
, op1
, result
, z
, s
, cy
, ov
;
772 trace_input ("cmp", OP_REG_REG_CMP
, 0);
773 /* Compute the result. */
774 op0
= State
.regs
[ OP
[0] ];
775 op1
= State
.regs
[ OP
[1] ];
778 /* Compute the condition codes. */
780 s
= (result
& 0x80000000);
782 ov
= ((op1
& 0x80000000) != (op0
& 0x80000000)
783 && (op1
& 0x80000000) != (result
& 0x80000000));
785 /* Set condition codes. */
786 PSW
&= ~(PSW_Z
| PSW_S
| PSW_CY
| PSW_OV
);
787 PSW
|= ((z
? PSW_Z
: 0) | (s
? PSW_S
: 0)
788 | (cy
? PSW_CY
: 0) | (ov
? PSW_OV
: 0));
789 trace_output (OP_REG_REG_CMP
);
794 /* cmp sign_extend(imm5), reg */
798 unsigned int op0
, op1
, result
, z
, s
, cy
, ov
;
801 /* Compute the result. */
802 trace_input ("cmp", OP_IMM_REG_CMP
, 0);
803 temp
= SEXT5 (OP
[0]);
805 op1
= State
.regs
[OP
[1]];
808 /* Compute the condition codes. */
810 s
= (result
& 0x80000000);
812 ov
= ((op1
& 0x80000000) != (op0
& 0x80000000)
813 && (op1
& 0x80000000) != (result
& 0x80000000));
815 /* Set condition codes. */
816 PSW
&= ~(PSW_Z
| PSW_S
| PSW_CY
| PSW_OV
);
817 PSW
|= ((z
? PSW_Z
: 0) | (s
? PSW_S
: 0)
818 | (cy
? PSW_CY
: 0) | (ov
? PSW_OV
: 0));
819 trace_output (OP_IMM_REG_CMP
);
828 trace_input ("setf", OP_EX1
, 0);
830 State
.regs
[ OP
[1] ] = condition_met (OP
[0]);
832 trace_output (OP_EX1
);
841 unsigned int op0
, op1
, result
, z
, s
, cy
, ov
, sat
;
843 trace_input ("satadd", OP_REG_REG
, 0);
844 /* Compute the result. */
845 op0
= State
.regs
[ OP
[0] ];
846 op1
= State
.regs
[ OP
[1] ];
849 /* Compute the condition codes. */
851 s
= (result
& 0x80000000);
852 cy
= (result
< op0
|| result
< op1
);
853 ov
= ((op0
& 0x80000000) == (op1
& 0x80000000)
854 && (op0
& 0x80000000) != (result
& 0x80000000));
857 /* Handle saturated results. */
860 /* An overflow that results in a negative result implies that we
861 became too positive. */
867 /* Any other overflow must have thus been too negative. */
873 /* Store the result and condition codes. */
874 State
.regs
[OP
[1]] = result
;
875 PSW
&= ~(PSW_Z
| PSW_S
| PSW_CY
| PSW_OV
);
876 PSW
|= ((z
? PSW_Z
: 0) | (s
? PSW_S
: 0)
877 | (cy
? PSW_CY
: 0) | (ov
? PSW_OV
: 0)
878 | (sat
? PSW_SAT
: 0));
880 trace_output (OP_REG_REG
);
885 /* satadd sign_extend(imm5), reg */
889 unsigned int op0
, op1
, result
, z
, s
, cy
, ov
, sat
;
893 trace_input ("satadd", OP_IMM_REG
, 0);
895 /* Compute the result. */
896 temp
= SEXT5 (OP
[0]);
898 op1
= State
.regs
[OP
[1]];
901 /* Compute the condition codes. */
903 s
= (result
& 0x80000000);
904 cy
= (result
< op0
|| result
< op1
);
905 ov
= ((op0
& 0x80000000) == (op1
& 0x80000000)
906 && (op0
& 0x80000000) != (result
& 0x80000000));
909 /* Handle saturated results. */
912 /* An overflow that results in a negative result implies that we
913 became too positive. */
919 /* Any other overflow must have thus been too negative. */
925 /* Store the result and condition codes. */
926 State
.regs
[OP
[1]] = result
;
927 PSW
&= ~(PSW_Z
| PSW_S
| PSW_CY
| PSW_OV
);
928 PSW
|= ((z
? PSW_Z
: 0) | (s
? PSW_S
: 0)
929 | (cy
? PSW_CY
: 0) | (ov
? PSW_OV
: 0)
930 | (sat
? PSW_SAT
: 0));
931 trace_output (OP_IMM_REG
);
936 /* satsub reg1, reg2 */
940 unsigned int op0
, op1
, result
, z
, s
, cy
, ov
, sat
;
942 trace_input ("satsub", OP_REG_REG
, 0);
944 /* Compute the result. */
945 op0
= State
.regs
[ OP
[0] ];
946 op1
= State
.regs
[ OP
[1] ];
949 /* Compute the condition codes. */
951 s
= (result
& 0x80000000);
953 ov
= ((op1
& 0x80000000) != (op0
& 0x80000000)
954 && (op1
& 0x80000000) != (result
& 0x80000000));
957 /* Handle saturated results. */
960 /* An overflow that results in a negative result implies that we
961 became too positive. */
967 /* Any other overflow must have thus been too negative. */
973 /* Store the result and condition codes. */
974 State
.regs
[OP
[1]] = result
;
975 PSW
&= ~(PSW_Z
| PSW_S
| PSW_CY
| PSW_OV
);
976 PSW
|= ((z
? PSW_Z
: 0) | (s
? PSW_S
: 0)
977 | (cy
? PSW_CY
: 0) | (ov
? PSW_OV
: 0)
978 | (sat
? PSW_SAT
: 0));
980 trace_output (OP_REG_REG
);
984 /* satsubi sign_extend(imm16), reg */
988 unsigned int op0
, op1
, result
, z
, s
, cy
, ov
, sat
;
991 trace_input ("satsubi", OP_IMM_REG
, 0);
993 /* Compute the result. */
994 temp
= EXTEND16 (OP
[2]);
996 op1
= State
.regs
[ OP
[0] ];
999 /* Compute the condition codes. */
1001 s
= (result
& 0x80000000);
1003 ov
= ((op1
& 0x80000000) != (op0
& 0x80000000)
1004 && (op1
& 0x80000000) != (result
& 0x80000000));
1007 /* Handle saturated results. */
1010 /* An overflow that results in a negative result implies that we
1011 became too positive. */
1012 result
= 0x7fffffff;
1017 /* Any other overflow must have thus been too negative. */
1018 result
= 0x80000000;
1023 /* Store the result and condition codes. */
1024 State
.regs
[OP
[1]] = result
;
1025 PSW
&= ~(PSW_Z
| PSW_S
| PSW_CY
| PSW_OV
);
1026 PSW
|= ((z
? PSW_Z
: 0) | (s
? PSW_S
: 0)
1027 | (cy
? PSW_CY
: 0) | (ov
? PSW_OV
: 0)
1028 | (sat
? PSW_SAT
: 0));
1030 trace_output (OP_IMM_REG
);
1035 /* satsubr reg,reg */
1039 unsigned int op0
, op1
, result
, z
, s
, cy
, ov
, sat
;
1041 trace_input ("satsubr", OP_REG_REG
, 0);
1043 /* Compute the result. */
1044 op0
= State
.regs
[ OP
[0] ];
1045 op1
= State
.regs
[ OP
[1] ];
1048 /* Compute the condition codes. */
1050 s
= (result
& 0x80000000);
1052 ov
= ((op0
& 0x80000000) != (op1
& 0x80000000)
1053 && (op0
& 0x80000000) != (result
& 0x80000000));
1056 /* Handle saturated results. */
1059 /* An overflow that results in a negative result implies that we
1060 became too positive. */
1061 result
= 0x7fffffff;
1066 /* Any other overflow must have thus been too negative. */
1067 result
= 0x80000000;
1072 /* Store the result and condition codes. */
1073 State
.regs
[OP
[1]] = result
;
1074 PSW
&= ~(PSW_Z
| PSW_S
| PSW_CY
| PSW_OV
);
1075 PSW
|= ((z
? PSW_Z
: 0) | (s
? PSW_S
: 0)
1076 | (cy
? PSW_CY
: 0) | (ov
? PSW_OV
: 0)
1077 | (sat
? PSW_SAT
: 0));
1079 trace_output (OP_REG_REG
);
1088 unsigned int op0
, op1
, result
, z
, s
;
1090 trace_input ("tst", OP_REG_REG_CMP
, 0);
1092 /* Compute the result. */
1093 op0
= State
.regs
[ OP
[0] ];
1094 op1
= State
.regs
[ OP
[1] ];
1097 /* Compute the condition codes. */
1099 s
= (result
& 0x80000000);
1101 /* Store the condition codes. */
1102 PSW
&= ~(PSW_Z
| PSW_S
| PSW_OV
);
1103 PSW
|= ((z
? PSW_Z
: 0) | (s
? PSW_S
: 0));
1104 trace_output (OP_REG_REG_CMP
);
1109 /* mov sign_extend(imm5), reg */
1113 int value
= SEXT5 (OP
[0]);
1115 trace_input ("mov", OP_IMM_REG_MOVE
, 0);
1117 State
.regs
[ OP
[1] ] = value
;
1119 trace_output (OP_IMM_REG_MOVE
);
1124 /* movhi imm16, reg, reg */
1128 trace_input ("movhi", OP_UIMM16_REG_REG
, 16);
1130 State
.regs
[ OP
[1] ] = State
.regs
[ OP
[0] ] + (OP
[2] << 16);
1132 trace_output (OP_UIMM16_REG_REG
);
1137 /* sar zero_extend(imm5),reg1 */
1141 unsigned int op0
, op1
, result
, z
, s
, cy
;
1143 trace_input ("sar", OP_IMM_REG
, 0);
1145 op1
= State
.regs
[ OP
[1] ];
1146 result
= (signed)op1
>> op0
;
1148 /* Compute the condition codes. */
1150 s
= (result
& 0x80000000);
1151 cy
= op0
? (op1
& (1 << (op0
- 1))) : 0;
1153 /* Store the result and condition codes. */
1154 State
.regs
[ OP
[1] ] = result
;
1155 PSW
&= ~(PSW_Z
| PSW_S
| PSW_OV
| PSW_CY
);
1156 PSW
|= ((z
? PSW_Z
: 0) | (s
? PSW_S
: 0)
1157 | (cy
? PSW_CY
: 0));
1158 trace_output (OP_IMM_REG
);
1163 /* sar reg1, reg2 */
1167 unsigned int op0
, op1
, result
, z
, s
, cy
;
1169 trace_input ("sar", OP_REG_REG
, 0);
1171 op0
= State
.regs
[ OP
[0] ] & 0x1f;
1172 op1
= State
.regs
[ OP
[1] ];
1173 result
= (signed)op1
>> op0
;
1175 /* Compute the condition codes. */
1177 s
= (result
& 0x80000000);
1178 cy
= op0
? (op1
& (1 << (op0
- 1))) : 0;
1180 /* Store the result and condition codes. */
1181 State
.regs
[OP
[1]] = result
;
1182 PSW
&= ~(PSW_Z
| PSW_S
| PSW_OV
| PSW_CY
);
1183 PSW
|= ((z
? PSW_Z
: 0) | (s
? PSW_S
: 0)
1184 | (cy
? PSW_CY
: 0));
1185 trace_output (OP_REG_REG
);
1190 /* shl zero_extend(imm5),reg1 */
1194 unsigned int op0
, op1
, result
, z
, s
, cy
;
1196 trace_input ("shl", OP_IMM_REG
, 0);
1198 op1
= State
.regs
[ OP
[1] ];
1199 result
= op1
<< op0
;
1201 /* Compute the condition codes. */
1203 s
= (result
& 0x80000000);
1204 cy
= op0
? (op1
& (1 << (32 - op0
))) : 0;
1206 /* Store the result and condition codes. */
1207 State
.regs
[OP
[1]] = result
;
1208 PSW
&= ~(PSW_Z
| PSW_S
| PSW_OV
| PSW_CY
);
1209 PSW
|= ((z
? PSW_Z
: 0) | (s
? PSW_S
: 0)
1210 | (cy
? PSW_CY
: 0));
1211 trace_output (OP_IMM_REG
);
1216 /* shl reg1, reg2 */
1220 unsigned int op0
, op1
, result
, z
, s
, cy
;
1222 trace_input ("shl", OP_REG_REG
, 0);
1223 op0
= State
.regs
[ OP
[0] ] & 0x1f;
1224 op1
= State
.regs
[ OP
[1] ];
1225 result
= op1
<< op0
;
1227 /* Compute the condition codes. */
1229 s
= (result
& 0x80000000);
1230 cy
= op0
? (op1
& (1 << (32 - op0
))) : 0;
1232 /* Store the result and condition codes. */
1233 State
.regs
[OP
[1]] = result
;
1234 PSW
&= ~(PSW_Z
| PSW_S
| PSW_OV
| PSW_CY
);
1235 PSW
|= ((z
? PSW_Z
: 0) | (s
? PSW_S
: 0)
1236 | (cy
? PSW_CY
: 0));
1237 trace_output (OP_REG_REG
);
1242 /* shr zero_extend(imm5),reg1 */
1246 unsigned int op0
, op1
, result
, z
, s
, cy
;
1248 trace_input ("shr", OP_IMM_REG
, 0);
1250 op1
= State
.regs
[ OP
[1] ];
1251 result
= op1
>> op0
;
1253 /* Compute the condition codes. */
1255 s
= (result
& 0x80000000);
1256 cy
= op0
? (op1
& (1 << (op0
- 1))) : 0;
1258 /* Store the result and condition codes. */
1259 State
.regs
[OP
[1]] = result
;
1260 PSW
&= ~(PSW_Z
| PSW_S
| PSW_OV
| PSW_CY
);
1261 PSW
|= ((z
? PSW_Z
: 0) | (s
? PSW_S
: 0)
1262 | (cy
? PSW_CY
: 0));
1263 trace_output (OP_IMM_REG
);
1268 /* shr reg1, reg2 */
1272 unsigned int op0
, op1
, result
, z
, s
, cy
;
1274 trace_input ("shr", OP_REG_REG
, 0);
1275 op0
= State
.regs
[ OP
[0] ] & 0x1f;
1276 op1
= State
.regs
[ OP
[1] ];
1277 result
= op1
>> op0
;
1279 /* Compute the condition codes. */
1281 s
= (result
& 0x80000000);
1282 cy
= op0
? (op1
& (1 << (op0
- 1))) : 0;
1284 /* Store the result and condition codes. */
1285 State
.regs
[OP
[1]] = result
;
1286 PSW
&= ~(PSW_Z
| PSW_S
| PSW_OV
| PSW_CY
);
1287 PSW
|= ((z
? PSW_Z
: 0) | (s
? PSW_S
: 0)
1288 | (cy
? PSW_CY
: 0));
1289 trace_output (OP_REG_REG
);
1298 unsigned int op0
, op1
, result
, z
, s
;
1300 trace_input ("or", OP_REG_REG
, 0);
1302 /* Compute the result. */
1303 op0
= State
.regs
[ OP
[0] ];
1304 op1
= State
.regs
[ OP
[1] ];
1307 /* Compute the condition codes. */
1309 s
= (result
& 0x80000000);
1311 /* Store the result and condition codes. */
1312 State
.regs
[OP
[1]] = result
;
1313 PSW
&= ~(PSW_Z
| PSW_S
| PSW_OV
);
1314 PSW
|= ((z
? PSW_Z
: 0) | (s
? PSW_S
: 0));
1315 trace_output (OP_REG_REG
);
1320 /* ori zero_extend(imm16), reg, reg */
1324 unsigned int op0
, op1
, result
, z
, s
;
1326 trace_input ("ori", OP_UIMM16_REG_REG
, 0);
1328 op1
= State
.regs
[ OP
[0] ];
1331 /* Compute the condition codes. */
1333 s
= (result
& 0x80000000);
1335 /* Store the result and condition codes. */
1336 State
.regs
[OP
[1]] = result
;
1337 PSW
&= ~(PSW_Z
| PSW_S
| PSW_OV
);
1338 PSW
|= ((z
? PSW_Z
: 0) | (s
? PSW_S
: 0));
1339 trace_output (OP_UIMM16_REG_REG
);
1348 unsigned int op0
, op1
, result
, z
, s
;
1350 trace_input ("and", OP_REG_REG
, 0);
1352 /* Compute the result. */
1353 op0
= State
.regs
[ OP
[0] ];
1354 op1
= State
.regs
[ OP
[1] ];
1357 /* Compute the condition codes. */
1359 s
= (result
& 0x80000000);
1361 /* Store the result and condition codes. */
1362 State
.regs
[OP
[1]] = result
;
1363 PSW
&= ~(PSW_Z
| PSW_S
| PSW_OV
);
1364 PSW
|= ((z
? PSW_Z
: 0) | (s
? PSW_S
: 0));
1365 trace_output (OP_REG_REG
);
1370 /* andi zero_extend(imm16), reg, reg */
1374 unsigned int result
, z
;
1376 trace_input ("andi", OP_UIMM16_REG_REG
, 0);
1378 result
= OP
[2] & State
.regs
[ OP
[0] ];
1380 /* Compute the condition codes. */
1383 /* Store the result and condition codes. */
1384 State
.regs
[ OP
[1] ] = result
;
1386 PSW
&= ~(PSW_Z
| PSW_S
| PSW_OV
);
1387 PSW
|= (z
? PSW_Z
: 0);
1389 trace_output (OP_UIMM16_REG_REG
);
1398 unsigned int op0
, op1
, result
, z
, s
;
1400 trace_input ("xor", OP_REG_REG
, 0);
1402 /* Compute the result. */
1403 op0
= State
.regs
[ OP
[0] ];
1404 op1
= State
.regs
[ OP
[1] ];
1407 /* Compute the condition codes. */
1409 s
= (result
& 0x80000000);
1411 /* Store the result and condition codes. */
1412 State
.regs
[OP
[1]] = result
;
1413 PSW
&= ~(PSW_Z
| PSW_S
| PSW_OV
);
1414 PSW
|= ((z
? PSW_Z
: 0) | (s
? PSW_S
: 0));
1415 trace_output (OP_REG_REG
);
1420 /* xori zero_extend(imm16), reg, reg */
1424 unsigned int op0
, op1
, result
, z
, s
;
1426 trace_input ("xori", OP_UIMM16_REG_REG
, 0);
1428 op1
= State
.regs
[ OP
[0] ];
1431 /* Compute the condition codes. */
1433 s
= (result
& 0x80000000);
1435 /* Store the result and condition codes. */
1436 State
.regs
[OP
[1]] = result
;
1437 PSW
&= ~(PSW_Z
| PSW_S
| PSW_OV
);
1438 PSW
|= ((z
? PSW_Z
: 0) | (s
? PSW_S
: 0));
1439 trace_output (OP_UIMM16_REG_REG
);
1444 /* not reg1, reg2 */
1448 unsigned int op0
, result
, z
, s
;
1450 trace_input ("not", OP_REG_REG_MOVE
, 0);
1451 /* Compute the result. */
1452 op0
= State
.regs
[ OP
[0] ];
1455 /* Compute the condition codes. */
1457 s
= (result
& 0x80000000);
1459 /* Store the result and condition codes. */
1460 State
.regs
[OP
[1]] = result
;
1461 PSW
&= ~(PSW_Z
| PSW_S
| PSW_OV
);
1462 PSW
|= ((z
? PSW_Z
: 0) | (s
? PSW_S
: 0));
1463 trace_output (OP_REG_REG_MOVE
);
1472 unsigned int op0
, op1
, op2
;
1475 trace_input ("set1", OP_BIT
, 0);
1476 op0
= State
.regs
[ OP
[0] ];
1478 temp
= EXTEND16 (OP
[2]);
1480 temp
= load_mem (op0
+ op2
, 1);
1482 if ((temp
& (1 << op1
)) == 0)
1485 store_mem (op0
+ op2
, 1, temp
);
1486 trace_output (OP_BIT
);
1495 unsigned int op0
, op1
, op2
;
1498 trace_input ("not1", OP_BIT
, 0);
1499 op0
= State
.regs
[ OP
[0] ];
1501 temp
= EXTEND16 (OP
[2]);
1503 temp
= load_mem (op0
+ op2
, 1);
1505 if ((temp
& (1 << op1
)) == 0)
1508 store_mem (op0
+ op2
, 1, temp
);
1509 trace_output (OP_BIT
);
1518 unsigned int op0
, op1
, op2
;
1521 trace_input ("clr1", OP_BIT
, 0);
1522 op0
= State
.regs
[ OP
[0] ];
1524 temp
= EXTEND16 (OP
[2]);
1526 temp
= load_mem (op0
+ op2
, 1);
1528 if ((temp
& (1 << op1
)) == 0)
1530 temp
&= ~(1 << op1
);
1531 store_mem (op0
+ op2
, 1, temp
);
1532 trace_output (OP_BIT
);
1541 unsigned int op0
, op1
, op2
;
1544 trace_input ("tst1", OP_BIT
, 0);
1545 op0
= State
.regs
[ OP
[0] ];
1547 temp
= EXTEND16 (OP
[2]);
1549 temp
= load_mem (op0
+ op2
, 1);
1551 if ((temp
& (1 << op1
)) == 0)
1553 trace_output (OP_BIT
);
1562 trace_input ("di", OP_NONE
, 0);
1564 trace_output (OP_NONE
);
1573 trace_input ("ei", OP_NONE
, 0);
1575 trace_output (OP_NONE
);
1584 trace_input ("halt", OP_NONE
, 0);
1585 /* FIXME this should put processor into a mode where NMI still handled */
1586 trace_output (OP_NONE
);
1587 sim_engine_halt (simulator
, STATE_CPU (simulator
, 0), NULL
, PC
,
1588 sim_stopped
, SIM_SIGTRAP
);
1596 trace_input ("trap", OP_TRAP
, 0);
1597 trace_output (OP_TRAP
);
1599 /* Trap 31 is used for simulating OS I/O functions */
1603 int save_errno
= errno
;
1606 /* Registers passed to trap 0 */
1608 #define FUNC State.regs[6] /* function number, return value */
1609 #define PARM1 State.regs[7] /* optional parm 1 */
1610 #define PARM2 State.regs[8] /* optional parm 2 */
1611 #define PARM3 State.regs[9] /* optional parm 3 */
1613 /* Registers set by trap 0 */
1615 #define RETVAL State.regs[10] /* return value */
1616 #define RETERR State.regs[11] /* return error code */
1618 /* Turn a pointer in a register into a pointer into real memory. */
1620 #define MEMPTR(x) (map (x))
1628 #ifdef TARGET_SYS_fork
1629 case TARGET_SYS_fork
:
1637 #ifdef TARGET_SYS_execv
1638 case TARGET_SYS_execve
:
1640 char *path
= fetch_str (simulator
, PARM1
);
1641 char **argv
= fetch_argv (simulator
, PARM2
);
1642 char **envp
= fetch_argv (simulator
, PARM3
);
1643 RETVAL
= execve (path
, (void *)argv
, (void *)envp
);
1654 #ifdef TARGET_SYS_execv
1655 case TARGET_SYS_execv
:
1657 char *path
= fetch_str (simulator
, PARM1
);
1658 char **argv
= fetch_argv (simulator
, PARM2
);
1659 RETVAL
= execv (path
, (void *)argv
);
1669 #ifdef TARGET_SYS_pipe
1670 case TARGET_SYS_pipe
:
1676 RETVAL
= pipe (host_fd
);
1677 SW (buf
, host_fd
[0]);
1678 buf
+= sizeof (uint16
);
1679 SW (buf
, host_fd
[1]);
1687 #ifdef TARGET_SYS_wait
1688 case TARGET_SYS_wait
:
1692 RETVAL
= wait (&status
);
1700 #ifdef TARGET_SYS_read
1701 case TARGET_SYS_read
:
1703 char *buf
= zalloc (PARM3
);
1704 RETVAL
= sim_io_read (simulator
, PARM1
, buf
, PARM3
);
1705 sim_write (simulator
, PARM2
, (unsigned char *) buf
, PARM3
);
1707 if ((int) RETVAL
< 0)
1708 RETERR
= sim_io_get_errno (simulator
);
1713 #ifdef TARGET_SYS_write
1714 case TARGET_SYS_write
:
1716 char *buf
= zalloc (PARM3
);
1717 sim_read (simulator
, PARM2
, (unsigned char *) buf
, PARM3
);
1719 RETVAL
= sim_io_write_stdout (simulator
, buf
, PARM3
);
1721 RETVAL
= sim_io_write (simulator
, PARM1
, buf
, PARM3
);
1723 if ((int) RETVAL
< 0)
1724 RETERR
= sim_io_get_errno (simulator
);
1729 #ifdef TARGET_SYS_lseek
1730 case TARGET_SYS_lseek
:
1731 RETVAL
= sim_io_lseek (simulator
, PARM1
, PARM2
, PARM3
);
1732 if ((int) RETVAL
< 0)
1733 RETERR
= sim_io_get_errno (simulator
);
1737 #ifdef TARGET_SYS_close
1738 case TARGET_SYS_close
:
1739 RETVAL
= sim_io_close (simulator
, PARM1
);
1740 if ((int) RETVAL
< 0)
1741 RETERR
= sim_io_get_errno (simulator
);
1745 #ifdef TARGET_SYS_open
1746 case TARGET_SYS_open
:
1748 char *buf
= fetch_str (simulator
, PARM1
);
1749 RETVAL
= sim_io_open (simulator
, buf
, PARM2
);
1751 if ((int) RETVAL
< 0)
1752 RETERR
= sim_io_get_errno (simulator
);
1757 #ifdef TARGET_SYS_exit
1758 case TARGET_SYS_exit
:
1759 if ((PARM1
& 0xffff0000) == 0xdead0000 && (PARM1
& 0xffff) != 0)
1760 /* get signal encoded by kill */
1761 sim_engine_halt (simulator
, STATE_CPU (simulator
, 0), NULL
, PC
,
1762 sim_signalled
, PARM1
& 0xffff);
1763 else if (PARM1
== 0xdead)
1765 sim_engine_halt (simulator
, STATE_CPU (simulator
, 0), NULL
, PC
,
1766 sim_stopped
, SIM_SIGABRT
);
1768 /* PARM1 has exit status */
1769 sim_engine_halt (simulator
, STATE_CPU (simulator
, 0), NULL
, PC
,
1774 #ifdef TARGET_SYS_stat
1775 case TARGET_SYS_stat
: /* added at hmsi */
1776 /* stat system call */
1778 struct stat host_stat
;
1780 char *path
= fetch_str (simulator
, PARM1
);
1782 RETVAL
= sim_io_stat (simulator
, path
, &host_stat
);
1787 /* Just wild-assed guesses. */
1788 store_mem (buf
, 2, host_stat
.st_dev
);
1789 store_mem (buf
+ 2, 2, host_stat
.st_ino
);
1790 store_mem (buf
+ 4, 4, host_stat
.st_mode
);
1791 store_mem (buf
+ 8, 2, host_stat
.st_nlink
);
1792 store_mem (buf
+ 10, 2, host_stat
.st_uid
);
1793 store_mem (buf
+ 12, 2, host_stat
.st_gid
);
1794 store_mem (buf
+ 14, 2, host_stat
.st_rdev
);
1795 store_mem (buf
+ 16, 4, host_stat
.st_size
);
1796 store_mem (buf
+ 20, 4, host_stat
.st_atime
);
1797 store_mem (buf
+ 28, 4, host_stat
.st_mtime
);
1798 store_mem (buf
+ 36, 4, host_stat
.st_ctime
);
1800 if ((int) RETVAL
< 0)
1801 RETERR
= sim_io_get_errno (simulator
);
1806 #ifdef TARGET_SYS_fstat
1807 case TARGET_SYS_fstat
:
1808 /* fstat system call */
1810 struct stat host_stat
;
1813 RETVAL
= sim_io_fstat (simulator
, PARM1
, &host_stat
);
1817 /* Just wild-assed guesses. */
1818 store_mem (buf
, 2, host_stat
.st_dev
);
1819 store_mem (buf
+ 2, 2, host_stat
.st_ino
);
1820 store_mem (buf
+ 4, 4, host_stat
.st_mode
);
1821 store_mem (buf
+ 8, 2, host_stat
.st_nlink
);
1822 store_mem (buf
+ 10, 2, host_stat
.st_uid
);
1823 store_mem (buf
+ 12, 2, host_stat
.st_gid
);
1824 store_mem (buf
+ 14, 2, host_stat
.st_rdev
);
1825 store_mem (buf
+ 16, 4, host_stat
.st_size
);
1826 store_mem (buf
+ 20, 4, host_stat
.st_atime
);
1827 store_mem (buf
+ 28, 4, host_stat
.st_mtime
);
1828 store_mem (buf
+ 36, 4, host_stat
.st_ctime
);
1830 if ((int) RETVAL
< 0)
1831 RETERR
= sim_io_get_errno (simulator
);
1836 #ifdef TARGET_SYS_rename
1837 case TARGET_SYS_rename
:
1839 char *oldpath
= fetch_str (simulator
, PARM1
);
1840 char *newpath
= fetch_str (simulator
, PARM2
);
1841 RETVAL
= sim_io_rename (simulator
, oldpath
, newpath
);
1844 if ((int) RETVAL
< 0)
1845 RETERR
= sim_io_get_errno (simulator
);
1850 #ifdef TARGET_SYS_unlink
1851 case TARGET_SYS_unlink
:
1853 char *path
= fetch_str (simulator
, PARM1
);
1854 RETVAL
= sim_io_unlink (simulator
, path
);
1856 if ((int) RETVAL
< 0)
1857 RETERR
= sim_io_get_errno (simulator
);
1862 #ifdef TARGET_SYS_chown
1863 case TARGET_SYS_chown
:
1865 char *path
= fetch_str (simulator
, PARM1
);
1866 RETVAL
= chown (path
, PARM2
, PARM3
);
1874 #ifdef TARGET_SYS_chmod
1875 case TARGET_SYS_chmod
:
1877 char *path
= fetch_str (simulator
, PARM1
);
1878 RETVAL
= chmod (path
, PARM2
);
1886 #ifdef TARGET_SYS_time
1888 case TARGET_SYS_time
:
1891 RETVAL
= time (&now
);
1892 store_mem (PARM1
, 4, now
);
1899 #if !defined(__GO32__) && !defined(_WIN32)
1900 #ifdef TARGET_SYS_times
1901 case TARGET_SYS_times
:
1904 RETVAL
= times (&tms
);
1905 store_mem (PARM1
, 4, tms
.tms_utime
);
1906 store_mem (PARM1
+ 4, 4, tms
.tms_stime
);
1907 store_mem (PARM1
+ 8, 4, tms
.tms_cutime
);
1908 store_mem (PARM1
+ 12, 4, tms
.tms_cstime
);
1915 #ifdef TARGET_SYS_gettimeofday
1916 #if !defined(__GO32__) && !defined(_WIN32)
1917 case TARGET_SYS_gettimeofday
:
1921 RETVAL
= gettimeofday (&t
, &tz
);
1922 store_mem (PARM1
, 4, t
.tv_sec
);
1923 store_mem (PARM1
+ 4, 4, t
.tv_usec
);
1924 store_mem (PARM2
, 4, tz
.tz_minuteswest
);
1925 store_mem (PARM2
+ 4, 4, tz
.tz_dsttime
);
1932 #ifdef TARGET_SYS_utime
1934 case TARGET_SYS_utime
:
1936 /* Cast the second argument to void *, to avoid type mismatch
1937 if a prototype is present. */
1938 sim_io_error (simulator
, "Utime not supported");
1939 /* RETVAL = utime (path, (void *) MEMPTR (PARM2)); */
1953 { /* Trap 0 -> 30 */
1958 ECR
|= 0x40 + OP
[0];
1959 /* Flag that we are now doing exception processing. */
1960 PSW
|= PSW_EP
| PSW_ID
;
1961 PC
= (OP
[0] < 0x10) ? 0x40 : 0x50;
1967 /* tst1 reg2, [reg1] */
1973 trace_input ("tst1", OP_BIT
, 1);
1975 temp
= load_mem (State
.regs
[ OP
[0] ], 1);
1978 if ((temp
& (1 << (State
.regs
[ OP
[1] ] & 0x7))) == 0)
1981 trace_output (OP_BIT
);
1986 /* mulu reg1, reg2, reg3 */
1990 trace_input ("mulu", OP_REG_REG_REG
, 0);
1992 Multiply64 (0, State
.regs
[ OP
[0] ]);
1994 trace_output (OP_REG_REG_REG
);
1999 #define BIT_CHANGE_OP( name, binop ) \
2001 unsigned int temp; \
2003 trace_input (name, OP_BIT_CHANGE, 0); \
2005 bit = 1 << (State.regs[ OP[1] ] & 0x7); \
2006 temp = load_mem (State.regs[ OP[0] ], 1); \
2009 if ((temp & bit) == 0) \
2013 store_mem (State.regs[ OP[0] ], 1, temp); \
2015 trace_output (OP_BIT_CHANGE); \
2019 /* clr1 reg2, [reg1] */
2023 BIT_CHANGE_OP ("clr1", &= ~ );
2026 /* not1 reg2, [reg1] */
2030 BIT_CHANGE_OP ("not1", ^= );
2037 BIT_CHANGE_OP ("set1", |= );
2044 trace_input ("sasf", OP_EX1
, 0);
2046 State
.regs
[ OP
[1] ] = (State
.regs
[ OP
[1] ] << 1) | condition_met (OP
[0]);
2048 trace_output (OP_EX1
);
2053 /* This function is courtesy of Sugimoto at NEC, via Seow Tan
2054 (Soew_Tan@el.nec.com) */
2059 unsigned long int als
,
2060 unsigned long int sfi
,
2061 unsigned32
/*unsigned long int*/ * quotient_ptr
,
2062 unsigned32
/*unsigned long int*/ * remainder_ptr
,
2066 unsigned long ald
= sfi
>> (N
- 1);
2067 unsigned long alo
= als
;
2072 unsigned int R1
= 1;
2073 unsigned int DBZ
= (als
== 0) ? 1 : 0;
2074 unsigned long alt
= Q
? ~als
: als
;
2077 alo
= ald
+ alt
+ Q
;
2078 C
= (((alt
>> 31) & (ald
>> 31))
2079 | (((alt
>> 31) ^ (ald
>> 31)) & (~alo
>> 31)));
2082 R1
= (alo
== 0) ? 0 : (R1
& Q
);
2083 if ((S
^ (alo
>>31)) && !C
)
2088 sfi
= (sfi
<< (32-N
+1)) | Q
;
2089 ald
= (alo
<< 1) | (sfi
>> 31);
2091 /* 2nd - N-1th Loop */
2092 for (i
= 2; i
< N
; i
++)
2094 alt
= Q
? ~als
: als
;
2095 alo
= ald
+ alt
+ Q
;
2096 C
= (((alt
>> 31) & (ald
>> 31))
2097 | (((alt
>> 31) ^ (ald
>> 31)) & (~alo
>> 31)));
2100 R1
= (alo
== 0) ? 0 : (R1
& Q
);
2101 if ((S
^ (alo
>>31)) && !C
&& !DBZ
)
2106 sfi
= (sfi
<< 1) | Q
;
2107 ald
= (alo
<< 1) | (sfi
>> 31);
2111 alt
= Q
? ~als
: als
;
2112 alo
= ald
+ alt
+ Q
;
2113 C
= (((alt
>> 31) & (ald
>> 31))
2114 | (((alt
>> 31) ^ (ald
>> 31)) & (~alo
>> 31)));
2117 R1
= (alo
== 0) ? 0 : (R1
& Q
);
2118 if ((S
^ (alo
>>31)) && !C
)
2123 * quotient_ptr
= (sfi
<< 1) | Q
;
2124 * remainder_ptr
= Q
? alo
: (alo
+ als
);
2125 * overflow_ptr
= DBZ
| R1
;
2128 /* This function is courtesy of Sugimoto at NEC, via Seow Tan (Soew_Tan@el.nec.com) */
2133 unsigned long int als
,
2134 unsigned long int sfi
,
2135 signed32
/*signed long int*/ * quotient_ptr
,
2136 signed32
/*signed long int*/ * remainder_ptr
,
2140 unsigned long ald
= (signed long) sfi
>> (N
- 1);
2141 unsigned long alo
= als
;
2142 unsigned int SS
= als
>> 31;
2143 unsigned int SD
= sfi
>> 31;
2144 unsigned int R1
= 1;
2146 unsigned int DBZ
= als
== 0 ? 1 : 0;
2147 unsigned int Q
= ~(SS
^ SD
) & 1;
2151 unsigned long alt
= Q
? ~als
: als
;
2156 alo
= ald
+ alt
+ Q
;
2157 C
= (((alt
>> 31) & (ald
>> 31))
2158 | (((alt
>> 31) ^ (ald
>> 31)) & (~alo
>> 31)));
2160 R1
= (alo
== 0) ? 0 : (R1
& (Q
^ (SS
^ SD
)));
2162 sfi
= (sfi
<< (32-N
+1)) | Q
;
2163 ald
= (alo
<< 1) | (sfi
>> 31);
2164 if ((alo
>> 31) ^ (ald
>> 31))
2169 /* 2nd - N-1th Loop */
2171 for (i
= 2; i
< N
; i
++)
2173 alt
= Q
? ~als
: als
;
2174 alo
= ald
+ alt
+ Q
;
2175 C
= (((alt
>> 31) & (ald
>> 31))
2176 | (((alt
>> 31) ^ (ald
>> 31)) & (~alo
>> 31)));
2178 R1
= (alo
== 0) ? 0 : (R1
& (Q
^ (SS
^ SD
)));
2180 sfi
= (sfi
<< 1) | Q
;
2181 ald
= (alo
<< 1) | (sfi
>> 31);
2182 if ((alo
>> 31) ^ (ald
>> 31))
2189 alt
= Q
? ~als
: als
;
2190 alo
= ald
+ alt
+ Q
;
2191 C
= (((alt
>> 31) & (ald
>> 31))
2192 | (((alt
>> 31) ^ (ald
>> 31)) & (~alo
>> 31)));
2194 R1
= (alo
== 0) ? 0 : (R1
& (Q
^ (SS
^ SD
)));
2195 sfi
= (sfi
<< (32-N
+1));
2201 alt
= Q
? ~als
: als
;
2202 alo
= ald
+ alt
+ Q
;
2204 R1
= R1
& ((~alo
>> 31) ^ SD
);
2205 if ((alo
!= 0) && ((Q
^ (SS
^ SD
)) ^ R1
)) alo
= ald
;
2207 ald
= sfi
= (long) ((sfi
>> 1) | (SS
^ SD
) << 31) >> (32-N
-1) | Q
;
2209 ald
= sfi
= sfi
| Q
;
2211 OV
= DBZ
| ((alo
== 0) ? 0 : R1
);
2213 * remainder_ptr
= alo
;
2216 if (((alo
!= 0) && ((SS
^ SD
) ^ R1
))
2217 || ((alo
== 0) && (SS
^ R1
)))
2222 OV
= (DBZ
| R1
) ? OV
: ((alo
>> 31) & (~ald
>> 31));
2224 * quotient_ptr
= alo
;
2225 * overflow_ptr
= OV
;
2228 /* sdivun imm5, reg1, reg2, reg3 */
2232 unsigned32
/*unsigned long int*/ quotient
;
2233 unsigned32
/*unsigned long int*/ remainder
;
2234 unsigned long int divide_by
;
2235 unsigned long int divide_this
;
2239 trace_input ("sdivun", OP_IMM_REG_REG_REG
, 0);
2241 imm5
= 32 - ((OP
[3] & 0x3c0000) >> 17);
2243 divide_by
= State
.regs
[ OP
[0] ];
2244 divide_this
= State
.regs
[ OP
[1] ] << imm5
;
2246 divun (imm5
, divide_by
, divide_this
, & quotient
, & remainder
, & overflow
);
2248 State
.regs
[ OP
[1] ] = quotient
;
2249 State
.regs
[ OP
[2] >> 11 ] = remainder
;
2251 /* Set condition codes. */
2252 PSW
&= ~(PSW_Z
| PSW_S
| PSW_OV
);
2254 if (overflow
) PSW
|= PSW_OV
;
2255 if (quotient
== 0) PSW
|= PSW_Z
;
2256 if (quotient
& 0x80000000) PSW
|= PSW_S
;
2258 trace_output (OP_IMM_REG_REG_REG
);
2263 /* sdivn imm5, reg1, reg2, reg3 */
2267 signed32
/*signed long int*/ quotient
;
2268 signed32
/*signed long int*/ remainder
;
2269 signed long int divide_by
;
2270 signed long int divide_this
;
2274 trace_input ("sdivn", OP_IMM_REG_REG_REG
, 0);
2276 imm5
= 32 - ((OP
[3] & 0x3c0000) >> 17);
2278 divide_by
= (signed32
) State
.regs
[ OP
[0] ];
2279 divide_this
= (signed32
) (State
.regs
[ OP
[1] ] << imm5
);
2281 divn (imm5
, divide_by
, divide_this
, & quotient
, & remainder
, & overflow
);
2283 State
.regs
[ OP
[1] ] = quotient
;
2284 State
.regs
[ OP
[2] >> 11 ] = remainder
;
2286 /* Set condition codes. */
2287 PSW
&= ~(PSW_Z
| PSW_S
| PSW_OV
);
2289 if (overflow
) PSW
|= PSW_OV
;
2290 if (quotient
== 0) PSW
|= PSW_Z
;
2291 if (quotient
< 0) PSW
|= PSW_S
;
2293 trace_output (OP_IMM_REG_REG_REG
);
2298 /* sdivhun imm5, reg1, reg2, reg3 */
2302 unsigned32
/*unsigned long int*/ quotient
;
2303 unsigned32
/*unsigned long int*/ remainder
;
2304 unsigned long int divide_by
;
2305 unsigned long int divide_this
;
2309 trace_input ("sdivhun", OP_IMM_REG_REG_REG
, 0);
2311 imm5
= 32 - ((OP
[3] & 0x3c0000) >> 17);
2313 divide_by
= State
.regs
[ OP
[0] ] & 0xffff;
2314 divide_this
= State
.regs
[ OP
[1] ] << imm5
;
2316 divun (imm5
, divide_by
, divide_this
, & quotient
, & remainder
, & overflow
);
2318 State
.regs
[ OP
[1] ] = quotient
;
2319 State
.regs
[ OP
[2] >> 11 ] = remainder
;
2321 /* Set condition codes. */
2322 PSW
&= ~(PSW_Z
| PSW_S
| PSW_OV
);
2324 if (overflow
) PSW
|= PSW_OV
;
2325 if (quotient
== 0) PSW
|= PSW_Z
;
2326 if (quotient
& 0x80000000) PSW
|= PSW_S
;
2328 trace_output (OP_IMM_REG_REG_REG
);
2333 /* sdivhn imm5, reg1, reg2, reg3 */
2337 signed32
/*signed long int*/ quotient
;
2338 signed32
/*signed long int*/ remainder
;
2339 signed long int divide_by
;
2340 signed long int divide_this
;
2344 trace_input ("sdivhn", OP_IMM_REG_REG_REG
, 0);
2346 imm5
= 32 - ((OP
[3] & 0x3c0000) >> 17);
2348 divide_by
= EXTEND16 (State
.regs
[ OP
[0] ]);
2349 divide_this
= (signed32
) (State
.regs
[ OP
[1] ] << imm5
);
2351 divn (imm5
, divide_by
, divide_this
, & quotient
, & remainder
, & overflow
);
2353 State
.regs
[ OP
[1] ] = quotient
;
2354 State
.regs
[ OP
[2] >> 11 ] = remainder
;
2356 /* Set condition codes. */
2357 PSW
&= ~(PSW_Z
| PSW_S
| PSW_OV
);
2359 if (overflow
) PSW
|= PSW_OV
;
2360 if (quotient
== 0) PSW
|= PSW_Z
;
2361 if (quotient
< 0) PSW
|= PSW_S
;
2363 trace_output (OP_IMM_REG_REG_REG
);
2368 /* divu reg1, reg2, reg3 */
2372 unsigned long int quotient
;
2373 unsigned long int remainder
;
2374 unsigned long int divide_by
;
2375 unsigned long int divide_this
;
2378 trace_input ("divu", OP_REG_REG_REG
, 0);
2380 /* Compute the result. */
2382 divide_by
= State
.regs
[ OP
[0] ];
2383 divide_this
= State
.regs
[ OP
[1] ];
2391 State
.regs
[ OP
[1] ] = quotient
= divide_this
/ divide_by
;
2392 State
.regs
[ OP
[2] >> 11 ] = remainder
= divide_this
% divide_by
;
2394 /* Set condition codes. */
2395 PSW
&= ~(PSW_Z
| PSW_S
| PSW_OV
);
2397 if (overflow
) PSW
|= PSW_OV
;
2398 if (quotient
== 0) PSW
|= PSW_Z
;
2399 if (quotient
& 0x80000000) PSW
|= PSW_S
;
2402 trace_output (OP_REG_REG_REG
);
2407 /* div reg1, reg2, reg3 */
2411 signed long int quotient
;
2412 signed long int remainder
;
2413 signed long int divide_by
;
2414 signed long int divide_this
;
2416 trace_input ("div", OP_REG_REG_REG
, 0);
2418 /* Compute the result. */
2420 divide_by
= (signed32
) State
.regs
[ OP
[0] ];
2421 divide_this
= State
.regs
[ OP
[1] ];
2427 else if (divide_by
== -1 && divide_this
== (1L << 31))
2430 PSW
|= PSW_OV
| PSW_S
;
2431 State
.regs
[ OP
[1] ] = (1 << 31);
2432 State
.regs
[ OP
[2] >> 11 ] = 0;
2436 divide_this
= (signed32
) divide_this
;
2437 State
.regs
[ OP
[1] ] = quotient
= divide_this
/ divide_by
;
2438 State
.regs
[ OP
[2] >> 11 ] = remainder
= divide_this
% divide_by
;
2440 /* Set condition codes. */
2441 PSW
&= ~(PSW_Z
| PSW_S
| PSW_OV
);
2443 if (quotient
== 0) PSW
|= PSW_Z
;
2444 if (quotient
< 0) PSW
|= PSW_S
;
2447 trace_output (OP_REG_REG_REG
);
2452 /* divhu reg1, reg2, reg3 */
2456 unsigned long int quotient
;
2457 unsigned long int remainder
;
2458 unsigned long int divide_by
;
2459 unsigned long int divide_this
;
2462 trace_input ("divhu", OP_REG_REG_REG
, 0);
2464 /* Compute the result. */
2466 divide_by
= State
.regs
[ OP
[0] ] & 0xffff;
2467 divide_this
= State
.regs
[ OP
[1] ];
2475 State
.regs
[ OP
[1] ] = quotient
= divide_this
/ divide_by
;
2476 State
.regs
[ OP
[2] >> 11 ] = remainder
= divide_this
% divide_by
;
2478 /* Set condition codes. */
2479 PSW
&= ~(PSW_Z
| PSW_S
| PSW_OV
);
2481 if (overflow
) PSW
|= PSW_OV
;
2482 if (quotient
== 0) PSW
|= PSW_Z
;
2483 if (quotient
& 0x80000000) PSW
|= PSW_S
;
2486 trace_output (OP_REG_REG_REG
);
2491 /* divh reg1, reg2, reg3 */
2495 signed long int quotient
;
2496 signed long int remainder
;
2497 signed long int divide_by
;
2498 signed long int divide_this
;
2501 trace_input ("divh", OP_REG_REG_REG
, 0);
2503 /* Compute the result. */
2505 divide_by
= EXTEND16 (State
.regs
[ OP
[0] ]);
2506 divide_this
= State
.regs
[ OP
[1] ];
2512 else if (divide_by
== -1 && divide_this
== (1L << 31))
2515 PSW
|= PSW_OV
| PSW_S
;
2516 State
.regs
[ OP
[1] ] = (1 << 31);
2517 State
.regs
[ OP
[2] >> 11 ] = 0;
2521 divide_this
= (signed32
) divide_this
;
2522 State
.regs
[ OP
[1] ] = quotient
= divide_this
/ divide_by
;
2523 State
.regs
[ OP
[2] >> 11 ] = remainder
= divide_this
% divide_by
;
2525 /* Set condition codes. */
2526 PSW
&= ~(PSW_Z
| PSW_S
| PSW_OV
);
2528 if (quotient
== 0) PSW
|= PSW_Z
;
2529 if (quotient
< 0) PSW
|= PSW_S
;
2532 trace_output (OP_REG_REG_REG
);
2537 /* mulu imm9, reg2, reg3 */
2541 trace_input ("mulu", OP_IMM_REG_REG
, 0);
2543 Multiply64 (0, (OP
[3] & 0x1f) | ((OP
[3] >> 13) & 0x1e0));
2545 trace_output (OP_IMM_REG_REG
);
2550 /* mul imm9, reg2, reg3 */
2554 trace_input ("mul", OP_IMM_REG_REG
, 0);
2556 Multiply64 (1, SEXT9 ((OP
[3] & 0x1f) | ((OP
[3] >> 13) & 0x1e0)));
2558 trace_output (OP_IMM_REG_REG
);
2569 trace_input ("ld.hu", OP_LOAD32
, 2);
2571 adr
= State
.regs
[ OP
[0] ] + EXTEND16 (OP
[2] & ~1);
2574 State
.regs
[ OP
[1] ] = load_mem (adr
, 2);
2576 trace_output (OP_LOAD32
);
2588 trace_input ("ld.bu", OP_LOAD32
, 1);
2590 adr
= (State
.regs
[ OP
[0] ]
2591 + (EXTEND16 (OP
[2] & ~1) | ((OP
[3] >> 5) & 1)));
2593 State
.regs
[ OP
[1] ] = load_mem (adr
, 1);
2595 trace_output (OP_LOAD32
);
2600 /* prepare list12, imm5, imm32 */
2606 trace_input ("prepare", OP_PUSHPOP1
, 0);
2608 /* Store the registers with lower number registers being placed at higher addresses. */
2609 for (i
= 0; i
< 12; i
++)
2610 if ((OP
[3] & (1 << type1_regs
[ i
])))
2613 store_mem (SP
, 4, State
.regs
[ 20 + i
]);
2616 SP
-= (OP
[3] & 0x3e) << 1;
2618 EP
= load_mem (PC
+ 4, 4);
2620 trace_output (OP_PUSHPOP1
);
2625 /* prepare list12, imm5, imm16-32 */
2631 trace_input ("prepare", OP_PUSHPOP1
, 0);
2633 /* Store the registers with lower number registers being placed at higher addresses. */
2634 for (i
= 0; i
< 12; i
++)
2635 if ((OP
[3] & (1 << type1_regs
[ i
])))
2638 store_mem (SP
, 4, State
.regs
[ 20 + i
]);
2641 SP
-= (OP
[3] & 0x3e) << 1;
2643 EP
= load_mem (PC
+ 4, 2) << 16;
2645 trace_output (OP_PUSHPOP1
);
2650 /* prepare list12, imm5, imm16 */
2656 trace_input ("prepare", OP_PUSHPOP1
, 0);
2658 /* Store the registers with lower number registers being placed at higher addresses. */
2659 for (i
= 0; i
< 12; i
++)
2660 if ((OP
[3] & (1 << type1_regs
[ i
])))
2663 store_mem (SP
, 4, State
.regs
[ 20 + i
]);
2666 SP
-= (OP
[3] & 0x3e) << 1;
2668 EP
= EXTEND16 (load_mem (PC
+ 4, 2));
2670 trace_output (OP_PUSHPOP1
);
2675 /* prepare list12, imm5, sp */
2681 trace_input ("prepare", OP_PUSHPOP1
, 0);
2683 /* Store the registers with lower number registers being placed at higher addresses. */
2684 for (i
= 0; i
< 12; i
++)
2685 if ((OP
[3] & (1 << type1_regs
[ i
])))
2688 store_mem (SP
, 4, State
.regs
[ 20 + i
]);
2691 SP
-= (OP
[3] & 0x3e) << 1;
2695 trace_output (OP_PUSHPOP1
);
2700 /* mul reg1, reg2, reg3 */
2704 trace_input ("mul", OP_REG_REG_REG
, 0);
2706 Multiply64 (1, State
.regs
[ OP
[0] ]);
2708 trace_output (OP_REG_REG_REG
);
2719 trace_input ("popmh", OP_PUSHPOP2
, 0);
2721 if (OP
[3] & (1 << 19))
2723 if ((PSW
& PSW_NP
) && ((PSW
& PSW_EP
) == 0))
2725 FEPSW
= load_mem ( SP
& ~ 3, 4);
2726 FEPC
= load_mem ((SP
+ 4) & ~ 3, 4);
2730 EIPSW
= load_mem ( SP
& ~ 3, 4);
2731 EIPC
= load_mem ((SP
+ 4) & ~ 3, 4);
2737 /* Load the registers with lower number registers being retrieved from higher addresses. */
2739 if ((OP
[3] & (1 << type2_regs
[ i
])))
2741 State
.regs
[ i
+ 16 ] = load_mem (SP
& ~ 3, 4);
2745 trace_output (OP_PUSHPOP2
);
2756 trace_input ("popml", OP_PUSHPOP3
, 0);
2758 if (OP
[3] & (1 << 19))
2760 if ((PSW
& PSW_NP
) && ((PSW
& PSW_EP
) == 0))
2762 FEPSW
= load_mem ( SP
& ~ 3, 4);
2763 FEPC
= load_mem ((SP
+ 4) & ~ 3, 4);
2767 EIPSW
= load_mem ( SP
& ~ 3, 4);
2768 EIPC
= load_mem ((SP
+ 4) & ~ 3, 4);
2774 if (OP
[3] & (1 << 3))
2776 PSW
= load_mem (SP
& ~ 3, 4);
2780 /* Load the registers with lower number registers being retrieved from higher addresses. */
2782 if ((OP
[3] & (1 << type3_regs
[ i
])))
2784 State
.regs
[ i
+ 1 ] = load_mem (SP
& ~ 3, 4);
2788 trace_output (OP_PUSHPOP2
);
2799 trace_input ("pushmh", OP_PUSHPOP2
, 0);
2801 /* Store the registers with lower number registers being placed at higher addresses. */
2802 for (i
= 0; i
< 16; i
++)
2803 if ((OP
[3] & (1 << type2_regs
[ i
])))
2806 store_mem (SP
& ~ 3, 4, State
.regs
[ i
+ 16 ]);
2809 if (OP
[3] & (1 << 19))
2813 if ((PSW
& PSW_NP
) && ((PSW
& PSW_EP
) == 0))
2815 store_mem ((SP
+ 4) & ~ 3, 4, FEPC
);
2816 store_mem ( SP
& ~ 3, 4, FEPSW
);
2820 store_mem ((SP
+ 4) & ~ 3, 4, EIPC
);
2821 store_mem ( SP
& ~ 3, 4, EIPSW
);
2825 trace_output (OP_PUSHPOP2
);
2830 /* V850E2R FPU functions */
2832 sim_fpu_status_invalid_snan = 1, -V--- (sim spec.)
2833 sim_fpu_status_invalid_qnan = 2, ----- (sim spec.)
2834 sim_fpu_status_invalid_isi = 4, (inf - inf) -V---
2835 sim_fpu_status_invalid_idi = 8, (inf / inf) -V---
2836 sim_fpu_status_invalid_zdz = 16, (0 / 0) -V---
2837 sim_fpu_status_invalid_imz = 32, (inf * 0) -V---
2838 sim_fpu_status_invalid_cvi = 64, convert to integer -V---
2839 sim_fpu_status_invalid_div0 = 128, (X / 0) --Z--
2840 sim_fpu_status_invalid_cmp = 256, compare ----- (sim spec.)
2841 sim_fpu_status_invalid_sqrt = 512, -V---
2842 sim_fpu_status_rounded = 1024, I----
2843 sim_fpu_status_inexact = 2048, I---- (sim spec.)
2844 sim_fpu_status_overflow = 4096, I--O-
2845 sim_fpu_status_underflow = 8192, I---U
2846 sim_fpu_status_denorm = 16384, ----U (sim spec.)
2850 update_fpsr (SIM_DESC sd
, sim_fpu_status status
, unsigned int mask
, unsigned int double_op_p
)
2852 unsigned int fpsr
= FPSR
& mask
;
2854 unsigned int flags
= 0;
2857 && ((status
& (sim_fpu_status_rounded
2858 | sim_fpu_status_overflow
2859 | sim_fpu_status_inexact
))
2860 || (status
& sim_fpu_status_underflow
2861 && (fpsr
& (FPSR_XEU
| FPSR_XEI
)) == 0
2862 && fpsr
& FPSR_FS
)))
2864 flags
|= FPSR_XCI
| FPSR_XPI
;
2868 && (status
& (sim_fpu_status_invalid_isi
2869 | sim_fpu_status_invalid_imz
2870 | sim_fpu_status_invalid_zdz
2871 | sim_fpu_status_invalid_idi
2872 | sim_fpu_status_invalid_cvi
2873 | sim_fpu_status_invalid_sqrt
2874 | sim_fpu_status_invalid_snan
)))
2876 flags
|= FPSR_XCV
| FPSR_XPV
;
2880 && (status
& sim_fpu_status_invalid_div0
))
2882 flags
|= FPSR_XCV
| FPSR_XPV
;
2886 && (status
& sim_fpu_status_overflow
))
2888 flags
|= FPSR_XCO
| FPSR_XPO
;
2891 if (((fpsr
& FPSR_XEU
) || (fpsr
& FPSR_FS
) == 0)
2892 && (status
& (sim_fpu_status_underflow
2893 | sim_fpu_status_denorm
)))
2895 flags
|= FPSR_XCU
| FPSR_XPU
;
2903 SignalExceptionFPE (sd
, double_op_p
);
2910 SignalException (SIM_DESC sd
)
2914 PSW
= PSW
& ~(PSW_NPV
| PSW_DMP
| PSW_IMP
);
2919 SignalExceptionFPE (SIM_DESC sd
, unsigned int double_op_p
)
2921 if (((PSW
& (PSW_NP
|PSW_ID
)) == 0)
2922 || !(FPSR
& (double_op_p
? FPSR_DEM
: FPSR_SEM
)))
2926 EIIC
= (FPSR
& (double_op_p
? FPSR_DEM
: FPSR_SEM
))
2928 PSW
|= (PSW_EP
| PSW_ID
);
2931 SignalException (sd
);
2936 check_invalid_snan (SIM_DESC sd
, sim_fpu_status status
, unsigned int double_op_p
)
2938 if ((FPSR
& FPSR_XEI
)
2939 && (status
& sim_fpu_status_invalid_snan
))
2944 SignalExceptionFPE (sd
, double_op_p
);
2949 v850_float_compare (SIM_DESC sd
, int cmp
, sim_fpu wop1
, sim_fpu wop2
, int double_op_p
)
2953 if (sim_fpu_is_nan (&wop1
) || sim_fpu_is_nan (&wop2
))
2957 if (FPSR
& FPSR_XEV
)
2959 FPSR
|= FPSR_XCV
| FPSR_XPV
;
2960 SignalExceptionFPE (sd
, double_op_p
);
3018 else if (sim_fpu_is_infinity (&wop1
) && sim_fpu_is_infinity (&wop2
)
3019 && sim_fpu_sign (&wop1
) == sim_fpu_sign (&wop2
))
3077 int gt
= 0,lt
= 0,eq
= 0, status
;
3079 status
= sim_fpu_cmp (&wop1
, &wop2
);
3083 case SIM_FPU_IS_SNAN
:
3084 case SIM_FPU_IS_QNAN
:
3088 case SIM_FPU_IS_NINF
:
3091 case SIM_FPU_IS_PINF
:
3094 case SIM_FPU_IS_NNUMBER
:
3097 case SIM_FPU_IS_PNUMBER
:
3100 case SIM_FPU_IS_NDENORM
:
3103 case SIM_FPU_IS_PDENORM
:
3106 case SIM_FPU_IS_NZERO
:
3107 case SIM_FPU_IS_PZERO
:
3165 ASSERT (result
!= -1);
3170 v850_div (SIM_DESC sd
, unsigned int op0
, unsigned int op1
, unsigned int *op2p
, unsigned int *op3p
)
3172 signed long int quotient
;
3173 signed long int remainder
;
3174 signed long int divide_by
;
3175 signed long int divide_this
;
3176 bfd_boolean overflow
= FALSE
;
3178 /* Compute the result. */
3182 if (divide_by
== 0 || (divide_by
== -1 && divide_this
== (1 << 31)))
3188 quotient
= divide_this
/ divide_by
;
3189 remainder
= divide_this
% divide_by
;
3191 /* Set condition codes. */
3192 PSW
&= ~(PSW_Z
| PSW_S
| PSW_OV
);
3194 if (overflow
) PSW
|= PSW_OV
;
3195 if (quotient
== 0) PSW
|= PSW_Z
;
3196 if (quotient
< 0) PSW
|= PSW_S
;
3203 v850_divu (SIM_DESC sd
, unsigned int op0
, unsigned int op1
, unsigned int *op2p
, unsigned int *op3p
)
3205 unsigned long int quotient
;
3206 unsigned long int remainder
;
3207 unsigned long int divide_by
;
3208 unsigned long int divide_this
;
3209 bfd_boolean overflow
= FALSE
;
3211 /* Compute the result. */
3222 quotient
= divide_this
/ divide_by
;
3223 remainder
= divide_this
% divide_by
;
3225 /* Set condition codes. */
3226 PSW
&= ~(PSW_Z
| PSW_S
| PSW_OV
);
3228 if (overflow
) PSW
|= PSW_OV
;
3229 if (quotient
== 0) PSW
|= PSW_Z
;
3230 if (quotient
& 0x80000000) PSW
|= PSW_S
;
3237 v850_sar (SIM_DESC sd
, unsigned int op0
, unsigned int op1
, unsigned int *op2p
)
3239 unsigned int result
, z
, s
, cy
;
3242 result
= (signed)op1
>> op0
;
3244 /* Compute the condition codes. */
3246 s
= (result
& 0x80000000);
3247 cy
= (op1
& (1 << (op0
- 1)));
3249 /* Store the result and condition codes. */
3250 PSW
&= ~(PSW_Z
| PSW_S
| PSW_OV
| PSW_CY
);
3251 PSW
|= ((z
? PSW_Z
: 0) | (s
? PSW_S
: 0)
3252 | (cy
? PSW_CY
: 0));
3258 v850_shl (SIM_DESC sd
, unsigned int op0
, unsigned int op1
, unsigned int *op2p
)
3260 unsigned int result
, z
, s
, cy
;
3263 result
= op1
<< op0
;
3265 /* Compute the condition codes. */
3267 s
= (result
& 0x80000000);
3268 cy
= (op1
& (1 << (32 - op0
)));
3270 /* Store the result and condition codes. */
3271 PSW
&= ~(PSW_Z
| PSW_S
| PSW_OV
| PSW_CY
);
3272 PSW
|= ((z
? PSW_Z
: 0) | (s
? PSW_S
: 0)
3273 | (cy
? PSW_CY
: 0));
3279 v850_rotl (SIM_DESC sd
, unsigned int amount
, unsigned int src
, unsigned int * dest
)
3281 unsigned int result
, z
, s
, cy
;
3284 result
= src
<< amount
;
3285 result
|= src
>> (32 - amount
);
3287 /* Compute the condition codes. */
3289 s
= (result
& 0x80000000);
3290 cy
= ! (result
& 1);
3292 /* Store the result and condition codes. */
3293 PSW
&= ~(PSW_Z
| PSW_S
| PSW_OV
| PSW_CY
);
3294 PSW
|= ((z
? PSW_Z
: 0) | (s
? PSW_S
: 0)
3295 | (cy
? PSW_CY
: 0));
3301 v850_bins (SIM_DESC sd
, unsigned int source
, unsigned int lsb
, unsigned int msb
,
3302 unsigned int * dest
)
3305 unsigned int result
, pos
, width
;
3309 width
= (msb
- lsb
) + 1;
3311 mask
= ~ (-(1 << width
));
3314 result
= (* dest
) & ~ mask
;
3315 result
|= source
<< pos
;
3317 /* Compute the condition codes. */
3319 s
= result
& 0x80000000;
3321 /* Store the result and condition codes. */
3322 PSW
&= ~(PSW_Z
| PSW_S
| PSW_OV
);
3323 PSW
|= (z
? PSW_Z
: 0) | (s
? PSW_S
: 0);
3329 v850_shr (SIM_DESC sd
, unsigned int op0
, unsigned int op1
, unsigned int *op2p
)
3331 unsigned int result
, z
, s
, cy
;
3334 result
= op1
>> op0
;
3336 /* Compute the condition codes. */
3338 s
= (result
& 0x80000000);
3339 cy
= (op1
& (1 << (op0
- 1)));
3341 /* Store the result and condition codes. */
3342 PSW
&= ~(PSW_Z
| PSW_S
| PSW_OV
| PSW_CY
);
3343 PSW
|= ((z
? PSW_Z
: 0) | (s
? PSW_S
: 0)
3344 | (cy
? PSW_CY
: 0));
3350 v850_satadd (SIM_DESC sd
, unsigned int op0
, unsigned int op1
, unsigned int *op2p
)
3352 unsigned int result
, z
, s
, cy
, ov
, sat
;
3356 /* Compute the condition codes. */
3358 s
= (result
& 0x80000000);
3359 cy
= (result
< op0
|| result
< op1
);
3360 ov
= ((op0
& 0x80000000) == (op1
& 0x80000000)
3361 && (op0
& 0x80000000) != (result
& 0x80000000));
3364 /* Store the result and condition codes. */
3365 PSW
&= ~(PSW_Z
| PSW_S
| PSW_CY
| PSW_OV
);
3366 PSW
|= ((z
? PSW_Z
: 0) | (s
? PSW_S
: 0)
3367 | (cy
? PSW_CY
: 0) | (ov
? PSW_OV
: 0)
3368 | (sat
? PSW_SAT
: 0));
3370 /* Handle saturated results. */
3373 result
= 0x7fffffff;
3378 result
= 0x80000000;
3386 v850_satsub (SIM_DESC sd
, unsigned int op0
, unsigned int op1
, unsigned int *op2p
)
3388 unsigned int result
, z
, s
, cy
, ov
, sat
;
3390 /* Compute the result. */
3393 /* Compute the condition codes. */
3395 s
= (result
& 0x80000000);
3397 ov
= ((op1
& 0x80000000) != (op0
& 0x80000000)
3398 && (op1
& 0x80000000) != (result
& 0x80000000));
3401 /* Store the result and condition codes. */
3402 PSW
&= ~(PSW_Z
| PSW_S
| PSW_CY
| PSW_OV
);
3403 PSW
|= ((z
? PSW_Z
: 0) | (s
? PSW_S
: 0)
3404 | (cy
? PSW_CY
: 0) | (ov
? PSW_OV
: 0)
3405 | (sat
? PSW_SAT
: 0));
3407 /* Handle saturated results. */
3410 result
= 0x7fffffff;
3415 result
= 0x80000000;
3423 load_data_mem (SIM_DESC sd
,
3432 data
= sim_core_read_unaligned_1 (STATE_CPU (sd
, 0),
3433 PC
, read_map
, addr
);
3436 data
= sim_core_read_unaligned_2 (STATE_CPU (sd
, 0),
3437 PC
, read_map
, addr
);
3440 data
= sim_core_read_unaligned_4 (STATE_CPU (sd
, 0),
3441 PC
, read_map
, addr
);
3450 store_data_mem (SIM_DESC sd
,
3458 store_mem (addr
, 1, data
);
3461 store_mem (addr
, 2, data
);
3464 store_mem (addr
, 4, data
);
3472 mpu_load_mem_test (SIM_DESC sd
, unsigned int addr
, int size
, int base_reg
)
3478 if (IPE0
&& addr
>= IPA2ADDR (IPA0L
) && addr
<= IPA2ADDR (IPA0L
) && IPR0
)
3482 else if (IPE1
&& addr
>= IPA2ADDR (IPA1L
) && addr
<= IPA2ADDR (IPA1L
) && IPR1
)
3486 else if (IPE2
&& addr
>= IPA2ADDR (IPA2L
) && addr
<= IPA2ADDR (IPA2L
) && IPR2
)
3490 else if (IPE3
&& addr
>= IPA2ADDR (IPA3L
) && addr
<= IPA2ADDR (IPA3L
) && IPR3
)
3494 else if (addr
>= PPA2ADDR (PPA
& ~PPM
) && addr
<= DPA2ADDR (PPA
| PPM
))
3496 /* preifarallel area */
3498 else if (addr
>= PPA2ADDR (SPAL
) && addr
<= DPA2ADDR (SPAU
))
3502 else if (DPE0
&& addr
>= DPA2ADDR (DPA0L
) && addr
<= DPA2ADDR (DPA0L
) && DPR0
3503 && ((SPAL
& SPAL_SPS
) ? base_reg
== SP_REGNO
: 1))
3507 else if (DPE1
&& addr
>= DPA2ADDR (DPA1L
) && addr
<= DPA2ADDR (DPA1L
) && DPR1
3508 && ((SPAL
& SPAL_SPS
) ? base_reg
== SP_REGNO
: 1))
3512 else if (DPE2
&& addr
>= DPA2ADDR (DPA2L
) && addr
<= DPA2ADDR (DPA2L
) && DPR2
3513 && ((SPAL
& SPAL_SPS
) ? base_reg
== SP_REGNO
: 1))
3517 else if (DPE3
&& addr
>= DPA2ADDR (DPA3L
) && addr
<= DPA2ADDR (DPA3L
) && DPR3
3518 && ((SPAL
& SPAL_SPS
) ? base_reg
== SP_REGNO
: 1))
3524 VMECR
&= ~(VMECR_VMW
| VMECR_VMX
);
3532 SignalException (sd
);
3541 mpu_store_mem_test (SIM_DESC sd
, unsigned int addr
, int size
, int base_reg
)
3547 if (addr
>= PPA2ADDR (PPA
& ~PPM
) && addr
<= DPA2ADDR (PPA
| PPM
))
3549 /* preifarallel area */
3551 else if (addr
>= PPA2ADDR (SPAL
) && addr
<= DPA2ADDR (SPAU
))
3555 else if (DPE0
&& addr
>= DPA2ADDR (DPA0L
) && addr
<= DPA2ADDR (DPA0L
) && DPW0
3556 && ((SPAL
& SPAL_SPS
) ? base_reg
== SP_REGNO
: 1))
3560 else if (DPE1
&& addr
>= DPA2ADDR (DPA1L
) && addr
<= DPA2ADDR (DPA1L
) && DPW1
3561 && ((SPAL
& SPAL_SPS
) ? base_reg
== SP_REGNO
: 1))
3565 else if (DPE2
&& addr
>= DPA2ADDR (DPA2L
) && addr
<= DPA2ADDR (DPA2L
) && DPW2
3566 && ((SPAL
& SPAL_SPS
) ? base_reg
== SP_REGNO
: 1))
3570 else if (DPE3
&& addr
>= DPA2ADDR (DPA3L
) && addr
<= DPA2ADDR (DPA3L
) && DPW3
3571 && ((SPAL
& SPAL_SPS
) ? base_reg
== SP_REGNO
: 1))
3577 if (addr
>= PPA2ADDR (PPA
& ~PPM
) && addr
<= DPA2ADDR (PPA
| PPM
))
3592 VMECR
&= ~(VMECR_VMW
| VMECR_VMX
);