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[thirdparty/binutils-gdb.git] / sim / v850 / simops.c
1 #include "sim-main.h"
2 #include "v850_sim.h"
3 #include "simops.h"
4
5 #ifdef HAVE_UTIME_H
6 #include <utime.h>
7 #endif
8
9 #ifdef HAVE_TIME_H
10 #include <time.h>
11 #endif
12
13 #ifdef HAVE_UNISTD_H
14 #include <unistd.h>
15 #endif
16
17 #ifdef HAVE_STRING_H
18 #include <string.h>
19 #else
20 #ifdef HAVE_STRINGS_H
21 #include <strings.h>
22 #endif
23 #endif
24
25 #include "targ-vals.h"
26
27 #include "libiberty.h"
28
29 #include <errno.h>
30 #if !defined(__GO32__) && !defined(_WIN32)
31 #include <sys/stat.h>
32 #include <sys/times.h>
33 #include <sys/time.h>
34 #endif
35
36 /* This is an array of the bit positions of registers r20 .. r31 in
37 that order in a prepare/dispose instruction. */
38 int type1_regs[12] = { 27, 26, 25, 24, 31, 30, 29, 28, 23, 22, 0, 21 };
39 /* This is an array of the bit positions of registers r16 .. r31 in
40 that order in a push/pop instruction. */
41 int type2_regs[16] = { 3, 2, 1, 0, 27, 26, 25, 24, 31, 30, 29, 28, 23, 22, 20, 21};
42 /* This is an array of the bit positions of registers r1 .. r15 in
43 that order in a push/pop instruction. */
44 int type3_regs[15] = { 2, 1, 0, 27, 26, 25, 24, 31, 30, 29, 28, 23, 22, 20, 21};
45
46 #ifdef DEBUG
47 #ifndef SIZE_INSTRUCTION
48 #define SIZE_INSTRUCTION 18
49 #endif
50
51 #ifndef SIZE_VALUES
52 #define SIZE_VALUES 11
53 #endif
54
55
56 unsigned32 trace_values[3];
57 int trace_num_values;
58 unsigned32 trace_pc;
59 const char *trace_name;
60 int trace_module;
61
62
63 void
64 trace_input (name, type, size)
65 char *name;
66 enum op_types type;
67 int size;
68 {
69
70 if (!TRACE_ALU_P (STATE_CPU (simulator, 0)))
71 return;
72
73 trace_pc = PC;
74 trace_name = name;
75 trace_module = TRACE_ALU_IDX;
76
77 switch (type)
78 {
79 default:
80 case OP_UNKNOWN:
81 case OP_NONE:
82 case OP_TRAP:
83 trace_num_values = 0;
84 break;
85
86 case OP_REG:
87 case OP_REG_REG_MOVE:
88 trace_values[0] = State.regs[OP[0]];
89 trace_num_values = 1;
90 break;
91
92 case OP_BIT_CHANGE:
93 case OP_REG_REG:
94 case OP_REG_REG_CMP:
95 trace_values[0] = State.regs[OP[1]];
96 trace_values[1] = State.regs[OP[0]];
97 trace_num_values = 2;
98 break;
99
100 case OP_IMM_REG:
101 case OP_IMM_REG_CMP:
102 trace_values[0] = SEXT5 (OP[0]);
103 trace_values[1] = OP[1];
104 trace_num_values = 2;
105 break;
106
107 case OP_IMM_REG_MOVE:
108 trace_values[0] = SEXT5 (OP[0]);
109 trace_num_values = 1;
110 break;
111
112 case OP_COND_BR:
113 trace_values[0] = State.pc;
114 trace_values[1] = SEXT9 (OP[0]);
115 trace_values[2] = PSW;
116 trace_num_values = 3;
117 break;
118
119 case OP_LOAD16:
120 trace_values[0] = OP[1] * size;
121 trace_values[1] = State.regs[30];
122 trace_num_values = 2;
123 break;
124
125 case OP_STORE16:
126 trace_values[0] = State.regs[OP[0]];
127 trace_values[1] = OP[1] * size;
128 trace_values[2] = State.regs[30];
129 trace_num_values = 3;
130 break;
131
132 case OP_LOAD32:
133 trace_values[0] = EXTEND16 (OP[2]);
134 trace_values[1] = State.regs[OP[0]];
135 trace_num_values = 2;
136 break;
137
138 case OP_STORE32:
139 trace_values[0] = State.regs[OP[1]];
140 trace_values[1] = EXTEND16 (OP[2]);
141 trace_values[2] = State.regs[OP[0]];
142 trace_num_values = 3;
143 break;
144
145 case OP_JUMP:
146 trace_values[0] = SEXT22 (OP[0]);
147 trace_values[1] = State.pc;
148 trace_num_values = 2;
149 break;
150
151 case OP_IMM_REG_REG:
152 trace_values[0] = EXTEND16 (OP[0]) << size;
153 trace_values[1] = State.regs[OP[1]];
154 trace_num_values = 2;
155 break;
156
157 case OP_IMM16_REG_REG:
158 trace_values[0] = EXTEND16 (OP[2]) << size;
159 trace_values[1] = State.regs[OP[1]];
160 trace_num_values = 2;
161 break;
162
163 case OP_UIMM_REG_REG:
164 trace_values[0] = (OP[0] & 0xffff) << size;
165 trace_values[1] = State.regs[OP[1]];
166 trace_num_values = 2;
167 break;
168
169 case OP_UIMM16_REG_REG:
170 trace_values[0] = (OP[2]) << size;
171 trace_values[1] = State.regs[OP[1]];
172 trace_num_values = 2;
173 break;
174
175 case OP_BIT:
176 trace_num_values = 0;
177 break;
178
179 case OP_EX1:
180 trace_values[0] = PSW;
181 trace_num_values = 1;
182 break;
183
184 case OP_EX2:
185 trace_num_values = 0;
186 break;
187
188 case OP_LDSR:
189 trace_values[0] = State.regs[OP[0]];
190 trace_num_values = 1;
191 break;
192
193 case OP_STSR:
194 trace_values[0] = State.sregs[OP[1]];
195 trace_num_values = 1;
196 }
197
198 }
199
200 void
201 trace_result (int has_result, unsigned32 result)
202 {
203 char buf[1000];
204 char *chp;
205
206 buf[0] = '\0';
207 chp = buf;
208
209 /* write out the values saved during the trace_input call */
210 {
211 int i;
212 for (i = 0; i < trace_num_values; i++)
213 {
214 sprintf (chp, "%*s0x%.8lx", SIZE_VALUES - 10, "", trace_values[i]);
215 chp = strchr (chp, '\0');
216 }
217 while (i++ < 3)
218 {
219 sprintf (chp, "%*s", SIZE_VALUES, "");
220 chp = strchr (chp, '\0');
221 }
222 }
223
224 /* append any result to the end of the buffer */
225 if (has_result)
226 sprintf (chp, " :: 0x%.8lx", (unsigned long)result);
227
228 trace_generic (simulator, STATE_CPU (simulator, 0), trace_module, buf);
229 }
230
231 void
232 trace_output (result)
233 enum op_types result;
234 {
235 if (!TRACE_ALU_P (STATE_CPU (simulator, 0)))
236 return;
237
238 switch (result)
239 {
240 default:
241 case OP_UNKNOWN:
242 case OP_NONE:
243 case OP_TRAP:
244 case OP_REG:
245 case OP_REG_REG_CMP:
246 case OP_IMM_REG_CMP:
247 case OP_COND_BR:
248 case OP_STORE16:
249 case OP_STORE32:
250 case OP_BIT:
251 case OP_EX2:
252 trace_result (0, 0);
253 break;
254
255 case OP_LOAD16:
256 case OP_STSR:
257 trace_result (1, State.regs[OP[0]]);
258 break;
259
260 case OP_REG_REG:
261 case OP_REG_REG_MOVE:
262 case OP_IMM_REG:
263 case OP_IMM_REG_MOVE:
264 case OP_LOAD32:
265 case OP_EX1:
266 trace_result (1, State.regs[OP[1]]);
267 break;
268
269 case OP_IMM_REG_REG:
270 case OP_UIMM_REG_REG:
271 case OP_IMM16_REG_REG:
272 case OP_UIMM16_REG_REG:
273 trace_result (1, State.regs[OP[1]]);
274 break;
275
276 case OP_JUMP:
277 if (OP[1] != 0)
278 trace_result (1, State.regs[OP[1]]);
279 else
280 trace_result (0, 0);
281 break;
282
283 case OP_LDSR:
284 trace_result (1, State.sregs[OP[1]]);
285 break;
286 }
287 }
288 #endif
289
290 \f
291 /* Returns 1 if the specific condition is met, returns 0 otherwise. */
292 int
293 condition_met (unsigned code)
294 {
295 unsigned int psw = PSW;
296
297 switch (code & 0xf)
298 {
299 case 0x0: return ((psw & PSW_OV) != 0);
300 case 0x1: return ((psw & PSW_CY) != 0);
301 case 0x2: return ((psw & PSW_Z) != 0);
302 case 0x3: return ((((psw & PSW_CY) != 0) | ((psw & PSW_Z) != 0)) != 0);
303 case 0x4: return ((psw & PSW_S) != 0);
304 /*case 0x5: return 1;*/
305 case 0x6: return ((((psw & PSW_S) != 0) ^ ((psw & PSW_OV) != 0)) != 0);
306 case 0x7: return (((((psw & PSW_S) != 0) ^ ((psw & PSW_OV) != 0)) || ((psw & PSW_Z) != 0)) != 0);
307 case 0x8: return ((psw & PSW_OV) == 0);
308 case 0x9: return ((psw & PSW_CY) == 0);
309 case 0xa: return ((psw & PSW_Z) == 0);
310 case 0xb: return ((((psw & PSW_CY) != 0) | ((psw & PSW_Z) != 0)) == 0);
311 case 0xc: return ((psw & PSW_S) == 0);
312 case 0xd: return ((psw & PSW_SAT) != 0);
313 case 0xe: return ((((psw & PSW_S) != 0) ^ ((psw & PSW_OV) != 0)) == 0);
314 case 0xf: return (((((psw & PSW_S) != 0) ^ ((psw & PSW_OV) != 0)) || ((psw & PSW_Z) != 0)) == 0);
315 }
316
317 return 1;
318 }
319
320 static unsigned long
321 Add32 (unsigned long a1, unsigned long a2, int * carry)
322 {
323 unsigned long result = (a1 + a2);
324
325 * carry = (result < a1);
326
327 return result;
328 }
329
330 static void
331 Multiply64 (boolean sign, unsigned long op0)
332 {
333 unsigned long op1;
334 unsigned long lo;
335 unsigned long mid1;
336 unsigned long mid2;
337 unsigned long hi;
338 unsigned long RdLo;
339 unsigned long RdHi;
340 int carry;
341
342 op1 = State.regs[ OP[1] ];
343
344 if (sign)
345 {
346 /* Compute sign of result and adjust operands if necessary. */
347
348 sign = (op0 ^ op1) & 0x80000000;
349
350 if (((signed long) op0) < 0)
351 op0 = - op0;
352
353 if (((signed long) op1) < 0)
354 op1 = - op1;
355 }
356
357 /* We can split the 32x32 into four 16x16 operations. This ensures
358 that we do not lose precision on 32bit only hosts: */
359 lo = ( (op0 & 0xFFFF) * (op1 & 0xFFFF));
360 mid1 = ( (op0 & 0xFFFF) * ((op1 >> 16) & 0xFFFF));
361 mid2 = (((op0 >> 16) & 0xFFFF) * (op1 & 0xFFFF));
362 hi = (((op0 >> 16) & 0xFFFF) * ((op1 >> 16) & 0xFFFF));
363
364 /* We now need to add all of these results together, taking care
365 to propogate the carries from the additions: */
366 RdLo = Add32 (lo, (mid1 << 16), & carry);
367 RdHi = carry;
368 RdLo = Add32 (RdLo, (mid2 << 16), & carry);
369 RdHi += (carry + ((mid1 >> 16) & 0xFFFF) + ((mid2 >> 16) & 0xFFFF) + hi);
370
371 if (sign)
372 {
373 /* Negate result if necessary. */
374
375 RdLo = ~ RdLo;
376 RdHi = ~ RdHi;
377 if (RdLo == 0xFFFFFFFF)
378 {
379 RdLo = 0;
380 RdHi += 1;
381 }
382 else
383 RdLo += 1;
384 }
385
386 /* Don't store into register 0. */
387 if (OP[1])
388 State.regs[ OP[1] ] = RdLo;
389 if (OP[2] >> 11)
390 State.regs[ OP[2] >> 11 ] = RdHi;
391
392 return;
393 }
394
395 \f
396 /* Read a null terminated string from memory, return in a buffer */
397 static char *
398 fetch_str (sd, addr)
399 SIM_DESC sd;
400 address_word addr;
401 {
402 char *buf;
403 int nr = 0;
404 while (sim_core_read_1 (STATE_CPU (sd, 0),
405 PC, read_map, addr + nr) != 0)
406 nr++;
407 buf = NZALLOC (char, nr + 1);
408 sim_read (simulator, addr, buf, nr);
409 return buf;
410 }
411
412 /* Read a null terminated argument vector from memory, return in a
413 buffer */
414 static char **
415 fetch_argv (sd, addr)
416 SIM_DESC sd;
417 address_word addr;
418 {
419 int max_nr = 64;
420 int nr = 0;
421 char **buf = xmalloc (max_nr * sizeof (char*));
422 while (1)
423 {
424 unsigned32 a = sim_core_read_4 (STATE_CPU (sd, 0),
425 PC, read_map, addr + nr * 4);
426 if (a == 0) break;
427 buf[nr] = fetch_str (sd, a);
428 nr ++;
429 if (nr == max_nr - 1)
430 {
431 max_nr += 50;
432 buf = xrealloc (buf, max_nr * sizeof (char*));
433 }
434 }
435 buf[nr] = 0;
436 return buf;
437 }
438
439 \f
440 /* sst.b */
441 int
442 OP_380 ()
443 {
444 trace_input ("sst.b", OP_STORE16, 1);
445
446 store_mem (State.regs[30] + (OP[3] & 0x7f), 1, State.regs[ OP[1] ]);
447
448 trace_output (OP_STORE16);
449
450 return 2;
451 }
452
453 /* sst.h */
454 int
455 OP_480 ()
456 {
457 trace_input ("sst.h", OP_STORE16, 2);
458
459 store_mem (State.regs[30] + ((OP[3] & 0x7f) << 1), 2, State.regs[ OP[1] ]);
460
461 trace_output (OP_STORE16);
462
463 return 2;
464 }
465
466 /* sst.w */
467 int
468 OP_501 ()
469 {
470 trace_input ("sst.w", OP_STORE16, 4);
471
472 store_mem (State.regs[30] + ((OP[3] & 0x7e) << 1), 4, State.regs[ OP[1] ]);
473
474 trace_output (OP_STORE16);
475
476 return 2;
477 }
478
479 /* ld.b */
480 int
481 OP_700 ()
482 {
483 int adr;
484
485 trace_input ("ld.b", OP_LOAD32, 1);
486
487 adr = State.regs[ OP[0] ] + EXTEND16 (OP[2]);
488
489 State.regs[ OP[1] ] = EXTEND8 (load_mem (adr, 1));
490
491 trace_output (OP_LOAD32);
492
493 return 4;
494 }
495
496 /* ld.h */
497 int
498 OP_720 ()
499 {
500 int adr;
501
502 trace_input ("ld.h", OP_LOAD32, 2);
503
504 adr = State.regs[ OP[0] ] + EXTEND16 (OP[2]);
505 adr &= ~0x1;
506
507 State.regs[ OP[1] ] = EXTEND16 (load_mem (adr, 2));
508
509 trace_output (OP_LOAD32);
510
511 return 4;
512 }
513
514 /* ld.w */
515 int
516 OP_10720 ()
517 {
518 int adr;
519
520 trace_input ("ld.w", OP_LOAD32, 4);
521
522 adr = State.regs[ OP[0] ] + EXTEND16 (OP[2] & ~1);
523 adr &= ~0x3;
524
525 State.regs[ OP[1] ] = load_mem (adr, 4);
526
527 trace_output (OP_LOAD32);
528
529 return 4;
530 }
531
532 /* st.b */
533 int
534 OP_740 ()
535 {
536 trace_input ("st.b", OP_STORE32, 1);
537
538 store_mem (State.regs[ OP[0] ] + EXTEND16 (OP[2]), 1, State.regs[ OP[1] ]);
539
540 trace_output (OP_STORE32);
541
542 return 4;
543 }
544
545 /* st.h */
546 int
547 OP_760 ()
548 {
549 int adr;
550
551 trace_input ("st.h", OP_STORE32, 2);
552
553 adr = State.regs[ OP[0] ] + EXTEND16 (OP[2]);
554 adr &= ~1;
555
556 store_mem (adr, 2, State.regs[ OP[1] ]);
557
558 trace_output (OP_STORE32);
559
560 return 4;
561 }
562
563 /* st.w */
564 int
565 OP_10760 ()
566 {
567 int adr;
568
569 trace_input ("st.w", OP_STORE32, 4);
570
571 adr = State.regs[ OP[0] ] + EXTEND16 (OP[2] & ~1);
572 adr &= ~3;
573
574 store_mem (adr, 4, State.regs[ OP[1] ]);
575
576 trace_output (OP_STORE32);
577
578 return 4;
579 }
580
581 /* add reg, reg */
582 int
583 OP_1C0 ()
584 {
585 unsigned int op0, op1, result, z, s, cy, ov;
586
587 trace_input ("add", OP_REG_REG, 0);
588
589 /* Compute the result. */
590
591 op0 = State.regs[ OP[0] ];
592 op1 = State.regs[ OP[1] ];
593
594 result = op0 + op1;
595
596 /* Compute the condition codes. */
597 z = (result == 0);
598 s = (result & 0x80000000);
599 cy = (result < op0 || result < op1);
600 ov = ((op0 & 0x80000000) == (op1 & 0x80000000)
601 && (op0 & 0x80000000) != (result & 0x80000000));
602
603 /* Store the result and condition codes. */
604 State.regs[OP[1]] = result;
605 PSW &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
606 PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
607 | (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0));
608 trace_output (OP_REG_REG);
609
610 return 2;
611 }
612
613 /* add sign_extend(imm5), reg */
614 int
615 OP_240 ()
616 {
617 unsigned int op0, op1, result, z, s, cy, ov;
618 int temp;
619
620 trace_input ("add", OP_IMM_REG, 0);
621
622 /* Compute the result. */
623 temp = SEXT5 (OP[0]);
624 op0 = temp;
625 op1 = State.regs[OP[1]];
626 result = op0 + op1;
627
628 /* Compute the condition codes. */
629 z = (result == 0);
630 s = (result & 0x80000000);
631 cy = (result < op0 || result < op1);
632 ov = ((op0 & 0x80000000) == (op1 & 0x80000000)
633 && (op0 & 0x80000000) != (result & 0x80000000));
634
635 /* Store the result and condition codes. */
636 State.regs[OP[1]] = result;
637 PSW &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
638 PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
639 | (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0));
640 trace_output (OP_IMM_REG);
641
642 return 2;
643 }
644
645 /* addi sign_extend(imm16), reg, reg */
646 int
647 OP_600 ()
648 {
649 unsigned int op0, op1, result, z, s, cy, ov;
650
651 trace_input ("addi", OP_IMM16_REG_REG, 0);
652
653 /* Compute the result. */
654
655 op0 = EXTEND16 (OP[2]);
656 op1 = State.regs[ OP[0] ];
657 result = op0 + op1;
658
659 /* Compute the condition codes. */
660 z = (result == 0);
661 s = (result & 0x80000000);
662 cy = (result < op0 || result < op1);
663 ov = ((op0 & 0x80000000) == (op1 & 0x80000000)
664 && (op0 & 0x80000000) != (result & 0x80000000));
665
666 /* Store the result and condition codes. */
667 State.regs[OP[1]] = result;
668 PSW &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
669 PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
670 | (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0));
671 trace_output (OP_IMM16_REG_REG);
672
673 return 4;
674 }
675
676 /* sub reg1, reg2 */
677 int
678 OP_1A0 ()
679 {
680 unsigned int op0, op1, result, z, s, cy, ov;
681
682 trace_input ("sub", OP_REG_REG, 0);
683 /* Compute the result. */
684 op0 = State.regs[ OP[0] ];
685 op1 = State.regs[ OP[1] ];
686 result = op1 - op0;
687
688 /* Compute the condition codes. */
689 z = (result == 0);
690 s = (result & 0x80000000);
691 cy = (op1 < op0);
692 ov = ((op1 & 0x80000000) != (op0 & 0x80000000)
693 && (op1 & 0x80000000) != (result & 0x80000000));
694
695 /* Store the result and condition codes. */
696 State.regs[OP[1]] = result;
697 PSW &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
698 PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
699 | (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0));
700 trace_output (OP_REG_REG);
701
702 return 2;
703 }
704
705 /* subr reg1, reg2 */
706 int
707 OP_180 ()
708 {
709 unsigned int op0, op1, result, z, s, cy, ov;
710
711 trace_input ("subr", OP_REG_REG, 0);
712 /* Compute the result. */
713 op0 = State.regs[ OP[0] ];
714 op1 = State.regs[ OP[1] ];
715 result = op0 - op1;
716
717 /* Compute the condition codes. */
718 z = (result == 0);
719 s = (result & 0x80000000);
720 cy = (op0 < op1);
721 ov = ((op0 & 0x80000000) != (op1 & 0x80000000)
722 && (op0 & 0x80000000) != (result & 0x80000000));
723
724 /* Store the result and condition codes. */
725 State.regs[OP[1]] = result;
726 PSW &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
727 PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
728 | (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0));
729 trace_output (OP_REG_REG);
730
731 return 2;
732 }
733
734 /* sxh reg1 */
735 int
736 OP_E0 ()
737 {
738 trace_input ("mulh", OP_REG_REG, 0);
739
740 State.regs[ OP[1] ] = (EXTEND16 (State.regs[ OP[1] ]) * EXTEND16 (State.regs[ OP[0] ]));
741
742 trace_output (OP_REG_REG);
743
744 return 2;
745 }
746
747 /* mulh sign_extend(imm5), reg2 */
748 int
749 OP_2E0 ()
750 {
751 trace_input ("mulh", OP_IMM_REG, 0);
752
753 State.regs[ OP[1] ] = EXTEND16 (State.regs[ OP[1] ]) * SEXT5 (OP[0]);
754
755 trace_output (OP_IMM_REG);
756
757 return 2;
758 }
759
760 /* mulhi imm16, reg1, reg2 */
761 int
762 OP_6E0 ()
763 {
764 trace_input ("mulhi", OP_IMM16_REG_REG, 0);
765
766 State.regs[ OP[1] ] = EXTEND16 (State.regs[ OP[0] ]) * EXTEND16 (OP[2]);
767
768 trace_output (OP_IMM16_REG_REG);
769
770 return 4;
771 }
772
773 /* divh reg1, reg2 */
774 int
775 OP_40 ()
776 {
777 unsigned int op0, op1, result, ov, s, z;
778 int temp;
779
780 trace_input ("divh", OP_REG_REG, 0);
781
782 /* Compute the result. */
783 temp = EXTEND16 (State.regs[ OP[0] ]);
784 op0 = temp;
785 op1 = State.regs[OP[1]];
786
787 if (op0 == 0xffffffff && op1 == 0x80000000)
788 {
789 result = 0x80000000;
790 ov = 1;
791 }
792 else if (op0 != 0)
793 {
794 result = op1 / op0;
795 ov = 0;
796 }
797 else
798 {
799 result = 0x0;
800 ov = 1;
801 }
802
803 /* Compute the condition codes. */
804 z = (result == 0);
805 s = (result & 0x80000000);
806
807 /* Store the result and condition codes. */
808 State.regs[OP[1]] = result;
809 PSW &= ~(PSW_Z | PSW_S | PSW_OV);
810 PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
811 | (ov ? PSW_OV : 0));
812 trace_output (OP_REG_REG);
813
814 return 2;
815 }
816
817 /* cmp reg, reg */
818 int
819 OP_1E0 ()
820 {
821 unsigned int op0, op1, result, z, s, cy, ov;
822
823 trace_input ("cmp", OP_REG_REG_CMP, 0);
824 /* Compute the result. */
825 op0 = State.regs[ OP[0] ];
826 op1 = State.regs[ OP[1] ];
827 result = op1 - op0;
828
829 /* Compute the condition codes. */
830 z = (result == 0);
831 s = (result & 0x80000000);
832 cy = (op1 < op0);
833 ov = ((op1 & 0x80000000) != (op0 & 0x80000000)
834 && (op1 & 0x80000000) != (result & 0x80000000));
835
836 /* Set condition codes. */
837 PSW &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
838 PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
839 | (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0));
840 trace_output (OP_REG_REG_CMP);
841
842 return 2;
843 }
844
845 /* cmp sign_extend(imm5), reg */
846 int
847 OP_260 ()
848 {
849 unsigned int op0, op1, result, z, s, cy, ov;
850 int temp;
851
852 /* Compute the result. */
853 trace_input ("cmp", OP_IMM_REG_CMP, 0);
854 temp = SEXT5 (OP[0]);
855 op0 = temp;
856 op1 = State.regs[OP[1]];
857 result = op1 - op0;
858
859 /* Compute the condition codes. */
860 z = (result == 0);
861 s = (result & 0x80000000);
862 cy = (op1 < op0);
863 ov = ((op1 & 0x80000000) != (op0 & 0x80000000)
864 && (op1 & 0x80000000) != (result & 0x80000000));
865
866 /* Set condition codes. */
867 PSW &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
868 PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
869 | (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0));
870 trace_output (OP_IMM_REG_CMP);
871
872 return 2;
873 }
874
875 /* setf cccc,reg2 */
876 int
877 OP_7E0 ()
878 {
879 trace_input ("setf", OP_EX1, 0);
880
881 State.regs[ OP[1] ] = condition_met (OP[0]);
882
883 trace_output (OP_EX1);
884
885 return 4;
886 }
887
888 /* satadd reg,reg */
889 int
890 OP_C0 ()
891 {
892 unsigned int op0, op1, result, z, s, cy, ov, sat;
893
894 trace_input ("satadd", OP_REG_REG, 0);
895 /* Compute the result. */
896 op0 = State.regs[ OP[0] ];
897 op1 = State.regs[ OP[1] ];
898 result = op0 + op1;
899
900 /* Compute the condition codes. */
901 z = (result == 0);
902 s = (result & 0x80000000);
903 cy = (result < op0 || result < op1);
904 ov = ((op0 & 0x80000000) == (op1 & 0x80000000)
905 && (op0 & 0x80000000) != (result & 0x80000000));
906 sat = ov;
907
908 /* Store the result and condition codes. */
909 State.regs[OP[1]] = result;
910 PSW &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
911 PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
912 | (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0)
913 | (sat ? PSW_SAT : 0));
914
915 /* Handle saturated results. */
916 if (sat && s)
917 State.regs[OP[1]] = 0x80000000;
918 else if (sat)
919 State.regs[OP[1]] = 0x7fffffff;
920 trace_output (OP_REG_REG);
921
922 return 2;
923 }
924
925 /* satadd sign_extend(imm5), reg */
926 int
927 OP_220 ()
928 {
929 unsigned int op0, op1, result, z, s, cy, ov, sat;
930
931 int temp;
932
933 trace_input ("satadd", OP_IMM_REG, 0);
934
935 /* Compute the result. */
936 temp = SEXT5 (OP[0]);
937 op0 = temp;
938 op1 = State.regs[OP[1]];
939 result = op0 + op1;
940
941 /* Compute the condition codes. */
942 z = (result == 0);
943 s = (result & 0x80000000);
944 cy = (result < op0 || result < op1);
945 ov = ((op0 & 0x80000000) == (op1 & 0x80000000)
946 && (op0 & 0x80000000) != (result & 0x80000000));
947 sat = ov;
948
949 /* Store the result and condition codes. */
950 State.regs[OP[1]] = result;
951 PSW &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
952 PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
953 | (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0)
954 | (sat ? PSW_SAT : 0));
955
956 /* Handle saturated results. */
957 if (sat && s)
958 State.regs[OP[1]] = 0x80000000;
959 else if (sat)
960 State.regs[OP[1]] = 0x7fffffff;
961 trace_output (OP_IMM_REG);
962
963 return 2;
964 }
965
966 /* satsub reg1, reg2 */
967 int
968 OP_A0 ()
969 {
970 unsigned int op0, op1, result, z, s, cy, ov, sat;
971
972 trace_input ("satsub", OP_REG_REG, 0);
973
974 /* Compute the result. */
975 op0 = State.regs[ OP[0] ];
976 op1 = State.regs[ OP[1] ];
977 result = op1 - op0;
978
979 /* Compute the condition codes. */
980 z = (result == 0);
981 s = (result & 0x80000000);
982 cy = (op1 < op0);
983 ov = ((op1 & 0x80000000) != (op0 & 0x80000000)
984 && (op1 & 0x80000000) != (result & 0x80000000));
985 sat = ov;
986
987 /* Store the result and condition codes. */
988 State.regs[OP[1]] = result;
989 PSW &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
990 PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
991 | (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0)
992 | (sat ? PSW_SAT : 0));
993
994 /* Handle saturated results. */
995 if (sat && s)
996 State.regs[OP[1]] = 0x80000000;
997 else if (sat)
998 State.regs[OP[1]] = 0x7fffffff;
999 trace_output (OP_REG_REG);
1000 return 2;
1001 }
1002
1003 /* satsubi sign_extend(imm16), reg */
1004 int
1005 OP_660 ()
1006 {
1007 unsigned int op0, op1, result, z, s, cy, ov, sat;
1008 int temp;
1009
1010 trace_input ("satsubi", OP_IMM_REG, 0);
1011
1012 /* Compute the result. */
1013 temp = EXTEND16 (OP[2]);
1014 op0 = temp;
1015 op1 = State.regs[ OP[0] ];
1016 result = op1 - op0;
1017
1018 /* Compute the condition codes. */
1019 z = (result == 0);
1020 s = (result & 0x80000000);
1021 cy = (op1 < op0);
1022 ov = ((op1 & 0x80000000) != (op0 & 0x80000000)
1023 && (op1 & 0x80000000) != (result & 0x80000000));
1024 sat = ov;
1025
1026 /* Store the result and condition codes. */
1027 State.regs[OP[1]] = result;
1028 PSW &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
1029 PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
1030 | (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0)
1031 | (sat ? PSW_SAT : 0));
1032
1033 /* Handle saturated results. */
1034 if (sat && s)
1035 State.regs[OP[1]] = 0x80000000;
1036 else if (sat)
1037 State.regs[OP[1]] = 0x7fffffff;
1038 trace_output (OP_IMM_REG);
1039
1040 return 4;
1041 }
1042
1043 /* satsubr reg,reg */
1044 int
1045 OP_80 ()
1046 {
1047 unsigned int op0, op1, result, z, s, cy, ov, sat;
1048
1049 trace_input ("satsubr", OP_REG_REG, 0);
1050
1051 /* Compute the result. */
1052 op0 = State.regs[ OP[0] ];
1053 op1 = State.regs[ OP[1] ];
1054 result = op0 - op1;
1055
1056 /* Compute the condition codes. */
1057 z = (result == 0);
1058 s = (result & 0x80000000);
1059 cy = (result < op0);
1060 ov = ((op1 & 0x80000000) != (op0 & 0x80000000)
1061 && (op1 & 0x80000000) != (result & 0x80000000));
1062 sat = ov;
1063
1064 /* Store the result and condition codes. */
1065 State.regs[OP[1]] = result;
1066 PSW &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
1067 PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
1068 | (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0)
1069 | (sat ? PSW_SAT : 0));
1070
1071 /* Handle saturated results. */
1072 if (sat && s)
1073 State.regs[OP[1]] = 0x80000000;
1074 else if (sat)
1075 State.regs[OP[1]] = 0x7fffffff;
1076 trace_output (OP_REG_REG);
1077
1078 return 2;
1079 }
1080
1081 /* tst reg,reg */
1082 int
1083 OP_160 ()
1084 {
1085 unsigned int op0, op1, result, z, s;
1086
1087 trace_input ("tst", OP_REG_REG_CMP, 0);
1088
1089 /* Compute the result. */
1090 op0 = State.regs[ OP[0] ];
1091 op1 = State.regs[ OP[1] ];
1092 result = op0 & op1;
1093
1094 /* Compute the condition codes. */
1095 z = (result == 0);
1096 s = (result & 0x80000000);
1097
1098 /* Store the condition codes. */
1099 PSW &= ~(PSW_Z | PSW_S | PSW_OV);
1100 PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0));
1101 trace_output (OP_REG_REG_CMP);
1102
1103 return 2;
1104 }
1105
1106 /* mov sign_extend(imm5), reg */
1107 int
1108 OP_200 ()
1109 {
1110 int value = SEXT5 (OP[0]);
1111
1112 trace_input ("mov", OP_IMM_REG_MOVE, 0);
1113
1114 State.regs[ OP[1] ] = value;
1115
1116 trace_output (OP_IMM_REG_MOVE);
1117
1118 return 2;
1119 }
1120
1121 /* movhi imm16, reg, reg */
1122 int
1123 OP_640 ()
1124 {
1125 trace_input ("movhi", OP_UIMM16_REG_REG, 16);
1126
1127 State.regs[ OP[1] ] = State.regs[ OP[0] ] + (OP[2] << 16);
1128
1129 trace_output (OP_UIMM16_REG_REG);
1130
1131 return 4;
1132 }
1133
1134 /* sar zero_extend(imm5),reg1 */
1135 int
1136 OP_2A0 ()
1137 {
1138 unsigned int op0, op1, result, z, s, cy;
1139
1140 trace_input ("sar", OP_IMM_REG, 0);
1141 op0 = OP[0];
1142 op1 = State.regs[ OP[1] ];
1143 result = (signed)op1 >> op0;
1144
1145 /* Compute the condition codes. */
1146 z = (result == 0);
1147 s = (result & 0x80000000);
1148 cy = (op1 & (1 << (op0 - 1)));
1149
1150 /* Store the result and condition codes. */
1151 State.regs[ OP[1] ] = result;
1152 PSW &= ~(PSW_Z | PSW_S | PSW_OV | PSW_CY);
1153 PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
1154 | (cy ? PSW_CY : 0));
1155 trace_output (OP_IMM_REG);
1156
1157 return 2;
1158 }
1159
1160 /* sar reg1, reg2 */
1161 int
1162 OP_A007E0 ()
1163 {
1164 unsigned int op0, op1, result, z, s, cy;
1165
1166 trace_input ("sar", OP_REG_REG, 0);
1167
1168 op0 = State.regs[ OP[0] ] & 0x1f;
1169 op1 = State.regs[ OP[1] ];
1170 result = (signed)op1 >> op0;
1171
1172 /* Compute the condition codes. */
1173 z = (result == 0);
1174 s = (result & 0x80000000);
1175 cy = (op1 & (1 << (op0 - 1)));
1176
1177 /* Store the result and condition codes. */
1178 State.regs[OP[1]] = result;
1179 PSW &= ~(PSW_Z | PSW_S | PSW_OV | PSW_CY);
1180 PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
1181 | (cy ? PSW_CY : 0));
1182 trace_output (OP_REG_REG);
1183
1184 return 4;
1185 }
1186
1187 /* shl zero_extend(imm5),reg1 */
1188 int
1189 OP_2C0 ()
1190 {
1191 unsigned int op0, op1, result, z, s, cy;
1192
1193 trace_input ("shl", OP_IMM_REG, 0);
1194 op0 = OP[0];
1195 op1 = State.regs[ OP[1] ];
1196 result = op1 << op0;
1197
1198 /* Compute the condition codes. */
1199 z = (result == 0);
1200 s = (result & 0x80000000);
1201 cy = (op1 & (1 << (32 - op0)));
1202
1203 /* Store the result and condition codes. */
1204 State.regs[OP[1]] = result;
1205 PSW &= ~(PSW_Z | PSW_S | PSW_OV | PSW_CY);
1206 PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
1207 | (cy ? PSW_CY : 0));
1208 trace_output (OP_IMM_REG);
1209
1210 return 2;
1211 }
1212
1213 /* shl reg1, reg2 */
1214 int
1215 OP_C007E0 ()
1216 {
1217 unsigned int op0, op1, result, z, s, cy;
1218
1219 trace_input ("shl", OP_REG_REG, 0);
1220 op0 = State.regs[ OP[0] ] & 0x1f;
1221 op1 = State.regs[ OP[1] ];
1222 result = op1 << op0;
1223
1224 /* Compute the condition codes. */
1225 z = (result == 0);
1226 s = (result & 0x80000000);
1227 cy = (op1 & (1 << (32 - op0)));
1228
1229 /* Store the result and condition codes. */
1230 State.regs[OP[1]] = result;
1231 PSW &= ~(PSW_Z | PSW_S | PSW_OV | PSW_CY);
1232 PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
1233 | (cy ? PSW_CY : 0));
1234 trace_output (OP_REG_REG);
1235
1236 return 4;
1237 }
1238
1239 /* shr zero_extend(imm5),reg1 */
1240 int
1241 OP_280 ()
1242 {
1243 unsigned int op0, op1, result, z, s, cy;
1244
1245 trace_input ("shr", OP_IMM_REG, 0);
1246 op0 = OP[0];
1247 op1 = State.regs[ OP[1] ];
1248 result = op1 >> op0;
1249
1250 /* Compute the condition codes. */
1251 z = (result == 0);
1252 s = (result & 0x80000000);
1253 cy = (op1 & (1 << (op0 - 1)));
1254
1255 /* Store the result and condition codes. */
1256 State.regs[OP[1]] = result;
1257 PSW &= ~(PSW_Z | PSW_S | PSW_OV | PSW_CY);
1258 PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
1259 | (cy ? PSW_CY : 0));
1260 trace_output (OP_IMM_REG);
1261
1262 return 2;
1263 }
1264
1265 /* shr reg1, reg2 */
1266 int
1267 OP_8007E0 ()
1268 {
1269 unsigned int op0, op1, result, z, s, cy;
1270
1271 trace_input ("shr", OP_REG_REG, 0);
1272 op0 = State.regs[ OP[0] ] & 0x1f;
1273 op1 = State.regs[ OP[1] ];
1274 result = op1 >> op0;
1275
1276 /* Compute the condition codes. */
1277 z = (result == 0);
1278 s = (result & 0x80000000);
1279 cy = (op1 & (1 << (op0 - 1)));
1280
1281 /* Store the result and condition codes. */
1282 State.regs[OP[1]] = result;
1283 PSW &= ~(PSW_Z | PSW_S | PSW_OV | PSW_CY);
1284 PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
1285 | (cy ? PSW_CY : 0));
1286 trace_output (OP_REG_REG);
1287
1288 return 4;
1289 }
1290
1291 /* or reg, reg */
1292 int
1293 OP_100 ()
1294 {
1295 unsigned int op0, op1, result, z, s;
1296
1297 trace_input ("or", OP_REG_REG, 0);
1298
1299 /* Compute the result. */
1300 op0 = State.regs[ OP[0] ];
1301 op1 = State.regs[ OP[1] ];
1302 result = op0 | op1;
1303
1304 /* Compute the condition codes. */
1305 z = (result == 0);
1306 s = (result & 0x80000000);
1307
1308 /* Store the result and condition codes. */
1309 State.regs[OP[1]] = result;
1310 PSW &= ~(PSW_Z | PSW_S | PSW_OV);
1311 PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0));
1312 trace_output (OP_REG_REG);
1313
1314 return 2;
1315 }
1316
1317 /* ori zero_extend(imm16), reg, reg */
1318 int
1319 OP_680 ()
1320 {
1321 unsigned int op0, op1, result, z, s;
1322
1323 trace_input ("ori", OP_UIMM16_REG_REG, 0);
1324 op0 = OP[2];
1325 op1 = State.regs[ OP[0] ];
1326 result = op0 | op1;
1327
1328 /* Compute the condition codes. */
1329 z = (result == 0);
1330 s = (result & 0x80000000);
1331
1332 /* Store the result and condition codes. */
1333 State.regs[OP[1]] = result;
1334 PSW &= ~(PSW_Z | PSW_S | PSW_OV);
1335 PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0));
1336 trace_output (OP_UIMM16_REG_REG);
1337
1338 return 4;
1339 }
1340
1341 /* and reg, reg */
1342 int
1343 OP_140 ()
1344 {
1345 unsigned int op0, op1, result, z, s;
1346
1347 trace_input ("and", OP_REG_REG, 0);
1348
1349 /* Compute the result. */
1350 op0 = State.regs[ OP[0] ];
1351 op1 = State.regs[ OP[1] ];
1352 result = op0 & op1;
1353
1354 /* Compute the condition codes. */
1355 z = (result == 0);
1356 s = (result & 0x80000000);
1357
1358 /* Store the result and condition codes. */
1359 State.regs[OP[1]] = result;
1360 PSW &= ~(PSW_Z | PSW_S | PSW_OV);
1361 PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0));
1362 trace_output (OP_REG_REG);
1363
1364 return 2;
1365 }
1366
1367 /* andi zero_extend(imm16), reg, reg */
1368 int
1369 OP_6C0 ()
1370 {
1371 unsigned int result, z;
1372
1373 trace_input ("andi", OP_UIMM16_REG_REG, 0);
1374
1375 result = OP[2] & State.regs[ OP[0] ];
1376
1377 /* Compute the condition codes. */
1378 z = (result == 0);
1379
1380 /* Store the result and condition codes. */
1381 State.regs[ OP[1] ] = result;
1382
1383 PSW &= ~(PSW_Z | PSW_S | PSW_OV);
1384 PSW |= (z ? PSW_Z : 0);
1385
1386 trace_output (OP_UIMM16_REG_REG);
1387
1388 return 4;
1389 }
1390
1391 /* xor reg, reg */
1392 int
1393 OP_120 ()
1394 {
1395 unsigned int op0, op1, result, z, s;
1396
1397 trace_input ("xor", OP_REG_REG, 0);
1398
1399 /* Compute the result. */
1400 op0 = State.regs[ OP[0] ];
1401 op1 = State.regs[ OP[1] ];
1402 result = op0 ^ op1;
1403
1404 /* Compute the condition codes. */
1405 z = (result == 0);
1406 s = (result & 0x80000000);
1407
1408 /* Store the result and condition codes. */
1409 State.regs[OP[1]] = result;
1410 PSW &= ~(PSW_Z | PSW_S | PSW_OV);
1411 PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0));
1412 trace_output (OP_REG_REG);
1413
1414 return 2;
1415 }
1416
1417 /* xori zero_extend(imm16), reg, reg */
1418 int
1419 OP_6A0 ()
1420 {
1421 unsigned int op0, op1, result, z, s;
1422
1423 trace_input ("xori", OP_UIMM16_REG_REG, 0);
1424 op0 = OP[2];
1425 op1 = State.regs[ OP[0] ];
1426 result = op0 ^ op1;
1427
1428 /* Compute the condition codes. */
1429 z = (result == 0);
1430 s = (result & 0x80000000);
1431
1432 /* Store the result and condition codes. */
1433 State.regs[OP[1]] = result;
1434 PSW &= ~(PSW_Z | PSW_S | PSW_OV);
1435 PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0));
1436 trace_output (OP_UIMM16_REG_REG);
1437
1438 return 4;
1439 }
1440
1441 /* not reg1, reg2 */
1442 int
1443 OP_20 ()
1444 {
1445 unsigned int op0, result, z, s;
1446
1447 trace_input ("not", OP_REG_REG_MOVE, 0);
1448 /* Compute the result. */
1449 op0 = State.regs[ OP[0] ];
1450 result = ~op0;
1451
1452 /* Compute the condition codes. */
1453 z = (result == 0);
1454 s = (result & 0x80000000);
1455
1456 /* Store the result and condition codes. */
1457 State.regs[OP[1]] = result;
1458 PSW &= ~(PSW_Z | PSW_S | PSW_OV);
1459 PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0));
1460 trace_output (OP_REG_REG_MOVE);
1461
1462 return 2;
1463 }
1464
1465 /* set1 */
1466 int
1467 OP_7C0 ()
1468 {
1469 unsigned int op0, op1, op2;
1470 int temp;
1471
1472 trace_input ("set1", OP_BIT, 0);
1473 op0 = State.regs[ OP[0] ];
1474 op1 = OP[1] & 0x7;
1475 temp = EXTEND16 (OP[2]);
1476 op2 = temp;
1477 temp = load_mem (op0 + op2, 1);
1478 PSW &= ~PSW_Z;
1479 if ((temp & (1 << op1)) == 0)
1480 PSW |= PSW_Z;
1481 temp |= (1 << op1);
1482 store_mem (op0 + op2, 1, temp);
1483 trace_output (OP_BIT);
1484
1485 return 4;
1486 }
1487
1488 /* not1 */
1489 int
1490 OP_47C0 ()
1491 {
1492 unsigned int op0, op1, op2;
1493 int temp;
1494
1495 trace_input ("not1", OP_BIT, 0);
1496 op0 = State.regs[ OP[0] ];
1497 op1 = OP[1] & 0x7;
1498 temp = EXTEND16 (OP[2]);
1499 op2 = temp;
1500 temp = load_mem (op0 + op2, 1);
1501 PSW &= ~PSW_Z;
1502 if ((temp & (1 << op1)) == 0)
1503 PSW |= PSW_Z;
1504 temp ^= (1 << op1);
1505 store_mem (op0 + op2, 1, temp);
1506 trace_output (OP_BIT);
1507
1508 return 4;
1509 }
1510
1511 /* clr1 */
1512 int
1513 OP_87C0 ()
1514 {
1515 unsigned int op0, op1, op2;
1516 int temp;
1517
1518 trace_input ("clr1", OP_BIT, 0);
1519 op0 = State.regs[ OP[0] ];
1520 op1 = OP[1] & 0x7;
1521 temp = EXTEND16 (OP[2]);
1522 op2 = temp;
1523 temp = load_mem (op0 + op2, 1);
1524 PSW &= ~PSW_Z;
1525 if ((temp & (1 << op1)) == 0)
1526 PSW |= PSW_Z;
1527 temp &= ~(1 << op1);
1528 store_mem (op0 + op2, 1, temp);
1529 trace_output (OP_BIT);
1530
1531 return 4;
1532 }
1533
1534 /* tst1 */
1535 int
1536 OP_C7C0 ()
1537 {
1538 unsigned int op0, op1, op2;
1539 int temp;
1540
1541 trace_input ("tst1", OP_BIT, 0);
1542 op0 = State.regs[ OP[0] ];
1543 op1 = OP[1] & 0x7;
1544 temp = EXTEND16 (OP[2]);
1545 op2 = temp;
1546 temp = load_mem (op0 + op2, 1);
1547 PSW &= ~PSW_Z;
1548 if ((temp & (1 << op1)) == 0)
1549 PSW |= PSW_Z;
1550 trace_output (OP_BIT);
1551
1552 return 4;
1553 }
1554
1555 /* di */
1556 int
1557 OP_16007E0 ()
1558 {
1559 trace_input ("di", OP_NONE, 0);
1560 PSW |= PSW_ID;
1561 trace_output (OP_NONE);
1562
1563 return 4;
1564 }
1565
1566 /* ei */
1567 int
1568 OP_16087E0 ()
1569 {
1570 trace_input ("ei", OP_NONE, 0);
1571 PSW &= ~PSW_ID;
1572 trace_output (OP_NONE);
1573
1574 return 4;
1575 }
1576
1577 /* halt */
1578 int
1579 OP_12007E0 ()
1580 {
1581 trace_input ("halt", OP_NONE, 0);
1582 /* FIXME this should put processor into a mode where NMI still handled */
1583 trace_output (OP_NONE);
1584 sim_engine_halt (simulator, STATE_CPU (simulator, 0), NULL, PC,
1585 sim_stopped, SIM_SIGTRAP);
1586 return 0;
1587 }
1588
1589 /* trap */
1590 int
1591 OP_10007E0 ()
1592 {
1593 trace_input ("trap", OP_TRAP, 0);
1594 trace_output (OP_TRAP);
1595
1596 /* Trap 31 is used for simulating OS I/O functions */
1597
1598 if (OP[0] == 31)
1599 {
1600 int save_errno = errno;
1601 errno = 0;
1602
1603 /* Registers passed to trap 0 */
1604
1605 #define FUNC State.regs[6] /* function number, return value */
1606 #define PARM1 State.regs[7] /* optional parm 1 */
1607 #define PARM2 State.regs[8] /* optional parm 2 */
1608 #define PARM3 State.regs[9] /* optional parm 3 */
1609
1610 /* Registers set by trap 0 */
1611
1612 #define RETVAL State.regs[10] /* return value */
1613 #define RETERR State.regs[11] /* return error code */
1614
1615 /* Turn a pointer in a register into a pointer into real memory. */
1616
1617 #define MEMPTR(x) (map (x))
1618
1619 switch (FUNC)
1620 {
1621
1622 #ifdef HAVE_FORK
1623 #ifdef TARGET_SYS_fork
1624 case TARGET_SYS_fork:
1625 RETVAL = fork ();
1626 break;
1627 #endif
1628 #endif
1629
1630 #ifdef HAVE_EXECVE
1631 #ifdef TARGET_SYS_execv
1632 case TARGET_SYS_execve:
1633 {
1634 char *path = fetch_str (simulator, PARM1);
1635 char **argv = fetch_argv (simulator, PARM2);
1636 char **envp = fetch_argv (simulator, PARM3);
1637 RETVAL = execve (path, argv, envp);
1638 zfree (path);
1639 freeargv (argv);
1640 freeargv (envp);
1641 break;
1642 }
1643 #endif
1644 #endif
1645
1646 #if HAVE_EXECV
1647 #ifdef TARGET_SYS_execv
1648 case TARGET_SYS_execv:
1649 {
1650 char *path = fetch_str (simulator, PARM1);
1651 char **argv = fetch_argv (simulator, PARM2);
1652 RETVAL = execv (path, argv);
1653 zfree (path);
1654 freeargv (argv);
1655 break;
1656 }
1657 #endif
1658 #endif
1659
1660 #if 0
1661 #ifdef TARGET_SYS_pipe
1662 case TARGET_SYS_pipe:
1663 {
1664 reg_t buf;
1665 int host_fd[2];
1666
1667 buf = PARM1;
1668 RETVAL = pipe (host_fd);
1669 SW (buf, host_fd[0]);
1670 buf += sizeof(uint16);
1671 SW (buf, host_fd[1]);
1672 }
1673 break;
1674 #endif
1675 #endif
1676
1677 #if 0
1678 #ifdef TARGET_SYS_wait
1679 case TARGET_SYS_wait:
1680 {
1681 int status;
1682
1683 RETVAL = wait (&status);
1684 SW (PARM1, status);
1685 }
1686 break;
1687 #endif
1688 #endif
1689
1690 #ifdef TARGET_SYS_read
1691 case TARGET_SYS_read:
1692 {
1693 char *buf = zalloc (PARM3);
1694 RETVAL = sim_io_read (simulator, PARM1, buf, PARM3);
1695 sim_write (simulator, PARM2, buf, PARM3);
1696 zfree (buf);
1697 break;
1698 }
1699 #endif
1700
1701 #ifdef TARGET_SYS_write
1702 case TARGET_SYS_write:
1703 {
1704 char *buf = zalloc (PARM3);
1705 sim_read (simulator, PARM2, buf, PARM3);
1706 if (PARM1 == 1)
1707 RETVAL = sim_io_write_stdout (simulator, buf, PARM3);
1708 else
1709 RETVAL = sim_io_write (simulator, PARM1, buf, PARM3);
1710 zfree (buf);
1711 break;
1712 }
1713 #endif
1714
1715 #ifdef TARGET_SYS_lseek
1716 case TARGET_SYS_lseek:
1717 RETVAL = sim_io_lseek (simulator, PARM1, PARM2, PARM3);
1718 break;
1719 #endif
1720
1721 #ifdef TARGET_SYS_close
1722 case TARGET_SYS_close:
1723 RETVAL = sim_io_close (simulator, PARM1);
1724 break;
1725 #endif
1726
1727 #ifdef TARGET_SYS_open
1728 case TARGET_SYS_open:
1729 {
1730 char *buf = fetch_str (simulator, PARM1);
1731 RETVAL = sim_io_open (simulator, buf, PARM2);
1732 zfree (buf);
1733 break;
1734 }
1735 #endif
1736
1737 #ifdef TARGET_SYS_exit
1738 case TARGET_SYS_exit:
1739 if ((PARM1 & 0xffff0000) == 0xdead0000 && (PARM1 & 0xffff) != 0)
1740 /* get signal encoded by kill */
1741 sim_engine_halt (simulator, STATE_CPU (simulator, 0), NULL, PC,
1742 sim_signalled, PARM1 & 0xffff);
1743 else if (PARM1 == 0xdead)
1744 /* old libraries */
1745 sim_engine_halt (simulator, STATE_CPU (simulator, 0), NULL, PC,
1746 sim_stopped, SIM_SIGABRT);
1747 else
1748 /* PARM1 has exit status */
1749 sim_engine_halt (simulator, STATE_CPU (simulator, 0), NULL, PC,
1750 sim_exited, PARM1);
1751 break;
1752 #endif
1753
1754 #if !defined(__GO32__) && !defined(_WIN32)
1755 #ifdef TARGET_SYS_stat
1756 case TARGET_SYS_stat: /* added at hmsi */
1757 /* stat system call */
1758 {
1759 struct stat host_stat;
1760 reg_t buf;
1761 char *path = fetch_str (simulator, PARM1);
1762
1763 RETVAL = stat (path, &host_stat);
1764
1765 zfree (path);
1766 buf = PARM2;
1767
1768 /* Just wild-assed guesses. */
1769 store_mem (buf, 2, host_stat.st_dev);
1770 store_mem (buf + 2, 2, host_stat.st_ino);
1771 store_mem (buf + 4, 4, host_stat.st_mode);
1772 store_mem (buf + 8, 2, host_stat.st_nlink);
1773 store_mem (buf + 10, 2, host_stat.st_uid);
1774 store_mem (buf + 12, 2, host_stat.st_gid);
1775 store_mem (buf + 14, 2, host_stat.st_rdev);
1776 store_mem (buf + 16, 4, host_stat.st_size);
1777 store_mem (buf + 20, 4, host_stat.st_atime);
1778 store_mem (buf + 28, 4, host_stat.st_mtime);
1779 store_mem (buf + 36, 4, host_stat.st_ctime);
1780 }
1781 break;
1782 #endif
1783 #endif
1784
1785 #ifdef HAVE_CHOWN
1786 #ifdef TARGET_SYS_chown
1787 case TARGET_SYS_chown:
1788 {
1789 char *path = fetch_str (simulator, PARM1);
1790 RETVAL = chown (path, PARM2, PARM3);
1791 zfree (path);
1792 }
1793 break;
1794 #endif
1795 #endif
1796
1797 #if HAVE_CHMOD
1798 #ifdef TARGET_SYS_chmod
1799 case TARGET_SYS_chmod:
1800 {
1801 char *path = fetch_str (simulator, PARM1);
1802 RETVAL = chmod (path, PARM2);
1803 zfree (path);
1804 }
1805 break;
1806 #endif
1807 #endif
1808
1809 #ifdef TARGET_SYS_time
1810 #if HAVE_TIME
1811 case TARGET_SYS_time:
1812 {
1813 time_t now;
1814 RETVAL = time (&now);
1815 store_mem (PARM1, 4, now);
1816 }
1817 break;
1818 #endif
1819 #endif
1820
1821 #if !defined(__GO32__) && !defined(_WIN32)
1822 #ifdef TARGET_SYS_times
1823 case TARGET_SYS_times:
1824 {
1825 struct tms tms;
1826 RETVAL = times (&tms);
1827 store_mem (PARM1, 4, tms.tms_utime);
1828 store_mem (PARM1 + 4, 4, tms.tms_stime);
1829 store_mem (PARM1 + 8, 4, tms.tms_cutime);
1830 store_mem (PARM1 + 12, 4, tms.tms_cstime);
1831 break;
1832 }
1833 #endif
1834 #endif
1835
1836 #ifdef TARGET_SYS_gettimeofday
1837 #if !defined(__GO32__) && !defined(_WIN32)
1838 case TARGET_SYS_gettimeofday:
1839 {
1840 struct timeval t;
1841 struct timezone tz;
1842 RETVAL = gettimeofday (&t, &tz);
1843 store_mem (PARM1, 4, t.tv_sec);
1844 store_mem (PARM1 + 4, 4, t.tv_usec);
1845 store_mem (PARM2, 4, tz.tz_minuteswest);
1846 store_mem (PARM2 + 4, 4, tz.tz_dsttime);
1847 break;
1848 }
1849 #endif
1850 #endif
1851
1852 #ifdef TARGET_SYS_utime
1853 #if HAVE_UTIME
1854 case TARGET_SYS_utime:
1855 {
1856 /* Cast the second argument to void *, to avoid type mismatch
1857 if a prototype is present. */
1858 sim_io_error (simulator, "Utime not supported");
1859 /* RETVAL = utime (path, (void *) MEMPTR (PARM2)); */
1860 }
1861 break;
1862 #endif
1863 #endif
1864
1865 default:
1866 abort ();
1867 }
1868 RETERR = errno;
1869 errno = save_errno;
1870
1871 return 4;
1872 }
1873 else
1874 { /* Trap 0 -> 30 */
1875 EIPC = PC + 4;
1876 EIPSW = PSW;
1877 /* Mask out EICC */
1878 ECR &= 0xffff0000;
1879 ECR |= 0x40 + OP[0];
1880 /* Flag that we are now doing exception processing. */
1881 PSW |= PSW_EP | PSW_ID;
1882 PC = ((OP[0] < 0x10) ? 0x40 : 0x50) - 4;
1883
1884 return 0;
1885 }
1886 }
1887
1888 /* tst1 reg2, [reg1] */
1889 int
1890 OP_E607E0 (void)
1891 {
1892 int temp;
1893
1894 trace_input ("tst1", OP_BIT, 1);
1895
1896 temp = load_mem (State.regs[ OP[0] ], 1);
1897
1898 PSW &= ~PSW_Z;
1899 if ((temp & (1 << State.regs[ OP[1] & 0x7 ])) == 0)
1900 PSW |= PSW_Z;
1901
1902 trace_output (OP_BIT);
1903
1904 return 4;
1905 }
1906
1907 /* mulu reg1, reg2, reg3 */
1908 int
1909 OP_22207E0 (void)
1910 {
1911 trace_input ("mulu", OP_REG_REG_REG, 0);
1912
1913 Multiply64 (false, State.regs[ OP[0] ]);
1914
1915 trace_output (OP_REG_REG_REG);
1916
1917 return 4;
1918 }
1919
1920 #define BIT_CHANGE_OP( name, binop ) \
1921 unsigned int bit; \
1922 unsigned int temp; \
1923 \
1924 trace_input (name, OP_BIT_CHANGE, 0); \
1925 \
1926 bit = 1 << State.regs[ OP[1] & 0x7 ]; \
1927 temp = load_mem (State.regs[ OP[0] ], 1); \
1928 \
1929 PSW &= ~PSW_Z; \
1930 if ((temp & bit) == 0) \
1931 PSW |= PSW_Z; \
1932 temp binop bit; \
1933 \
1934 store_mem (State.regs[ OP[0] ], 1, temp); \
1935 \
1936 trace_output (OP_BIT_CHANGE); \
1937 \
1938 return 4;
1939
1940 /* clr1 reg2, [reg1] */
1941 int
1942 OP_E407E0 (void)
1943 {
1944 BIT_CHANGE_OP ("clr1", &= ~ );
1945 }
1946
1947 /* not1 reg2, [reg1] */
1948 int
1949 OP_E207E0 (void)
1950 {
1951 BIT_CHANGE_OP ("not1", ^= );
1952 }
1953
1954 /* set1 */
1955 int
1956 OP_E007E0 (void)
1957 {
1958 BIT_CHANGE_OP ("set1", |= );
1959 }
1960
1961 /* sasf */
1962 int
1963 OP_20007E0 (void)
1964 {
1965 trace_input ("sasf", OP_EX1, 0);
1966
1967 State.regs[ OP[1] ] = (State.regs[ OP[1] ] << 1) | condition_met (OP[0]);
1968
1969 trace_output (OP_EX1);
1970
1971 return 4;
1972 }
1973
1974 /* This function is courtesy of Sugimoto at NEC, via Seow Tan
1975 (Soew_Tan@el.nec.com) */
1976 void
1977 divun
1978 (
1979 unsigned int N,
1980 unsigned long int als,
1981 unsigned long int sfi,
1982 unsigned32 /*unsigned long int*/ * quotient_ptr,
1983 unsigned32 /*unsigned long int*/ * remainder_ptr,
1984 boolean * overflow_ptr
1985 )
1986 {
1987 unsigned long ald = sfi >> (N - 1);
1988 unsigned long alo = als;
1989 unsigned int Q = 1;
1990 unsigned int C;
1991 unsigned int S = 0;
1992 unsigned int i;
1993 unsigned int R1 = 1;
1994 unsigned int DBZ = (als == 0) ? 1 : 0;
1995 unsigned long alt = Q ? ~als : als;
1996
1997 /* 1st Loop */
1998 alo = ald + alt + Q;
1999 C = (((alt >> 31) & (ald >> 31))
2000 | (((alt >> 31) ^ (ald >> 31)) & (~alo >> 31)));
2001 C = C ^ Q;
2002 Q = ~(C ^ S) & 1;
2003 R1 = (alo == 0) ? 0 : (R1 & Q);
2004 if ((S ^ (alo>>31)) && !C)
2005 {
2006 DBZ = 1;
2007 }
2008 S = alo >> 31;
2009 sfi = (sfi << (32-N+1)) | Q;
2010 ald = (alo << 1) | (sfi >> 31);
2011
2012 /* 2nd - N-1th Loop */
2013 for (i = 2; i < N; i++)
2014 {
2015 alt = Q ? ~als : als;
2016 alo = ald + alt + Q;
2017 C = (((alt >> 31) & (ald >> 31))
2018 | (((alt >> 31) ^ (ald >> 31)) & (~alo >> 31)));
2019 C = C ^ Q;
2020 Q = ~(C ^ S) & 1;
2021 R1 = (alo == 0) ? 0 : (R1 & Q);
2022 if ((S ^ (alo>>31)) && !C && !DBZ)
2023 {
2024 DBZ = 1;
2025 }
2026 S = alo >> 31;
2027 sfi = (sfi << 1) | Q;
2028 ald = (alo << 1) | (sfi >> 31);
2029 }
2030
2031 /* Nth Loop */
2032 alt = Q ? ~als : als;
2033 alo = ald + alt + Q;
2034 C = (((alt >> 31) & (ald >> 31))
2035 | (((alt >> 31) ^ (ald >> 31)) & (~alo >> 31)));
2036 C = C ^ Q;
2037 Q = ~(C ^ S) & 1;
2038 R1 = (alo == 0) ? 0 : (R1 & Q);
2039 if ((S ^ (alo>>31)) && !C)
2040 {
2041 DBZ = 1;
2042 }
2043
2044 * quotient_ptr = (sfi << 1) | Q;
2045 * remainder_ptr = Q ? alo : (alo + als);
2046 * overflow_ptr = DBZ | R1;
2047 }
2048
2049 /* This function is courtesy of Sugimoto at NEC, via Seow Tan (Soew_Tan@el.nec.com) */
2050 void
2051 divn
2052 (
2053 unsigned int N,
2054 unsigned long int als,
2055 unsigned long int sfi,
2056 signed32 /*signed long int*/ * quotient_ptr,
2057 signed32 /*signed long int*/ * remainder_ptr,
2058 boolean * overflow_ptr
2059 )
2060 {
2061 unsigned long ald = (signed long) sfi >> (N - 1);
2062 unsigned long alo = als;
2063 unsigned int SS = als >> 31;
2064 unsigned int SD = sfi >> 31;
2065 unsigned int R1 = 1;
2066 unsigned int OV;
2067 unsigned int DBZ = als == 0 ? 1 : 0;
2068 unsigned int Q = ~(SS ^ SD) & 1;
2069 unsigned int C;
2070 unsigned int S;
2071 unsigned int i;
2072 unsigned long alt = Q ? ~als : als;
2073
2074
2075 /* 1st Loop */
2076
2077 alo = ald + alt + Q;
2078 C = (((alt >> 31) & (ald >> 31))
2079 | (((alt >> 31) ^ (ald >> 31)) & (~alo >> 31)));
2080 Q = C ^ SS;
2081 R1 = (alo == 0) ? 0 : (R1 & (Q ^ (SS ^ SD)));
2082 S = alo >> 31;
2083 sfi = (sfi << (32-N+1)) | Q;
2084 ald = (alo << 1) | (sfi >> 31);
2085 if ((alo >> 31) ^ (ald >> 31))
2086 {
2087 DBZ = 1;
2088 }
2089
2090 /* 2nd - N-1th Loop */
2091
2092 for (i = 2; i < N; i++)
2093 {
2094 alt = Q ? ~als : als;
2095 alo = ald + alt + Q;
2096 C = (((alt >> 31) & (ald >> 31))
2097 | (((alt >> 31) ^ (ald >> 31)) & (~alo >> 31)));
2098 Q = C ^ SS;
2099 R1 = (alo == 0) ? 0 : (R1 & (Q ^ (SS ^ SD)));
2100 S = alo >> 31;
2101 sfi = (sfi << 1) | Q;
2102 ald = (alo << 1) | (sfi >> 31);
2103 if ((alo >> 31) ^ (ald >> 31))
2104 {
2105 DBZ = 1;
2106 }
2107 }
2108
2109 /* Nth Loop */
2110 alt = Q ? ~als : als;
2111 alo = ald + alt + Q;
2112 C = (((alt >> 31) & (ald >> 31))
2113 | (((alt >> 31) ^ (ald >> 31)) & (~alo >> 31)));
2114 Q = C ^ SS;
2115 R1 = (alo == 0) ? 0 : (R1 & (Q ^ (SS ^ SD)));
2116 sfi = (sfi << (32-N+1));
2117 ald = alo;
2118
2119 /* End */
2120 if (alo != 0)
2121 {
2122 alt = Q ? ~als : als;
2123 alo = ald + alt + Q;
2124 }
2125 R1 = R1 & ((~alo >> 31) ^ SD);
2126 if ((alo != 0) && ((Q ^ (SS ^ SD)) ^ R1)) alo = ald;
2127 if (N != 32)
2128 ald = sfi = (long) ((sfi >> 1) | (SS ^ SD) << 31) >> (32-N-1) | Q;
2129 else
2130 ald = sfi = sfi | Q;
2131
2132 OV = DBZ | ((alo == 0) ? 0 : R1);
2133
2134 * remainder_ptr = alo;
2135
2136 /* Adj */
2137 if (((alo != 0) && ((SS ^ SD) ^ R1))
2138 || ((alo == 0) && (SS ^ R1)))
2139 alo = ald + 1;
2140 else
2141 alo = ald;
2142
2143 OV = (DBZ | R1) ? OV : ((alo >> 31) & (~ald >> 31));
2144
2145 * quotient_ptr = alo;
2146 * overflow_ptr = OV;
2147 }
2148
2149 /* sdivun imm5, reg1, reg2, reg3 */
2150 int
2151 OP_1C207E0 (void)
2152 {
2153 unsigned32 /*unsigned long int*/ quotient;
2154 unsigned32 /*unsigned long int*/ remainder;
2155 unsigned long int divide_by;
2156 unsigned long int divide_this;
2157 boolean overflow = false;
2158 unsigned int imm5;
2159
2160 trace_input ("sdivun", OP_IMM_REG_REG_REG, 0);
2161
2162 imm5 = 32 - ((OP[3] & 0x3c0000) >> 17);
2163
2164 divide_by = State.regs[ OP[0] ];
2165 divide_this = State.regs[ OP[1] ] << imm5;
2166
2167 divun (imm5, divide_by, divide_this, & quotient, & remainder, & overflow);
2168
2169 State.regs[ OP[1] ] = quotient;
2170 State.regs[ OP[2] >> 11 ] = remainder;
2171
2172 /* Set condition codes. */
2173 PSW &= ~(PSW_Z | PSW_S | PSW_OV);
2174
2175 if (overflow) PSW |= PSW_OV;
2176 if (quotient == 0) PSW |= PSW_Z;
2177 if (quotient & 0x80000000) PSW |= PSW_S;
2178
2179 trace_output (OP_IMM_REG_REG_REG);
2180
2181 return 4;
2182 }
2183
2184 /* sdivn imm5, reg1, reg2, reg3 */
2185 int
2186 OP_1C007E0 (void)
2187 {
2188 signed32 /*signed long int*/ quotient;
2189 signed32 /*signed long int*/ remainder;
2190 signed long int divide_by;
2191 signed long int divide_this;
2192 boolean overflow = false;
2193 unsigned int imm5;
2194
2195 trace_input ("sdivn", OP_IMM_REG_REG_REG, 0);
2196
2197 imm5 = 32 - ((OP[3] & 0x3c0000) >> 17);
2198
2199 divide_by = State.regs[ OP[0] ];
2200 divide_this = State.regs[ OP[1] ] << imm5;
2201
2202 divn (imm5, divide_by, divide_this, & quotient, & remainder, & overflow);
2203
2204 State.regs[ OP[1] ] = quotient;
2205 State.regs[ OP[2] >> 11 ] = remainder;
2206
2207 /* Set condition codes. */
2208 PSW &= ~(PSW_Z | PSW_S | PSW_OV);
2209
2210 if (overflow) PSW |= PSW_OV;
2211 if (quotient == 0) PSW |= PSW_Z;
2212 if (quotient < 0) PSW |= PSW_S;
2213
2214 trace_output (OP_IMM_REG_REG_REG);
2215
2216 return 4;
2217 }
2218
2219 /* sdivhun imm5, reg1, reg2, reg3 */
2220 int
2221 OP_18207E0 (void)
2222 {
2223 unsigned32 /*unsigned long int*/ quotient;
2224 unsigned32 /*unsigned long int*/ remainder;
2225 unsigned long int divide_by;
2226 unsigned long int divide_this;
2227 boolean overflow = false;
2228 unsigned int imm5;
2229
2230 trace_input ("sdivhun", OP_IMM_REG_REG_REG, 0);
2231
2232 imm5 = 32 - ((OP[3] & 0x3c0000) >> 17);
2233
2234 divide_by = State.regs[ OP[0] ] & 0xffff;
2235 divide_this = State.regs[ OP[1] ] << imm5;
2236
2237 divun (imm5, divide_by, divide_this, & quotient, & remainder, & overflow);
2238
2239 State.regs[ OP[1] ] = quotient;
2240 State.regs[ OP[2] >> 11 ] = remainder;
2241
2242 /* Set condition codes. */
2243 PSW &= ~(PSW_Z | PSW_S | PSW_OV);
2244
2245 if (overflow) PSW |= PSW_OV;
2246 if (quotient == 0) PSW |= PSW_Z;
2247 if (quotient & 0x80000000) PSW |= PSW_S;
2248
2249 trace_output (OP_IMM_REG_REG_REG);
2250
2251 return 4;
2252 }
2253
2254 /* sdivhn imm5, reg1, reg2, reg3 */
2255 int
2256 OP_18007E0 (void)
2257 {
2258 signed32 /*signed long int*/ quotient;
2259 signed32 /*signed long int*/ remainder;
2260 signed long int divide_by;
2261 signed long int divide_this;
2262 boolean overflow = false;
2263 unsigned int imm5;
2264
2265 trace_input ("sdivhn", OP_IMM_REG_REG_REG, 0);
2266
2267 imm5 = 32 - ((OP[3] & 0x3c0000) >> 17);
2268
2269 divide_by = EXTEND16 (State.regs[ OP[0] ]);
2270 divide_this = State.regs[ OP[1] ] << imm5;
2271
2272 divn (imm5, divide_by, divide_this, & quotient, & remainder, & overflow);
2273
2274 State.regs[ OP[1] ] = quotient;
2275 State.regs[ OP[2] >> 11 ] = remainder;
2276
2277 /* Set condition codes. */
2278 PSW &= ~(PSW_Z | PSW_S | PSW_OV);
2279
2280 if (overflow) PSW |= PSW_OV;
2281 if (quotient == 0) PSW |= PSW_Z;
2282 if (quotient < 0) PSW |= PSW_S;
2283
2284 trace_output (OP_IMM_REG_REG_REG);
2285
2286 return 4;
2287 }
2288
2289 /* divu reg1, reg2, reg3 */
2290 int
2291 OP_2C207E0 (void)
2292 {
2293 unsigned long int quotient;
2294 unsigned long int remainder;
2295 unsigned long int divide_by;
2296 unsigned long int divide_this;
2297 boolean overflow = false;
2298
2299 trace_input ("divu", OP_REG_REG_REG, 0);
2300
2301 /* Compute the result. */
2302
2303 divide_by = State.regs[ OP[0] ];
2304 divide_this = State.regs[ OP[1] ];
2305
2306 if (divide_by == 0)
2307 {
2308 overflow = true;
2309 divide_by = 1;
2310 }
2311
2312 State.regs[ OP[1] ] = quotient = divide_this / divide_by;
2313 State.regs[ OP[2] >> 11 ] = remainder = divide_this % divide_by;
2314
2315 /* Set condition codes. */
2316 PSW &= ~(PSW_Z | PSW_S | PSW_OV);
2317
2318 if (overflow) PSW |= PSW_OV;
2319 if (quotient == 0) PSW |= PSW_Z;
2320 if (quotient & 0x80000000) PSW |= PSW_S;
2321
2322 trace_output (OP_REG_REG_REG);
2323
2324 return 4;
2325 }
2326
2327 /* div reg1, reg2, reg3 */
2328 int
2329 OP_2C007E0 (void)
2330 {
2331 signed long int quotient;
2332 signed long int remainder;
2333 signed long int divide_by;
2334 signed long int divide_this;
2335 boolean overflow = false;
2336
2337 trace_input ("div", OP_REG_REG_REG, 0);
2338
2339 /* Compute the result. */
2340
2341 divide_by = State.regs[ OP[0] ];
2342 divide_this = State.regs[ OP[1] ];
2343
2344 if (divide_by == 0 || (divide_by == -1 && divide_this == (1 << 31)))
2345 {
2346 overflow = true;
2347 divide_by = 1;
2348 }
2349
2350 State.regs[ OP[1] ] = quotient = divide_this / divide_by;
2351 State.regs[ OP[2] >> 11 ] = remainder = divide_this % divide_by;
2352
2353 /* Set condition codes. */
2354 PSW &= ~(PSW_Z | PSW_S | PSW_OV);
2355
2356 if (overflow) PSW |= PSW_OV;
2357 if (quotient == 0) PSW |= PSW_Z;
2358 if (quotient < 0) PSW |= PSW_S;
2359
2360 trace_output (OP_REG_REG_REG);
2361
2362 return 4;
2363 }
2364
2365 /* divhu reg1, reg2, reg3 */
2366 int
2367 OP_28207E0 (void)
2368 {
2369 unsigned long int quotient;
2370 unsigned long int remainder;
2371 unsigned long int divide_by;
2372 unsigned long int divide_this;
2373 boolean overflow = false;
2374
2375 trace_input ("divhu", OP_REG_REG_REG, 0);
2376
2377 /* Compute the result. */
2378
2379 divide_by = State.regs[ OP[0] ] & 0xffff;
2380 divide_this = State.regs[ OP[1] ];
2381
2382 if (divide_by == 0)
2383 {
2384 overflow = true;
2385 divide_by = 1;
2386 }
2387
2388 State.regs[ OP[1] ] = quotient = divide_this / divide_by;
2389 State.regs[ OP[2] >> 11 ] = remainder = divide_this % divide_by;
2390
2391 /* Set condition codes. */
2392 PSW &= ~(PSW_Z | PSW_S | PSW_OV);
2393
2394 if (overflow) PSW |= PSW_OV;
2395 if (quotient == 0) PSW |= PSW_Z;
2396 if (quotient & 0x80000000) PSW |= PSW_S;
2397
2398 trace_output (OP_REG_REG_REG);
2399
2400 return 4;
2401 }
2402
2403 /* divh reg1, reg2, reg3 */
2404 int
2405 OP_28007E0 (void)
2406 {
2407 signed long int quotient;
2408 signed long int remainder;
2409 signed long int divide_by;
2410 signed long int divide_this;
2411 boolean overflow = false;
2412
2413 trace_input ("divh", OP_REG_REG_REG, 0);
2414
2415 /* Compute the result. */
2416
2417 divide_by = State.regs[ OP[0] ];
2418 divide_this = EXTEND16 (State.regs[ OP[1] ]);
2419
2420 if (divide_by == 0 || (divide_by == -1 && divide_this == (1 << 31)))
2421 {
2422 overflow = true;
2423 divide_by = 1;
2424 }
2425
2426 State.regs[ OP[1] ] = quotient = divide_this / divide_by;
2427 State.regs[ OP[2] >> 11 ] = remainder = divide_this % divide_by;
2428
2429 /* Set condition codes. */
2430 PSW &= ~(PSW_Z | PSW_S | PSW_OV);
2431
2432 if (overflow) PSW |= PSW_OV;
2433 if (quotient == 0) PSW |= PSW_Z;
2434 if (quotient < 0) PSW |= PSW_S;
2435
2436 trace_output (OP_REG_REG_REG);
2437
2438 return 4;
2439 }
2440
2441 /* mulu imm9, reg2, reg3 */
2442 int
2443 OP_24207E0 (void)
2444 {
2445 trace_input ("mulu", OP_IMM_REG_REG, 0);
2446
2447 Multiply64 (false, (OP[3] & 0x1f) | ((OP[3] >> 13) & 0x1e0));
2448
2449 trace_output (OP_IMM_REG_REG);
2450
2451 return 4;
2452 }
2453
2454 /* mul imm9, reg2, reg3 */
2455 int
2456 OP_24007E0 (void)
2457 {
2458 trace_input ("mul", OP_IMM_REG_REG, 0);
2459
2460 Multiply64 (true, (OP[3] & 0x1f) | ((OP[3] >> 13) & 0x1e0));
2461
2462 trace_output (OP_IMM_REG_REG);
2463
2464 return 4;
2465 }
2466
2467 /* ld.hu */
2468 int
2469 OP_107E0 (void)
2470 {
2471 int adr;
2472
2473 trace_input ("ld.hu", OP_LOAD32, 2);
2474
2475 adr = State.regs[ OP[0] ] + EXTEND16 (OP[2] & ~1);
2476 adr &= ~0x1;
2477
2478 State.regs[ OP[1] ] = load_mem (adr, 2);
2479
2480 trace_output (OP_LOAD32);
2481
2482 return 4;
2483 }
2484
2485
2486 /* ld.bu */
2487 int
2488 OP_10780 (void)
2489 {
2490 int adr;
2491
2492 trace_input ("ld.bu", OP_LOAD32, 1);
2493
2494 adr = (State.regs[ OP[0] ]
2495 + (EXTEND16 (OP[2] & ~1) | ((OP[3] >> 5) & 1)));
2496
2497 State.regs[ OP[1] ] = load_mem (adr, 1);
2498
2499 trace_output (OP_LOAD32);
2500
2501 return 4;
2502 }
2503
2504 /* prepare list12, imm5, imm32 */
2505 int
2506 OP_1B0780 (void)
2507 {
2508 int i;
2509
2510 trace_input ("prepare", OP_PUSHPOP1, 0);
2511
2512 /* Store the registers with lower number registers being placed at higher addresses. */
2513 for (i = 0; i < 12; i++)
2514 if ((OP[3] & (1 << type1_regs[ i ])))
2515 {
2516 SP -= 4;
2517 store_mem (SP, 4, State.regs[ 20 + i ]);
2518 }
2519
2520 SP -= (OP[3] & 0x3e) << 1;
2521
2522 EP = load_mem (PC + 4, 4);
2523
2524 trace_output (OP_PUSHPOP1);
2525
2526 return 8;
2527 }
2528
2529 /* prepare list12, imm5, imm16-32 */
2530 int
2531 OP_130780 (void)
2532 {
2533 int i;
2534
2535 trace_input ("prepare", OP_PUSHPOP1, 0);
2536
2537 /* Store the registers with lower number registers being placed at higher addresses. */
2538 for (i = 0; i < 12; i++)
2539 if ((OP[3] & (1 << type1_regs[ i ])))
2540 {
2541 SP -= 4;
2542 store_mem (SP, 4, State.regs[ 20 + i ]);
2543 }
2544
2545 SP -= (OP[3] & 0x3e) << 1;
2546
2547 EP = load_mem (PC + 4, 2) << 16;
2548
2549 trace_output (OP_PUSHPOP1);
2550
2551 return 6;
2552 }
2553
2554 /* prepare list12, imm5, imm16 */
2555 int
2556 OP_B0780 (void)
2557 {
2558 int i;
2559
2560 trace_input ("prepare", OP_PUSHPOP1, 0);
2561
2562 /* Store the registers with lower number registers being placed at higher addresses. */
2563 for (i = 0; i < 12; i++)
2564 if ((OP[3] & (1 << type1_regs[ i ])))
2565 {
2566 SP -= 4;
2567 store_mem (SP, 4, State.regs[ 20 + i ]);
2568 }
2569
2570 SP -= (OP[3] & 0x3e) << 1;
2571
2572 EP = EXTEND16 (load_mem (PC + 4, 2));
2573
2574 trace_output (OP_PUSHPOP1);
2575
2576 return 6;
2577 }
2578
2579 /* prepare list12, imm5, sp */
2580 int
2581 OP_30780 (void)
2582 {
2583 int i;
2584
2585 trace_input ("prepare", OP_PUSHPOP1, 0);
2586
2587 /* Store the registers with lower number registers being placed at higher addresses. */
2588 for (i = 0; i < 12; i++)
2589 if ((OP[3] & (1 << type1_regs[ i ])))
2590 {
2591 SP -= 4;
2592 store_mem (SP, 4, State.regs[ 20 + i ]);
2593 }
2594
2595 SP -= (OP[3] & 0x3e) << 1;
2596
2597 EP = SP;
2598
2599 trace_output (OP_PUSHPOP1);
2600
2601 return 4;
2602 }
2603
2604 /* mul reg1, reg2, reg3 */
2605 int
2606 OP_22007E0 (void)
2607 {
2608 trace_input ("mul", OP_REG_REG_REG, 0);
2609
2610 Multiply64 (true, State.regs[ OP[0] ]);
2611
2612 trace_output (OP_REG_REG_REG);
2613
2614 return 4;
2615 }
2616
2617 /* popmh list18 */
2618 int
2619 OP_307F0 (void)
2620 {
2621 int i;
2622
2623 trace_input ("popmh", OP_PUSHPOP2, 0);
2624
2625 if (OP[3] & (1 << 19))
2626 {
2627 if ((PSW & PSW_NP) && ((PSW & PSW_EP) == 0))
2628 {
2629 FEPSW = load_mem ( SP & ~ 3, 4);
2630 FEPC = load_mem ((SP + 4) & ~ 3, 4);
2631 }
2632 else
2633 {
2634 EIPSW = load_mem ( SP & ~ 3, 4);
2635 EIPC = load_mem ((SP + 4) & ~ 3, 4);
2636 }
2637
2638 SP += 8;
2639 }
2640
2641 /* Load the registers with lower number registers being retrieved from higher addresses. */
2642 for (i = 16; i--;)
2643 if ((OP[3] & (1 << type2_regs[ i ])))
2644 {
2645 State.regs[ i + 16 ] = load_mem (SP & ~ 3, 4);
2646 SP += 4;
2647 }
2648
2649 trace_output (OP_PUSHPOP2);
2650
2651 return 4;
2652 }
2653
2654 /* popml lsit18 */
2655 int
2656 OP_107F0 (void)
2657 {
2658 int i;
2659
2660 trace_input ("popml", OP_PUSHPOP3, 0);
2661
2662 if (OP[3] & (1 << 19))
2663 {
2664 if ((PSW & PSW_NP) && ((PSW & PSW_EP) == 0))
2665 {
2666 FEPSW = load_mem ( SP & ~ 3, 4);
2667 FEPC = load_mem ((SP + 4) & ~ 3, 4);
2668 }
2669 else
2670 {
2671 EIPSW = load_mem ( SP & ~ 3, 4);
2672 EIPC = load_mem ((SP + 4) & ~ 3, 4);
2673 }
2674
2675 SP += 8;
2676 }
2677
2678 if (OP[3] & (1 << 3))
2679 {
2680 PSW = load_mem (SP & ~ 3, 4);
2681 SP += 4;
2682 }
2683
2684 /* Load the registers with lower number registers being retrieved from higher addresses. */
2685 for (i = 15; i--;)
2686 if ((OP[3] & (1 << type3_regs[ i ])))
2687 {
2688 State.regs[ i + 1 ] = load_mem (SP & ~ 3, 4);
2689 SP += 4;
2690 }
2691
2692 trace_output (OP_PUSHPOP2);
2693
2694 return 4;
2695 }
2696
2697 /* pushmh list18 */
2698 int
2699 OP_307E0 (void)
2700 {
2701 int i;
2702
2703 trace_input ("pushmh", OP_PUSHPOP2, 0);
2704
2705 /* Store the registers with lower number registers being placed at higher addresses. */
2706 for (i = 0; i < 16; i++)
2707 if ((OP[3] & (1 << type2_regs[ i ])))
2708 {
2709 SP -= 4;
2710 store_mem (SP & ~ 3, 4, State.regs[ i + 16 ]);
2711 }
2712
2713 if (OP[3] & (1 << 19))
2714 {
2715 SP -= 8;
2716
2717 if ((PSW & PSW_NP) && ((PSW & PSW_EP) == 0))
2718 {
2719 store_mem ((SP + 4) & ~ 3, 4, FEPC);
2720 store_mem ( SP & ~ 3, 4, FEPSW);
2721 }
2722 else
2723 {
2724 store_mem ((SP + 4) & ~ 3, 4, EIPC);
2725 store_mem ( SP & ~ 3, 4, EIPSW);
2726 }
2727 }
2728
2729 trace_output (OP_PUSHPOP2);
2730
2731 return 4;
2732 }
2733
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