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[thirdparty/binutils-gdb.git] / sim / v850 / v850.igen
1 :option:::insn-bit-size:16
2 :option:::hi-bit-nr:15
3
4
5 :option:::format-names:I,II,III,IV,V,VI,VII,VIII,IX,X
6 :option:::format-names:XI,XII,XIII
7 :option:::format-names:XIV,XV
8 :option:::format-names:Z
9 :option:::format-names:F_I
10 :option:::format-names:C
11
12
13 :model:::v850:v850:
14
15 :option:::multi-sim:true
16 :model:::v850e:v850e:
17 :option:::multi-sim:true
18 :model:::v850e1:v850e1:
19 :option:::multi-sim:true
20 :model:::v850e2:v850e2:
21 :option:::multi-sim:true
22 :model:::v850e2v3:v850e2v3:
23 :option:::multi-sim:true
24 :model:::v850e3v5:v850e3v5:
25
26 // Cache macros
27
28 :cache:::unsigned:reg1:RRRRR:(RRRRR)
29 :cache:::unsigned:reg2:rrrrr:(rrrrr)
30 :cache:::unsigned:reg3:wwwww:(wwwww)
31 :cache:::unsigned:reg4:W,WWWW:(W + (WWWW << 1))
32
33 :cache:::unsigned:vreg1:VVVVV:(VVVVV)
34 :cache:::unsigned:vreg1:VVVV:(VVVV << 1)
35 :cache:::unsigned:vreg2:vvvvv:(vvvvv)
36 :cache:::unsigned:vreg2:vvvv:(vvvv << 1)
37 :cache:::unsigned:vreg3:xxxx:(xxxx << 1)
38 :cache:::unsigned:vreg3:xxxxx:(xxxxx)
39 :cache:::unsigned:imm2:ii:(ii)
40 :cache:::unsigned:imm1:i:(i)
41
42 :cache:::unsigned:reg1e:RRRR:(RRRR << 1)
43 :cache:::unsigned:reg2e:rrrr:(rrrr << 1)
44 :cache:::unsigned:reg3e:wwww:(wwww << 1)
45 :cache:::unsigned:reg4e:mmmm:(mmmm << 1)
46
47 :cache:::unsigned:disp4:dddd:(dddd)
48 :cache:::unsigned:disp5:dddd:(dddd << 1)
49 :cache:::unsigned:disp7:ddddddd:ddddddd
50 :cache:::unsigned:disp8:ddddddd:(ddddddd << 1)
51 :cache:::unsigned:disp8:dddddd:(dddddd << 2)
52 :cache:::unsigned:disp9:ddddd,ddd:SEXT32 ((ddddd << 4) + (ddd << 1), 9 - 1)
53 :cache:::unsigned:disp16:dddddddddddddddd:EXTEND16 (dddddddddddddddd)
54 :cache:::unsigned:disp16:ddddddddddddddd: EXTEND16 (ddddddddddddddd << 1)
55 :cache:::unsigned:disp17:d,ddddddddddddddd:SEXT32 (((d <<16) + (ddddddddddddddd << 1)), 17 - 1)
56 :cache:::unsigned:disp22:dddddd,ddddddddddddddd: SEXT32 ((dddddd << 16) + (ddddddddddddddd << 1), 22 - 1)
57 :cache:::unsigned:disp23:ddddddd,dddddddddddddddd: SEXT32 ((ddddddd) + (dddddddddddddddd << 7), 23 - 1)
58 :cache:::unsigned:disp23:dddddd,dddddddddddddddd: SEXT32 ((dddddd << 1) + (dddddddddddddddd << 7), 23 - 1)
59
60 :cache:::unsigned:imm5:iiiii:SEXT32 (iiiii, 4)
61 :cache:::unsigned:imm6:iiiiii:iiiiii
62 :cache:::unsigned:imm9:iiiii,IIII:SEXT ((IIII << 5) + iiiii, 9 - 1)
63 :cache:::unsigned:imm5:iiii:(32 - (iiii << 1))
64 :cache:::unsigned:simm16:iiiiiiiiiiiiiiii:EXTEND16 (iiiiiiiiiiiiiiii)
65 :cache:::unsigned:uimm16:iiiiiiiiiiiiiiii:iiiiiiiiiiiiiiii
66 :cache:::unsigned:imm32:iiiiiiiiiiiiiiii,IIIIIIIIIIIIIIII:(iiiiiiiiiiiiiiii < 16 + IIIIIIIIIIIIIIII)
67 :cache:::unsigned:uimm32:iiiiiiiiiiiiiiii,dddddddddddddddd:((iiiiiiiiiiiiiiii << 16) + dddddddddddddddd)
68
69 :cache:::unsigned:vector:iiiii:iiiii
70
71 :cache:::unsigned:list12:L,LLLLLLLLLLL:((L << 11) + LLLLLLLLLLL)
72 :cache:::unsigned:list18:LLLL,LLLLLLLLLLLL:((LLLL << 12) + LLLLLLLLLLLL)
73
74 :cache:::unsigned:bit3:bbb:bbb
75 :cache:::unsigned:bit4:bbbb:bbbb
76 :cache:::unsigned:bit13:B,BBB:((B << 3) + BBB)
77
78
79 // What do we do with an illegal instruction?
80 :internal::::illegal:
81 {
82 sim_io_eprintf (SD, "Illegal instruction at address 0x%lx\n",
83 (unsigned long) cia);
84 sim_engine_halt (SD, CPU, NULL, cia, sim_signalled, SIM_SIGILL);
85 }
86
87
88
89 // ADD
90 rrrrr,001110,RRRRR:I:::add
91 "add r<reg1>, r<reg2>"
92 {
93 COMPAT_1 (OP_1C0 ());
94 }
95
96 rrrrr,010010,iiiii:II:::add
97 "add <imm5>,r<reg2>"
98 {
99 COMPAT_1 (OP_240 ());
100 }
101
102
103
104 // ADDI
105 rrrrr,110000,RRRRR + iiiiiiiiiiiiiiii:VI:::addi
106 "addi <simm16>, r<reg1>, r<reg2>"
107 {
108 COMPAT_2 (OP_600 ());
109 }
110
111
112
113 // ADF
114 rrrrr,111111,RRRRR + wwwww,011101,cccc!13,0:XI:::adf
115 *v850e2
116 *v850e2v3
117 *v850e3v5
118 "adf %s<cccc>, r<reg1>, r<reg2>, r<reg3>"
119 {
120 int cond = condition_met (cccc);
121 TRACE_ALU_INPUT3 (cond, GR[reg1], GR[reg2]);
122 GR[reg3] = GR[reg1] + GR[reg2] + (cond ? 1 : 0);
123 TRACE_ALU_RESULT1 (GR[reg3]);
124 }
125
126
127
128 // AND
129 rrrrr,001010,RRRRR:I:::and
130 "and r<reg1>, r<reg2>"
131 {
132 COMPAT_1 (OP_140 ());
133 }
134
135
136
137 // ANDI
138 rrrrr,110110,RRRRR + iiiiiiiiiiiiiiii:VI:::andi
139 "andi <uimm16>, r<reg1>, r<reg2>"
140 {
141 COMPAT_2 (OP_6C0 ());
142 }
143
144
145
146 // Map condition code to a string
147 :%s::::cccc:int cccc
148 {
149 switch (cccc)
150 {
151 case 0xf: return "gt";
152 case 0xe: return "ge";
153 case 0x6: return "lt";
154
155 case 0x7: return "le";
156
157 case 0xb: return "h";
158 case 0x9: return "nl";
159 case 0x1: return "l";
160
161 case 0x3: return "nh";
162
163 case 0x2: return "e";
164
165 case 0xa: return "ne";
166
167 case 0x0: return "v";
168 case 0x8: return "nv";
169 case 0x4: return "n";
170 case 0xc: return "p";
171 /* case 0x1: return "c"; */
172 /* case 0x9: return "nc"; */
173 /* case 0x2: return "z"; */
174 /* case 0xa: return "nz"; */
175 case 0x5: return "r"; /* always */
176 case 0xd: return "sa";
177 }
178 return "(null)";
179 }
180
181
182 // Bcond
183 ddddd,1011,ddd,cccc:III:::Bcond
184 "b%s<cccc> <disp9>"
185 {
186 int cond;
187 if ((ddddd == 0x00) && (ddd == 0x00) && (cccc == 0x05)) {
188 // Special case - treat "br *" like illegal instruction
189 sim_engine_halt (SD, CPU, NULL, cia, sim_stopped, SIM_SIGTRAP);
190 } else {
191 cond = condition_met (cccc);
192 if (cond)
193 nia = cia + disp9;
194 TRACE_BRANCH1 (cond);
195 }
196 }
197
198 00000111111,d,cccc + ddddddddddddddd,1:VII:::Bcond
199 "breakpoint":((disp17 == 0) && (cccc == 0x05))
200 "b%s<cccc> <disp17>"
201 *v850e2v3
202 *v850e3v5
203 {
204 int cond;
205 cond = condition_met (cccc);
206 if (cond)
207 nia = cia + disp17;
208 TRACE_BRANCH_INPUT1 (cond);
209 TRACE_BRANCH_RESULT (nia);
210 }
211
212
213
214 // BSH
215 rrrrr,11111100000 + wwwww,01101000010:XII:::bsh
216 *v850e
217 *v850e1
218 *v850e2
219 *v850e2v3
220 *v850e3v5
221 "bsh r<reg2>, r<reg3>"
222 {
223 uint32_t value;
224 TRACE_ALU_INPUT1 (GR[reg2]);
225
226 value = (MOVED32 (GR[reg2], 23, 16, 31, 24)
227 | MOVED32 (GR[reg2], 31, 24, 23, 16)
228 | MOVED32 (GR[reg2], 7, 0, 15, 8)
229 | MOVED32 (GR[reg2], 15, 8, 7, 0));
230
231 GR[reg3] = value;
232 PSW &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
233 if ((value & 0xffff) == 0) PSW |= PSW_Z;
234 if (value & 0x80000000) PSW |= PSW_S;
235 if (((value & 0xff) == 0) || ((value & 0xff00) == 0)) PSW |= PSW_CY;
236
237 TRACE_ALU_RESULT (GR[reg3]);
238 }
239
240
241
242 // BSW
243 rrrrr,11111100000 + wwwww,01101000000:XII:::bsw
244 *v850e
245 *v850e1
246 *v850e2
247 *v850e2v3
248 *v850e3v5
249 "bsw r<reg2>, r<reg3>"
250 {
251 #define WORDHASNULLBYTE(x) (((x) - 0x01010101) & ~(x)&0x80808080)
252 uint32_t value;
253 TRACE_ALU_INPUT1 (GR[reg2]);
254
255 value = GR[reg2];
256 value >>= 24;
257 value |= (GR[reg2] << 24);
258 value |= ((GR[reg2] << 8) & 0x00ff0000);
259 value |= ((GR[reg2] >> 8) & 0x0000ff00);
260 GR[reg3] = value;
261
262 PSW &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
263
264 if (value == 0) PSW |= PSW_Z;
265 if (value & 0x80000000) PSW |= PSW_S;
266 if (WORDHASNULLBYTE (value)) PSW |= PSW_CY;
267
268 TRACE_ALU_RESULT (GR[reg3]);
269 }
270
271
272
273 // CALLT
274 0000001000,iiiiii:II:::callt
275 *v850e
276 *v850e1
277 *v850e2
278 *v850e2v3
279 *v850e3v5
280 "callt <imm6>"
281 {
282 uint32_t adr;
283 uint32_t off;
284 CTPC = cia + 2;
285 CTPSW = PSW;
286 adr = (CTBP & ~1) + (imm6 << 1);
287 off = load_mem (adr, 2) & ~1; /* Force alignment */
288 nia = (CTBP & ~1) + off;
289 TRACE_BRANCH3 (adr, CTBP, off);
290 }
291
292
293
294 // CAXI
295 rrrrr,111111,RRRRR + wwwww,00011101110:IX:::caxi
296 *v850e2
297 *v850e2v3
298 *v850e3v5
299 "caxi [reg1], reg2, reg3"
300 {
301 unsigned int z,s,cy,ov;
302 uint32_t addr;
303 uint32_t token,result;
304
305 addr = GR[reg1];
306
307 if (mpu_load_mem_test(sd, addr, 4, reg1)
308 && mpu_store_mem_test(sd, addr, 4, reg1))
309 {
310 token = load_data_mem (sd, addr, 4);
311
312 TRACE_ALU_INPUT2 (token, GR[reg2]);
313
314 result = GR[reg2] - token;
315
316 z = (result == 0);
317 s = (result & 0x80000000);
318 cy = (GR[reg2] < token);
319 ov = ((GR[reg2] & 0x80000000) != (token & 0x80000000)
320 && (GR[reg2] & 0x80000000) != (result & 0x80000000));
321
322 if (result == 0)
323 {
324 store_data_mem (sd, addr, 4, GR[reg3]);
325 GR[reg3] = token;
326 }
327 else
328 {
329 store_data_mem (sd, addr, 4, token);
330 GR[reg3] = token;
331 }
332
333 /* Set condition codes. */
334 PSW &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
335 PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
336 | (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0));
337
338 TRACE_ALU_RESULT1 (GR[reg3]);
339 }
340 }
341
342
343 // CLR1
344 10,bbb,111110,RRRRR + dddddddddddddddd:VIII:::clr1
345 "clr1 <bit3>, <disp16>[r<reg1>]"
346 {
347 COMPAT_2 (OP_87C0 ());
348 }
349
350 rrrrr,111111,RRRRR + 0000000011100100:IX:::clr1
351 *v850e
352 *v850e1
353 *v850e2
354 *v850e2v3
355 *v850e3v5
356 "clr1 r<reg2>, [r<reg1>]"
357 {
358 COMPAT_2 (OP_E407E0 ());
359 }
360
361
362
363 // CTRET
364 0000011111100000 + 0000000101000100:X:::ctret
365 *v850e
366 *v850e1
367 *v850e2
368 *v850e2v3
369 *v850e3v5
370 "ctret"
371 {
372 nia = (CTPC & ~1);
373 PSW = (CTPSW & (CPU)->psw_mask);
374 TRACE_BRANCH1 (PSW);
375 }
376
377
378
379 // CMOV
380 rrrrr,111111,RRRRR + wwwww,011001,cccc,0:XI:::cmov
381 *v850e
382 *v850e1
383 *v850e2
384 *v850e2v3
385 *v850e3v5
386 "cmov %s<cccc>, r<reg1>, r<reg2>, r<reg3>"
387 {
388 int cond = condition_met (cccc);
389 TRACE_ALU_INPUT3 (cond, GR[reg1], GR[reg2]);
390 GR[reg3] = cond ? GR[reg1] : GR[reg2];
391 TRACE_ALU_RESULT (GR[reg3]);
392 }
393
394 rrrrr,111111,iiiii + wwwww,011000,cccc,0:XII:::cmov
395 *v850e
396 *v850e1
397 *v850e2
398 *v850e2v3
399 *v850e3v5
400 "cmov %s<cccc>, <imm5>, r<reg2>, r<reg3>"
401 {
402 int cond = condition_met (cccc);
403 TRACE_ALU_INPUT3 (cond, imm5, GR[reg2]);
404 GR[reg3] = cond ? imm5 : GR[reg2];
405 TRACE_ALU_RESULT (GR[reg3]);
406 }
407
408
409
410 // CMP
411 rrrrr,001111,RRRRR:I:::cmp
412 "cmp r<reg1>, r<reg2>"
413 {
414 COMPAT_1 (OP_1E0 ());
415 }
416
417 rrrrr,010011,iiiii:II:::cmp
418 "cmp <imm5>, r<reg2>"
419 {
420 COMPAT_1 (OP_260 ());
421 }
422
423
424
425 // DI
426 0000011111100000 + 0000000101100000:X:::di
427 "di"
428 {
429 COMPAT_2 (OP_16007E0 ());
430 }
431
432
433
434 // DISPOSE
435 // 0000011001,iiiii,L + LLLLLLLLLLL,00000:XIII:::dispose
436 // "dispose <imm5>, <list12>"
437 0000011001,iiiii,L + LLLLLLLLLLL,RRRRR:XIII:::dispose
438 *v850e
439 *v850e1
440 *v850e2
441 *v850e2v3
442 *v850e3v5
443 "dispose <imm5>, <list12>":RRRRR == 0
444 "dispose <imm5>, <list12>, [reg1]"
445 {
446 int i;
447 SAVE_2;
448
449 trace_input ("dispose", OP_PUSHPOP1, 0);
450
451 SP += (OP[3] & 0x3e) << 1;
452
453 /* Load the registers with lower number registers being retrieved
454 from higher addresses. */
455 for (i = 12; i--;)
456 if ((OP[3] & (1 << type1_regs[ i ])))
457 {
458 State.regs[ 20 + i ] = load_mem (SP, 4);
459 SP += 4;
460 }
461
462 if ((OP[3] & 0x1f0000) != 0)
463 {
464 nia = State.regs[ (OP[3] >> 16) & 0x1f];
465 }
466
467 trace_output (OP_PUSHPOP1);
468 }
469
470
471
472 // DIV
473 rrrrr,111111,RRRRR + wwwww,01011000000:XI:::div
474 *v850e
475 *v850e1
476 *v850e2
477 *v850e2v3
478 *v850e3v5
479 "div r<reg1>, r<reg2>, r<reg3>"
480 {
481 COMPAT_2 (OP_2C007E0 ());
482 }
483
484
485 // DIVH
486 rrrrr!0,000010,RRRRR!0:I:::divh
487 "divh r<reg1>, r<reg2>"
488 {
489 uint32_t ov, s, z;
490 signed long int op0, op1, result;
491
492 trace_input ("divh", OP_REG_REG, 0);
493
494 PC = cia;
495 OP[0] = instruction_0 & 0x1f;
496 OP[1] = (instruction_0 >> 11) & 0x1f;
497
498 /* Compute the result. */
499 op0 = EXTEND16 (State.regs[OP[0]]);
500 op1 = State.regs[OP[1]];
501
502 if (op0 == -1 && op1 == 0x80000000)
503 {
504 PSW &= ~PSW_Z;
505 PSW |= PSW_OV | PSW_S;
506 State.regs[OP[1]] = 0x80000000;
507 }
508 else if (op0 == 0)
509 {
510 PSW |= PSW_OV;
511 }
512 else
513 {
514 result = (int32_t) op1 / op0;
515 ov = 0;
516
517 /* Compute the condition codes. */
518 z = (result == 0);
519 s = (result & 0x80000000);
520
521 /* Store the result and condition codes. */
522 State.regs[OP[1]] = result;
523 PSW &= ~(PSW_Z | PSW_S | PSW_OV);
524 PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0) | (ov ? PSW_OV : 0));
525 }
526
527 trace_output (OP_REG_REG);
528
529 PC += 2;
530 nia = PC;
531 }
532
533 rrrrr,111111,RRRRR + wwwww,01010000000:XI:::divh
534 *v850e
535 *v850e1
536 *v850e2
537 *v850e2v3
538 *v850e3v5
539 "divh r<reg1>, r<reg2>, r<reg3>"
540 {
541 COMPAT_2 (OP_28007E0 ());
542 }
543
544
545 // DIVHU
546 rrrrr,111111,RRRRR + wwwww,01010000010:XI:::divhu
547 *v850e
548 *v850e1
549 *v850e2
550 *v850e2v3
551 *v850e3v5
552 "divhu r<reg1>, r<reg2>, r<reg3>"
553 {
554 COMPAT_2 (OP_28207E0 ());
555 }
556
557
558 // DIVU
559 rrrrr,111111,RRRRR + wwwww,01011000010:XI:::divu
560 *v850e
561 *v850e1
562 *v850e2
563 *v850e2v3
564 *v850e3v5
565 "divu r<reg1>, r<reg2>, r<reg3>"
566 {
567 COMPAT_2 (OP_2C207E0 ());
568 }
569
570
571 // DIVQ
572 rrrrr,111111,RRRRR + wwwww,01011111100:XI:::divq
573 *v850e2
574 *v850e2v3
575 *v850e3v5
576 "divq r<reg1>, r<reg2>, r<reg3>"
577 {
578 unsigned int quotient;
579 unsigned int remainder;
580 unsigned int divide_by;
581 unsigned int divide_this;
582
583 TRACE_ALU_INPUT2 (GR[reg1], GR[reg2]);
584
585 divide_by = GR[reg1];
586 divide_this = GR[reg2];
587 v850_div (sd, divide_by, divide_this, &quotient, &remainder);
588 GR[reg2] = quotient;
589 GR[reg3] = remainder;
590
591 TRACE_ALU_RESULT2 (GR[reg2], GR[reg3]);
592 }
593
594
595 // DIVQU
596 rrrrr,111111,RRRRR + wwwww,01011111110:XI:::divqu
597 *v850e2
598 *v850e2v3
599 *v850e3v5
600 "divq r<reg1>, r<reg2>, r<reg3>"
601 {
602 unsigned int quotient;
603 unsigned int remainder;
604 unsigned int divide_by;
605 unsigned int divide_this;
606
607 TRACE_ALU_INPUT2 (GR[reg1], GR[reg2]);
608
609 divide_by = GR[reg1];
610 divide_this = GR[reg2];
611 v850_divu (sd, divide_by, divide_this, &quotient, &remainder);
612 GR[reg2] = quotient;
613 GR[reg3] = remainder;
614
615 TRACE_ALU_RESULT2 (GR[reg2], GR[reg3]);
616 }
617
618
619 // EI
620 1000011111100000 + 0000000101100000:X:::ei
621 "ei"
622 {
623 COMPAT_2 (OP_16087E0 ());
624 }
625
626
627
628 // EIRET
629 0000011111100000 + 0000000101001000:X:::eiret
630 "eiret"
631 *v850e2
632 *v850e2v3
633 *v850e3v5
634 {
635 TRACE_ALU_INPUT1 (MPM & MPM_AUE);
636
637 nia = EIPC; /* next PC */
638 if (MPM & MPM_AUE)
639 {
640 PSW = EIPSW;
641 }
642 else
643 {
644 PSW = (PSW & (PSW_NPV | PSW_DMP | PSW_IMP))
645 | (EIPSW & ~(PSW_NPV | PSW_DMP | PSW_IMP));
646 }
647
648 TRACE_ALU_RESULT1 (PSW);
649 TRACE_BRANCH_RESULT (nia);
650 }
651
652
653
654 // FERET
655 0000011111100000 + 0000000101001010:X:::feret
656 "feret"
657 *v850e2
658 *v850e2v3
659 *v850e3v5
660 {
661 TRACE_ALU_INPUT1 (MPM & MPM_AUE);
662
663 nia = FEPC; /* next PC */
664 if (MPM & MPM_AUE)
665 {
666 PSW = FEPSW;
667 }
668 else
669 {
670 PSW = (PSW & (PSW_NPV | PSW_DMP | PSW_IMP))
671 | (FEPSW & ~(PSW_NPV | PSW_DMP | PSW_IMP));
672 }
673
674 TRACE_ALU_RESULT1 (PSW);
675 TRACE_BRANCH_RESULT (nia);
676 }
677
678
679 // FETRAP
680 0,bbbb!0,00001000000:I:::fetrap
681 "fetrap"
682 *v850e2
683 *v850e2v3
684 *v850e3v5
685 {
686 TRACE_ALU_INPUT0 ();
687
688 FEPC = PC + 2;
689 FEPSW = PSW;
690 ECR &= ~ECR_FECC;
691 ECR |= (0x30 + bit4) << 16;
692 FEIC = 0x30 + bit4;
693 PSW |= PSW_EP | PSW_ID | PSW_NP;
694 nia = 0x30; /* next PC */
695
696 TRACE_ALU_RESULT1 (PSW);
697 TRACE_BRANCH_RESULT (nia);
698 }
699
700
701 // HALT
702 0000011111100000 + 0000000100100000:X:::halt
703 "halt"
704 {
705 COMPAT_2 (OP_12007E0 ());
706 }
707
708
709
710 // HSH
711 rrrrr,11111100000 + wwwww,01101000110:XII:::hsh
712 *v850e2
713 *v850e2v3
714 *v850e3v5
715 "hsh r<reg2>, r<reg3>"
716 {
717 uint32_t value;
718 TRACE_ALU_INPUT1 (GR[reg2]);
719
720 value = 0xffff & GR[reg2];
721 GR[reg3] = GR[reg2];
722
723 PSW &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
724
725 if (value == 0) { PSW |= PSW_Z; PSW |= PSW_CY; }
726 if (value & 0x80000000) PSW |= PSW_S;
727
728 TRACE_ALU_RESULT1 (GR[reg3]);
729 }
730
731
732 // HSW
733 rrrrr,11111100000 + wwwww,01101000100:XII:::hsw
734 *v850e
735 *v850e1
736 *v850e2
737 *v850e2v3
738 *v850e3v5
739 "hsw r<reg2>, r<reg3>"
740 {
741 uint32_t value;
742 TRACE_ALU_INPUT1 (GR[reg2]);
743
744 value = GR[reg2];
745 value >>= 16;
746 value |= (GR[reg2] << 16);
747
748 GR[reg3] = value;
749
750 PSW &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
751
752 if (value == 0) PSW |= PSW_Z;
753 if (value & 0x80000000) PSW |= PSW_S;
754 if (((value & 0xffff) == 0) || (value & 0xffff0000) == 0) PSW |= PSW_CY;
755
756 TRACE_ALU_RESULT (GR[reg3]);
757 }
758
759
760
761 // JARL
762 rrrrr!0,11110,dddddd + ddddddddddddddd,0:V:::jarl
763 "jarl <disp22>, r<reg2>"
764 {
765 GR[reg2] = nia;
766 nia = cia + disp22;
767 TRACE_BRANCH1 (GR[reg2]);
768 }
769
770 00000010111,RRRRR!0 + iiiiiiiiiiiiiiii + IIIIIIIIIIIIIIII:VI:::jarl32
771 *v850e2
772 *v850e2v3
773 *v850e3v5
774 "jarl <imm32>, r<reg1>"
775 {
776 GR[reg1] = nia;
777 nia = (cia + imm32) & ~1;
778
779 TRACE_BRANCH_RESULT (nia);
780 }
781
782
783 11000111111,RRRRR + wwwww!0,00101100000:XI:::jarl_reg
784 *v850e3v5
785 "jarl [r<reg1>], r<reg3>"
786 {
787 GR[reg3] = nia;
788 nia = GR[reg1];
789 TRACE_BRANCH_RESULT (nia);
790 }
791
792
793 // JMP
794 00000000011,RRRRR:I:::jmp
795 "jmp [r<reg1>]"
796 {
797 nia = GR[reg1] & ~1;
798 TRACE_BRANCH0 ();
799 }
800
801 00000110111,RRRRR + iiiiiiiiiiiiiiii + IIIIIIIIIIIIIIII:VI:::jmp32
802 *v850e2
803 *v850e2v3
804 *v850e3v5
805 "jmp <imm32>[r<reg1>]"
806 {
807 nia = (GR[reg1] + imm32) & ~1;
808
809 TRACE_BRANCH_RESULT (nia);
810 }
811
812
813 // JR
814 0000011110,dddddd + ddddddddddddddd,0:V:::jr
815 "jr <disp22>"
816 {
817 nia = cia + disp22;
818 TRACE_BRANCH0 ();
819 }
820
821
822 // JR32
823 0000001011100000 + iiiiiiiiiiiiiiii + IIIIIIIIIIIIIIII:VI:::jr32
824 *v850e2
825 *v850e2v3
826 *v850e3v5
827 "jr <imm32>"
828 {
829 nia = (cia + imm32) & ~1;
830
831 TRACE_BRANCH_RESULT (nia);
832 }
833
834
835 // LD
836 rrrrr,111000,RRRRR + dddddddddddddddd:VII:::ld.b
837 "ld.b <disp16>[r<reg1>], r<reg2>"
838 {
839 COMPAT_2 (OP_700 ());
840 }
841
842 00000111100,RRRRR+wwwww,ddddddd,0101+dddddddddddddddd:XIV:::ld.b
843 "ld.b <disp23>[r<reg1>], r<reg3>"
844 *v850e2v3
845 *v850e3v5
846 {
847 uint32_t addr = GR[reg1] + disp23;
848 uint32_t result = EXTEND8 (load_data_mem (sd, addr, 1));
849 GR[reg3] = result;
850 TRACE_LD (addr, result);
851 }
852
853 rrrrr,111001,RRRRR + ddddddddddddddd,0:VII:::ld.h
854 "ld.h <disp16>[r<reg1>], r<reg2>"
855 {
856 COMPAT_2 (OP_720 ());
857 }
858
859 00000111100,RRRRR+wwwww,dddddd,00111+dddddddddddddddd:XIV:::ld.h
860 *v850e2v3
861 *v850e3v5
862 "ld.h <disp23>[r<reg1>], r<reg3>"
863 {
864 uint32_t addr = GR[reg1] + disp23;
865 uint32_t result = EXTEND16 (load_data_mem (sd, addr, 2));
866 GR[reg3] = result;
867 TRACE_LD (addr, result);
868 }
869
870 rrrrr,111001,RRRRR + ddddddddddddddd,1:VII:::ld.w
871 "ld.w <disp16>[r<reg1>], r<reg2>"
872 {
873 COMPAT_2 (OP_10720 ());
874 }
875
876 00000111100,RRRRR+wwwww,dddddd,01001+dddddddddddddddd:XIV:::ld.w
877 *v850e2v3
878 *v850e3v5
879 "ld.w <disp23>[r<reg1>], r<reg3>"
880 {
881 uint32_t addr = GR[reg1] + disp23;
882 uint32_t result = load_data_mem (sd, addr, 4);
883 GR[reg3] = result;
884 TRACE_LD (addr, result);
885 }
886
887 00000111101,RRRRR+wwwww,dddddd,01001+dddddddddddddddd:XIV:::ld.dw
888 *v850e3v5
889 "ld.dw <disp23>[r<reg1>], r<reg3>"
890 {
891 uint32_t addr = GR[reg1] + disp23;
892 uint32_t result = load_data_mem (sd, addr, 4);
893 GR[reg3] = result;
894 TRACE_LD (addr, result);
895 result = load_data_mem (sd, addr + 4, 4);
896 GR[reg3 + 1] = result;
897 TRACE_LD (addr + 4, result);
898 }
899
900 rrrrr!0,11110,b,RRRRR + ddddddddddddddd,1:VII:::ld.bu
901 *v850e
902 *v850e1
903 *v850e2
904 *v850e2v3
905 *v850e3v5
906 "ld.bu <disp16>[r<reg1>], r<reg2>"
907 {
908 COMPAT_2 (OP_10780 ());
909 }
910
911 00000111101,RRRRR+wwwww,ddddddd,0101+dddddddddddddddd:XIV:::ld.bu
912 *v850e2v3
913 *v850e3v5
914 "ld.bu <disp23>[r<reg1>], r<reg3>"
915 {
916 uint32_t addr = GR[reg1] + disp23;
917 uint32_t result = load_data_mem (sd, addr, 1);
918 GR[reg3] = result;
919 TRACE_LD (addr, result);
920 }
921
922 rrrrr!0,111111,RRRRR + ddddddddddddddd,1:VII:::ld.hu
923 *v850e
924 *v850e1
925 *v850e2
926 *v850e2v3
927 *v850e3v5
928 "ld.hu <disp16>[r<reg1>], r<reg2>"
929 {
930 COMPAT_2 (OP_107E0 ());
931 }
932
933 00000111101,RRRRR+wwwww,dddddd,00111+dddddddddddddddd:XIV:::ld.hu
934 *v850e2v3
935 *v850e3v5
936 "ld.hu <disp23>[r<reg1>], r<reg3>"
937 {
938 uint32_t addr = GR[reg1] + disp23;
939 uint32_t result = load_data_mem (sd, addr, 2);
940 GR[reg3] = result;
941 TRACE_LD (addr, result);
942 }
943
944
945
946 // LDSR
947 regID,111111,RRRRR + selID,00000100000:IX:::ldsr
948 "ldsr r<reg1>, s<regID>":(selID == 0)
949 "ldsr r<reg1>, s<regID>, <selID>"
950 {
951 uint32_t sreg = GR[reg1];
952 TRACE_ALU_INPUT1 (GR[reg1]);
953
954 /* FIXME: For now we ignore the selID. */
955 if (idecode_issue == idecode_v850e3v5_issue && selID != 0)
956 {
957 (CPU)->reg.selID_sregs[selID][regID] = sreg;
958 }
959 else if (( idecode_issue == idecode_v850e2_issue
960 || idecode_issue == idecode_v850e3v5_issue
961 || idecode_issue == idecode_v850e2v3_issue)
962 && regID < 28)
963 {
964 int protect_p = (PSW & PSW_NPV) ? 1 : 0;
965
966 switch (BSEL & 0xffff)
967 {
968 case 0x0000:
969 if ((PSW & PSW_NPV)
970 && ((regID >= 8 && regID <= 12)
971 || (regID >= 22 && regID <= 27)
972 || regID == PSW_REGNO))
973 {
974 protect_p = 0;
975 }
976 break;
977 case 0x1000: /* MPU0 */
978 break;
979 case 0x1001: /* MPU1 */
980 break;
981 case 0x2000: /* FPU */
982 if ((PSW & PSW_NPV)
983 && ((/* regID >= 0 && */ regID <= 5)
984 || regID == 8
985 || regID == 9
986 || regID == 10
987 || (regID >= 11 && regID <= 26)))
988 {
989 protect_p = 0;
990 }
991 break;
992 case 0xff00:
993 if ((PSW & PSW_NPV)
994 && (regID == 6
995 || regID == 7
996 || regID == 8
997 || regID == 9
998 || regID == 10
999 || (regID >= 11 && regID <= 15)
1000 || regID == 18
1001 || regID == 19
1002 || (regID >= 21 && regID <= 27)))
1003 {
1004 protect_p = 0;
1005 }
1006 break;
1007 case 0xffff:
1008 if ((PSW & PSW_NPV)
1009 && (regID == 6
1010 || regID == 7
1011 || regID == 8
1012 || regID == 9
1013 || regID == 10
1014 || regID == 11
1015 || regID == 12
1016 || regID == 15
1017 || regID == 18
1018 || regID == 19
1019 || (regID >= 21 && regID <= 27)))
1020 {
1021 protect_p = 0;
1022 }
1023 break;
1024 }
1025
1026 if (!protect_p)
1027 {
1028 switch (BSEL & 0xffff)
1029 {
1030 case 0x0000:
1031 case 0xff00: /* user0 bank */
1032 case 0xffff: /* user1 bank */
1033 if(regID == PSW_REGNO)
1034 {
1035 SR[regID] = sreg & ((PSW & PSW_NPV) ? 0xf : ~0);
1036 }
1037 else
1038 {
1039 SR[regID] = sreg;
1040 }
1041 break;
1042 case 0x1000:
1043 MPU0_SR[regID] = sreg;
1044 break;
1045 case 0x1001:
1046 if (regID == MPC_REGNO)
1047 {
1048 PPC &= ~PPC_PPE;
1049 SPAL &= ~SPAL_SPE;
1050 IPA0L &= ~IPA_IPE;
1051 IPA1L &= ~IPA_IPE;
1052 IPA2L &= ~IPA_IPE;
1053 IPA3L &= ~IPA_IPE;
1054 DPA0L &= ~DPA_DPE;
1055 DPA1L &= ~DPA_DPE;
1056 DCC &= ~(DCC_DCE0 | DCC_DCE1);
1057 }
1058 else
1059 {
1060 MPU1_SR[regID] = sreg;
1061 }
1062 break;
1063 case 0x2000: /* FPU */
1064 if (regID == FPST_REGNO)
1065 {
1066 unsigned int val = FPSR & ~(FPSR_PR | FPSR_XC | FPSR_XP);
1067
1068 val |= ((sreg & FPST_PR) ? FPSR_PR : 0)
1069 | ((sreg & FPST_XCE) ? FPSR_XCE : 0)
1070 | ((sreg & FPST_XCV) ? FPSR_XCV : 0)
1071 | ((sreg & FPST_XCZ) ? FPSR_XCZ : 0)
1072 | ((sreg & FPST_XCO) ? FPSR_XCO : 0)
1073 | ((sreg & FPST_XCU) ? FPSR_XCU : 0)
1074 | ((sreg & FPST_XCI) ? FPSR_XCI : 0)
1075 | ((sreg & FPST_XPV) ? FPSR_XPV : 0)
1076 | ((sreg & FPST_XPZ) ? FPSR_XPZ : 0)
1077 | ((sreg & FPST_XPO) ? FPSR_XPO : 0)
1078 | ((sreg & FPST_XPU) ? FPSR_XPU : 0)
1079 | ((sreg & FPST_XPI) ? FPSR_XPI : 0);
1080 FPSR = val;
1081 }
1082 else if (regID == FPCFG_REGNO)
1083 {
1084 unsigned int val = FPSR & ~(FPSR_RM | FPSR_XE);
1085
1086 val |= (((sreg & FPCFG_RM) >> 7) << 18)
1087 | ((sreg & FPCFG_XEV) ? FPSR_XEV : 0)
1088 | ((sreg & FPCFG_XEZ) ? FPSR_XEZ : 0)
1089 | ((sreg & FPCFG_XEO) ? FPSR_XEO : 0)
1090 | ((sreg & FPCFG_XEU) ? FPSR_XEU : 0)
1091 | ((sreg & FPCFG_XEI) ? FPSR_XEI : 0);
1092 FPSR = val;
1093 }
1094
1095 FPU_SR[regID] = sreg;
1096 break;
1097 }
1098 }
1099 }
1100 else
1101 {
1102 SR[regID] = sreg;
1103 }
1104
1105 TRACE_ALU_RESULT (sreg);
1106 }
1107
1108
1109 // MAC
1110 rrrrr,111111,RRRRR + wwww,0011110,mmmm,0:XI:::mac
1111 *v850e2
1112 *v850e2v3
1113 *v850e3v5
1114 "mac r<reg1>, r<reg2>, r<reg3e>, r<reg4e>"
1115 {
1116 unsigned long op0;
1117 unsigned long op1;
1118 unsigned long op2;
1119 unsigned long op2hi;
1120 unsigned long lo;
1121 unsigned long mid1;
1122 unsigned long mid2;
1123 unsigned long hi;
1124 unsigned long RdLo;
1125 unsigned long RdHi;
1126 int carry;
1127 bfd_boolean sign;
1128
1129 op0 = GR[reg1];
1130 op1 = GR[reg2];
1131 op2 = GR[reg3e];
1132 op2hi = GR[reg3e+1];
1133
1134 TRACE_ALU_INPUT4 (op0, op1, op2, op2hi);
1135
1136 sign = (op0 ^ op1) & 0x80000000;
1137
1138 if (((signed long) op0) < 0)
1139 op0 = - op0;
1140
1141 if (((signed long) op1) < 0)
1142 op1 = - op1;
1143
1144 /* We can split the 32x32 into four 16x16 operations. This ensures
1145 that we do not lose precision on 32bit only hosts: */
1146 lo = ( (op0 & 0xFFFF) * (op1 & 0xFFFF));
1147 mid1 = ( (op0 & 0xFFFF) * ((op1 >> 16) & 0xFFFF));
1148 mid2 = (((op0 >> 16) & 0xFFFF) * (op1 & 0xFFFF));
1149 hi = (((op0 >> 16) & 0xFFFF) * ((op1 >> 16) & 0xFFFF));
1150
1151 /* We now need to add all of these results together, taking care
1152 to propogate the carries from the additions: */
1153 RdLo = Add32 (lo, (mid1 << 16), & carry);
1154 RdHi = carry;
1155 RdLo = Add32 (RdLo, (mid2 << 16), & carry);
1156 RdHi += (carry + ((mid1 >> 16) & 0xFFFF) + ((mid2 >> 16) & 0xFFFF) + hi);
1157
1158 if (sign)
1159 {
1160 RdLo = ~ RdLo;
1161 RdHi = ~ RdHi;
1162 if (RdLo == 0xFFFFFFFF)
1163 {
1164 RdLo = 0;
1165 RdHi += 1;
1166 }
1167 else
1168 RdLo += 1;
1169 }
1170
1171 RdLo = Add32 (RdLo, op2, & carry);
1172 RdHi += carry + op2hi;
1173
1174 /* Store the result and condition codes. */
1175 GR[reg4e] = RdLo;
1176 GR[reg4e + 1 ] = RdHi;
1177
1178 TRACE_ALU_RESULT2 (RdLo, RdHi);
1179 }
1180
1181
1182
1183 // MACU
1184 rrrrr,111111,RRRRR + wwww,0011111,mmmm,0:XI:::macu
1185 *v850e2
1186 *v850e2v3
1187 *v850e3v5
1188 "macu r<reg1>, r<reg2>, r<reg3e>, r<reg4e>"
1189 {
1190 unsigned long op0;
1191 unsigned long op1;
1192 unsigned long op2;
1193 unsigned long op2hi;
1194 unsigned long lo;
1195 unsigned long mid1;
1196 unsigned long mid2;
1197 unsigned long hi;
1198 unsigned long RdLo;
1199 unsigned long RdHi;
1200 int carry;
1201
1202 op0 = GR[reg1];
1203 op1 = GR[reg2];
1204 op2 = GR[reg3e];
1205 op2hi = GR[reg3e + 1];
1206
1207 TRACE_ALU_INPUT4 (op0, op1, op2, op2hi);
1208
1209 /* We can split the 32x32 into four 16x16 operations. This ensures
1210 that we do not lose precision on 32bit only hosts: */
1211 lo = ( (op0 & 0xFFFF) * (op1 & 0xFFFF));
1212 mid1 = ( (op0 & 0xFFFF) * ((op1 >> 16) & 0xFFFF));
1213 mid2 = (((op0 >> 16) & 0xFFFF) * (op1 & 0xFFFF));
1214 hi = (((op0 >> 16) & 0xFFFF) * ((op1 >> 16) & 0xFFFF));
1215
1216 /* We now need to add all of these results together, taking care
1217 to propogate the carries from the additions: */
1218 RdLo = Add32 (lo, (mid1 << 16), & carry);
1219 RdHi = carry;
1220 RdLo = Add32 (RdLo, (mid2 << 16), & carry);
1221 RdHi += (carry + ((mid1 >> 16) & 0xFFFF) + ((mid2 >> 16) & 0xFFFF) + hi);
1222
1223 RdLo = Add32 (RdLo, op2, & carry);
1224 RdHi += carry + op2hi;
1225
1226 /* Store the result and condition codes. */
1227 GR[reg4e] = RdLo;
1228 GR[reg4e+1] = RdHi;
1229
1230 TRACE_ALU_RESULT2 (RdLo, RdHi);
1231 }
1232
1233
1234
1235 // MOV
1236 rrrrr!0,000000,RRRRR:I:::mov
1237 "mov r<reg1>, r<reg2>"
1238 {
1239 TRACE_ALU_INPUT0 ();
1240 GR[reg2] = GR[reg1];
1241 TRACE_ALU_RESULT (GR[reg2]);
1242 }
1243
1244 rrrrr!0,010000,iiiii:II:::mov
1245 "mov <imm5>, r<reg2>"
1246 {
1247 COMPAT_1 (OP_200 ());
1248 }
1249
1250 00000110001,RRRRR + iiiiiiiiiiiiiiii + IIIIIIIIIIIIIIII:VI:::mov
1251 *v850e
1252 *v850e1
1253 *v850e2
1254 *v850e2v3
1255 *v850e3v5
1256 "mov <imm32>, r<reg1>"
1257 {
1258 SAVE_2;
1259 trace_input ("mov", OP_IMM_REG, 4);
1260 State.regs[ OP[0] ] = load_mem (PC + 2, 4);
1261 trace_output (OP_IMM_REG);
1262 }
1263
1264
1265
1266 // MOVEA
1267 rrrrr!0,110001,RRRRR + iiiiiiiiiiiiiiii:VI:::movea
1268 "movea <simm16>, r<reg1>, r<reg2>"
1269 {
1270 TRACE_ALU_INPUT2 (GR[reg1], simm16);
1271 GR[reg2] = GR[reg1] + simm16;
1272 TRACE_ALU_RESULT (GR[reg2]);
1273 }
1274
1275
1276
1277 // MOVHI
1278 rrrrr!0,110010,RRRRR + iiiiiiiiiiiiiiii:VI:::movhi
1279 "movhi <uimm16>, r<reg1>, r<reg2>"
1280 {
1281 COMPAT_2 (OP_640 ());
1282 }
1283
1284
1285
1286 // MUL
1287 rrrrr,111111,RRRRR + wwwww,01000100000:XI:::mul
1288 *v850e
1289 *v850e1
1290 *v850e2
1291 *v850e2v3
1292 *v850e3v5
1293 "mul r<reg1>, r<reg2>, r<reg3>"
1294 {
1295 COMPAT_2 (OP_22007E0 ());
1296 }
1297
1298 rrrrr,111111,iiiii + wwwww,01001,IIII,00:XII:::mul
1299 *v850e
1300 *v850e1
1301 *v850e2
1302 *v850e2v3
1303 *v850e3v5
1304 "mul <imm9>, r<reg2>, r<reg3>"
1305 {
1306 COMPAT_2 (OP_24007E0 ());
1307 }
1308
1309
1310 // MULH
1311 rrrrr!0,000111,RRRRR:I:::mulh
1312 "mulh r<reg1>, r<reg2>"
1313 {
1314 COMPAT_1 (OP_E0 ());
1315 }
1316
1317 rrrrr!0,010111,iiiii:II:::mulh
1318 "mulh <imm5>, r<reg2>"
1319 {
1320 COMPAT_1 (OP_2E0 ());
1321 }
1322
1323
1324
1325 // MULHI
1326 rrrrr!0,110111,RRRRR + iiiiiiiiiiiiiiii:VI:::mulhi
1327 "mulhi <uimm16>, r<reg1>, r<reg2>"
1328 {
1329 COMPAT_2 (OP_6E0 ());
1330 }
1331
1332
1333
1334 // MULU
1335 rrrrr,111111,RRRRR + wwwww,01000100010:XI:::mulu
1336 *v850e
1337 *v850e1
1338 *v850e2
1339 *v850e2v3
1340 *v850e3v5
1341 "mulu r<reg1>, r<reg2>, r<reg3>"
1342 {
1343 COMPAT_2 (OP_22207E0 ());
1344 }
1345
1346 rrrrr,111111,iiiii + wwwww,01001,IIII,10:XII:::mulu
1347 *v850e
1348 *v850e1
1349 *v850e2
1350 *v850e2v3
1351 *v850e3v5
1352 "mulu <imm9>, r<reg2>, r<reg3>"
1353 {
1354 COMPAT_2 (OP_24207E0 ());
1355 }
1356
1357
1358
1359 // NOP
1360 0000000000000000:I:::nop
1361 "nop"
1362 {
1363 /* do nothing, trace nothing */
1364 }
1365
1366
1367
1368 // NOT
1369 rrrrr,000001,RRRRR:I:::not
1370 "not r<reg1>, r<reg2>"
1371 {
1372 COMPAT_1 (OP_20 ());
1373 }
1374
1375
1376
1377 // NOT1
1378 01,bbb,111110,RRRRR + dddddddddddddddd:VIII:::not1
1379 "not1 <bit3>, <disp16>[r<reg1>]"
1380 {
1381 COMPAT_2 (OP_47C0 ());
1382 }
1383
1384 rrrrr,111111,RRRRR + 0000000011100010:IX:::not1
1385 *v850e
1386 *v850e1
1387 *v850e2
1388 *v850e2v3
1389 *v850e3v5
1390 "not1 r<reg2>, r<reg1>"
1391 {
1392 COMPAT_2 (OP_E207E0 ());
1393 }
1394
1395
1396
1397 // OR
1398 rrrrr,001000,RRRRR:I:::or
1399 "or r<reg1>, r<reg2>"
1400 {
1401 COMPAT_1 (OP_100 ());
1402 }
1403
1404
1405
1406 // ORI
1407 rrrrr,110100,RRRRR + iiiiiiiiiiiiiiii:VI:::ori
1408 "ori <uimm16>, r<reg1>, r<reg2>"
1409 {
1410 COMPAT_2 (OP_680 ());
1411 }
1412
1413
1414
1415 // PREPARE
1416 0000011110,iiiii,L + LLLLLLLLLLL,00001:XIII:::prepare
1417 *v850e
1418 *v850e1
1419 *v850e2
1420 *v850e2v3
1421 *v850e3v5
1422 "prepare <list12>, <imm5>"
1423 {
1424 int i;
1425 SAVE_2;
1426
1427 trace_input ("prepare", OP_PUSHPOP1, 0);
1428
1429 /* Store the registers with lower number registers being placed at
1430 higher addresses. */
1431 for (i = 0; i < 12; i++)
1432 if ((OP[3] & (1 << type1_regs[ i ])))
1433 {
1434 SP -= 4;
1435 store_mem (SP, 4, State.regs[ 20 + i ]);
1436 }
1437
1438 SP -= (OP[3] & 0x3e) << 1;
1439
1440 trace_output (OP_PUSHPOP1);
1441 }
1442
1443
1444 0000011110,iiiii,L + LLLLLLLLLLL,00011:XIII:::prepare00
1445 *v850e
1446 *v850e1
1447 *v850e2
1448 *v850e2v3
1449 *v850e3v5
1450 "prepare <list12>, <imm5>, sp"
1451 {
1452 COMPAT_2 (OP_30780 ());
1453 }
1454
1455 0000011110,iiiii,L + LLLLLLLLLLL,01011 + iiiiiiiiiiiiiiii:XIII:::prepare01
1456 *v850e
1457 *v850e1
1458 *v850e2
1459 *v850e2v3
1460 *v850e3v5
1461 "prepare <list12>, <imm5>, <uimm16>"
1462 {
1463 COMPAT_2 (OP_B0780 ());
1464 }
1465
1466 0000011110,iiiii,L + LLLLLLLLLLL,10011 + iiiiiiiiiiiiiiii:XIII:::prepare10
1467 *v850e
1468 *v850e1
1469 *v850e2
1470 *v850e2v3
1471 *v850e3v5
1472 "prepare <list12>, <imm5>, <uimm16>"
1473 {
1474 COMPAT_2 (OP_130780 ());
1475 }
1476
1477 0000011110,iiiii,L + LLLLLLLLLLL,11011 + iiiiiiiiiiiiiiii + dddddddddddddddd:XIII:::prepare11
1478 *v850e
1479 *v850e1
1480 *v850e2
1481 *v850e2v3
1482 *v850e3v5
1483 "prepare <list12>, <imm5>, <uimm32>"
1484 {
1485 COMPAT_2 (OP_1B0780 ());
1486 }
1487
1488 // RETI
1489 0000011111100000 + 0000000101000000:X:::reti
1490 "reti"
1491 {
1492 if ((PSW & PSW_EP))
1493 {
1494 nia = (EIPC & ~1);
1495 PSW = EIPSW;
1496 }
1497 else if ((PSW & PSW_NP))
1498 {
1499 nia = (FEPC & ~1);
1500 PSW = FEPSW;
1501 }
1502 else
1503 {
1504 nia = (EIPC & ~1);
1505 PSW = EIPSW;
1506 }
1507 TRACE_BRANCH1 (PSW);
1508 }
1509
1510
1511
1512 // SAR
1513 rrrrr,111111,RRRRR + 0000000010100000:IX:::sar
1514 "sar r<reg1>, r<reg2>"
1515 {
1516 COMPAT_2 (OP_A007E0 ());
1517 }
1518
1519 rrrrr,010101,iiiii:II:::sar
1520 "sar <imm5>, r<reg2>"
1521 {
1522 COMPAT_1 (OP_2A0 ());
1523 }
1524
1525 rrrrr,111111,RRRRR + wwwww,00010100010:XI:::sar
1526 *v850e2
1527 *v850e2v3
1528 *v850e3v5
1529 "sar r<reg1>, r<reg2>, r<reg3>"
1530 {
1531 TRACE_ALU_INPUT2 (GR[reg1], GR[reg2]);
1532 v850_sar(sd, GR[reg1], GR[reg2], &GR[reg3]);
1533 TRACE_ALU_RESULT1 (GR[reg3]);
1534 }
1535
1536
1537 // SASF
1538 rrrrr,1111110,cccc+0000001000000000:IX:::sasf
1539 *v850e
1540 *v850e1
1541 *v850e2
1542 *v850e2v3
1543 *v850e3v5
1544 "sasf %s<cccc>, r<reg2>"
1545 {
1546 COMPAT_2 (OP_20007E0 ());
1547 }
1548
1549
1550
1551 // SATADD
1552 rrrrr!0,000110,RRRRR:I:::satadd
1553 "satadd r<reg1>, r<reg2>"
1554 {
1555 COMPAT_1 (OP_C0 ());
1556 }
1557
1558 rrrrr!0,010001,iiiii:II:::satadd
1559 "satadd <imm5>, r<reg2>"
1560 {
1561 COMPAT_1 (OP_220 ());
1562 }
1563
1564 rrrrr,111111,RRRRR + wwwww,01110111010:XI:::satadd
1565 *v850e2
1566 *v850e2v3
1567 *v850e3v5
1568 "satadd r<reg1>, r<reg2>, r<reg3>"
1569 {
1570 TRACE_ALU_INPUT2 (GR[reg1], GR[reg2]);
1571 v850_satadd (sd, GR[reg1], GR[reg2], &GR[reg3]);
1572 TRACE_ALU_RESULT1 (GR[reg3]);
1573 }
1574
1575
1576
1577 // SATSUB
1578 rrrrr!0,000101,RRRRR:I:::satsub
1579 "satsub r<reg1>, r<reg2>"
1580 {
1581 COMPAT_1 (OP_A0 ());
1582 }
1583
1584 rrrrr,111111,RRRRR + wwwww,01110011010:XI:::satsub
1585 *v850e2
1586 *v850e2v3
1587 *v850e3v5
1588 "satsub r<reg1>, r<reg2>, r<reg3>"
1589 {
1590 TRACE_ALU_INPUT2 (GR[reg1], GR[reg2]);
1591 v850_satsub (sd, GR[reg1], GR[reg2], &GR[reg3]);
1592 TRACE_ALU_RESULT1 (GR[reg3]);
1593 }
1594
1595
1596
1597 // SATSUBI
1598 rrrrr!0,110011,RRRRR + iiiiiiiiiiiiiiii:VI:::satsubi
1599 "satsubi <simm16>, r<reg1>, r<reg2>"
1600 {
1601 COMPAT_2 (OP_660 ());
1602 }
1603
1604
1605
1606 // SATSUBR
1607 rrrrr!0,000100,RRRRR:I:::satsubr
1608 "satsubr r<reg1>, r<reg2>"
1609 {
1610 COMPAT_1 (OP_80 ());
1611 }
1612
1613
1614
1615 //SBF
1616 rrrrr,111111,RRRRR + wwwww,011100,cccc!13,0:XI:::sbf
1617 *v850e2
1618 *v850e2v3
1619 *v850e3v5
1620 "sbf %s<cccc>, r<reg1>, r<reg2>, r<reg3>"
1621 {
1622 int cond = condition_met (cccc);
1623 TRACE_ALU_INPUT3 (cond, GR[reg1], GR[reg2]);
1624 GR[reg3] = GR[reg2] - GR[reg1] - (cond ? 1 : 0);
1625 TRACE_ALU_RESULT1 (GR[reg3]);
1626 }
1627
1628
1629
1630 // SCH0L
1631 rrrrr,11111100000 + wwwww,01101100100:IX:::sch0l
1632 *v850e2
1633 *v850e2v3
1634 *v850e3v5
1635 "sch0l r<reg2>, r<reg3>"
1636 {
1637 unsigned int pos, op0;
1638
1639 TRACE_ALU_INPUT1 (GR[reg2]);
1640
1641 op0 = GR[reg2];
1642
1643 if (op0 == 0xffffffff)
1644 {
1645 PSW &= ~PSW_CY;
1646 PSW &= ~PSW_OV;
1647 PSW &= ~PSW_S;
1648 PSW |= PSW_Z;
1649 pos = 0;
1650 }
1651 else if (op0 == 0xfffffffe)
1652 {
1653 PSW |= PSW_CY;
1654 PSW &= ~PSW_OV;
1655 PSW &= ~PSW_S;
1656 PSW &= ~PSW_Z;
1657 pos = 32;
1658 }
1659 else
1660 {
1661 pos = 1;
1662 while (op0 & 0x80000000)
1663 {
1664 op0 <<= 1;
1665 pos++;
1666 }
1667 PSW &= ~PSW_CY;
1668 PSW &= ~PSW_OV;
1669 PSW &= ~PSW_S;
1670 PSW &= ~PSW_Z;
1671 }
1672
1673 GR[reg3] = pos;
1674
1675 TRACE_ALU_RESULT1 (GR[reg3]);
1676 }
1677
1678
1679
1680 // SCH0R
1681 rrrrr,11111100000 + wwwww,01101100000:IX:::sch0r
1682 *v850e2
1683 *v850e2v3
1684 *v850e3v5
1685 "sch0r r<reg2>, r<reg3>"
1686 {
1687 unsigned int pos, op0;
1688
1689 TRACE_ALU_INPUT1 (GR[reg2]);
1690
1691 op0 = GR[reg2];
1692
1693 if (op0 == 0xffffffff)
1694 {
1695 PSW &= ~PSW_CY;
1696 PSW &= ~PSW_OV;
1697 PSW &= ~PSW_S;
1698 PSW |= PSW_Z;
1699 pos = 0;
1700 }
1701 else if (op0 == 0x7fffffff)
1702 {
1703 PSW |= PSW_CY;
1704 PSW &= ~PSW_OV;
1705 PSW &= ~PSW_S;
1706 PSW &= ~PSW_Z;
1707 pos = 32;
1708 }
1709 else
1710 {
1711 pos = 1;
1712 while (op0 & 0x00000001)
1713 {
1714 op0 >>= 1;
1715 pos++;
1716 }
1717 PSW &= ~PSW_CY;
1718 PSW &= ~PSW_OV;
1719 PSW &= ~PSW_S;
1720 PSW &= ~PSW_Z;
1721 }
1722
1723 GR[reg3] = pos;
1724
1725 TRACE_ALU_RESULT1 (GR[reg3]);
1726 }
1727
1728 // SCH1L
1729 rrrrr,11111100000 + wwwww,01101100110:IX:::sch1l
1730 *v850e2
1731 *v850e2v3
1732 *v850e3v5
1733 "sch1l r<reg2>, r<reg3>"
1734 {
1735 unsigned int pos, op0;
1736
1737 TRACE_ALU_INPUT1 (GR[reg2]);
1738
1739 op0 = GR[reg2];
1740
1741 if (op0 == 0x00000000)
1742 {
1743 PSW &= ~PSW_CY;
1744 PSW &= ~PSW_OV;
1745 PSW &= ~PSW_S;
1746 PSW |= PSW_Z;
1747 pos = 0;
1748 }
1749 else if (op0 == 0x00000001)
1750 {
1751 PSW |= PSW_CY;
1752 PSW &= ~PSW_OV;
1753 PSW &= ~PSW_S;
1754 PSW &= ~PSW_Z;
1755 pos = 32;
1756 }
1757 else
1758 {
1759 pos = 1;
1760 while (!(op0 & 0x80000000))
1761 {
1762 op0 <<= 1;
1763 pos++;
1764 }
1765 PSW &= ~PSW_CY;
1766 PSW &= ~PSW_OV;
1767 PSW &= ~PSW_S;
1768 PSW &= ~PSW_Z;
1769 }
1770
1771 GR[reg3] = pos;
1772
1773 TRACE_ALU_RESULT1 (GR[reg3]);
1774 }
1775
1776 // SCH1R
1777 rrrrr,11111100000 + wwwww,01101100010:IX:::sch1r
1778 *v850e2
1779 *v850e2v3
1780 *v850e3v5
1781 "sch1r r<reg2>, r<reg3>"
1782 {
1783 unsigned int pos, op0;
1784
1785 TRACE_ALU_INPUT1 (GR[reg2]);
1786
1787 op0 = GR[reg2];
1788
1789 if (op0 == 0x00000000)
1790 {
1791 PSW &= ~PSW_CY;
1792 PSW &= ~PSW_OV;
1793 PSW &= ~PSW_S;
1794 PSW |= PSW_Z;
1795 pos = 0;
1796 }
1797 else if (op0 == 0x80000000)
1798 {
1799 PSW |= PSW_CY;
1800 PSW &= ~PSW_OV;
1801 PSW &= ~PSW_S;
1802 PSW &= ~PSW_Z;
1803 pos = 32;
1804 }
1805 else
1806 {
1807 pos = 1;
1808 while (!(op0 & 0x00000001))
1809 {
1810 op0 >>= 1;
1811 pos++;
1812 }
1813 PSW &= ~PSW_CY;
1814 PSW &= ~PSW_OV;
1815 PSW &= ~PSW_S;
1816 PSW &= ~PSW_Z;
1817 }
1818
1819 GR[reg3] = pos;
1820
1821 TRACE_ALU_RESULT1 (GR[reg3]);
1822 }
1823
1824 //SHL
1825 rrrrr,111111,RRRRR + wwwww,00011000010:XI:::shl
1826 *v850e2
1827 *v850e2v3
1828 *v850e3v5
1829 "shl r<reg1>, r<reg2>, r<reg3>"
1830 {
1831 TRACE_ALU_INPUT2 (GR[reg1], GR[reg2]);
1832 v850_shl(sd, GR[reg1], GR[reg2], &GR[reg3]);
1833 TRACE_ALU_RESULT1 (GR[reg3]);
1834 }
1835
1836 //SHR
1837 rrrrr,111111,RRRRR + wwwww,00010000010:XI:::shr
1838 *v850e2
1839 *v850e2v3
1840 *v850e3v5
1841 "shr r<reg1>, r<reg2>, r<reg3>"
1842 {
1843 TRACE_ALU_INPUT2 (GR[reg1], GR[reg2]);
1844 v850_shr(sd, GR[reg1], GR[reg2], &GR[reg3]);
1845 TRACE_ALU_RESULT1 (GR[reg3]);
1846 }
1847
1848
1849
1850 // SETF
1851 rrrrr,1111110,cccc + 0000000000000000:IX:::setf
1852 "setf %s<cccc>, r<reg2>"
1853 {
1854 COMPAT_2 (OP_7E0 ());
1855 }
1856
1857
1858
1859 // SET1
1860 00,bbb,111110,RRRRR + dddddddddddddddd:VIII:::set1
1861 "set1 <bit3>, <disp16>[r<reg1>]"
1862 {
1863 COMPAT_2 (OP_7C0 ());
1864 }
1865
1866 rrrrr,111111,RRRRR + 0000000011100000:IX:::set1
1867 *v850e
1868 *v850e1
1869 *v850e2
1870 *v850e2v3
1871 *v850e3v5
1872 "set1 r<reg2>, [r<reg1>]"
1873 {
1874 COMPAT_2 (OP_E007E0 ());
1875 }
1876
1877
1878
1879 // SHL
1880 rrrrr,111111,RRRRR + 0000000011000000:IX:::shl
1881 "shl r<reg1>, r<reg2>"
1882 {
1883 COMPAT_2 (OP_C007E0 ());
1884 }
1885
1886 rrrrr,010110,iiiii:II:::shl
1887 "shl <imm5>, r<reg2>"
1888 {
1889 COMPAT_1 (OP_2C0 ());
1890 }
1891
1892
1893
1894 // SHR
1895 rrrrr,111111,RRRRR + 0000000010000000:IX:::shr
1896 "shr r<reg1>, r<reg2>"
1897 {
1898 COMPAT_2 (OP_8007E0 ());
1899 }
1900
1901 rrrrr,010100,iiiii:II:::shr
1902 "shr <imm5>, r<reg2>"
1903 {
1904 COMPAT_1 (OP_280 ());
1905 }
1906
1907
1908
1909 // SLD
1910 rrrrr,0110,ddddddd:IV:::sld.b
1911 "sld.bu <disp7>[ep], r<reg2>":(PSW & PSW_US)
1912 "sld.b <disp7>[ep], r<reg2>"
1913 {
1914 uint32_t addr = EP + disp7;
1915 uint32_t result = load_mem (addr, 1);
1916 if (PSW & PSW_US)
1917 {
1918 GR[reg2] = result;
1919 TRACE_LD_NAME ("sld.bu", addr, result);
1920 }
1921 else
1922 {
1923 result = EXTEND8 (result);
1924 GR[reg2] = result;
1925 TRACE_LD (addr, result);
1926 }
1927 }
1928
1929 rrrrr,1000,ddddddd:IV:::sld.h
1930 "sld.hu <disp8>[ep], r<reg2>":(PSW & PSW_US)
1931 "sld.h <disp8>[ep], r<reg2>"
1932 {
1933 uint32_t addr = EP + disp8;
1934 uint32_t result = load_mem (addr, 2);
1935 if (PSW & PSW_US)
1936 {
1937 GR[reg2] = result;
1938 TRACE_LD_NAME ("sld.hu", addr, result);
1939 }
1940 else
1941 {
1942 result = EXTEND16 (result);
1943 GR[reg2] = result;
1944 TRACE_LD (addr, result);
1945 }
1946 }
1947
1948 rrrrr,1010,dddddd,0:IV:::sld.w
1949 "sld.w <disp8>[ep], r<reg2>"
1950 {
1951 uint32_t addr = EP + disp8;
1952 uint32_t result = load_mem (addr, 4);
1953 GR[reg2] = result;
1954 TRACE_LD (addr, result);
1955 }
1956
1957 rrrrr!0,0000110,dddd:IV:::sld.bu
1958 *v850e
1959 *v850e1
1960 *v850e2
1961 *v850e2v3
1962 *v850e3v5
1963 "sld.b <disp4>[ep], r<reg2>":(PSW & PSW_US)
1964 "sld.bu <disp4>[ep], r<reg2>"
1965 {
1966 uint32_t addr = EP + disp4;
1967 uint32_t result = load_mem (addr, 1);
1968 if (PSW & PSW_US)
1969 {
1970 result = EXTEND8 (result);
1971 GR[reg2] = result;
1972 TRACE_LD_NAME ("sld.b", addr, result);
1973 }
1974 else
1975 {
1976 GR[reg2] = result;
1977 TRACE_LD (addr, result);
1978 }
1979 }
1980
1981 rrrrr!0,0000111,dddd:IV:::sld.hu
1982 *v850e
1983 *v850e1
1984 *v850e2
1985 *v850e2v3
1986 *v850e3v5
1987 "sld.h <disp5>[ep], r<reg2>":(PSW & PSW_US)
1988 "sld.hu <disp5>[ep], r<reg2>"
1989 {
1990 uint32_t addr = EP + disp5;
1991 uint32_t result = load_mem (addr, 2);
1992 if (PSW & PSW_US)
1993 {
1994 result = EXTEND16 (result);
1995 GR[reg2] = result;
1996 TRACE_LD_NAME ("sld.h", addr, result);
1997 }
1998 else
1999 {
2000 GR[reg2] = result;
2001 TRACE_LD (addr, result);
2002 }
2003 }
2004
2005
2006
2007 // SST
2008 rrrrr,0111,ddddddd:IV:::sst.b
2009 "sst.b r<reg2>, <disp7>[ep]"
2010 {
2011 COMPAT_1 (OP_380 ());
2012 }
2013
2014 rrrrr,1001,ddddddd:IV:::sst.h
2015 "sst.h r<reg2>, <disp8>[ep]"
2016 {
2017 COMPAT_1 (OP_480 ());
2018 }
2019
2020 rrrrr,1010,dddddd,1:IV:::sst.w
2021 "sst.w r<reg2>, <disp8>[ep]"
2022 {
2023 COMPAT_1 (OP_501 ());
2024 }
2025
2026 // ST
2027 rrrrr,111010,RRRRR + dddddddddddddddd:VII:::st.b
2028 "st.b r<reg2>, <disp16>[r<reg1>]"
2029 {
2030 COMPAT_2 (OP_740 ());
2031 }
2032
2033 00000111100,RRRRR + wwwww,ddddddd,1101 + dddddddddddddddd:XIV:::st.b
2034 *v850e2v3
2035 *v850e3v5
2036 "st.b r<reg3>, <disp23>[r<reg1>]"
2037 {
2038 uint32_t addr = GR[reg1] + disp23;
2039 store_data_mem (sd, addr, 1, GR[reg3]);
2040 TRACE_ST (addr, GR[reg3]);
2041 }
2042
2043 rrrrr,111011,RRRRR + ddddddddddddddd,0:VII:::st.h
2044 "st.h r<reg2>, <disp16>[r<reg1>]"
2045 {
2046 COMPAT_2 (OP_760 ());
2047 }
2048
2049 00000111101,RRRRR+wwwww,dddddd,01101+dddddddddddddddd:XIV:::st.h
2050 *v850e2v3
2051 *v850e3v5
2052 "st.h r<reg3>, <disp23>[r<reg1>]"
2053 {
2054 uint32_t addr = GR[reg1] + disp23;
2055 store_data_mem (sd, addr, 2, GR[reg3]);
2056 TRACE_ST (addr, GR[reg3]);
2057 }
2058
2059 rrrrr,111011,RRRRR + ddddddddddddddd,1:VII:::st.w
2060 "st.w r<reg2>, <disp16>[r<reg1>]"
2061 {
2062 COMPAT_2 (OP_10760 ());
2063 }
2064
2065 00000111100,RRRRR+wwwww,dddddd,01111+dddddddddddddddd:XIV:::st.w
2066 *v850e2v3
2067 *v850e3v5
2068 "st.w r<reg3>, <disp23>[r<reg1>]"
2069 {
2070 uint32_t addr = GR[reg1] + disp23;
2071 store_data_mem (sd, addr, 4, GR[reg3]);
2072 TRACE_ST (addr, GR[reg3]);
2073 }
2074
2075 00000111101,RRRRR+wwwww,dddddd,01111+dddddddddddddddd:XIV:::st.dw
2076 *v850e3v5
2077 "st.dw r<reg3>, <disp23>[r<reg1>]"
2078 {
2079 uint32_t addr = GR[reg1] + disp23;
2080 store_data_mem (sd, addr, 4, GR[reg3]);
2081 TRACE_ST (addr, GR[reg3]);
2082 store_data_mem (sd, addr + 4, 4, GR[reg3 + 1]);
2083 TRACE_ST (addr + 4, GR[reg3 + 1]);
2084 }
2085
2086
2087 // STSR
2088 rrrrr,111111,regID + 0000000001000000:IX:::stsr
2089 "stsr s<regID>, r<reg2>"
2090 {
2091 uint32_t sreg = 0;
2092
2093 if ((idecode_issue == idecode_v850e2_issue
2094 || idecode_issue == idecode_v850e3v5_issue
2095 || idecode_issue == idecode_v850e2v3_issue)
2096 && regID < 28)
2097 {
2098 switch (BSEL & 0xffff)
2099 {
2100 case 0x0000:
2101 case 0xff00: /* USER 0 */
2102 case 0xffff: /* USER 1 */
2103 sreg = SR[regID];
2104 break;
2105 case 0x1000:
2106 sreg = MPU0_SR[regID];
2107 break;
2108 case 0x1001:
2109 sreg = MPU1_SR[regID];
2110 break;
2111 case 0x2000:
2112 if (regID == FPST_REGNO)
2113 {
2114 sreg = ((FPSR & FPSR_PR) ? FPST_PR : 0)
2115 | ((FPSR & FPSR_XCE) ? FPST_XCE : 0)
2116 | ((FPSR & FPSR_XCV) ? FPST_XCV : 0)
2117 | ((FPSR & FPSR_XCZ) ? FPST_XCZ : 0)
2118 | ((FPSR & FPSR_XCO) ? FPST_XCO : 0)
2119 | ((FPSR & FPSR_XCU) ? FPST_XCU : 0)
2120 | ((FPSR & FPSR_XCI) ? FPST_XCI : 0)
2121 | ((FPSR & FPSR_XPV) ? FPST_XPV : 0)
2122 | ((FPSR & FPSR_XPZ) ? FPST_XPZ : 0)
2123 | ((FPSR & FPSR_XPO) ? FPST_XPO : 0)
2124 | ((FPSR & FPSR_XPU) ? FPST_XPU : 0)
2125 | ((FPSR & FPSR_XPI) ? FPST_XPI : 0);
2126 }
2127 else if (regID == FPCFG_REGNO)
2128 {
2129 sreg = (((FPSR & FPSR_RM) >> 18) << 7)
2130 | ((FPSR & FPSR_XEV) ? FPCFG_XEV : 0)
2131 | ((FPSR & FPSR_XEZ) ? FPCFG_XEZ : 0)
2132 | ((FPSR & FPSR_XEO) ? FPCFG_XEO : 0)
2133 | ((FPSR & FPSR_XEU) ? FPCFG_XEU : 0)
2134 | ((FPSR & FPSR_XEI) ? FPCFG_XEI : 0);
2135 }
2136 else
2137 {
2138 sreg = FPU_SR[regID];
2139 }
2140 break;
2141 }
2142 }
2143 else
2144 {
2145 sreg = SR[regID];
2146 }
2147
2148 TRACE_ALU_INPUT1 (sreg);
2149 GR[reg2] = sreg;
2150 TRACE_ALU_RESULT (GR[reg2]);
2151 }
2152
2153 // SUB
2154 rrrrr,001101,RRRRR:I:::sub
2155 "sub r<reg1>, r<reg2>"
2156 {
2157 COMPAT_1 (OP_1A0 ());
2158 }
2159
2160 // SUBR
2161 rrrrr,001100,RRRRR:I:::subr
2162 "subr r<reg1>, r<reg2>"
2163 {
2164 COMPAT_1 (OP_180 ());
2165 }
2166
2167 // SWITCH
2168 00000000010,RRRRR:I:::switch
2169 *v850e
2170 *v850e1
2171 *v850e2
2172 *v850e2v3
2173 *v850e3v5
2174 "switch r<reg1>"
2175 {
2176 unsigned long adr;
2177 SAVE_1;
2178 trace_input ("switch", OP_REG, 0);
2179 adr = (cia + 2) + (State.regs[ reg1 ] << 1);
2180 nia = (cia + 2) + (EXTEND16 (load_mem (adr, 2)) << 1);
2181 trace_output (OP_REG);
2182 }
2183
2184 // SXB
2185 00000000101,RRRRR:I:::sxb
2186 *v850e
2187 *v850e1
2188 *v850e2
2189 *v850e2v3
2190 *v850e3v5
2191 "sxb r<reg1>"
2192 {
2193 TRACE_ALU_INPUT1 (GR[reg1]);
2194 GR[reg1] = EXTEND8 (GR[reg1]);
2195 TRACE_ALU_RESULT (GR[reg1]);
2196 }
2197
2198 // SXH
2199 00000000111,RRRRR:I:::sxh
2200 *v850e
2201 *v850e1
2202 *v850e2
2203 *v850e2v3
2204 *v850e3v5
2205 "sxh r<reg1>"
2206 {
2207 TRACE_ALU_INPUT1 (GR[reg1]);
2208 GR[reg1] = EXTEND16 (GR[reg1]);
2209 TRACE_ALU_RESULT (GR[reg1]);
2210 }
2211
2212 // TRAP
2213 00000111111,iiiii + 0000000100000000:X:::trap
2214 "trap <vector>"
2215 {
2216 COMPAT_2 (OP_10007E0 ());
2217 }
2218
2219 // TST
2220 rrrrr,001011,RRRRR:I:::tst
2221 "tst r<reg1>, r<reg2>"
2222 {
2223 COMPAT_1 (OP_160 ());
2224 }
2225
2226 // TST1
2227 11,bbb,111110,RRRRR + dddddddddddddddd:VIII:::tst1
2228 "tst1 <bit3>, <disp16>[r<reg1>]"
2229 {
2230 COMPAT_2 (OP_C7C0 ());
2231 }
2232
2233 rrrrr,111111,RRRRR + 0000000011100110:IX:::tst1
2234 *v850e
2235 *v850e1
2236 *v850e2
2237 *v850e2v3
2238 *v850e3v5
2239 "tst1 r<reg2>, [r<reg1>]"
2240 {
2241 COMPAT_2 (OP_E607E0 ());
2242 }
2243
2244 // XOR
2245 rrrrr,001001,RRRRR:I:::xor
2246 "xor r<reg1>, r<reg2>"
2247 {
2248 COMPAT_1 (OP_120 ());
2249 }
2250
2251 // XORI
2252 rrrrr,110101,RRRRR + iiiiiiiiiiiiiiii:VI:::xori
2253 "xori <uimm16>, r<reg1>, r<reg2>"
2254 {
2255 COMPAT_2 (OP_6A0 ());
2256 }
2257
2258 // ZXB
2259 00000000100,RRRRR:I:::zxb
2260 *v850e
2261 *v850e1
2262 *v850e2
2263 *v850e2v3
2264 *v850e3v5
2265 "zxb r<reg1>"
2266 {
2267 TRACE_ALU_INPUT1 (GR[reg1]);
2268 GR[reg1] = GR[reg1] & 0xff;
2269 TRACE_ALU_RESULT (GR[reg1]);
2270 }
2271
2272 // ZXH
2273 00000000110,RRRRR:I:::zxh
2274 *v850e
2275 *v850e1
2276 *v850e2
2277 *v850e2v3
2278 *v850e3v5
2279 "zxh r<reg1>"
2280 {
2281 TRACE_ALU_INPUT1 (GR[reg1]);
2282 GR[reg1] = GR[reg1] & 0xffff;
2283 TRACE_ALU_RESULT (GR[reg1]);
2284 }
2285
2286 // Right field must be zero so that it doesn't clash with DIVH
2287 // Left field must be non-zero so that it doesn't clash with SWITCH
2288 11111,000010,00000:I:::break
2289 *v850
2290 *v850e
2291 {
2292 sim_engine_halt (SD, CPU, NULL, cia, sim_stopped, SIM_SIGTRAP);
2293 }
2294
2295 11111,000010,00000:I:::dbtrap
2296 *v850e1
2297 *v850e2
2298 *v850e2v3
2299 *v850e3v5
2300 "dbtrap"
2301 {
2302 if (STATE_OPEN_KIND (SD) == SIM_OPEN_DEBUG)
2303 {
2304 sim_engine_halt (SD, CPU, NULL, cia, sim_stopped, SIM_SIGTRAP);
2305 }
2306 else
2307 {
2308 DBPC = cia + 2;
2309 DBPSW = PSW;
2310 PSW = PSW | (PSW_NP | PSW_EP | PSW_ID);
2311 PC = 0x00000060;
2312 nia = 0x00000060;
2313 TRACE_BRANCH0 ();
2314 }
2315 }
2316
2317 // New breakpoint: 0x7E0 0x7E0
2318 00000,111111,00000 + 00000,11111,100000:X:::ilgop
2319 {
2320 sim_engine_halt (SD, CPU, NULL, cia, sim_stopped, SIM_SIGTRAP);
2321 }
2322
2323 // Return from debug trap: 0x146007e0
2324 0000011111100000 + 0000000101000110:X:::dbret
2325 *v850e1
2326 *v850e2
2327 *v850e2v3
2328 *v850e3v5
2329 "dbret"
2330 {
2331 nia = DBPC;
2332 PSW = DBPSW;
2333 TRACE_BRANCH1 (PSW);
2334 }
2335
2336
2337 //
2338 // FLOAT
2339 //
2340
2341 // Map condition code to a string
2342 :%s::::FFFF:int FFFF
2343 {
2344 switch (FFFF)
2345 {
2346 case 0: return "f";
2347 case 1: return "un";
2348 case 2: return "eq";
2349 case 3: return "ueq";
2350 case 4: return "olt";
2351 case 5: return "ult";
2352 case 6: return "ole";
2353 case 7: return "ule";
2354 case 8: return "sf";
2355 case 9: return "ngle";
2356 case 10: return "seq";
2357 case 11: return "ngl";
2358 case 12: return "lt";
2359 case 13: return "nge";
2360 case 14: return "le";
2361 case 15: return "ngt";
2362 }
2363 return "(null)";
2364 }
2365
2366 // ABSF.D
2367 rrrr,011111100000 + wwww,010001011000:F_I:::absf_d
2368 *v850e2v3
2369 *v850e3v5
2370 "absf.d r<reg2e>, r<reg3e>"
2371 {
2372 sim_fpu ans, wop;
2373 sim_fpu_status status;
2374
2375 sim_fpu_232to (&wop, GR[reg2e+1], GR[reg2e]);
2376 TRACE_FP_INPUT_FPU1 (&wop);
2377
2378 status = sim_fpu_abs (&ans, &wop);
2379 check_invalid_snan(sd, status, 1);
2380
2381 sim_fpu_to232 (&GR[reg3e+1], &GR[reg3e], &ans);
2382
2383 TRACE_FP_RESULT_FPU1 (&ans);
2384 }
2385
2386 // ABSF.S
2387 rrrrr,11111100000 + wwwww,10001001000:F_I:::absf_s
2388 *v850e2v3
2389 *v850e3v5
2390 "absf.s r<reg2>, r<reg3>"
2391 {
2392 sim_fpu ans, wop;
2393 sim_fpu_status status;
2394
2395 sim_fpu_32to (&wop, GR[reg2]);
2396 TRACE_FP_INPUT_FPU1 (&wop);
2397
2398 status = sim_fpu_abs (&ans, &wop);
2399 check_invalid_snan(sd, status, 0);
2400
2401 sim_fpu_to32 (&GR[reg3], &ans);
2402 TRACE_FP_RESULT_FPU1 (&ans);
2403 }
2404
2405 // ADDF.D
2406 rrrr,0111111,RRRR,0 + wwww,010001110000:F_I:::addf_d
2407 *v850e2v3
2408 *v850e3v5
2409 "addf.d r<reg1e>, r<reg2e>, r<reg3e>"
2410 {
2411 sim_fpu ans, wop1, wop2;
2412 sim_fpu_status status;
2413
2414 sim_fpu_232to (&wop1, GR[reg1e+1], GR[reg1e]);
2415 sim_fpu_232to (&wop2, GR[reg2e+1], GR[reg2e]);
2416 TRACE_FP_INPUT_FPU2 (&wop1, &wop2);
2417
2418 status = sim_fpu_add (&ans, &wop1, &wop2);
2419 status |= sim_fpu_round_64 (&ans, FPSR_GET_ROUND(), sim_fpu_denorm_underflow_inexact);
2420
2421 update_fpsr (sd, status, FPSR_XEV | FPSR_XEI | FPSR_XEO | FPSR_XEU, 1);
2422
2423 sim_fpu_to232 (&GR[reg3e+1], &GR[reg3e], &ans);
2424 TRACE_FP_RESULT_FPU1 (&ans);
2425 }
2426
2427 // ADDF.S
2428 rrrrr,111111,RRRRR + wwwww,10001100000:F_I:::addf_s
2429 *v850e2v3
2430 *v850e3v5
2431 "addf.s r<reg1>, r<reg2>, r<reg3>"
2432 {
2433 sim_fpu ans, wop1, wop2;
2434 sim_fpu_status status;
2435
2436 sim_fpu_32to (&wop1, GR[reg1]);
2437 sim_fpu_32to (&wop2, GR[reg2]);
2438 TRACE_FP_INPUT_FPU2 (&wop1, &wop2);
2439
2440 status = sim_fpu_add (&ans, &wop1, &wop2);
2441 status |= sim_fpu_round_32 (&ans, FPSR_GET_ROUND(), sim_fpu_denorm_underflow_inexact);
2442
2443 update_fpsr (sd, status, FPSR_XEV | FPSR_XEI | FPSR_XEO | FPSR_XEU, 0);
2444
2445 sim_fpu_to32 (&GR[reg3], &ans);
2446 TRACE_FP_RESULT_FPU1 (&ans);
2447 }
2448
2449 // CMOVF.D
2450 rrrr,0111111,RRRR,0 + wwww!0,01000001,bbb,0:F_I:::cmovf_d
2451 *v850e2v3
2452 *v850e3v5
2453 "cmovf.d <bbb>, r<reg1e>, r<reg2e>, r<reg3e>"
2454 {
2455 unsigned int ophi,oplow;
2456 sim_fpu ans, wop1, wop2;
2457
2458 sim_fpu_232to (&wop1, GR[reg1e+1], GR[reg1e]);
2459 sim_fpu_232to (&wop2, GR[reg2e+1], GR[reg2e]);
2460 TRACE_FP_INPUT_BOOL1_FPU2 (TEST_FPCC(bbb), &wop1, &wop2);
2461
2462 if (TEST_FPCC(bbb))
2463 {
2464 ophi = GR[reg1e+1];
2465 oplow = GR[reg1e];
2466 ans = wop1;
2467 }
2468 else
2469 {
2470 ophi = GR[reg2e+1];
2471 oplow = GR[reg2e];
2472 ans = wop2;
2473 }
2474
2475 GR[reg3e+1] = ophi;
2476 GR[reg3e] = oplow;
2477 TRACE_FP_RESULT_FPU1 (&ans);;
2478 }
2479
2480 // CMOVF.S
2481 rrrrr,111111,RRRRR!0 + wwwww!0,1000000,bbb,0:F_I:::cmovf_s
2482 *v850e2v3
2483 *v850e3v5
2484 "cmovf.d <bbb>, r<reg1>, r<reg2>, r<reg3>"
2485 {
2486 unsigned int op;
2487 sim_fpu ans, wop1, wop2;
2488
2489 sim_fpu_32to (&wop1, GR[reg1]);
2490 sim_fpu_32to (&wop2, GR[reg2]);
2491 TRACE_FP_INPUT_BOOL1_FPU2 (TEST_FPCC(bbb), &wop1, &wop2);
2492
2493 if (TEST_FPCC(bbb))
2494 {
2495 op = GR[reg1];
2496 ans = wop1;
2497 }
2498 else
2499 {
2500 op = GR[reg2];
2501 ans = wop2;
2502 }
2503
2504 GR[reg3] = op;
2505 TRACE_FP_RESULT_FPU1 (&ans);
2506 }
2507
2508 // CMPF.D
2509 rrrr,0111111,RRRR,0 + 0,FFFF,1000011,bbb,0:F_I:::cmpf_d
2510 *v850e2v3
2511 *v850e3v5
2512 "cmpf.d %s<FFFF>, r<reg2e>, r<reg1e>":(bbb == 0)
2513 "cmpf.d %s<FFFF>, r<reg2e>, r<reg1e>, <bbb>"
2514 {
2515 int result;
2516 sim_fpu wop1;
2517 sim_fpu wop2;
2518
2519 sim_fpu_232to (&wop1, GR[reg1e+1], GR[reg1e]);
2520 sim_fpu_232to (&wop2, GR[reg2e+1], GR[reg2e]);
2521 TRACE_FP_INPUT_FPU2 (&wop2, &wop1);
2522
2523 result = v850_float_compare(sd, FFFF, wop2, wop1, 1);
2524
2525 if (result)
2526 SET_FPCC(bbb);
2527 else
2528 CLEAR_FPCC(bbb);
2529
2530 TRACE_FP_RESULT_BOOL (result);
2531 }
2532
2533 // CMPF.S
2534 rrrrr,111111,RRRRR + 0,FFFF,1000010,bbb,0:F_I:::cmpf_s
2535 *v850e2v3
2536 *v850e3v5
2537 "cmpf.s %s<FFFF>, r<reg2>, r<reg1>":(bbb == 0)
2538 "cmpf.s %s<FFFF>, r<reg2>, r<reg1>, <bbb>"
2539 {
2540 int result;
2541 sim_fpu wop1;
2542 sim_fpu wop2;
2543
2544 sim_fpu_32to( &wop1, GR[reg1] );
2545 sim_fpu_32to( &wop2, GR[reg2] );
2546 TRACE_FP_INPUT_FPU2 (&wop2, &wop1);
2547
2548 result = v850_float_compare(sd, FFFF, wop2, wop1, 0);
2549
2550 if (result)
2551 SET_FPCC(bbb);
2552 else
2553 CLEAR_FPCC(bbb);
2554
2555 TRACE_FP_RESULT_BOOL (result);
2556 }
2557
2558 // CVTF.DL
2559 rrrr,011111100100 + wwww,010001010100:F_I:::cvtf_dl
2560 *v850e2v3
2561 *v850e3v5
2562 "cvtf.dl r<reg2e>, r<reg3e>"
2563 {
2564 int64_t ans;
2565 sim_fpu wop;
2566 sim_fpu_status status;
2567
2568 sim_fpu_232to (&wop, GR[reg2e+1], GR[reg2e]);
2569 TRACE_FP_INPUT_FPU1 (&wop);
2570
2571 status = sim_fpu_round_64 (&wop, FPSR_GET_ROUND(), sim_fpu_denorm_zero);
2572 status |= sim_fpu_to64i (&ans, &wop, FPSR_GET_ROUND());
2573
2574 check_cvt_fi(sd, status, 1);
2575
2576 GR[reg3e] = ans;
2577 GR[reg3e+1] = ans>>32L;
2578 TRACE_FP_RESULT_WORD2 (GR[reg3e], GR[reg3e+1]);
2579 }
2580
2581 // CVTF.DS
2582 rrrr,011111100011 + wwwww,10001010010:F_I:::cvtf_ds
2583 *v850e2v3
2584 *v850e3v5
2585 "cvtf.ds r<reg2e>, r<reg3>"
2586 {
2587 sim_fpu wop;
2588 sim_fpu_status status;
2589
2590 sim_fpu_232to (&wop, GR[reg2e+1], GR[reg2e]);
2591 TRACE_FP_INPUT_FPU1 (&wop);
2592
2593 status = sim_fpu_round_32 (&wop, FPSR_GET_ROUND(), sim_fpu_denorm_underflow_inexact);
2594
2595 check_cvt_fi(sd, status, 0);
2596
2597 sim_fpu_to32 (&GR[reg3], &wop);
2598 TRACE_FP_RESULT_FPU1 (&wop);
2599 }
2600
2601 // CVTF.DW
2602 rrrr,011111100100 + wwwww,10001010000:F_I:::cvtf_dw
2603 *v850e2v3
2604 *v850e3v5
2605 "cvtf.dw r<reg2e>, r<reg3>"
2606 {
2607 int32_t ans;
2608 sim_fpu wop;
2609 sim_fpu_status status;
2610
2611 sim_fpu_232to (&wop, GR[reg2e+1], GR[reg2e]);
2612 TRACE_FP_INPUT_FPU1 (&wop);
2613
2614 status = sim_fpu_round_32 (&wop, FPSR_GET_ROUND(), sim_fpu_denorm_zero);
2615 status |= sim_fpu_to32i (&ans, &wop, FPSR_GET_ROUND());
2616
2617 check_cvt_fi(sd, status, 1);
2618
2619 GR[reg3] = ans;
2620 TRACE_FP_RESULT_WORD1 (ans);
2621 }
2622
2623 // CVTF.LD
2624 rrrr,011111100001 + wwww,010001010010:F_I:::cvtf_ld
2625 *v850e2v3
2626 *v850e3v5
2627 "cvtf.ld r<reg2e>, r<reg3e>"
2628 {
2629 int64_t op;
2630 sim_fpu wop;
2631 sim_fpu_status status;
2632
2633 op = ((int64_t)GR[reg2e+1] << 32L) | GR[reg2e];
2634 TRACE_FP_INPUT_WORD2 (GR[reg2e], GR[reg2e+1]);
2635
2636 sim_fpu_i64to (&wop, op, FPSR_GET_ROUND());
2637 status = sim_fpu_round_64 (&wop, FPSR_GET_ROUND(), sim_fpu_denorm_zero);
2638
2639 check_cvt_if(sd, status, 1);
2640
2641 sim_fpu_to232 (&GR[reg3e+1], &GR[reg3e], &wop);
2642 TRACE_FP_RESULT_FPU1 (&wop);
2643 }
2644
2645 // CVTF.LS
2646 rrrr,011111100001 + wwwww,10001000010:F_I:::cvtf_ls
2647 *v850e2v3
2648 *v850e3v5
2649 "cvtf.ls r<reg2e>, r<reg3>"
2650 {
2651 int64_t op;
2652 sim_fpu wop;
2653 sim_fpu_status status;
2654
2655 op = ((int64_t)GR[reg2e+1] << 32L) | GR[reg2e];
2656 TRACE_FP_INPUT_WORD2 (GR[reg2e], GR[reg2e+1]);
2657
2658 sim_fpu_i64to (&wop, op, FPSR_GET_ROUND());
2659 status = sim_fpu_round_32 (&wop, FPSR_GET_ROUND(), sim_fpu_denorm_zero);
2660
2661 check_cvt_if(sd, status, 0);
2662
2663 sim_fpu_to32 (&GR[reg3], &wop);
2664 TRACE_FP_RESULT_FPU1 (&wop);
2665 }
2666
2667 // CVTF.SD
2668 rrrrr,11111100010 + wwww,010001010010:F_I:::cvtf_sd
2669 *v850e2v3
2670 *v850e3v5
2671 "cvtf.sd r<reg2>, r<reg3e>"
2672 {
2673 sim_fpu wop;
2674 sim_fpu_status status;
2675
2676 sim_fpu_32to (&wop, GR[reg2]);
2677 TRACE_FP_INPUT_FPU1 (&wop);
2678 status = sim_fpu_round_64 (&wop, FPSR_GET_ROUND(), sim_fpu_denorm_underflow_inexact);
2679
2680 check_cvt_ff(sd, status, 1);
2681
2682 sim_fpu_to232 (&GR[reg3e+1], &GR[reg3e], &wop);
2683 TRACE_FP_RESULT_FPU1 (&wop);
2684 }
2685
2686 // CVTF.SL
2687 rrrrr,11111100100 + wwww,010001000100:F_I:::cvtf_sl
2688 *v850e2v3
2689 *v850e3v5
2690 "cvtf.sl r<reg2>, r<reg3e>"
2691 {
2692 int64_t ans;
2693 sim_fpu wop;
2694 sim_fpu_status status;
2695
2696 sim_fpu_32to (&wop, GR[reg2]);
2697 TRACE_FP_INPUT_FPU1 (&wop);
2698
2699 status = sim_fpu_round_64 (&wop, FPSR_GET_ROUND(), sim_fpu_denorm_zero);
2700 status |= sim_fpu_to64i (&ans, &wop, FPSR_GET_ROUND());
2701
2702 check_cvt_fi(sd, status, 0);
2703
2704 GR[reg3e] = ans;
2705 GR[reg3e+1] = ans >> 32L;
2706 TRACE_FP_RESULT_WORD2 (GR[reg3e], GR[reg3e+1]);
2707 }
2708
2709 // CVTF.SW
2710 rrrrr,11111100100 + wwwww,10001000000:F_I:::cvtf_sw
2711 *v850e2v3
2712 *v850e3v5
2713 "cvtf.sw r<reg2>, r<reg3>"
2714 {
2715 int32_t ans;
2716 sim_fpu wop;
2717 sim_fpu_status status;
2718
2719 sim_fpu_32to (&wop, GR[reg2]);
2720 TRACE_FP_INPUT_FPU1 (&wop);
2721
2722 status = sim_fpu_round_32 (&wop, FPSR_GET_ROUND(), sim_fpu_denorm_zero);
2723 status |= sim_fpu_to32i (&ans, &wop, sim_fpu_round_zero);
2724
2725 check_cvt_fi(sd, status, 0);
2726
2727 GR[reg3] = ans;
2728 TRACE_FP_RESULT_WORD1 (ans);
2729 }
2730
2731 // CVTF.WD
2732 rrrrr,11111100000 + wwww,010001010010:F_I:::cvtf_wd
2733 *v850e2v3
2734 *v850e3v5
2735 "cvtf.wd r<reg2>, r<reg3e>"
2736 {
2737 sim_fpu wop;
2738 sim_fpu_status status;
2739
2740 TRACE_FP_INPUT_WORD1 (GR[reg2]);
2741 sim_fpu_i32to (&wop, GR[reg2], FPSR_GET_ROUND());
2742 status = sim_fpu_round_64 (&wop, FPSR_GET_ROUND(), sim_fpu_denorm_zero);
2743
2744 check_cvt_if(sd, status, 1);
2745
2746 sim_fpu_to232 (&GR[reg3e+1], &GR[reg3e], &wop);
2747 TRACE_FP_RESULT_FPU1 (&wop);
2748 }
2749
2750 // CVTF.WS
2751 rrrrr,11111100000 + wwwww,10001000010:F_I:::cvtf_ws
2752 *v850e2v3
2753 *v850e3v5
2754 "cvtf.ws r<reg2>, r<reg3>"
2755 {
2756 sim_fpu wop;
2757 sim_fpu_status status;
2758
2759 TRACE_FP_INPUT_WORD1 (GR[reg2]);
2760 sim_fpu_i32to (&wop, GR[reg2], FPSR_GET_ROUND());
2761 status = sim_fpu_round_32 (&wop, FPSR_GET_ROUND(), sim_fpu_denorm_zero);
2762
2763 check_cvt_if(sd, status, 0);
2764
2765 sim_fpu_to32 (&GR[reg3], &wop);
2766 TRACE_FP_RESULT_FPU1 (&wop);
2767 }
2768
2769 // DIVF.D
2770 rrrr,0111111,RRRR,0 + wwww,010001111110:F_I:::divf_d
2771 *v850e2v3
2772 *v850e3v5
2773 "divf.d r<reg1e>, r<reg2e>, r<reg3e>"
2774 {
2775 sim_fpu ans, wop1, wop2;
2776 sim_fpu_status status;
2777
2778 sim_fpu_232to (&wop1, GR[reg1e+1], GR[reg1e]);
2779 sim_fpu_232to (&wop2, GR[reg2e+1], GR[reg2e]);
2780 TRACE_FP_INPUT_FPU2 (&wop1, &wop2);
2781
2782 status = sim_fpu_div (&ans, &wop2, &wop1);
2783 status |= sim_fpu_round_64 (&ans, FPSR_GET_ROUND(), sim_fpu_denorm_underflow_inexact);
2784
2785 update_fpsr (sd, status, FPSR_XEV | FPSR_XEZ | FPSR_XEI | FPSR_XEO | FPSR_XEU, 1);
2786
2787 sim_fpu_to232 (&GR[reg3e+1], &GR[reg3e], &ans);
2788 TRACE_FP_RESULT_FPU1 (&ans);
2789 }
2790
2791 // DIVF.S
2792 rrrrr,111111,RRRRR + wwwww,10001101110:F_I:::divf_s
2793 *v850e2v3
2794 *v850e3v5
2795 "divf.s r<reg1>, r<reg2>, r<reg3>"
2796 {
2797 sim_fpu ans, wop1, wop2;
2798 sim_fpu_status status;
2799
2800 sim_fpu_32to (&wop1, GR[reg1]);
2801 sim_fpu_32to (&wop2, GR[reg2]);
2802 TRACE_FP_INPUT_FPU2 (&wop1, &wop2);
2803
2804 status = sim_fpu_div (&ans, &wop2, &wop1);
2805 status |= sim_fpu_round_32 (&ans, FPSR_GET_ROUND(), sim_fpu_denorm_underflow_inexact);
2806
2807 update_fpsr (sd, status, FPSR_XEV | FPSR_XEZ | FPSR_XEI | FPSR_XEO | FPSR_XEU, 0);
2808
2809 sim_fpu_to32 (&GR[reg3], &ans);
2810 TRACE_FP_RESULT_FPU1 (&ans);
2811 }
2812
2813 // MADDF.S
2814 rrrrr,111111,RRRRR + wwwww,101,W,00,WWWW,0:F_I:::maddf_s
2815 *v850e2v3
2816 "maddf.s r<reg1>, r<reg2>, r<reg3>, r<reg4>"
2817 {
2818 sim_fpu ans, wop1, wop2, wop3;
2819 sim_fpu_status status;
2820
2821 sim_fpu_32to (&wop1, GR[reg1]);
2822 sim_fpu_32to (&wop2, GR[reg2]);
2823 sim_fpu_32to (&wop3, GR[reg3]);
2824 TRACE_FP_INPUT_FPU3 (&wop1, &wop2, &wop3);
2825
2826 status = sim_fpu_mul (&ans, &wop1, &wop2);
2827 wop1 = ans;
2828 status |= sim_fpu_add (&ans, &wop1, &wop3);
2829 status |= sim_fpu_round_64 (&ans, FPSR_GET_ROUND(), sim_fpu_denorm_underflow_inexact);
2830
2831 update_fpsr (sd, status, FPSR_XEV | FPSR_XEI | FPSR_XEO | FPSR_XEU, 0);
2832
2833 sim_fpu_to32 (&GR[reg4], &ans);
2834 TRACE_FP_RESULT_FPU1 (&ans);
2835 }
2836
2837 // FMAF.S
2838 rrrrr,111111,RRRRR + wwwww,10011100000:F_I:::fmaf_s
2839 *v850e3v5
2840 "fmaf.s r<reg1>, r<reg2>, r<reg3>"
2841 {
2842 sim_fpu ans, wop1, wop2, wop3;
2843 sim_fpu_status status;
2844
2845 sim_fpu_32to (&wop1, GR[reg1]);
2846 sim_fpu_32to (&wop2, GR[reg2]);
2847 sim_fpu_32to (&wop3, GR[reg3]);
2848 TRACE_FP_INPUT_FPU3 (&wop1, &wop2, &wop3);
2849
2850 status = sim_fpu_mul (&ans, &wop1, &wop2);
2851 wop1 = ans;
2852 status |= sim_fpu_add (&ans, &wop1, &wop3);
2853 status |= sim_fpu_round_64 (&ans, FPSR_GET_ROUND(), sim_fpu_denorm_underflow_inexact);
2854
2855 update_fpsr (sd, status, FPSR_XEV | FPSR_XEI | FPSR_XEO | FPSR_XEU, 0);
2856
2857 sim_fpu_to32 (&GR[reg3], &ans);
2858 TRACE_FP_RESULT_FPU1 (&ans);
2859 }
2860
2861 // MAXF.D
2862 rrrr,0111111,RRRR,0 + wwww,010001111000:F_I:::maxf_d
2863 *v850e2v3
2864 *v850e3v5
2865 "maxf.d r<reg1e>, r<reg2e>, r<reg3e>"
2866 {
2867 sim_fpu ans, wop1, wop2;
2868
2869 sim_fpu_232to (&wop1, GR[reg1e+1], GR[reg1e]);
2870 sim_fpu_232to (&wop2, GR[reg2e+1], GR[reg2e]);
2871 TRACE_FP_INPUT_FPU2 (&wop1, &wop2);
2872
2873 if (sim_fpu_is_nan(&wop1) || sim_fpu_is_nan(&wop2))
2874 {
2875 if (FPSR & FPSR_XEV)
2876 {
2877 SignalExceptionFPE(sd, 1);
2878 }
2879 else
2880 {
2881 ans = sim_fpu_qnan;
2882 }
2883 }
2884 else if (FPSR & FPSR_FS
2885 && ((sim_fpu_is_zero (&wop1) || sim_fpu_is_denorm (&wop1))
2886 && (sim_fpu_is_zero (&wop2) || sim_fpu_is_denorm (&wop2))))
2887 {
2888 ans = sim_fpu_zero;
2889 }
2890 else
2891 {
2892 sim_fpu_max (&ans, &wop1, &wop2);
2893 }
2894
2895 sim_fpu_to232 (&GR[reg3e+1], &GR[reg3e], &ans);
2896 TRACE_FP_RESULT_FPU1 (&ans);
2897 }
2898
2899 // MAXF.S
2900 rrrrr,111111,RRRRR + wwwww,10001101000:F_I:::maxf_s
2901 *v850e2v3
2902 *v850e3v5
2903 "maxf.s r<reg1>, r<reg2>, r<reg3>"
2904 {
2905 sim_fpu ans, wop1, wop2;
2906
2907 sim_fpu_32to (&wop1, GR[reg1]);
2908 sim_fpu_32to (&wop2, GR[reg2]);
2909 TRACE_FP_INPUT_FPU2 (&wop1, &wop2);
2910
2911 if (sim_fpu_is_nan(&wop1) || sim_fpu_is_nan(&wop2))
2912 {
2913 if (FPSR & FPSR_XEV)
2914 {
2915 SignalExceptionFPE(sd, 0);
2916 }
2917 else
2918 {
2919 ans = sim_fpu_qnan;
2920 }
2921 }
2922 else if ((FPSR & FPSR_FS)
2923 && ((sim_fpu_is_zero (&wop1) || sim_fpu_is_denorm (&wop1))
2924 && (sim_fpu_is_zero (&wop2)|| sim_fpu_is_denorm (&wop2))))
2925 {
2926 ans = sim_fpu_zero;
2927 }
2928 else
2929 {
2930 sim_fpu_max (&ans, &wop1, &wop2);
2931 }
2932
2933 sim_fpu_to32 (&GR[reg3], &ans);
2934 TRACE_FP_RESULT_FPU1 (&ans);
2935 }
2936
2937 // MINF.D
2938 rrrr,0111111,RRRR,0 + wwww,010001111010:F_I:::minf_d
2939 *v850e2v3
2940 *v850e3v5
2941 "minf.d r<reg1e>, r<reg2e>, r<reg3e>"
2942 {
2943 sim_fpu ans, wop1, wop2;
2944
2945 sim_fpu_232to (&wop1, GR[reg1e+1], GR[reg1e]);
2946 sim_fpu_232to (&wop2, GR[reg2e+1], GR[reg2e]);
2947 TRACE_FP_INPUT_FPU2 (&wop1, &wop2);
2948
2949 if (sim_fpu_is_nan(&wop1) || sim_fpu_is_nan(&wop2))
2950 {
2951 if (FPSR & FPSR_XEV)
2952 {
2953 SignalExceptionFPE(sd, 1);
2954 }
2955 else
2956 {
2957 ans = sim_fpu_qnan;
2958 }
2959 }
2960 else if (FPSR & FPSR_FS
2961 && ((sim_fpu_is_zero (&wop1) || sim_fpu_is_denorm (&wop1))
2962 && (sim_fpu_is_zero (&wop2) || sim_fpu_is_denorm (&wop2))))
2963 {
2964 ans = sim_fpu_zero;
2965 }
2966 else
2967 {
2968 sim_fpu_min (&ans, &wop1, &wop2);
2969 }
2970
2971 sim_fpu_to232 (&GR[reg3e+1], &GR[reg3e], &ans);
2972 TRACE_FP_RESULT_FPU1 (&ans);
2973 }
2974
2975 // MINF.S
2976 rrrrr,111111,RRRRR + wwwww,10001101010:F_I:::minf_s
2977 *v850e2v3
2978 *v850e3v5
2979 "minf.s r<reg1>, r<reg2>, r<reg3>"
2980 {
2981 sim_fpu ans, wop1, wop2;
2982
2983 sim_fpu_32to (&wop1, GR[reg1]);
2984 sim_fpu_32to (&wop2, GR[reg2]);
2985 TRACE_FP_INPUT_FPU2 (&wop1, &wop2);
2986
2987 if (sim_fpu_is_nan(&wop1) || sim_fpu_is_nan(&wop2))
2988 {
2989 if (FPSR & FPSR_XEV)
2990 {
2991 SignalExceptionFPE(sd, 0);
2992 }
2993 else
2994 {
2995 ans = sim_fpu_qnan;
2996 }
2997 }
2998 else if (FPSR & FPSR_FS
2999 && ((sim_fpu_is_zero (&wop1) || sim_fpu_is_denorm (&wop1))
3000 && (sim_fpu_is_zero (&wop2) || sim_fpu_is_denorm (&wop2))))
3001 {
3002 ans = sim_fpu_zero;
3003 }
3004 else
3005 {
3006 sim_fpu_min (&ans, &wop1, &wop2);
3007 }
3008
3009 sim_fpu_to32 (&GR[reg3], &ans);
3010 TRACE_FP_RESULT_FPU1 (&ans);
3011 }
3012
3013 // MSUBF.S
3014 rrrrr,111111,RRRRR + wwwww,101,W,01,WWWW,0:F_I:::msubf_s
3015 *v850e2v3
3016 "msubf.s r<reg1>, r<reg2>, r<reg3>, r<reg4>"
3017 {
3018 sim_fpu ans, wop1, wop2, wop3;
3019 sim_fpu_status status;
3020
3021 sim_fpu_32to (&wop1, GR[reg1]);
3022 sim_fpu_32to (&wop2, GR[reg2]);
3023 sim_fpu_32to (&wop3, GR[reg3]);
3024 TRACE_FP_INPUT_FPU3 (&wop1, &wop2, &wop3);
3025
3026 status = sim_fpu_mul (&ans, &wop1, &wop2);
3027 status |= sim_fpu_round_64 (&ans, FPSR_GET_ROUND(), sim_fpu_denorm_underflow_inexact);
3028 wop1 = ans;
3029 status |= sim_fpu_sub (&ans, &wop1, &wop3);
3030 status |= sim_fpu_round_64 (&ans, FPSR_GET_ROUND(), sim_fpu_denorm_underflow_inexact);
3031
3032 update_fpsr (sd, status, FPSR_XEV | FPSR_XEI | FPSR_XEO | FPSR_XEU, 0);
3033
3034 sim_fpu_to32 (&GR[reg4], &ans);
3035 TRACE_FP_RESULT_FPU1 (&ans);
3036 }
3037
3038 // FMSF.S
3039 rrrrr,111111,RRRRR + wwwww,10011100010:F_I:::fmsf_s
3040 *v850e3v5
3041 "fmsf.s r<reg1>, r<reg2>, r<reg3>"
3042 {
3043 sim_fpu ans, wop1, wop2, wop3;
3044 sim_fpu_status status;
3045
3046 sim_fpu_32to (&wop1, GR[reg1]);
3047 sim_fpu_32to (&wop2, GR[reg2]);
3048 sim_fpu_32to (&wop3, GR[reg3]);
3049 TRACE_FP_INPUT_FPU3 (&wop1, &wop2, &wop3);
3050
3051 status = sim_fpu_mul (&ans, &wop1, &wop2);
3052 status |= sim_fpu_round_64 (&ans, FPSR_GET_ROUND(), sim_fpu_denorm_underflow_inexact);
3053 wop1 = ans;
3054 status |= sim_fpu_sub (&ans, &wop1, &wop3);
3055 status |= sim_fpu_round_64 (&ans, FPSR_GET_ROUND(), sim_fpu_denorm_underflow_inexact);
3056
3057 update_fpsr (sd, status, FPSR_XEV | FPSR_XEI | FPSR_XEO | FPSR_XEU, 0);
3058
3059 sim_fpu_to32 (&GR[reg3], &ans);
3060 TRACE_FP_RESULT_FPU1 (&ans);
3061 }
3062
3063 // MULF.D
3064 rrrr,0111111,RRRR,0 + wwww,010001110100:F_I:::mulf_d
3065 *v850e2v3
3066 *v850e3v5
3067 "mulf.d r<reg1e>, r<reg2e>, r<reg3e>"
3068 {
3069 sim_fpu ans, wop1, wop2;
3070 sim_fpu_status status;
3071
3072 sim_fpu_232to (&wop1, GR[reg1e+1], GR[reg1e]);
3073 sim_fpu_232to (&wop2, GR[reg2e+1], GR[reg2e]);
3074 TRACE_FP_INPUT_FPU2 (&wop1, &wop2);
3075
3076 status = sim_fpu_mul (&ans, &wop1, &wop2);
3077 status |= sim_fpu_round_64 (&ans, FPSR_GET_ROUND(), sim_fpu_denorm_underflow_inexact);
3078
3079 update_fpsr (sd, status, FPSR_XEV | FPSR_XEI | FPSR_XEO | FPSR_XEU, 1);
3080
3081 sim_fpu_to232 (&GR[reg3e+1], &GR[reg3e], &ans);
3082 TRACE_FP_RESULT_FPU1 (&ans);
3083 }
3084
3085 // MULF.S
3086 rrrrr,111111,RRRRR + wwwww,10001100100:F_I:::mulf_s
3087 *v850e2v3
3088 *v850e3v5
3089 "mulf.s r<reg1>, r<reg2>, r<reg3>"
3090 {
3091 sim_fpu ans, wop1, wop2;
3092 sim_fpu_status status;
3093
3094 sim_fpu_32to (&wop1, GR[reg1]);
3095 sim_fpu_32to (&wop2, GR[reg2]);
3096 TRACE_FP_INPUT_FPU2 (&wop1, &wop2);
3097
3098 status = sim_fpu_mul (&ans, &wop1, &wop2);
3099 status |= sim_fpu_round_32 (&ans, FPSR_GET_ROUND(), sim_fpu_denorm_underflow_inexact);
3100
3101 update_fpsr (sd, status, FPSR_XEV | FPSR_XEI | FPSR_XEO | FPSR_XEU, 0);
3102
3103 sim_fpu_to32 (&GR[reg3], &ans);
3104 TRACE_FP_RESULT_FPU1 (&ans);
3105 }
3106
3107 // NEGF.D
3108 rrrr,011111100001 + wwww,010001011000:F_I:::negf_d
3109 *v850e2v3
3110 *v850e3v5
3111 "negf.d r<reg2e>, r<reg3e>"
3112 {
3113 sim_fpu ans, wop;
3114 sim_fpu_status status;
3115
3116 sim_fpu_232to (&wop, GR[reg2e+1], GR[reg2e]);
3117 TRACE_FP_INPUT_FPU1 (&wop);
3118
3119 status = sim_fpu_neg (&ans, &wop);
3120
3121 check_invalid_snan(sd, status, 1);
3122
3123 sim_fpu_to232 (&GR[reg3e+1], &GR[reg3e], &ans);
3124 TRACE_FP_RESULT_FPU1 (&ans);
3125 }
3126
3127 // NEGF.S
3128 rrrrr,11111100001 + wwwww,10001001000:F_I:::negf_s
3129 *v850e2v3
3130 *v850e3v5
3131 "negf.s r<reg2>, r<reg3>"
3132 {
3133 sim_fpu ans, wop;
3134 sim_fpu_status status;
3135
3136 sim_fpu_32to (&wop, GR[reg2]);
3137 TRACE_FP_INPUT_FPU1 (&wop);
3138
3139 status = sim_fpu_neg (&ans, &wop);
3140
3141 check_invalid_snan(sd, status, 0);
3142
3143 sim_fpu_to32 (&GR[reg3], &ans);
3144 TRACE_FP_RESULT_FPU1 (&ans);
3145 }
3146
3147 // NMADDF.S
3148 rrrrr,111111,RRRRR + wwwww,101,W,10,WWWW,0:F_I:::nmaddf_s
3149 *v850e2v3
3150 "nmaddf.s r<reg1>, r<reg2>, r<reg3>, r<reg4>"
3151 {
3152 sim_fpu ans, wop1, wop2, wop3;
3153 sim_fpu_status status;
3154
3155 sim_fpu_32to (&wop1, GR[reg1]);
3156 sim_fpu_32to (&wop2, GR[reg2]);
3157 sim_fpu_32to (&wop3, GR[reg3]);
3158 TRACE_FP_INPUT_FPU3 (&wop1, &wop2, &wop3);
3159
3160 status = sim_fpu_mul (&ans, &wop1, &wop2);
3161 wop1 = ans;
3162 status |= sim_fpu_add (&ans, &wop1, &wop3);
3163 status |= sim_fpu_round_64 (&ans, FPSR_GET_ROUND(), sim_fpu_denorm_underflow_inexact);
3164 wop1 = ans;
3165 status |= sim_fpu_neg (&ans, &wop1);
3166
3167 update_fpsr (sd, status, FPSR_XEV | FPSR_XEI | FPSR_XEO | FPSR_XEU, 0);
3168
3169 sim_fpu_to32 (&GR[reg4], &ans);
3170 TRACE_FP_RESULT_FPU1 (&ans);
3171 }
3172
3173 // FNMAF.S
3174 rrrrr,111111,RRRRR + wwwww,10011100100:F_I:::fnmaf_s
3175 *v850e3v5
3176 "fnmaf.s r<reg1>, r<reg2>, r<reg3>"
3177 {
3178 sim_fpu ans, wop1, wop2, wop3;
3179 sim_fpu_status status;
3180
3181 sim_fpu_32to (&wop1, GR[reg1]);
3182 sim_fpu_32to (&wop2, GR[reg2]);
3183 sim_fpu_32to (&wop3, GR[reg3]);
3184 TRACE_FP_INPUT_FPU3 (&wop1, &wop2, &wop3);
3185
3186 status = sim_fpu_mul (&ans, &wop1, &wop2);
3187 wop1 = ans;
3188 status |= sim_fpu_add (&ans, &wop1, &wop3);
3189 status |= sim_fpu_round_64 (&ans, FPSR_GET_ROUND(), sim_fpu_denorm_underflow_inexact);
3190 wop1 = ans;
3191 status |= sim_fpu_neg (&ans, &wop1);
3192
3193 update_fpsr (sd, status, FPSR_XEV | FPSR_XEI | FPSR_XEO | FPSR_XEU, 0);
3194
3195 sim_fpu_to32 (&GR[reg3], &ans);
3196 TRACE_FP_RESULT_FPU1 (&ans);
3197 }
3198
3199 // NMSUBF.S
3200 rrrrr,111111,RRRRR + wwwww,101,W,11,WWWW,0:F_I:::nmsubf_s
3201 *v850e2v3
3202 "nmsubf.s r<reg1>, r<reg2>, r<reg3>, r<reg4>"
3203 {
3204 sim_fpu ans, wop1, wop2, wop3;
3205 sim_fpu_status status;
3206
3207 sim_fpu_32to (&wop1, GR[reg1]);
3208 sim_fpu_32to (&wop2, GR[reg2]);
3209 sim_fpu_32to (&wop3, GR[reg3]);
3210 TRACE_FP_INPUT_FPU3 (&wop1, &wop2, &wop3);
3211
3212 status = sim_fpu_mul (&ans, &wop1, &wop2);
3213 status |= sim_fpu_round_64 (&ans, FPSR_GET_ROUND(), sim_fpu_denorm_underflow_inexact);
3214 wop1 = ans;
3215 status |= sim_fpu_sub (&ans, &wop1, &wop3);
3216 status |= sim_fpu_round_64 (&ans, FPSR_GET_ROUND(), sim_fpu_denorm_underflow_inexact);
3217 wop1 = ans;
3218 status |= sim_fpu_neg (&ans, &wop1);
3219
3220 update_fpsr (sd, status, FPSR_XEV | FPSR_XEI | FPSR_XEO | FPSR_XEU, 0);
3221
3222 sim_fpu_to32 (&GR[reg4], &ans);
3223 TRACE_FP_RESULT_FPU1 (&ans);
3224 }
3225
3226 // FNMSF.S
3227 rrrrr,111111,RRRRR + wwwww,10011100110:F_I:::fnmsf_s
3228 *v850e3v5
3229 "fnmsf.s r<reg1>, r<reg2>, r<reg3>"
3230 {
3231 sim_fpu ans, wop1, wop2, wop3;
3232 sim_fpu_status status;
3233
3234 sim_fpu_32to (&wop1, GR[reg1]);
3235 sim_fpu_32to (&wop2, GR[reg2]);
3236 sim_fpu_32to (&wop3, GR[reg3]);
3237 TRACE_FP_INPUT_FPU3 (&wop1, &wop2, &wop3);
3238
3239 status = sim_fpu_mul (&ans, &wop1, &wop2);
3240 status |= sim_fpu_round_64 (&ans, FPSR_GET_ROUND(), sim_fpu_denorm_underflow_inexact);
3241 wop1 = ans;
3242 status |= sim_fpu_sub (&ans, &wop1, &wop3);
3243 status |= sim_fpu_round_64 (&ans, FPSR_GET_ROUND(), sim_fpu_denorm_underflow_inexact);
3244 wop1 = ans;
3245 status |= sim_fpu_neg (&ans, &wop1);
3246
3247 update_fpsr (sd, status, FPSR_XEV | FPSR_XEI | FPSR_XEO | FPSR_XEU, 0);
3248
3249 sim_fpu_to32 (&GR[reg3], &ans);
3250 TRACE_FP_RESULT_FPU1 (&ans);
3251 }
3252
3253 // RECIPF.D
3254 rrrr,011111100001 + wwww,010001011110:F_I:::recipf.d
3255 *v850e2v3
3256 *v850e3v5
3257 "recipf.d r<reg2e>, r<reg3e>"
3258 {
3259 sim_fpu ans, wop;
3260 sim_fpu_status status;
3261
3262 sim_fpu_232to (&wop, GR[reg2e+1], GR[reg2e]);
3263 TRACE_FP_INPUT_FPU1 (&wop);
3264
3265 status = sim_fpu_div (&ans, &sim_fpu_one, &wop);
3266 status |= sim_fpu_round_64 (&ans, FPSR_GET_ROUND(), sim_fpu_denorm_underflow_inexact);
3267
3268 update_fpsr (sd, status, FPSR_XEV | FPSR_XEZ | FPSR_XEI | FPSR_XEO | FPSR_XEU, 1);
3269
3270 sim_fpu_to232 (&GR[reg3e+1], &GR[reg3e], &ans);
3271 TRACE_FP_RESULT_FPU1 (&ans);
3272 }
3273
3274 // RECIPF.S
3275 rrrrr,11111100001 + wwwww,10001001110:F_I:::recipf.s
3276 *v850e2v3
3277 *v850e3v5
3278 "recipf.s r<reg2>, r<reg3>"
3279 {
3280 sim_fpu ans, wop;
3281 sim_fpu_status status;
3282
3283 sim_fpu_32to (&wop, GR[reg2]);
3284 TRACE_FP_INPUT_FPU1 (&wop);
3285
3286 status = sim_fpu_div (&ans, &sim_fpu_one, &wop);
3287 status |= sim_fpu_round_64 (&ans, FPSR_GET_ROUND(), sim_fpu_denorm_underflow_inexact);
3288
3289 update_fpsr (sd, status, FPSR_XEV | FPSR_XEZ | FPSR_XEI | FPSR_XEO | FPSR_XEU, 0);
3290
3291 sim_fpu_to32 (&GR[reg3], &ans);
3292 TRACE_FP_RESULT_FPU1 (&ans);
3293 }
3294
3295 // RSQRTF.D
3296 rrrr,011111100010 + wwww,010001011110:F_I:::rsqrtf.d
3297 *v850e2v3
3298 *v850e3v5
3299 "rsqrtf.d r<reg2e>, r<reg3e>"
3300 {
3301 sim_fpu ans, wop;
3302 sim_fpu_status status;
3303
3304 sim_fpu_232to (&wop, GR[reg2e+1], GR[reg2e]);
3305 TRACE_FP_INPUT_FPU1 (&wop);
3306
3307 status = sim_fpu_sqrt (&ans, &wop);
3308 status |= sim_fpu_round_64 (&ans, FPSR_GET_ROUND(), sim_fpu_denorm_underflow_inexact);
3309 wop = ans;
3310 status = sim_fpu_div (&ans, &sim_fpu_one, &wop);
3311 status |= sim_fpu_round_64 (&ans, FPSR_GET_ROUND(), sim_fpu_denorm_underflow_inexact);
3312
3313 update_fpsr (sd, status, FPSR_XEV | FPSR_XEZ | FPSR_XEI | FPSR_XEO | FPSR_XEU, 1);
3314
3315 sim_fpu_to232 (&GR[reg3e+1], &GR[reg3e], &ans);
3316 TRACE_FP_RESULT_FPU1 (&ans);
3317 }
3318
3319 // RSQRTF.S
3320 rrrrr,11111100010 + wwwww,10001001110:F_I:::rsqrtf.s
3321 *v850e2v3
3322 *v850e3v5
3323 "rsqrtf.s r<reg2>, r<reg3>"
3324 {
3325 sim_fpu ans, wop;
3326 sim_fpu_status status;
3327
3328 sim_fpu_32to (&wop, GR[reg2]);
3329 TRACE_FP_INPUT_FPU1 (&wop);
3330
3331 status = sim_fpu_sqrt (&ans, &wop);
3332 status |= sim_fpu_round_32 (&ans, FPSR_GET_ROUND(), sim_fpu_denorm_underflow_inexact);
3333 wop = ans;
3334 status = sim_fpu_div (&ans, &sim_fpu_one, &wop);
3335 status |= sim_fpu_round_32 (&ans, FPSR_GET_ROUND(), sim_fpu_denorm_underflow_inexact);
3336
3337 update_fpsr (sd, status, FPSR_XEV | FPSR_XEZ | FPSR_XEI | FPSR_XEO | FPSR_XEU, 0);
3338
3339 sim_fpu_to32 (&GR[reg3], &ans);
3340 TRACE_FP_RESULT_FPU1 (&ans);
3341 }
3342
3343 // SQRTF.D
3344 rrrr,011111100000 + wwww,010001011110:F_I:::sqrtf.d
3345 *v850e2v3
3346 *v850e3v5
3347 "sqrtf.d r<reg2e>, r<reg3e>"
3348 {
3349 sim_fpu ans, wop;
3350 sim_fpu_status status;
3351
3352 sim_fpu_232to (&wop, GR[reg2e+1], GR[reg2e]);
3353 TRACE_FP_INPUT_FPU1 (&wop);
3354
3355 status = sim_fpu_sqrt (&ans, &wop);
3356 status |= sim_fpu_round_64 (&ans, FPSR_GET_ROUND(), sim_fpu_denorm_underflow_inexact);
3357
3358 update_fpsr (sd, status, FPSR_XEV | FPSR_XEI, 1);
3359
3360 sim_fpu_to232 (&GR[reg3e+1], &GR[reg3e], &ans);
3361 TRACE_FP_RESULT_FPU1 (&ans);
3362 }
3363
3364 // SQRTF.S
3365 rrrrr,11111100000 + wwwww,10001001110:F_I:::sqrtf.s
3366 *v850e2v3
3367 *v850e3v5
3368 "sqrtf.s r<reg2>, r<reg3>"
3369 {
3370 sim_fpu ans, wop;
3371 sim_fpu_status status;
3372
3373 sim_fpu_32to (&wop, GR[reg2]);
3374 TRACE_FP_INPUT_FPU1 (&wop);
3375
3376 status = sim_fpu_sqrt (&ans, &wop);
3377 status |= sim_fpu_round_32 (&ans, FPSR_GET_ROUND(), sim_fpu_denorm_underflow_inexact);
3378
3379 update_fpsr (sd, status, FPSR_XEV | FPSR_XEI, 0);
3380
3381 sim_fpu_to32 (&GR[reg3], &ans);
3382 TRACE_FP_RESULT_FPU1 (&ans);
3383 }
3384
3385 // SUBF.D
3386 rrrr,0111111,RRRR,0 + wwww,010001110010:F_I:::subf.d
3387 *v850e2v3
3388 *v850e3v5
3389 "subf.d r<reg1e>, r<reg2e>, r<reg3e>"
3390 {
3391 sim_fpu ans, wop1, wop2;
3392 sim_fpu_status status;
3393
3394 sim_fpu_232to (&wop1, GR[reg1e+1], GR[reg1e]);
3395 sim_fpu_232to (&wop2, GR[reg2e+1], GR[reg2e]);
3396 TRACE_FP_INPUT_FPU2 (&wop1, &wop2);
3397
3398 status = sim_fpu_sub (&ans, &wop2, &wop1);
3399 status |= sim_fpu_round_64 (&ans, FPSR_GET_ROUND(), sim_fpu_denorm_underflow_inexact);
3400
3401 update_fpsr (sd, status, FPSR_XEV | FPSR_XEI | FPSR_XEO | FPSR_XEU, 1);
3402
3403 sim_fpu_to232 (&GR[reg3e+1], &GR[reg3e], &ans);
3404 TRACE_FP_RESULT_FPU1 (&ans);
3405 }
3406
3407 // SUBF.S
3408 rrrrr,111111,RRRRR + wwwww,10001100010:F_I:::subf.s
3409 *v850e2v3
3410 *v850e3v5
3411 "subf.s r<reg1>, r<reg2>, r<reg3>"
3412 {
3413 sim_fpu ans, wop1, wop2;
3414 sim_fpu_status status;
3415
3416 sim_fpu_32to (&wop1, GR[reg1]);
3417 sim_fpu_32to (&wop2, GR[reg2]);
3418 TRACE_FP_INPUT_FPU2 (&wop1, &wop2);
3419
3420 status = sim_fpu_sub (&ans, &wop2, &wop1);
3421 status |= sim_fpu_round_32 (&ans, FPSR_GET_ROUND(), sim_fpu_denorm_underflow_inexact);
3422
3423 update_fpsr (sd, status, FPSR_XEV | FPSR_XEI | FPSR_XEO | FPSR_XEU, 0);
3424
3425 sim_fpu_to32 (&GR[reg3], &ans);
3426 TRACE_FP_RESULT_FPU1 (&ans);
3427 }
3428
3429 // TRFSR
3430 0000011111100000 + 000001000000,bbb,0:F_I:::trfsr
3431 *v850e2v3
3432 *v850e3v5
3433 "trfsr":(bbb == 0)
3434 "trfsr <bbb>"
3435 {
3436 TRACE_ALU_INPUT1 (GET_FPCC());
3437
3438 if (TEST_FPCC (bbb))
3439 PSW |= PSW_Z;
3440 else
3441 PSW &= ~PSW_Z;
3442
3443 TRACE_ALU_RESULT1 (PSW);
3444 }
3445
3446 // TRNCF.DL
3447 rrrr,011111100001 + wwww,010001010100:F_I:::trncf_dl
3448 *v850e2v3
3449 *v850e3v5
3450 "trncf.dl r<reg2e>, r<reg3e>"
3451 {
3452 int64_t ans;
3453 sim_fpu wop;
3454 sim_fpu_status status;
3455
3456 sim_fpu_232to (&wop, GR[reg2e+1], GR[reg2e]);
3457 TRACE_FP_INPUT_FPU1 (&wop);
3458
3459 status = sim_fpu_to64i (&ans, &wop, sim_fpu_round_zero);
3460
3461 check_cvt_fi(sd, status, 1);
3462
3463 GR[reg3e] = ans;
3464 GR[reg3e+1] = ans>>32L;
3465 TRACE_FP_RESULT_WORD2 (GR[reg3e], GR[reg3e+1]);
3466 }
3467
3468 // TRNCF.DUL
3469 rrrr,011111110001 + wwww,010001010100:F_I:::trncf_dul
3470 *v850e2v3
3471 *v850e3v5
3472 "trncf.dul r<reg2e>, r<reg3e>"
3473 {
3474 uint64_t ans;
3475 sim_fpu wop;
3476 sim_fpu_status status;
3477
3478 sim_fpu_232to (&wop, GR[reg2e+1], GR[reg2e]);
3479 TRACE_FP_INPUT_FPU1 (&wop);
3480
3481 status = sim_fpu_to64u (&ans, &wop, sim_fpu_round_zero);
3482
3483 check_cvt_fi(sd, status, 1);
3484
3485 GR[reg3e] = ans;
3486 GR[reg3e+1] = ans>>32L;
3487 TRACE_FP_RESULT_WORD2 (GR[reg3e], GR[reg3e+1]);
3488 }
3489
3490 // TRNCF.DW
3491 rrrr,011111100001 + wwwww,10001010000:F_I:::trncf_dw
3492 *v850e2v3
3493 *v850e3v5
3494 "trncf.dw r<reg2e>, r<reg3>"
3495 {
3496 int32_t ans;
3497 sim_fpu wop;
3498 sim_fpu_status status;
3499
3500 sim_fpu_232to (&wop, GR[reg2e+1], GR[reg2e]);
3501 TRACE_FP_INPUT_FPU1 (&wop);
3502
3503 status = sim_fpu_to32i (&ans, &wop, sim_fpu_round_zero);
3504
3505 check_cvt_fi(sd, status, 1);
3506
3507 GR[reg3] = ans;
3508 TRACE_FP_RESULT_WORD1 (ans);
3509 }
3510
3511 // TRNCF.DUW
3512 rrrr,011111110001 + wwwww,10001010000:F_I:::trncf_duw
3513 *v850e2v3
3514 *v850e3v5
3515 "trncf.duw r<reg2e>, r<reg3>"
3516 {
3517 uint32_t ans;
3518 sim_fpu wop;
3519 sim_fpu_status status;
3520
3521 sim_fpu_232to (&wop, GR[reg2e+1], GR[reg2e]);
3522 TRACE_FP_INPUT_FPU1 (&wop);
3523
3524 status = sim_fpu_to32u (&ans, &wop, sim_fpu_round_zero);
3525
3526 check_cvt_fi(sd, status, 1);
3527
3528 GR[reg3] = ans;
3529 TRACE_FP_RESULT_WORD1 (ans);
3530 }
3531
3532 // TRNCF.SL
3533 rrrrr,11111100001 + wwww,010001000100:F_I:::trncf_sl
3534 *v850e2v3
3535 *v850e3v5
3536 "trncf.sl r<reg2>, r<reg3e>"
3537 {
3538 int64_t ans;
3539 sim_fpu wop;
3540 sim_fpu_status status;
3541
3542 sim_fpu_32to (&wop, GR[reg2]);
3543 TRACE_FP_INPUT_FPU1 (&wop);
3544
3545 status = sim_fpu_to64i (&ans, &wop, sim_fpu_round_zero);
3546
3547 GR[reg3e] = ans;
3548 GR[reg3e+1] = ans >> 32L;
3549 TRACE_FP_RESULT_WORD2 (GR[reg3e], GR[reg3e+1]);
3550 }
3551
3552 // TRNCF.SUL
3553 rrrrr,11111110001 + wwww,010001000100:F_I:::trncf_sul
3554 *v850e2v3
3555 *v850e3v5
3556 "trncf.sul r<reg2>, r<reg3e>"
3557 {
3558 uint64_t ans;
3559 sim_fpu wop;
3560 sim_fpu_status status;
3561
3562 sim_fpu_32to (&wop, GR[reg2]);
3563 TRACE_FP_INPUT_FPU1 (&wop);
3564
3565 status = sim_fpu_to64u (&ans, &wop, sim_fpu_round_zero);
3566
3567 GR[reg3e] = ans;
3568 GR[reg3e+1] = ans >> 32L;
3569 TRACE_FP_RESULT_WORD2 (GR[reg3e], GR[reg3e+1]);
3570 }
3571
3572 // TRNCF.SW
3573 rrrrr,11111100001 + wwwww,10001000000:F_I:::trncf_sw
3574 *v850e2v3
3575 *v850e3v5
3576 "trncf.sw r<reg2>, r<reg3>"
3577 {
3578 int32_t ans;
3579 sim_fpu wop;
3580 sim_fpu_status status;
3581
3582 sim_fpu_32to (&wop, GR[reg2]);
3583 TRACE_FP_INPUT_FPU1 (&wop);
3584
3585 status = sim_fpu_to32i (&ans, &wop, sim_fpu_round_zero);
3586
3587 check_cvt_fi(sd, status, 0);
3588
3589 GR[reg3] = ans;
3590 TRACE_FP_RESULT_WORD1 (ans);
3591 }
3592
3593 // TRNCF.SUW
3594 rrrrr,11111110001 + wwwww,10001000000:F_I:::trncf_suw
3595 *v850e2v3
3596 *v850e3v5
3597 "trncf.suw r<reg2>, r<reg3>"
3598 {
3599 uint32_t ans;
3600 sim_fpu wop;
3601 sim_fpu_status status;
3602
3603 sim_fpu_32to (&wop, GR[reg2]);
3604 TRACE_FP_INPUT_FPU1 (&wop);
3605
3606 status = sim_fpu_to32u (&ans, &wop, sim_fpu_round_zero);
3607
3608 check_cvt_fi(sd, status, 0);
3609
3610 GR[reg3] = ans;
3611 TRACE_FP_RESULT_WORD1 (ans);
3612 }
3613
3614 // ROTL
3615 rrrrr,111111,iiiii+wwwww,00011000100:VII:::rotl_imm
3616 *v850e3v5
3617 "rotl imm5, r<reg2>, r<reg3>"
3618 {
3619 TRACE_ALU_INPUT1 (GR[reg2]);
3620 v850_rotl (sd, imm5, GR[reg2], & GR[reg3]);
3621 TRACE_ALU_RESULT1 (GR[reg3]);
3622 }
3623
3624 rrrrr,111111,RRRRR+wwwww,00011000110:VII:::rotl
3625 *v850e3v5
3626 "rotl r<reg1>, r<reg2>, r<reg3>"
3627 {
3628 TRACE_ALU_INPUT2 (GR[reg1], GR[reg2]);
3629 v850_rotl (sd, GR[reg1], GR[reg2], & GR[reg3]);
3630 TRACE_ALU_RESULT1 (GR[reg3]);
3631 }
3632
3633 // BINS
3634 rrrrr,111111,RRRRR+bbbb,B,0001001,BBB,0:IX:::bins_top
3635 *v850e3v5
3636 "bins r<reg1>, <bit13> + 16, <bit4> - <bit13> + 17, r<reg2>"
3637 {
3638 TRACE_ALU_INPUT1 (GR[reg1]);
3639 v850_bins (sd, GR[reg1], bit13 + 16, bit4 + 16, & GR[reg2]);
3640 TRACE_ALU_RESULT1 (GR[reg2]);
3641 }
3642
3643 rrrrr,111111,RRRRR+bbbb,B,0001011,BBB,0:IX:::bins_middle
3644 *v850e3v5
3645 "bins r<reg1>, <bit13>, <bit4> - <bit13> + 17, r<reg2>"
3646 {
3647 TRACE_ALU_INPUT1 (GR[reg1]);
3648 v850_bins (sd, GR[reg1], bit13, bit4 + 16, & GR[reg2]);
3649 TRACE_ALU_RESULT1 (GR[reg2]);
3650 }
3651
3652 rrrrr,111111,RRRRR+bbbb,B,0001101,BBB,0:IX:::bins_bottom
3653 *v850e3v5
3654 "bins r<reg1>, <bit13>, <bit4> - <bit13> + 1, r<reg2>"
3655 {
3656 TRACE_ALU_INPUT1 (GR[reg1]);
3657 v850_bins (sd, GR[reg1], bit13, bit4, & GR[reg2]);
3658 TRACE_ALU_RESULT1 (GR[reg2]);
3659 }
3660
3661 vvvvv,11111100100+xxxxx,11001111110:C:::cnvq15q30
3662 *v850e3v5
3663 "cnvq15q30 v<vreg2>, v<vreg3>"
3664 {
3665 reg64_t v;
3666
3667 TRACE_ALU_INPUT1 (VR[vreg2]);
3668
3669 if (VR[vreg2] & (1 << 15))
3670 v = 0x0001ffffffff0000 | VR[vreg2];
3671 else
3672 v = VR[vreg2];
3673 VR[vreg3] = v << 15;
3674
3675 TRACE_ALU_RESULT1 (VR[vreg3]);
3676 }
3677
3678 vvvvv,11111100110+xxxxx,11001111110:C:::cnvq30q15
3679 *v850e3v5
3680 "cnvq30q15 v<vreg2>, v<vreg3>"
3681 {
3682 reg64_t v;
3683
3684 TRACE_ALU_INPUT1 (VR[vreg2]);
3685
3686 v = ROUND_Q62_Q15 (VR[vreg2]);
3687 SAT16 (v);
3688 VR[vreg3] &= 0xffffffffffff0000UL;
3689 v &= 0xffffUL;
3690 VR[vreg3] |= v;
3691
3692 TRACE_ALU_RESULT1 (VR[vreg3]);
3693 }
3694
3695 vvvvv,11111100101+xxxxx,11001111110:C:::cnvq31q62
3696 *v850e3v5
3697 "cnvq31q62 v<vreg2>, v<vreg3>"
3698 {
3699 reg64_t v;
3700
3701 TRACE_ALU_INPUT1 (VR[vreg2]);
3702
3703 if (VR[vreg2] & (1 << 31))
3704 v = 0xffffffff00000000 | VR[vreg2];
3705 else
3706 v = VR[vreg2];
3707 VR[vreg3] = v << 31;
3708
3709 TRACE_ALU_RESULT1 (VR[vreg3]);
3710 }
3711
3712 vvvvv,11111100111+xxxxx,11001111110:C:::cnvq62q31
3713 *v850e3v5
3714 "cnvq62q31 v<vreg2>, v<vreg3>"
3715 {
3716 reg64_t v;
3717
3718 TRACE_ALU_INPUT1 (VR[vreg2]);
3719
3720 v = ROUND_Q62_Q31 (VR[vreg2]);
3721 SAT32 (v);
3722 VR[vreg3] &= 0xffffffff00000000UL;
3723 v &= 0xffffffffUL;
3724 VR[vreg3] |= v;
3725
3726 TRACE_ALU_RESULT1 (VR[vreg3]);
3727 }
3728
3729 vvvvv,111111100,ii+xxxxx,11011011100:C:::dup.h
3730 *v850e3v5
3731 "dup.h <imm2> v<vreg2>, v<vreg3>"
3732 {
3733 reg64_t v;
3734
3735 TRACE_ALU_INPUT1 (VR[vreg2]);
3736 switch (imm2)
3737 {
3738 case 0: v = VR[vreg2] & 0xffff; break;
3739 case 1: v = (VR[vreg2] >> 16) & 0xffff; break;
3740 case 2: v = (VR[vreg2] >> 32) & 0xffff; break;
3741 case 3: v = (VR[vreg2] >> 48) & 0xffff; break;
3742 default:
3743 sim_engine_halt (SD, CPU, NULL, cia, sim_signalled, SIM_SIGILL);
3744 v = 0;
3745 }
3746
3747 VR[vreg3] = v | (v << 16) | (v << 32) | (v << 48);
3748 TRACE_ALU_RESULT1 (VR[vreg3]);
3749 }
3750
3751 vvvvv,1111111100,i+xxxxx,11011011110:C:::dup.w
3752 *v850e3v5
3753 "dup.w <imm1> v<vreg2>, v<vreg3>"
3754 {
3755 reg64_t v;
3756
3757 TRACE_ALU_INPUT1 (VR[vreg2]);
3758 switch (imm1)
3759 {
3760 case 0: v = VR[vreg2] & 0xffffffff; break;
3761 case 1: v = (VR[vreg2] >> 32) & 0xffffffff; break;
3762 default:
3763 sim_engine_halt (SD, CPU, NULL, cia, sim_signalled, SIM_SIGILL);
3764 v = 0;
3765 }
3766
3767 VR[vreg3] = v | (v << 32);
3768 TRACE_ALU_RESULT1 (VR[vreg3]);
3769 }
3770
3771 vvvvv,11111101000+xxxxx,11001111110:C:::expq31
3772 *v850e3v5
3773 "expq31 v<vreg2>, v<vreg3>"
3774 {
3775 int i;
3776 reg64_t v;
3777
3778 TRACE_ALU_INPUT1 (VR[vreg2]);
3779 v = VR[vreg2] & 0xffffffff;
3780 if (v & (1 << 31))
3781 {
3782 if (v == 0x80000000)
3783 i = 31;
3784 else if (v == 0xffffffff)
3785 i = 0;
3786 else
3787 for (i = 31; i; --i)
3788 if ((v & (1 << i)) == 0)
3789 break;
3790 }
3791 else
3792 {
3793 if (v == 0x7fffffff)
3794 i = 31;
3795 else if (v == 0x0)
3796 i = 0;
3797 else
3798 for (i = 31; i; --i)
3799 if (v & (1 << i))
3800 break;
3801 }
3802 VR[vreg3] = 31 - i;
3803 TRACE_ALU_RESULT1 (VR[vreg3]);
3804 }
3805
3806 rrrr,011111100000+0000011011011000:C:::modadd
3807 *v850e3v5
3808 "modadd r<reg2e>"
3809 {
3810 reg_t r;
3811 int32_t inc;
3812 reg_t max;
3813
3814 TRACE_ALU_INPUT1 (GR[reg2e]);
3815 r = GR[reg2e];
3816 inc = r >> 16;
3817 r = r & 0xffff;
3818 max = GR[reg2e + 1];
3819 max &= 0xffff;
3820 r += inc;
3821 if (inc > 0 && r > max)
3822 r = 0;
3823 else if (inc < 0 && r < 0)
3824 r = max;
3825 GR[reg2e] = (r & 0xffff) | (inc << 16);
3826 TRACE_ALU_RESULT1 (GR[reg2e]);
3827 }
3828
3829 vvvvv,11111111000+wwwww,11011011010:C:::mov_dw_to_gr
3830 *v850e3v5
3831 "mov.dw v<vreg2>, r<reg3>"
3832 {
3833 TRACE_ALU_INPUT1 (VR[vreg2]);
3834 GR[reg3] = VR[vreg2] & 0xffffffff;
3835 GR[reg3 + 1] = VR[vreg2] >> 32;
3836 TRACE_ALU_RESULT2 (GR[reg3], GR[reg3 + 1]);
3837 }
3838
3839 rrrrr,11111111100+xxxxx,11011011010:C:::mov_dw_to_vr
3840 *v850e3v5
3841 "mov.dw r<reg2>, v<vreg3>"
3842 {
3843 TRACE_ALU_INPUT2 (GR[reg2], GR[reg2 + 1]);
3844 VR[vreg3] = GR[reg2 + 1];
3845 VR[vreg3] <<= 32;
3846 VR[vreg3] |= GR[reg2];
3847 TRACE_ALU_RESULT1 (VR[vreg3]);
3848 }
3849
3850 vvvvv,111111000,ii+xxxxx,11011011100:C:::mov.h
3851 *v850e3v5
3852 "mov.h <imm2> v<vreg2>, v<vreg3>"
3853 {
3854 reg64_t v = VR[vreg2];
3855 reg64_t mask = 0xffffUL;
3856 int shift;
3857
3858 TRACE_ALU_INPUT1 (VR[vreg2]);
3859
3860 switch (imm2)
3861 {
3862 default:
3863 sim_engine_halt (SD, CPU, NULL, cia, sim_signalled, SIM_SIGILL);
3864 case 0: shift = 0; break;
3865 case 1: shift = 16; break;
3866 case 2: shift = 32; break;
3867 case 3: shift = 48; break;
3868 }
3869
3870 v &= mask;
3871 VR[vreg3] &= ~ (mask << shift);
3872 VR[vreg3] |= (v << shift);
3873
3874 TRACE_ALU_RESULT1 (VR[vreg3]);
3875 }
3876
3877 vvvvv,1111110000,i+xxxxx,11011011010:C:::mov.w.vreg_to_vreg
3878 *v850e3v5
3879 "mov.w <imm1> v<vreg2>, v<vreg3>"
3880 {
3881 reg64_t v = VR[vreg2];
3882 reg64_t mask = 0xffffffffUL;
3883 int shift;
3884
3885 TRACE_ALU_INPUT1 (VR[vreg2]);
3886 switch (imm1)
3887 {
3888 default:
3889 sim_engine_halt (SD, CPU, NULL, cia, sim_signalled, SIM_SIGILL);
3890 case 0: shift = 0; break;
3891 case 1: shift = 32; break;
3892 }
3893
3894 v &= mask;
3895 VR[vreg3] &= ~ (mask << shift);
3896 VR[vreg3] |= (v << shift);
3897
3898 TRACE_ALU_RESULT1 (VR[vreg3]);
3899 }
3900
3901 rrrrr,1111111000,i+xxxxx,11011011010:C:::mov.w.reg_to_vreg
3902 *v850e3v5
3903 "mov.w <imm1> r<reg2>, v<vreg3>"
3904 {
3905 reg64_t v;
3906 reg64_t mask = 0xffffffffUL;
3907 int shift;
3908
3909 TRACE_ALU_INPUT1 (GR[reg2]);
3910 switch (imm1)
3911 {
3912 default:
3913 sim_engine_halt (SD, CPU, NULL, cia, sim_signalled, SIM_SIGILL);
3914 case 0: shift = 0; break;
3915 case 1: shift = 32; break;
3916 }
3917
3918 v = GR[reg2];
3919 VR[vreg3] &= ~ (mask << shift);
3920 VR[vreg3] |= (v << shift);
3921
3922 TRACE_ALU_RESULT1 (VR[vreg3]);
3923 }
3924
3925 vvvvv,1111110100,i+wwwww,11011011010:C:::mov.w.vreg_to_reg
3926 *v850e3v5
3927 "mov.w <imm1> v<vreg2>, r<reg3>"
3928 {
3929 TRACE_ALU_INPUT1 (VR[vreg2]);
3930
3931 switch (imm1)
3932 {
3933 default:
3934 sim_engine_halt (SD, CPU, NULL, cia, sim_signalled, SIM_SIGILL);
3935 case 0:
3936 GR[reg3] = VR[vreg2];
3937 break;
3938 case 1:
3939 GR[reg3] = VR[vreg2] >> 32;
3940 break;
3941 }
3942
3943 TRACE_ALU_RESULT1 (GR[reg3]);
3944 }
3945
3946 vvvvv,111111,VVVVV+xxxxx,11001101010:C:::pki16i32
3947 *v850e3v5
3948 "pki16i32 v<vreg1>, v<vreg2>, v<vreg3>"
3949 {
3950 reg64_t v,t;
3951
3952 TRACE_ALU_INPUT1 (VR[vreg1]);
3953
3954 v = VR[vreg1];
3955 VR[vreg2] = (SEXT32 (v, 16) & 0xffffffff);
3956 v >>= 16;
3957 t = SEXT32 (v, 16);
3958 VR[vreg2] |= t << 32;
3959
3960 v >>= 16;
3961 VR[vreg3] = (SEXT32 (v, 16) & 0xffffffff);
3962 v >>= 16;
3963 t = SEXT32 (v, 16);
3964 VR[vreg3] |= t << 32;
3965
3966 TRACE_ALU_RESULT2 (VR[vreg2], VR[vreg3]);
3967 }
3968
3969 vvvvv,111111,VVVVV+xxxxx,11001100110:C:::pki16ui8
3970 *v850e3v5
3971 "pki16ui8 v<vreg1>, v<vreg2>, v<vreg3>"
3972 {
3973 TRACE_ALU_INPUT2 (VR[vreg1], VR[vreg2]);
3974
3975 VR[vreg3] = VR[vreg1] & 0xff;
3976 VR[vreg3] |= ((VR[vreg1] >> 8) & 0xff00);
3977 VR[vreg3] |= ((VR[vreg1] >> 16) & 0xff0000);
3978 VR[vreg3] |= ((VR[vreg1] >> 24) & 0xff000000);
3979
3980 VR[vreg3] |= ((VR[vreg2] << 32) & 0xff00000000UL);
3981 VR[vreg3] |= ((VR[vreg2] << 24) & 0xff0000000000UL);
3982 VR[vreg3] |= ((VR[vreg2] << 16) & 0xff000000000000UL);
3983 VR[vreg3] |= ((VR[vreg2] << 8) & 0xff00000000000000UL);
3984
3985 TRACE_ALU_RESULT1 (VR[vreg3]);
3986 }
3987
3988 vvvvv,111111,VVVVV+xxxxx,11001100100:C:::pki32i16
3989 *v850e3v5
3990 "pki32i16 v<vreg1>, v<vreg2>, v<vreg3>"
3991 {
3992 reg64_t v;
3993
3994 TRACE_ALU_INPUT2 (VR[vreg1], VR[vreg2]);
3995
3996 v = VR[vreg1] & 0xffffffff;
3997 SAT16 (v);
3998 VR[vreg3] = v & 0xffff;
3999
4000 v = VR[vreg1] >> 32;
4001 SAT16 (v);
4002 VR[vreg3] |= ((v & 0xffff) << 16);
4003
4004 v = VR[vreg2] & 0xffffffff;
4005 SAT16 (v);
4006 VR[vreg3] = ((v & 0xffff) << 32);
4007
4008 v = VR[vreg2] >> 32;
4009 SAT16 (v);
4010 VR[vreg3] |= ((v & 0xffff) << 48);
4011
4012 TRACE_ALU_RESULT1 (VR[vreg3]);
4013 }
4014
4015 vvvvv,111111,VVVVV+xxxxx,11001100010:C:::pki64i32
4016 *v850e3v5
4017 "pki64i32 v<vreg1>, v<vreg2>, v<vreg3>"
4018 {
4019 reg64_t v;
4020
4021 TRACE_ALU_INPUT2 (VR[vreg1], VR[vreg2]);
4022
4023 v = VR[vreg1];
4024 SAT32 (v);
4025 VR[vreg3] = v & 0xffffffff;
4026
4027 v = VR[vreg2];
4028 SAT32 (v);
4029 VR[vreg3] |= v << 32;
4030
4031 TRACE_ALU_RESULT1 (VR[vreg3]);
4032 }
4033
4034 vvvvv,111111,VVVVV+xxxxx,11001101000:C:::pkq15q31
4035 *v850e3v5
4036 "pkq15q31 v<vreg1>, v<vreg2>, v<vreg3>"
4037 {
4038 reg64_t v;
4039
4040 TRACE_ALU_INPUT1 (VR[vreg1]);
4041
4042 v = VR[vreg1];
4043 VR[vreg2] = ((v & 0xffff) << 16);
4044 VR[vreg2] |= ((v & 0xffff0000) << 32);
4045
4046 VR[vreg3] = ((v & 0xffff00000000UL) >> 16);
4047 VR[vreg3] |= ((v & 0xffff000000000000UL));
4048
4049 TRACE_ALU_RESULT2 (VR[vreg2], VR[vreg3]);
4050 }
4051
4052 vvvvv,111111,VVVVV+xxxxx,11001011110:C:::pkq30q31
4053 *v850e3v5
4054 "pkq30q31 v<vreg1>, v<vreg2>, v<vreg3>"
4055 {
4056 reg64_t v;
4057
4058 TRACE_ALU_INPUT2 (VR[vreg1], VR[vreg2]);
4059
4060 v = VR[vreg1];
4061 v <<= 1;
4062 SAT32 (v);
4063 VR[vreg3] = v & 0xffffffff;
4064
4065 v = VR[vreg2];
4066 v <<= 1;
4067 SAT32 (v);
4068 VR[vreg3] = v << 32;
4069
4070 TRACE_ALU_RESULT1 (VR[vreg3]);
4071 }
4072
4073 vvvvv,111111,VVVVV+xxxxx,11001100000:C:::pkq31q15
4074 *v850e3v5
4075 "pkq31q15 v<vreg1>, v<vreg2>, v<vreg3>"
4076 {
4077 reg64_t v;
4078
4079 TRACE_ALU_INPUT2 (VR[vreg1], VR[vreg2]);
4080
4081 v = ROUND_Q31_Q15 (VR[vreg1] & 0xffffffff);
4082 SAT16 (v);
4083 VR[vreg3] = v & 0xffff;
4084
4085 v = ROUND_Q31_Q15 (VR[vreg1] >> 32);
4086 SAT16 (v);
4087 VR[vreg3] |= (v & 0xffff) << 16;
4088
4089 v = ROUND_Q31_Q15 (VR[vreg2] & 0xffffffff);
4090 SAT16 (v);
4091 VR[vreg3] |= (v & 0xffff) << 32;
4092
4093 v = ROUND_Q31_Q15 (VR[vreg2] >> 32);
4094 SAT16 (v);
4095 VR[vreg3] |= (v & 0xffff) << 48;
4096
4097 TRACE_ALU_RESULT1 (VR[vreg3]);
4098 }
4099
4100 vvvvv,111111,VVVVV+xxxxx,11001101100:C:::pkui8i16
4101 *v850e3v5
4102 "pkui8i16 v<vreg1>, v<vreg2>, v<vreg3>"
4103 {
4104 reg64_t v;
4105
4106 TRACE_ALU_INPUT1 (VR[vreg1]);
4107
4108 v = VR[vreg1];
4109
4110 VR[vreg2] = v & 0x00ff;
4111 VR[vreg2] |= (v << 8) & 0x00ff0000;
4112 VR[vreg2] |= (v << 16) & 0x00ff00000000UL;
4113 VR[vreg2] |= (v << 24) & 0x00ff000000000000UL;
4114
4115 VR[vreg3] = (v >> 32) & 0x00ff;
4116 VR[vreg3] |= (v >> 24) & 0x00ff0000;
4117 VR[vreg3] |= (v >> 16) & 0x00ff00000000UL;
4118 VR[vreg3] |= (v >> 8) & 0x00ff000000000000UL;
4119
4120 TRACE_ALU_RESULT2 (VR[vreg2], VR[vreg3]);
4121 }
4122
4123 vvvvv,11111100000+xxxxx,11001111110:C:::vabs.h
4124 *v850e3v5
4125 "vabs.h v<vreg2>, v<vreg3>"
4126 {
4127 int shift;
4128
4129 TRACE_ALU_INPUT1 (VR[vreg2]);
4130
4131 VR[vreg3] = 0;
4132 for (shift = 0; shift < 64; shift += 16);
4133 {
4134 reg64_t v;
4135
4136 v = VR[vreg2] >> shift;
4137 ABS16 (v);
4138 VR[vreg3] |= v << shift;
4139 }
4140
4141 TRACE_ALU_RESULT1 (VR[vreg3]);
4142 }
4143
4144 vvvvv,11111100001+xxxxx,11001111110:C:::vabs.w
4145 *v850e3v5
4146 "vabs.w v<vreg2>, v<vreg3>"
4147 {
4148 reg64_t v;
4149
4150 TRACE_ALU_INPUT1 (VR[vreg2]);
4151
4152 v = VR[vreg2];
4153 ABS32 (v);
4154 VR[vreg3] = v;
4155
4156 v = VR[vreg2] >> 32;
4157 ABS32 (v);
4158 VR[vreg3] |= v << 32;
4159
4160 TRACE_ALU_RESULT1 (VR[vreg3]);
4161 }
4162
4163 vvvvv,111111,VVVVV+xxxxx,11001011000:C:::vadd.dw
4164 *v850e3v5
4165 "vadd.dw v<vreg1>, v<vreg2>, v<vreg3>"
4166 {
4167 TRACE_ALU_INPUT2 (VR[vreg1], VR[vreg2]);
4168
4169 /* FIXME: saturation handling needed. */
4170 sim_engine_halt (SD, CPU, NULL, cia, sim_signalled, SIM_SIGILL);
4171
4172 VR[vreg3] = VR[vreg1] + VR[vreg2];
4173
4174 TRACE_ALU_RESULT1 (VR[vreg3]);
4175 }
4176
4177 vvvvv,111111,VVVVV+xxxxx,11000000000:C:::vadd.h
4178 *v850e3v5
4179 "vadd.h v<vreg1>, v<vreg2>, v<vreg3>"
4180 {
4181 TRACE_ALU_INPUT2 (VR[vreg1], VR[vreg2]);
4182
4183 /* FIXME: Implementation needed. */
4184 sim_engine_halt (SD, CPU, NULL, cia, sim_signalled, SIM_SIGILL);
4185
4186 TRACE_ALU_RESULT1 (VR[vreg3]);
4187 }
4188
4189 vvvvv,111111,VVVVV+xxxxx,11000000010:C:::vadd.w
4190 *v850e3v5
4191 "vadd.w v<vreg1>, v<vreg2>, v<vreg3>"
4192 {
4193 TRACE_ALU_INPUT2 (VR[vreg1], VR[vreg2]);
4194
4195 /* FIXME: Implementation needed. */
4196 sim_engine_halt (SD, CPU, NULL, cia, sim_signalled, SIM_SIGILL);
4197
4198 TRACE_ALU_RESULT1 (VR[vreg3]);
4199 }
4200
4201 vvvvv,111111,VVVVV+xxxxx,11000001000:C:::vadds.h
4202 *v850e3v5
4203 "vadds.h v<vreg1>, v<vreg2>, v<vreg3>"
4204 {
4205 TRACE_ALU_INPUT2 (VR[vreg1], VR[vreg2]);
4206
4207 /* FIXME: Implementation needed. */
4208 sim_engine_halt (SD, CPU, NULL, cia, sim_signalled, SIM_SIGILL);
4209
4210 TRACE_ALU_RESULT1 (VR[vreg3]);
4211 }
4212
4213 vvvvv,111111,VVVVV+xxxxx,11000001010:C:::vadds.w
4214 *v850e3v5
4215 "vadds.w v<vreg1>, v<vreg2>, v<vreg3>"
4216 {
4217 TRACE_ALU_INPUT2 (VR[vreg1], VR[vreg2]);
4218
4219 /* FIXME: Implementation needed. */
4220 sim_engine_halt (SD, CPU, NULL, cia, sim_signalled, SIM_SIGILL);
4221
4222 TRACE_ALU_RESULT1 (VR[vreg3]);
4223 }
4224
4225 vvvvv,111111,VVVVV+xxxxx,11000010000:C:::vaddsat.h
4226 *v850e3v5
4227 "vaddsat.h v<vreg1>, v<vreg2>, v<vreg3>"
4228 {
4229 TRACE_ALU_INPUT2 (VR[vreg1], VR[vreg2]);
4230
4231 /* FIXME: Implementation needed. */
4232 sim_engine_halt (SD, CPU, NULL, cia, sim_signalled, SIM_SIGILL);
4233
4234 TRACE_ALU_RESULT1 (VR[vreg3]);
4235 }
4236
4237 vvvvv,111111,VVVVV+xxxxx,11000010010:C:::vaddsat.w
4238 *v850e3v5
4239 "vaddsat.w v<vreg1>, v<vreg2>, v<vreg3>"
4240 {
4241 TRACE_ALU_INPUT2 (VR[vreg1], VR[vreg2]);
4242
4243 /* FIXME: Implementation needed. */
4244 sim_engine_halt (SD, CPU, NULL, cia, sim_signalled, SIM_SIGILL);
4245
4246 TRACE_ALU_RESULT1 (VR[vreg3]);
4247 }
4248
4249 vvvvv,111111,VVVVV+xxxxx,11010000000:C:::vand
4250 *v850e3v5
4251 "vand v<vreg1>, v<vreg2>, v<vreg3>"
4252 {
4253 TRACE_ALU_INPUT2 (VR[vreg1], VR[vreg2]);
4254
4255 VR[vreg3] = VR[vreg1] & VR[vreg2];
4256
4257 TRACE_ALU_RESULT1 (VR[vreg3]);
4258 }
4259
4260 vvvvv,111111,VVVVV+xxxxx,11001011100:C:::vbiq.h
4261 *v850e3v5
4262 "vbiq.h v<vreg1>, v<vreg2>, v<vreg3>"
4263 {
4264 TRACE_ALU_INPUT2 (VR[vreg1], VR[vreg2]);
4265
4266 /* FIXME: Implementation needed. */
4267 sim_engine_halt (SD, CPU, NULL, cia, sim_signalled, SIM_SIGILL);
4268
4269 TRACE_ALU_RESULT2 (VR[vreg2], VR[vreg3]);
4270 }
4271
4272 vvvvv,11111100111+xxxxx,11011011110:C:::vbswap.dw
4273 *v850e3v5
4274 "vbswap.dw v<vreg2>, v<vreg3>"
4275 {
4276 TRACE_ALU_INPUT1 (VR[vreg2]);
4277
4278 /* FIXME: Implementation needed. */
4279 sim_engine_halt (SD, CPU, NULL, cia, sim_signalled, SIM_SIGILL);
4280
4281 TRACE_ALU_RESULT1 (VR[vreg3]);
4282 }
4283
4284 vvvvv,11111100101+xxxxx,11011011110:C:::vbswap.h
4285 *v850e3v5
4286 "vbswap.h v<vreg2>, v<vreg3>"
4287 {
4288 TRACE_ALU_INPUT1 (VR[vreg2]);
4289
4290 /* FIXME: Implementation needed. */
4291 sim_engine_halt (SD, CPU, NULL, cia, sim_signalled, SIM_SIGILL);
4292
4293 TRACE_ALU_RESULT1 (VR[vreg3]);
4294 }
4295
4296 vvvvv,11111100110+xxxxx,11011011110:C:::vbswap.w
4297 *v850e3v5
4298 "vbswap.w v<vreg2>, v<vreg3>"
4299 {
4300 TRACE_ALU_INPUT1 (VR[vreg2]);
4301
4302 /* FIXME: Implementation needed. */
4303 sim_engine_halt (SD, CPU, NULL, cia, sim_signalled, SIM_SIGILL);
4304
4305 TRACE_ALU_RESULT1 (VR[vreg3]);
4306 }
4307
4308 vvvvv,111111,VVVVV+xxxxx,11001110000:C:::vcalc.h
4309 *v850e3v5
4310 "vcalc.h v<vreg1>,v<vreg2>, v<vreg3>"
4311 {
4312 TRACE_ALU_INPUT2 (VR[vreg1], VR[vreg2]);
4313
4314 /* FIXME: Implementation needed. */
4315 sim_engine_halt (SD, CPU, NULL, cia, sim_signalled, SIM_SIGILL);
4316
4317 TRACE_ALU_RESULT1 (VR[vreg3]);
4318 }
4319
4320 vvvvv,111111,VVVVV+xxxxx,11001110010:C:::vcalc.w
4321 *v850e3v5
4322 "vcalc.w v<vreg1>,v<vreg2>, v<vreg3>"
4323 {
4324 TRACE_ALU_INPUT2 (VR[vreg1], VR[vreg2]);
4325
4326 /* FIXME: Implementation needed. */
4327 sim_engine_halt (SD, CPU, NULL, cia, sim_signalled, SIM_SIGILL);
4328
4329 TRACE_ALU_RESULT1 (VR[vreg3]);
4330 }
4331
4332 vvvvv,111111,VVVVV+xxxxx,11010110000:C:::vcmov
4333 *v850e3v5
4334 "vcmov v<vreg1>, v<vreg2>, v<vreg3>"
4335 {
4336 TRACE_ALU_INPUT2 (VR[vreg1], VR[vreg2]);
4337
4338 /* FIXME: Implementation needed. */
4339 sim_engine_halt (SD, CPU, NULL, cia, sim_signalled, SIM_SIGILL);
4340
4341 TRACE_ALU_RESULT1 (VR[vreg3]);
4342 }
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