unsigned int DBZ = als == 0 ? 1 : 0;
unsigned int Q = ~(SS ^ SD) & 1;
unsigned int C;
- unsigned int S;
unsigned int i;
unsigned long alt = Q ? ~als : als;
| (((alt >> 31) ^ (ald >> 31)) & (~alo >> 31)));
Q = C ^ SS;
R1 = (alo == 0) ? 0 : (R1 & (Q ^ (SS ^ SD)));
- S = alo >> 31;
+ /* S = alo >> 31; */
sfi = (sfi << (32-N+1)) | Q;
ald = (alo << 1) | (sfi >> 31);
if ((alo >> 31) ^ (ald >> 31))
| (((alt >> 31) ^ (ald >> 31)) & (~alo >> 31)));
Q = C ^ SS;
R1 = (alo == 0) ? 0 : (R1 & (Q ^ (SS ^ SD)));
- S = alo >> 31;
+ /* S = alo >> 31; */
sfi = (sfi << 1) | Q;
ald = (alo << 1) | (sfi >> 31);
if ((alo >> 31) ^ (ald >> 31))
}
else
{
- int gt = 0,lt = 0,eq = 0, status;
+ int lt = 0, eq = 0, status;
status = sim_fpu_cmp (&wop1, &wop2);
lt = 1;
break;
case SIM_FPU_IS_PINF:
- gt = 1;
+ /* gt = 1; */
break;
case SIM_FPU_IS_NNUMBER:
lt = 1;
break;
case SIM_FPU_IS_PNUMBER:
- gt = 1;
+ /* gt = 1; */
break;
case SIM_FPU_IS_NDENORM:
lt = 1;
break;
case SIM_FPU_IS_PDENORM:
- gt = 1;
+ /* gt = 1; */
break;
case SIM_FPU_IS_NZERO:
case SIM_FPU_IS_PZERO:
{
int64_t ans;
sim_fpu wop;
- sim_fpu_status status;
sim_fpu_32to (&wop, GR[reg2]);
TRACE_FP_INPUT_FPU1 (&wop);
- status = sim_fpu_to64i (&ans, &wop, sim_fpu_round_zero);
+ sim_fpu_to64i (&ans, &wop, sim_fpu_round_zero);
GR[reg3e] = ans;
GR[reg3e+1] = ans >> 32L;
{
uint64_t ans;
sim_fpu wop;
- sim_fpu_status status;
sim_fpu_32to (&wop, GR[reg2]);
TRACE_FP_INPUT_FPU1 (&wop);
- status = sim_fpu_to64u (&ans, &wop, sim_fpu_round_zero);
+ sim_fpu_to64u (&ans, &wop, sim_fpu_round_zero);
GR[reg3e] = ans;
GR[reg3e+1] = ans >> 32L;