cpu-vax.lo \
cpu-visium.lo \
cpu-wasm32.lo \
- cpu-xc16x.lo \
cpu-xgate.lo \
cpu-xstormy16.lo \
cpu-xtensa.lo \
cpu-vax.c \
cpu-visium.c \
cpu-wasm32.c \
- cpu-xc16x.c \
cpu-xgate.c \
cpu-xstormy16.c \
cpu-xtensa.c \
elf32-vax.lo \
elf32-visium.lo \
elf32-wasm32.lo \
- elf32-xc16x.lo \
elf32-xgate.lo \
elf32-xstormy16.lo \
elf32-xtensa.lo \
elf32-vax.c \
elf32-visium.c \
elf32-wasm32.c \
- elf32-xc16x.c \
elf32-xgate.c \
elf32-xstormy16.c \
elf32-xtensa.c \
cpu-vax.lo \
cpu-visium.lo \
cpu-wasm32.lo \
- cpu-xc16x.lo \
cpu-xgate.lo \
cpu-xstormy16.lo \
cpu-xtensa.lo \
cpu-vax.c \
cpu-visium.c \
cpu-wasm32.c \
- cpu-xc16x.c \
cpu-xgate.c \
cpu-xstormy16.c \
cpu-xtensa.c \
elf32-vax.lo \
elf32-visium.lo \
elf32-wasm32.lo \
- elf32-xc16x.lo \
elf32-xgate.lo \
elf32-xstormy16.lo \
elf32-xtensa.lo \
elf32-vax.c \
elf32-visium.c \
elf32-wasm32.c \
- elf32-xc16x.c \
elf32-xgate.c \
elf32-xstormy16.c \
elf32-xtensa.c \
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/cpu-vax.Plo@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/cpu-visium.Plo@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/cpu-wasm32.Plo@am__quote@
-@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/cpu-xc16x.Plo@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/cpu-xgate.Plo@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/cpu-xstormy16.Plo@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/cpu-xtensa.Plo@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/elf32-vax.Plo@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/elf32-visium.Plo@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/elf32-wasm32.Plo@am__quote@
-@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/elf32-xc16x.Plo@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/elf32-xgate.Plo@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/elf32-xstormy16.Plo@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/elf32-xtensa.Plo@am__quote@
.#define bfd_mach_msp46 46
.#define bfd_mach_msp47 47
.#define bfd_mach_msp54 54
-. bfd_arch_xc16x, {* Infineon's XC16X Series. *}
-.#define bfd_mach_xc16x 1
-.#define bfd_mach_xc16xl 2
-.#define bfd_mach_xc16xs 3
. bfd_arch_xgate, {* Freescale XGATE. *}
.#define bfd_mach_xgate 1
. bfd_arch_xtensa, {* Tensilica's Xtensa cores. *}
extern const bfd_arch_info_type bfd_wasm32_arch;
extern const bfd_arch_info_type bfd_xstormy16_arch;
extern const bfd_arch_info_type bfd_xtensa_arch;
-extern const bfd_arch_info_type bfd_xc16x_arch;
extern const bfd_arch_info_type bfd_xgate_arch;
extern const bfd_arch_info_type bfd_z80_arch;
extern const bfd_arch_info_type bfd_z8k_arch;
&bfd_wasm32_arch,
&bfd_xstormy16_arch,
&bfd_xtensa_arch,
- &bfd_xc16x_arch,
&bfd_xgate_arch,
&bfd_z80_arch,
&bfd_z8k_arch,
#define bfd_mach_msp46 46
#define bfd_mach_msp47 47
#define bfd_mach_msp54 54
- bfd_arch_xc16x, /* Infineon's XC16X Series. */
-#define bfd_mach_xc16x 1
-#define bfd_mach_xc16xl 2
-#define bfd_mach_xc16xs 3
bfd_arch_xgate, /* Freescale XGATE. */
#define bfd_mach_xgate 1
bfd_arch_xtensa, /* Tensilica's Xtensa cores. */
BFD_RELOC_RELC,
-/* Infineon Relocations. */
- BFD_RELOC_XC16X_PAG,
- BFD_RELOC_XC16X_POF,
- BFD_RELOC_XC16X_SEG,
- BFD_RELOC_XC16X_SOF,
-
/* Relocations used by VAX ELF. */
BFD_RELOC_VAX_GLOB_DAT,
BFD_RELOC_VAX_JMP_SLOT,
targ_selvecs="wasm_vec"
;;
- xc16x-*-elf)
- targ_defvec=xc16x_elf32_vec
- ;;
-
xgate-*-*)
targ_defvec=xgate_elf32_vec
targ_selvecs="xgate_elf32_vec"
x86_64_pe_vec) tb="$tb pe-x86_64.lo pex64igen.lo $coff"; target_size=64 ;;
x86_64_pe_big_vec) tb="$tb pe-x86_64.lo pex64igen.lo $coff"; target_size=64 ;;
x86_64_pei_vec) tb="$tb pei-x86_64.lo pex64igen.lo $coff"; target_size=64 ;;
- xc16x_elf32_vec) tb="$tb elf32-xc16x.lo elf32.lo $elf" ;;
xgate_elf32_vec) tb="$tb elf32-xgate.lo elf32.lo $elf" ;;
xstormy16_elf32_vec) tb="$tb elf32-xstormy16.lo elf32.lo $elf" ;;
xtensa_elf32_be_vec) tb="$tb xtensa-isa.lo xtensa-modules.lo elf32-xtensa.lo elf32.lo $elf" ;;
x86_64_pe_vec) tb="$tb pe-x86_64.lo pex64igen.lo $coff"; target_size=64 ;;
x86_64_pe_big_vec) tb="$tb pe-x86_64.lo pex64igen.lo $coff"; target_size=64 ;;
x86_64_pei_vec) tb="$tb pei-x86_64.lo pex64igen.lo $coff"; target_size=64 ;;
- xc16x_elf32_vec) tb="$tb elf32-xc16x.lo elf32.lo $elf" ;;
xgate_elf32_vec) tb="$tb elf32-xgate.lo elf32.lo $elf" ;;
xstormy16_elf32_vec) tb="$tb elf32-xstormy16.lo elf32.lo $elf" ;;
xtensa_elf32_be_vec) tb="$tb xtensa-isa.lo xtensa-modules.lo elf32-xtensa.lo elf32.lo $elf" ;;
+++ /dev/null
-/* BFD support for the Infineon XC16X Microcontroller.
- Copyright (C) 2006-2022 Free Software Foundation, Inc.
- Contributed by KPIT Cummins Infosystems
-
- This file is part of BFD, the Binary File Descriptor library.
- Contributed by Anil Paranjpe(anilp1@kpitcummins.com)
-
- This program is free software; you can redistribute it and/or modify
- it under the terms of the GNU General Public License as published by
- the Free Software Foundation; either version 3 of the License, or
- (at your option) any later version.
-
- This program is distributed in the hope that it will be useful,
- but WITHOUT ANY WARRANTY; without even the implied warranty of
- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- GNU General Public License for more details.
-
- You should have received a copy of the GNU General Public License
- along with this program; if not, write to the Free Software
- Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
- 02110-1301, USA. */
-
-#include "sysdep.h"
-#include "bfd.h"
-#include "libbfd.h"
-
-#define N(BITS_ADDR, NUMBER, PRINT, DEFAULT, NEXT) \
- { \
- 16, /* Bits in a word. */ \
- BITS_ADDR, /* Bits in an address. */ \
- 8, /* Bits in a byte. */ \
- bfd_arch_xc16x, \
- NUMBER, \
- "xc16x", \
- PRINT, \
- 1, /* Section alignment power. */ \
- DEFAULT, \
- bfd_default_compatible, \
- bfd_default_scan, \
- bfd_arch_default_fill, \
- NEXT, \
- 0 /* Maximum offset of a reloc from the start of an insn. */ \
- }
-
-const bfd_arch_info_type xc16xs_info_struct =
- N (16, bfd_mach_xc16xs, "xc16xs", false, NULL);
-
-const bfd_arch_info_type xc16xl_info_struct =
- N (32, bfd_mach_xc16xl, "xc16xl", false, & xc16xs_info_struct);
-
-const bfd_arch_info_type bfd_xc16x_arch =
- N (16, bfd_mach_xc16x, "xc16x", true, & xc16xl_info_struct);
-
+++ /dev/null
-/* Infineon XC16X-specific support for 16-bit ELF.
- Copyright (C) 2006-2022 Free Software Foundation, Inc.
- Contributed by KPIT Cummins Infosystems
-
- This file is part of BFD, the Binary File Descriptor library.
-
- This program is free software; you can redistribute it and/or modify
- it under the terms of the GNU General Public License as published by
- the Free Software Foundation; either version 3 of the License, or
- (at your option) any later version.
-
- This program is distributed in the hope that it will be useful,
- but WITHOUT ANY WARRANTY; without even the implied warranty of
- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- GNU General Public License for more details.
-
- You should have received a copy of the GNU General Public License
- along with this program; if not, write to the Free Software
- Foundation, 51 Franklin Street - Fifth Floor, Boston,
- MA 02110-1301, USA. */
-
-#include "sysdep.h"
-#include "bfd.h"
-#include "libbfd.h"
-#include "elf-bfd.h"
-#include "elf/xc16x.h"
-#include "dwarf2.h"
-#include "libiberty.h"
-
-static reloc_howto_type xc16x_elf_howto_table [] =
-{
- /* This reloc does nothing. */
- HOWTO (R_XC16X_NONE, /* type */
- 0, /* rightshift */
- 0, /* size */
- 0, /* bitsize */
- false, /* pc_relative */
- 0, /* bitpos */
- complain_overflow_dont, /* complain_on_overflow */
- bfd_elf_generic_reloc, /* special_function */
- "R_XC16X_NONE", /* name */
- false, /* partial_inplace */
- 0, /* src_mask */
- 0, /* dst_mask */
- false), /* pcrel_offset */
-
- /* An 8 bit absolute relocation. */
- HOWTO (R_XC16X_ABS_8, /* type */
- 0, /* rightshift */
- 1, /* size */
- 8, /* bitsize */
- false, /* pc_relative */
- 8, /* bitpos */
- complain_overflow_bitfield, /* complain_on_overflow */
- bfd_elf_generic_reloc, /* special_function */
- "R_XC16X_ABS_8", /* name */
- true, /* partial_inplace */
- 0x0000, /* src_mask */
- 0x00ff, /* dst_mask */
- false), /* pcrel_offset */
-
- /* A 16 bit absolute relocation. */
- HOWTO (R_XC16X_ABS_16, /* type */
- 0, /* rightshift */
- 2, /* size */
- 16, /* bitsize */
- false, /* pc_relative */
- 0, /* bitpos */
- complain_overflow_dont, /* complain_on_overflow */
- bfd_elf_generic_reloc, /* special_function */
- "R_XC16X_ABS_16", /* name */
- true, /* partial_inplace */
- 0x00000000, /* src_mask */
- 0x0000ffff, /* dst_mask */
- false), /* pcrel_offset */
-
- HOWTO (R_XC16X_ABS_32, /* type */
- 0, /* rightshift */
- 4, /* size */
- 32, /* bitsize */
- false, /* pc_relative */
- 0, /* bitpos */
- complain_overflow_bitfield, /* complain_on_overflow */
- bfd_elf_generic_reloc, /* special_function */
- "R_XC16X_ABS_32", /* name */
- true, /* partial_inplace */
- 0x00000000, /* src_mask */
- 0xffffffff, /* dst_mask */
- false), /* pcrel_offset */
-
-
- /* A PC relative 8 bit relocation. */
- HOWTO (R_XC16X_8_PCREL, /* type */
- 0, /* rightshift */
- 1, /* size */
- 8, /* bitsize */
- true, /* pc_relative */
- 8, /* bitpos */
- complain_overflow_signed, /* complain_on_overflow */
- bfd_elf_generic_reloc, /* special_function */
- "R_XC16X_8_PCREL", /* name */
- false, /* partial_inplace */
- 0x0000, /* src_mask */
- 0x00ff, /* dst_mask */
- true), /* pcrel_offset */
-
- /* Relocation regarding page number. */
- HOWTO (R_XC16X_PAG, /* type */
- 0, /* rightshift */
- 2, /* size */
- 16, /* bitsize */
- false, /* pc_relative */
- 0, /* bitpos */
- complain_overflow_signed, /* complain_on_overflow */
- bfd_elf_generic_reloc, /* special_function */
- "R_XC16X_PAG", /* name */
- true, /* partial_inplace */
- 0x00000000, /* src_mask */
- 0x0000ffff, /* dst_mask */
- false), /* pcrel_offset */
-
-
- /* Relocation regarding page number. */
- HOWTO (R_XC16X_POF, /* type */
- 0, /* rightshift */
- 2, /* size */
- 16, /* bitsize */
- false, /* pc_relative */
- 0, /* bitpos */
- complain_overflow_signed, /* complain_on_overflow */
- bfd_elf_generic_reloc, /* special_function */
- "R_XC16X_POF", /* name */
- true, /* partial_inplace */
- 0x00000000, /* src_mask */
- 0x0000ffff, /* dst_mask */
- false), /* pcrel_offset */
-
-
- /* Relocation regarding segment number. */
- HOWTO (R_XC16X_SEG, /* type */
- 0, /* rightshift */
- 2, /* size */
- 16, /* bitsize */
- false, /* pc_relative */
- 0, /* bitpos */
- complain_overflow_signed, /* complain_on_overflow */
- bfd_elf_generic_reloc, /* special_function */
- "R_XC16X_SEG", /* name */
- true, /* partial_inplace */
- 0x00000000, /* src_mask */
- 0x0000ffff, /* dst_mask */
- false), /* pcrel_offset */
-
- /* Relocation regarding segment offset. */
- HOWTO (R_XC16X_SOF, /* type */
- 0, /* rightshift */
- 2, /* size */
- 16, /* bitsize */
- false, /* pc_relative */
- 0, /* bitpos */
- complain_overflow_signed, /* complain_on_overflow */
- bfd_elf_generic_reloc, /* special_function */
- "R_XC16X_SOF", /* name */
- true, /* partial_inplace */
- 0x00000000, /* src_mask */
- 0x0000ffff, /* dst_mask */
- false) /* pcrel_offset */
-};
-
-
-/* Map BFD reloc types to XC16X ELF reloc types. */
-
-struct xc16x_reloc_map
-{
- bfd_reloc_code_real_type bfd_reloc_val;
- unsigned int xc16x_reloc_val;
-};
-
-static const struct xc16x_reloc_map xc16x_reloc_map [] =
-{
- { BFD_RELOC_NONE, R_XC16X_NONE },
- { BFD_RELOC_8, R_XC16X_ABS_8 },
- { BFD_RELOC_16, R_XC16X_ABS_16 },
- { BFD_RELOC_32, R_XC16X_ABS_32 },
- { BFD_RELOC_8_PCREL, R_XC16X_8_PCREL },
- { BFD_RELOC_XC16X_PAG, R_XC16X_PAG},
- { BFD_RELOC_XC16X_POF, R_XC16X_POF},
- { BFD_RELOC_XC16X_SEG, R_XC16X_SEG},
- { BFD_RELOC_XC16X_SOF, R_XC16X_SOF},
-};
-
-
-/* This function is used to search for correct relocation type from
- howto structure. */
-
-static reloc_howto_type *
-xc16x_reloc_type_lookup (bfd *abfd ATTRIBUTE_UNUSED,
- bfd_reloc_code_real_type code)
-{
- unsigned int i;
-
- for (i = ARRAY_SIZE (xc16x_reloc_map); --i;)
- if (xc16x_reloc_map [i].bfd_reloc_val == code)
- return & xc16x_elf_howto_table [xc16x_reloc_map[i].xc16x_reloc_val];
-
- return NULL;
-}
-
-static reloc_howto_type *
-xc16x_reloc_name_lookup (bfd *abfd ATTRIBUTE_UNUSED,
- const char *r_name)
-{
- unsigned int i;
-
- for (i = 0; i < ARRAY_SIZE (xc16x_elf_howto_table); i++)
- if (xc16x_elf_howto_table[i].name != NULL
- && strcasecmp (xc16x_elf_howto_table[i].name, r_name) == 0)
- return &xc16x_elf_howto_table[i];
-
- return NULL;
-}
-
-static reloc_howto_type *
-elf32_xc16x_rtype_to_howto (bfd *abfd ATTRIBUTE_UNUSED, unsigned r_type)
-{
- if (r_type < ARRAY_SIZE (xc16x_elf_howto_table))
- return & xc16x_elf_howto_table[r_type];
-
- return NULL;
-}
-
-/* For a particular operand this function is
- called to finalise the type of relocation. */
-
-static bool
-elf32_xc16x_info_to_howto (bfd *abfd, arelent *bfd_reloc,
- Elf_Internal_Rela *elf_reloc)
-{
- unsigned int r;
- unsigned int i;
-
- r = ELF32_R_TYPE (elf_reloc->r_info);
- for (i = 0; i < ARRAY_SIZE (xc16x_elf_howto_table); i++)
- if (xc16x_elf_howto_table[i].type == r)
- {
- bfd_reloc->howto = &xc16x_elf_howto_table[i];
- return true;
- }
- /* xgettext:c-format */
- _bfd_error_handler (_("%pB: unsupported relocation type %#x"), abfd, r);
- bfd_set_error (bfd_error_bad_value);
- return false;
-}
-
-static bfd_reloc_status_type
-elf32_xc16x_final_link_relocate (unsigned long r_type,
- bfd *input_bfd,
- bfd *output_bfd ATTRIBUTE_UNUSED,
- asection *input_section ATTRIBUTE_UNUSED,
- bfd_byte *contents,
- bfd_vma offset,
- bfd_vma value,
- bfd_vma addend,
- struct bfd_link_info *info ATTRIBUTE_UNUSED,
- asection *sym_sec ATTRIBUTE_UNUSED,
- int is_local ATTRIBUTE_UNUSED)
-{
- bfd_byte *hit_data = contents + offset;
- bfd_vma val1;
-
- switch (r_type)
- {
- case R_XC16X_NONE:
- return bfd_reloc_ok;
-
- case R_XC16X_ABS_16:
- value += addend;
- bfd_put_16 (input_bfd, value, hit_data);
- return bfd_reloc_ok;
-
- case R_XC16X_8_PCREL:
- bfd_put_8 (input_bfd, value, hit_data);
- return bfd_reloc_ok;
-
- /* Following case is to find page number from actual
- address for this divide value by 16k i.e. page size. */
-
- case R_XC16X_PAG:
- value += addend;
- value /= 0x4000;
- bfd_put_16 (input_bfd, value, hit_data);
- return bfd_reloc_ok;
-
- /* Following case is to find page offset from actual address
- for this take modulo of value by 16k i.e. page size. */
-
- case R_XC16X_POF:
- value += addend;
- value %= 0x4000;
- bfd_put_16 (input_bfd, value, hit_data);
- return bfd_reloc_ok;
-
- /* Following case is to find segment number from actual
- address for this divide value by 64k i.e. segment size. */
-
- case R_XC16X_SEG:
- value += addend;
- value /= 0x10000;
- bfd_put_16 (input_bfd, value, hit_data);
- return bfd_reloc_ok;
-
- /* Following case is to find segment offset from actual address
- for this take modulo of value by 64k i.e. segment size. */
-
- case R_XC16X_SOF:
- value += addend;
- value %= 0x10000;
- bfd_put_16 (input_bfd, value, hit_data);
- return bfd_reloc_ok;
-
- case R_XC16X_ABS_32:
- if (!strstr (input_section->name,".debug"))
- {
- value += addend;
- val1 = value;
- value %= 0x4000;
- val1 /= 0x4000;
- val1 = val1 << 16;
- value += val1;
- bfd_put_32 (input_bfd, value, hit_data);
- }
- else
- {
- value += addend;
- bfd_put_32 (input_bfd, value, hit_data);
- }
- return bfd_reloc_ok;
-
- default:
- return bfd_reloc_notsupported;
- }
-}
-
-static int
-elf32_xc16x_relocate_section (bfd *output_bfd,
- struct bfd_link_info *info,
- bfd *input_bfd,
- asection *input_section,
- bfd_byte *contents,
- Elf_Internal_Rela *relocs,
- Elf_Internal_Sym *local_syms,
- asection **local_sections)
-{
- Elf_Internal_Shdr *symtab_hdr;
- struct elf_link_hash_entry **sym_hashes;
- Elf_Internal_Rela *rel, *relend;
-
- symtab_hdr = &elf_tdata (input_bfd)->symtab_hdr;
- sym_hashes = elf_sym_hashes (input_bfd);
-
- rel = relocs;
- relend = relocs + input_section->reloc_count;
- for (; rel < relend; rel++)
- {
- unsigned int r_type;
- unsigned long r_symndx;
- Elf_Internal_Sym *sym;
- asection *sec;
- struct elf_link_hash_entry *h;
- bfd_vma relocation;
-
- /* This is a final link. */
- r_symndx = ELF32_R_SYM (rel->r_info);
- r_type = ELF32_R_TYPE (rel->r_info);
- h = NULL;
- sym = NULL;
- sec = NULL;
- if (r_symndx < symtab_hdr->sh_info)
- {
- sym = local_syms + r_symndx;
- sec = local_sections[r_symndx];
- relocation = _bfd_elf_rela_local_sym (output_bfd, sym, &sec, rel);
- }
- else
- {
- bool unresolved_reloc, warned, ignored;
-
- RELOC_FOR_GLOBAL_SYMBOL (info, input_bfd, input_section, rel,
- r_symndx, symtab_hdr, sym_hashes,
- h, sec, relocation,
- unresolved_reloc, warned, ignored);
- }
-
- if (sec != NULL && discarded_section (sec))
- {
- /* For relocs against symbols from removed linkonce sections,
- or sections discarded by a linker script, we just want the
- section contents cleared. Avoid any special processing. */
- reloc_howto_type *howto;
- howto = elf32_xc16x_rtype_to_howto (input_bfd, r_type);
- RELOC_AGAINST_DISCARDED_SECTION (info, input_bfd, input_section,
- rel, 1, relend, howto, 0, contents);
- }
-
- if (bfd_link_relocatable (info))
- continue;
-
- elf32_xc16x_final_link_relocate (r_type, input_bfd, output_bfd,
- input_section,
- contents, rel->r_offset,
- relocation, rel->r_addend,
- info, sec, h == NULL);
- }
-
- return true;
-}
-
-
-static bool
-elf32_xc16x_final_write_processing (bfd *abfd)
-{
- unsigned long val;
-
- switch (bfd_get_mach (abfd))
- {
- default:
- case bfd_mach_xc16x:
- val = 0x1000;
- break;
-
- case bfd_mach_xc16xl:
- val = 0x1001;
- break;
-
- case bfd_mach_xc16xs:
- val = 0x1002;
- break;
- }
-
- elf_elfheader (abfd)->e_flags |= val;
- return _bfd_elf_final_write_processing (abfd);
-}
-
-static unsigned long
-elf32_xc16x_mach (flagword flags)
-{
- switch (flags)
- {
- case 0x1000:
- default:
- return bfd_mach_xc16x;
-
- case 0x1001:
- return bfd_mach_xc16xl;
-
- case 0x1002:
- return bfd_mach_xc16xs;
- }
-}
-
-
-static bool
-elf32_xc16x_object_p (bfd *abfd)
-{
- bfd_default_set_arch_mach (abfd, bfd_arch_xc16x,
- elf32_xc16x_mach (elf_elfheader (abfd)->e_flags));
- return true;
-}
-
-
-#define ELF_ARCH bfd_arch_xc16x
-#define ELF_MACHINE_CODE EM_XC16X
-#define ELF_MAXPAGESIZE 0x100
-
-#define TARGET_LITTLE_SYM xc16x_elf32_vec
-#define TARGET_LITTLE_NAME "elf32-xc16x"
-#define elf_backend_final_write_processing elf32_xc16x_final_write_processing
-#define elf_backend_object_p elf32_xc16x_object_p
-#define elf_backend_can_gc_sections 1
-#define bfd_elf32_bfd_reloc_type_lookup xc16x_reloc_type_lookup
-#define bfd_elf32_bfd_reloc_name_lookup xc16x_reloc_name_lookup
-#define elf_info_to_howto elf32_xc16x_info_to_howto
-#define elf_info_to_howto_rel elf32_xc16x_info_to_howto
-#define elf_backend_relocate_section elf32_xc16x_relocate_section
-#define elf_backend_rela_normal 1
-
-#include "elf32-target.h"
"BFD_RELOC_XSTORMY16_FPTR16",
"BFD_RELOC_RELC",
- "BFD_RELOC_XC16X_PAG",
- "BFD_RELOC_XC16X_POF",
- "BFD_RELOC_XC16X_SEG",
- "BFD_RELOC_XC16X_SOF",
"BFD_RELOC_VAX_GLOB_DAT",
"BFD_RELOC_VAX_JMP_SLOT",
"BFD_RELOC_VAX_RELATIVE",
cpu-vax.c
cpu-visium.c
cpu-wasm32.c
-cpu-xc16x.c
cpu-xgate.c
cpu-xstormy16.c
cpu-xtensa.c
elf32-vax.c
elf32-visium.c
elf32-wasm32.c
-elf32-xc16x.c
elf32-xgate.c
elf32-xstormy16.c
elf32-xtensa.c
Self-describing complex relocations.
COMMENT
-ENUM
- BFD_RELOC_XC16X_PAG
-ENUMX
- BFD_RELOC_XC16X_POF
-ENUMX
- BFD_RELOC_XC16X_SEG
-ENUMX
- BFD_RELOC_XC16X_SOF
-ENUMDOC
- Infineon Relocations.
-
ENUM
BFD_RELOC_VAX_GLOB_DAT
ENUMX
extern const bfd_target x86_64_pe_vec;
extern const bfd_target x86_64_pe_big_vec;
extern const bfd_target x86_64_pei_vec;
-extern const bfd_target xc16x_elf32_vec;
extern const bfd_target xgate_elf32_vec;
extern const bfd_target xstormy16_elf32_vec;
extern const bfd_target xtensa_elf32_be_vec;
&x86_64_pei_vec,
#endif
- &xc16x_elf32_vec,
-
&xgate_elf32_vec,
&xstormy16_elf32_vec,
#include "elf/visium.h"
#include "elf/wasm32.h"
#include "elf/x86-64.h"
-#include "elf/xc16x.h"
#include "elf/xgate.h"
#include "elf/xstormy16.h"
#include "elf/xtensa.h"
rtype = elf_metag_reloc_type (type);
break;
- case EM_XC16X:
- case EM_C166:
- rtype = elf_xc16x_reloc_type (type);
- break;
-
case EM_TI_C6000:
rtype = elf_tic6x_reloc_type (type);
break;
case EM_L1OM:
case EM_K1OM:
return reloc_type == 10; /* R_X86_64_32. */
- case EM_XC16X:
- case EM_C166:
- return reloc_type == 3; /* R_XC16C_ABS_32. */
case EM_XGATE:
return reloc_type == 4; /* R_XGATE_32. */
case EM_XSTORMY16:
return reloc_type == 2; /* R_C6000_ABS16. */
case EM_VISIUM:
return reloc_type == 2; /* R_VISIUM_16. */
- case EM_XC16X:
- case EM_C166:
- return reloc_type == 2; /* R_XC16C_ABS_16. */
case EM_XGATE:
return reloc_type == 3; /* R_XGATE_16. */
case EM_Z80:
case EM_ARC_COMPACT2: /* R_ARC_NONE. */
case EM_ARC_COMPACT: /* R_ARC_NONE. */
case EM_ARM: /* R_ARM_NONE. */
- case EM_C166: /* R_XC16X_NONE. */
case EM_CRIS: /* R_CRIS_NONE. */
case EM_FT32: /* R_FT32_NONE. */
case EM_IA_64: /* R_IA64_NONE. */
case EM_TILEPRO: /* R_TILEPRO_NONE. */
case EM_TI_C6000:/* R_C6000_NONE. */
case EM_X86_64: /* R_X86_64_NONE. */
- case EM_XC16X:
case EM_Z80: /* R_Z80_NONE. */
case EM_WEBASSEMBLY: /* R_WASM32_NONE. */
return reloc_type == 0;
+++ /dev/null
-; Infineon XC16X CPU description. -*- Scheme -*-
-;
-; Copyright 2006, 2007, 2009 Free Software Foundation, Inc.
-;
-; Contributed by KPIT Cummins Infosystems Ltd.; developed under contract
-; from Infineon Systems, GMBH , Germany.
-;
-; This file is part of the GNU Binutils.
-;
-; This program is free software; you can redistribute it and/or modify
-; it under the terms of the GNU General Public License as published by
-; the Free Software Foundation; either version 3 of the License, or
-; (at your option) any later version.
-;
-; This program is distributed in the hope that it will be useful,
-; but WITHOUT ANY WARRANTY; without even the implied warranty of
-; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-; GNU General Public License for more details.
-;
-; You should have received a copy of the GNU General Public License
-; along with this program; if not, write to the Free Software
-; Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
-; 02110-1301, USA.
-
-(define-rtl-version 0 8)
-
-(include "simplify.inc")
-
-; define-arch appears first
-
-(define-arch
- (name xc16x) ; name of cpu family
- (comment "Infineon XC16X")
- (default-alignment aligned)
- (insn-lsb0? #t)
- (machs xc16x)
- (isas xc16x)
-)
-
-; Attributes.
-; An attribute to describe which pipeline an insn runs in generally OS.
-(define-attr
- (for insn)
- (type enum)
- (name PIPE)
- (comment "parallel execution pipeline selection")
- (values NONE OS)
-)
-
-; Instruction set parameters.
-
-(define-isa
- (name xc16x)
- (default-insn-bitsize 32)
- (base-insn-bitsize 32)
- (default-insn-word-bitsize 16)
- (decode-assist (15 14 13 12))
- ; The XC16X fetches 1 insn at a time.
- (liw-insns 1)
- (parallel-insns 1)
-)
-
-; Cpu family definitions.
-
-(define-cpu
- ; cpu names must be distinct from the architecture name and machine names.
- ; The "b" suffix stands for "base" and is the convention.
- ; The "f" suffix stands for "family" and is the convention.
- (name xc16xbf)
- (comment "Infineon XC16X base family")
- (endian little)
- (insn-chunk-bitsize 32)
- (word-bitsize 16)
- (parallel-insns 1)
-)
-
-(define-mach
- (name xc16x)
- (comment "Infineon XC16X cpu")
- (cpu xc16xbf)
-)
-
-; Model descriptions.
-
-(define-model
- (name xc16x) (comment "XC16X") (attrs)
- (mach xc16x)
-
- (pipeline p-mem "" () ((prefetch) (fetch) (decode) (address) (memory) (execute) (writeback)))
-
- ; `state' is a list of variables for recording model state
- (state
- ; bit mask of h-gr registers, =1 means value being loaded from memory
- (h-gr UINT)
- )
-
- (unit u-exec "Execution Unit" ()
- 1 1 ; issue done
- () ; state
- ((dr INT -1) (sr INT -1)) ; inputs
- ((dr INT -1)) ; outputs
- () ; profile action (default)
- )
- (unit u-cmp "Compare Unit" ()
- 1 1 ; issue done
- () ; state
- ((src1 INT -1) (src2 INT -1)) ; inputs
- () ; outputs
- () ; profile action (default)
- )
- (unit u-cti "Jump & Call Unit" ()
- 1 1 ; issue done
- () ; state
- ((condbit) (sr INT -1)) ; inputs
- ((pc)) ; outputs
- () ; profile action (default)
- )
- (unit u-mov "Data Movement Unit" ()
- 1 1 ; issue done
- () ;state
- ((dr INT -1) (sr INT -1)) ; inputs
- ((dr INT -1)) ; output
- () ; profile action (default)
- )
- )
-
-; Instruction fields.
-;
-; Attributes:
-; PCREL-ADDR: pc relative value (for reloc and disassembly purposes)
-; ABS-ADDR: absolute address (for reloc and disassembly purposes)
-; RELOC: there is a relocation associated with this field (experiment)
-
-(define-attr
- (for ifield operand)
- (type boolean)
- (name RELOC)
- (comment "there is a reloc associated with this field (experiment)")
-)
-
-(dnf f-op1 "op1" () 7 4)
-(dnf f-op2 "op2" () 3 4)
-(dnf f-condcode "condcode" () 7 4) ;condition code required in other jmps and calls
-(dnf f-icondcode "indrct condcode" () 15 4) ;condition code required in other jmpi and calli
-(dnf f-rcond "relative-cond" () 7 4) ;condition code required in JMPR
-(dnf f-qcond "qbit" () 7 4) ;used in enum of bset/bclear macro
-(dnf f-extccode "extended condcode" () 15 5) ;condition code required in other jmpa and calla
-(dnf f-r0 "r0" () 9 2) ;required where 2 bit register used(only R0-R3)
-(dnf f-r1 "r1" () 15 4)
-(dnf f-r2 "r2" () 11 4)
-(dnf f-r3 "r3" () 12 4)
-(dnf f-r4 "r4" () 11 4)
-(dnf f-uimm2 "uimm2" () 13 2) ;used for immediate data,eg in ADD,MOV insns
-(dnf f-uimm3 "uimm3" () 10 3) ;used for immediate data,eg in ADD,SUB insns
-(dnf f-uimm4 "uimm4" () 15 4) ;used for immediate data,eg in MOV insns
-(dnf f-uimm7 "uimm7" (PCREL-ADDR RELOC) 15 7) ;used in TRAP
-(dnf f-uimm8 "uimm8" () 23 8) ;used in immediate byte data,eg in ADDB,MOVB insns
-(dnf f-uimm16 "uimm16" () 31 16) ;used for immediate word data
-(dnf f-memory "memory" () 31 16) ; used for memory operands
-(dnf f-memgr8 "memory" () 31 16) ; memory location of gr
-(dnf f-rel8 "rel8" (PCREL-ADDR RELOC) 15 8) ;used in JMPR,CALLR
-(dnf f-relhi8 "relhi8" (PCREL-ADDR RELOC) 23 8) ;used in JB,JBC,JNB,JNBS
-(dnf f-reg8 "reg8" () 15 8) ;required where 8bit gp register used
-(dnf f-regmem8 "regmem8" () 15 8) ;required where 8bit register used
-(dnf f-regoff8 "regoff8" () 15 8) ;required for offset calc
-(dnf f-reghi8 "reghi8" () 23 8) ;required where 8bit register number used
-(dnf f-regb8 "regb8" () 15 8) ;required for byte registers RL0,RH0, till RL8,RH8
-(dnf f-seg8 "seg8" () 15 8) ;used as segment number in JMPS,CALLS
-(dnf f-segnum8 "segnum8" () 23 8) ;used in EXTS,EXTSR
-(dnf f-mask8 "mask8" () 23 8) ;used as mask in BFLDH,BFLDL insns
-(dnf f-pagenum "page num" () 25 10);used in EXTP,EXTPR
-(dnf f-datahi8 "datahi8" () 31 8) ;used for filling with const data
-(dnf f-data8 "data8" () 23 8) ;used for filling with const data
-(dnf f-offset16 "address offset16" (ABS-ADDR RELOC) 31 16) ;used in JMPS,JMPA,CALLA,CALLS
-(dnf f-op-bit1 "gap of 1 bit" () 11 1) ;used for filling with const data
-(dnf f-op-bit2 "gap of 2 bits" () 11 2) ;used for filling with const data
-(dnf f-op-bit4 "gap of 4 bits" () 11 4) ;used for filling with const data
-(dnf f-op-bit3 "gap of 3 bits" () 10 3) ;used in CALLA, JMPA
-(dnf f-op-2bit "gap of 2 bits" () 10 2) ;used in CALLA
-(dnf f-op-bitone "gap of 1 bit " () 10 1) ;used in JMPA
-(dnf f-op-onebit "gap of 1 bit " () 9 1) ;used in JMPA
-(dnf f-op-1bit "gap of 1 bit " () 8 1) ;used in JMPA, CALLA
-(dnf f-op-lbit4 "gap of 4 bits" () 15 4) ;used for filling with const data
-(dnf f-op-lbit2 "gap of 2 bits" () 15 2) ;used for filling with const data
-(dnf f-op-bit8 "gap of 8 bits" () 31 8) ;used for filling with const data
-(dnf f-op-bit16 "gap of 16 bits" () 31 16) ;used for filling with const data
-(dnf f-qbit "qbit" () 7 4) ;used in bit field of bset/bclear
-(dnf f-qlobit "qlobit" () 31 4) ;used for filling with const data
-(dnf f-qhibit "qhibit" () 27 4) ;used for filling with const data
-(dnf f-qlobit2 "qlobit2" () 27 2) ;used for filling with const data
-(dnf f-pof "upof16" () 31 16) ; used for memory operands
-
-; Enums.
-; insn-op1: bits 0-3
-(define-normal-insn-enum insn-op1 "insn format enums" () OP1_ f-op1
- ("0" "1" "2" "3" "4" "5" "6" "7"
- "8" "9" "10" "11" "12" "13" "14" "15")
-)
-
-; insn-op2: bits 4-7
-(define-normal-insn-enum insn-op2 "op2 enums" () OP2_ f-op2
- ("0" "1" "2" "3" "4" "5" "6" "7"
- "8" "9" "10" "11" "12" "13" "14" "15")
-)
-
-;/*for bclr/bset*/
-; insn-rcond: bits 0-3
-(define-normal-insn-enum insn-qcond "bit set/clear enums" () QBIT_ f-qcond
- (("0" 0) ("1" 1) ("2" 2) ("3" 3) ("4" 4) ("5" 5) ("6" 6) ("7" 7) ("8" 8) ("9" 9) ("10" 10)
- ("11" 11) ("12" 12) ("13" 13) ("14" 14) ("15" 15))
-)
-;/************/
-; insn-rcond: bits 0-3
-(define-normal-insn-enum insn-rcond "relative jump condition code op2 enums" () COND_ f-rcond
- (("UC" 0) ("NET" 1) ("Z" 2) ("NE_NZ" 3) ("V" 4) ("NV" 5) ("N" 6) ("NN" 7)
- ("C" 8) ("NC" 9) ("SGT" 10) ("SLE" 11) ("SLT" 12) ("SGE" 13) ("UGT" 14) ("ULE" 15)
- ("EQ" 2) ("NE" 3) ("ULT" 8) ("UGE" 9))
-)
-
-
-
-; Hardware pieces.
-; These entries list the elements of the raw hardware.
-; They're also used to provide tables and other elements of the assembly
-; language.
-
-(dnh h-pc "program counter" (PC) (pc) () () ())
-
-(define-keyword
- (name gr-names)
- (enum-prefix H-GR-)
- (values (r0 0) (r1 1) (r2 2) (r3 3) (r4 4) (r5 5) (r6 6) (r7 7)
- (r8 8) (r9 9) (r10 10) (r11 11) (r12 12) (r13 13) (r14 14) (r15 15))
-
-)
-(define-hardware
- (name h-gr)
- (comment "general registers")
- (attrs PROFILE CACHE-ADDR)
- (type register HI (16))
- (indices extern-keyword gr-names)
-)
-
-;; HACK: Various semantics refer to h-cr.
-;; This is here to keep things working.
-(define-hardware
- (name h-cr)
- (comment "cr registers")
- (attrs PROFILE CACHE-ADDR)
- (type register HI (16))
- (indices extern-keyword gr-names)
-)
-
-(define-keyword
- (name ext-names)
- (enum-prefix H-EXT-)
- (values (0x1 0) (0x2 1) (0x3 2) (0x4 3)
- ("1" 0) ("2" 1) ("3" 2) ("4" 3))
-
-)
-
-(define-hardware
- (name h-ext)
- (comment "ext values")
- (attrs PROFILE CACHE-ADDR)
- (type register HI (8))
- (indices extern-keyword ext-names)
-)
-
-(define-keyword
- (name psw-names)
- (enum-prefix H-PSW-)
- (values ("IEN" 136) ("r0.11" 240) ("r1.11" 241) ("r2.11" 242) ("r3.11" 243) ("r4.11" 244)
- ("r5.11" 245) ("r6.11" 246) ("r7.11" 247) ("r8.11" 248)
- ("r9.11" 249) ("r10.11" 250) ("r11.11" 251) ("r12.11" 252)
- ("r13.11" 253) ("r14.11" 254) ("r15.11" 255))
-)
-
-(define-hardware
- (name h-psw)
- (comment "ext values")
- (attrs PROFILE CACHE-ADDR)
- (type register HI (1))
- (indices extern-keyword psw-names)
-)
-
-(define-keyword
- (name grb-names)
- (enum-prefix H-GRB-)
- (values (rl0 0) (rh0 1) (rl1 2) (rh1 3) (rl2 4) (rh2 5) (rl3 6) (rh3 7)
- (rl4 8) (rh4 9) (rl5 10) (rh5 11) (rl6 12) (rh6 13) (rl7 14) (rh7 15))
-)
-
-(define-hardware
- (name h-grb)
- (comment "general registers")
- (attrs PROFILE CACHE-ADDR)
- (type register QI (16))
- (indices extern-keyword grb-names)
-)
-
-(define-keyword
- (name conditioncode-names)
- (enum-prefix H-CC-)
- (values (cc_UC 0) (cc_NET 1) (cc_Z 2) (cc_EQ 2) (cc_NZ 3) (cc_NE 3) (cc_V 4) (cc_NV 5) (cc_N 6) (cc_NN 7) (cc_ULT 8) (cc_UGE 9)
- (cc_C 8) (cc_NC 9) (cc_SGT 10) (cc_SLE 11) (cc_SLT 12) (cc_SGE 13) (cc_UGT 14)
- (cc_ULE 15))
-)
-(define-hardware
- (name h-cc)
- (comment "condition codes")
- (attrs PROFILE CACHE-ADDR)
- (type register QI (16))
- (indices extern-keyword conditioncode-names)
-)
-
-(define-keyword
- (name extconditioncode-names)
- (enum-prefix H-ECC-)
- (values(cc_UC 0) (cc_NET 2) (cc_Z 4) (cc_EQ 4) (cc_NZ 6) (cc_NE 6) (cc_V 8) (cc_NV 10) (cc_N 12) (cc_NN 14) (cc_ULT 16) (cc_UGE 18) (cc_C 16) (cc_NC 18) (cc_SGT 20)
- (cc_SLE 22) (cc_SLT 24) (cc_SGE 26) (cc_UGT 28) (cc_ULE 30) (cc_nusr0 1)
- (cc_nusr1 3) (cc_usr0 5) (cc_usr1 7))
-)
-(define-hardware
- (name h-ecc)
- (comment "extended condition codes")
- (attrs PROFILE CACHE-ADDR)
- (type register QI (4))
- (indices extern-keyword extconditioncode-names)
-)
-
-(define-keyword
- (name grb8-names)
- (enum-prefix H-GRB8-)
- (values (dpp0 0) (dpp1 1) (dpp2 2) (dpp3 3)
- (psw 136) (cp 8) (mdl 7) (mdh 6)
- (mdc 135) (sp 9) (csp 4) (vecseg 137)
- (stkov 10) (stkun 11) (cpucon1 12) (cpucon2 13)
- (zeros 142) (ones 143) (spseg 134) (tfr 214)
- (rl0 240) (rh0 241) (rl1 242) (rh1 243) (rl2 244) (rh2 245) (rl3 246) (rh3 247)
- (rl4 248) (rh4 249) (rl5 250) (rh5 251) (rl6 252) (rh6 253) (rl7 254) (rh7 255))
-)
-
-(define-hardware
- (name h-grb8)
- (comment "general byte registers")
- (attrs PROFILE CACHE-ADDR)
- (type register QI (36))
- (indices extern-keyword grb8-names)
-)
-
-(define-keyword
- (name r8-names)
- (enum-prefix H-R8-)
- (values (dpp0 0) (dpp1 1) (dpp2 2) (dpp3 3)
- (psw 136) (cp 8) (mdl 7) (mdh 6)
- (mdc 135) (sp 9) (csp 4) (vecseg 137)
- (stkov 10) (stkun 11) (cpucon1 12) (cpucon2 13)
- (zeros 142) (ones 143) (spseg 134) (tfr 214)
- (r0 240) (r1 241) (r2 242) (r3 243) (r4 244) (r5 245) (r6 246) (r7 247)
- (r8 248) (r9 249) (r10 250) (r11 251) (r12 252) (r13 253) (r14 254) (r15 255))
-)
-
-(define-hardware
- (name h-r8)
- (comment "registers")
- (attrs PROFILE CACHE-ADDR)
- (type register HI (36))
- (indices extern-keyword r8-names)
-)
-
-(define-keyword
- (name regmem8-names)
- (enum-prefix H-REGMEM8-)
- (values (dpp0 0) (dpp1 1) (dpp2 2) (dpp3 3)
- (psw 136) (cp 8) (mdl 7) (mdh 6)
- (mdc 135) (sp 9) (csp 4) (vecseg 137)
- (stkov 10) (stkun 11) (cpucon1 12) (cpucon2 13)
- (zeros 142) (ones 143) (spseg 134) (tfr 214)
- (r0 240) (r1 241) (r2 242) (r3 243) (r4 244) (r5 245) (r6 246) (r7 247)
- (r8 248) (r9 249) (r10 250) (r11 251) (r12 252) (r13 253) (r14 254) (r15 255))
-)
-
-(define-hardware
- (name h-regmem8)
- (comment "registers")
- (attrs )
- (type register HI (16))
- (indices extern-keyword regmem8-names)
-)
-
-(define-keyword
- (name regdiv8-names)
- (enum-prefix H-REGDIV8-)
- (values (r0 0) (r1 17) (r2 34) (r3 51) (r4 68) (r5 85) (r6 102) (r7 119)
- (r8 136) (r9 153) (r10 170) (r11 187) (r12 204) (r13 221) (r14 238) (r15 255))
-)
-
-(define-hardware
- (name h-regdiv8)
- (comment "division insn registers")
- (attrs PROFILE CACHE-ADDR)
- (type register HI (16))
- (indices extern-keyword regdiv8-names)
-)
-
-(define-keyword
- (name reg0-name)
- (enum-prefix H-REG0-)
- (values (0x1 1) (0x2 2) (0x3 3) (0x4 4) (0x5 5) (0x6 6) (0x7 7) (0x8 8) (0x9 9) (0xa 10) (0xb 11)
- (0xc 12) (0xd 13) (0xe 14) (0xf 15)
- ("1" 1) ("2" 2) ("3" 3) ("4" 4) ("5" 5) ("6" 6) ("7" 7) ("8" 8) ("9" 9) ("10" 10) ("11" 11)
- ("12" 12) ("13" 13) ("14" 14) ("15" 15))
-)
-
-(define-hardware
- (name h-r0)
- (comment "for 4-bit data excuding 0")
- (attrs PROFILE CACHE-ADDR)
- (type register HI (30))
- (indices extern-keyword reg0-name)
-)
-
-(define-keyword
- (name reg0-name1)
- (enum-prefix H-REG01-)
- (values (0x1 1) (0x2 2) (0x3 3) (0x4 4) (0x5 5) (0x6 6) (0x7 7)
- ("1" 1) ("2" 2) ("3" 3) ("4" 4) ("5" 5) ("6" 6) ("7" 7))
-)
-
-(define-hardware
- (name h-r01)
- (comment "for 4-bit data excuding 0")
- (attrs PROFILE CACHE-ADDR)
- (type register HI (14))
- (indices extern-keyword reg0-name1)
-)
-
-(define-keyword
- (name regbmem8-names)
- (enum-prefix H-REGBMEM8-)
- (values (dpp0 0) (dpp1 1) (dpp2 2) (dpp3 3)
- (psw 136) (cp 8) (mdl 7) (mdh 6)
- (mdc 135) (sp 9) (csp 4) (vecseg 137)
- (stkov 10) (stkun 11) (cpucon1 12) (cpucon2 13)
- (zeros 142) (ones 143) (spseg 134) (tfr 214)
- (rl0 240) (rh0 241) (rl1 242) (rh1 243) (rl2 244) (rh2 245) (rl3 246) (rh3 247)
- (rl4 248) (rh4 249) (rl5 250) (rh5 251) (rl6 252) (rh6 253) (rl7 254) (rh7 255))
-)
-
-(define-hardware
- (name h-regbmem8)
- (comment "registers")
- (attrs PROFILE CACHE-ADDR)
- (type register HI (36))
- (indices extern-keyword regbmem8-names)
-)
-
-(define-keyword
- (name memgr8-names)
- (enum-prefix H-MEMGR8-)
- (values (dpp0 65024) (dpp1 65026) (dpp2 65028) (dpp3 65030)
- (psw 65296) (cp 65040) (mdl 65038) (mdh 65036)
- (mdc 65294) (sp 65042) (csp 65032) (vecseg 65298)
- (stkov 65044) (stkun 65046) (cpucon1 65048) (cpucon2 65050)
- (zeros 65308) (ones 65310) (spseg 65292) (tfr 65452) )
-)
-
-(define-hardware
- (name h-memgr8)
- (comment "memory location of registers")
- (attrs )
- (type register HI (20))
- (indices extern-keyword memgr8-names)
-)
-
-(dsh h-cond "condition bit" () (register BI)) ;any bit from PSW while comparison
-; This bit is part of the PSW register
-(dsh h-cbit "carry bit" () (register BI))
-
-(dsh h-sgtdis "segmentation enable bit" () (register BI)) ;0 means segmentation enabled
-
-;Instruction operands
-; -- layer between the assembler and the raw hardware description
-; -- the main means of manipulating instruction fields in the semantic code
-
-; XC16X specific operand attributes:
-
-(define-attr
- (for operand)
- (type boolean)
- (name HASH-PREFIX)
- (comment "immediates have an optional '#' prefix")
-)
-
-(define-attr
- (for operand)
- (type boolean)
- (name DOT-PREFIX)
- (comment "bit addr have an optional '.' prefix")
-)
-
-(define-attr
- (for operand)
- (type boolean)
- (name POF-PREFIX)
- (comment "page offset ")
-)
-
-(define-attr
- (for operand)
- (type boolean)
- (name PAG-PREFIX)
- (comment "page ")
-)
-
-(define-attr
- (for operand)
- (type boolean)
- (name SOF-PREFIX)
- (comment "segment offset selection")
-)
-
-(define-attr
- (for operand)
- (type boolean)
- (name SEG-PREFIX)
- (comment "segment")
-)
-
-;; Define an operand that takes a set of handlers.
-;; dowh: define-operand-with-handlers
-(define-pmacro (dowh x-name x-comment x-attrs x-type x-index x-handlers)
- (define-operand (name x-name) (comment x-comment)
- (.splice attrs (.unsplice x-attrs))
- (type x-type) (index x-index)
- (.splice handlers (.unsplice x-handlers)))
-)
-
-(dnop sr "source register" () h-gr f-r2)
-(dnop dr "destination register" () h-gr f-r1)
-(dnop dri "destination register" () h-gr f-r4)
-(dnop srb "source register" () h-grb f-r2)
-(dnop drb "destination register" () h-grb f-r1)
-(dnop sr2 "2 bit source register" () h-gr f-r0)
-(dnop src1 "source register 1" () h-gr f-r1)
-(dnop src2 "source register 2" () h-gr f-r2)
-(dnop srdiv "source register 2" () h-regdiv8 f-reg8)
-(dnop RegNam "PSW bits" () h-psw f-reg8)
-(dnop uimm2 "2 bit unsigned number" (HASH-PREFIX) h-ext f-uimm2)
-(dnop uimm3 "3 bit unsigned number" (HASH-PREFIX) h-r01 f-uimm3)
-(dnop uimm4 "4 bit unsigned number" (HASH-PREFIX) h-uint f-uimm4)
-(dnop uimm7 "7 bit trap number" (HASH-PREFIX) h-uint f-uimm7)
-(dnop uimm8 "8 bit unsigned immediate" (HASH-PREFIX) h-uint f-uimm8)
-(dnop uimm16 "16 bit unsigned immediate" (HASH-PREFIX) h-uint f-uimm16)
-(dowh upof16 "16 bit unsigned immediate" (POF-PREFIX) h-addr f-memory ((print "with_pof_prefix")))
-(dnop reg8 "8 bit word register number" () h-r8 f-reg8)
-(dnop regmem8 "8 bit word register number" () h-regmem8 f-regmem8)
-(dnop regbmem8 "8 bit byte register number" () h-regbmem8 f-regmem8)
-(dnop regoff8 "8 bit word register number" () h-r8 f-regoff8)
-(dnop reghi8 "8 bit word register number" () h-r8 f-reghi8)
-(dnop regb8 "8 bit byte register number" () h-grb8 f-regb8)
-(dnop genreg "8 bit word register number" () h-r8 f-regb8)
-(dnop seg "8 bit segment number" () h-uint f-seg8)
-(dnop seghi8 "8 bit hi segment number" () h-uint f-segnum8)
-(dnop caddr "16 bit address offset" () h-addr f-offset16)
-(dnop rel "8 bit signed relative offset" () h-sint f-rel8)
-(dnop relhi "hi 8 bit signed relative offset" () h-sint f-relhi8)
-(dnop condbit "condition bit" (SEM-ONLY) h-cond f-nil)
-(dnop bit1 "gap of 1 bit" () h-uint f-op-bit1)
-(dnop bit2 "gap of 2 bits" () h-uint f-op-bit2)
-(dnop bit4 "gap of 4 bits" () h-uint f-op-bit4)
-(dnop lbit4 "gap of 4 bits" () h-uint f-op-lbit4)
-(dnop lbit2 "gap of 2 bits" () h-uint f-op-lbit2)
-(dnop bit8 "gap of 8 bits" () h-uint f-op-bit8)
-(dnop u4 "gap of 4 bits" () h-r0 f-uimm4)
-(dnop bitone "field of 1 bit" () h-uint f-op-onebit)
-(dnop bit01 "field of 1 bit" () h-uint f-op-1bit)
-(dnop cond "condition code" () h-cc f-condcode)
-(dnop icond "indirect condition code" () h-cc f-icondcode)
-(dnop extcond "extended condition code" () h-ecc f-extccode)
-(dnop memory "16 bit memory" () h-addr f-memory)
-(dnop memgr8 "16 bit memory" () h-memgr8 f-memgr8)
-(dnop cbit "carry bit" (SEM-ONLY) h-cbit f-nil)
-(dowh qbit "bit addr" (DOT-PREFIX) h-uint f-qbit ((print "with_dot_prefix")))
-(dowh qlobit "bit addr" (DOT-PREFIX) h-uint f-qlobit ((print "with_dot_prefix")))
-(dowh qhibit "bit addr" (DOT-PREFIX) h-uint f-qhibit ((print "with_dot_prefix")))
-(dnop mask8 "8 bit mask" (HASH-PREFIX) h-uint f-mask8)
-(dnop masklo8 "8 bit mask" (HASH-PREFIX) h-uint f-datahi8)
-(dnop pagenum "10 bit page number" (HASH-PREFIX) h-uint f-pagenum)
-(dnop data8 "8 bit data" (HASH-PREFIX) h-uint f-data8)
-(dnop datahi8 "8 bit data" (HASH-PREFIX) h-uint f-datahi8)
-(dnop sgtdisbit "segmentation enable bit" (SEM-ONLY) h-sgtdis f-nil)
-(dowh upag16 "16 bit unsigned immediate" (PAG-PREFIX) h-uint f-uimm16 ((print "with_pag_prefix")))
-(dnop useg8 "8 bit segment " (SEG-PREFIX) h-uint f-seg8)
-(dnop useg16 "16 bit address offset" (SEG-PREFIX) h-uint f-offset16)
-(dnop usof16 "16 bit address offset" (SOF-PREFIX) h-uint f-offset16)
-
-; define hash operator
-(define-operand (name hash) (comment "# prefix") (attrs)
- (type h-sint)
- (index f-nil)
- (handlers (parse "hash") (print "hash"))
-)
-
-; define dot operator
-(define-operand (name dot) (comment ". prefix") (attrs)
- (type h-sint)
- (index f-nil)
- (handlers (parse "dot") (print "dot"))
-)
-
-; define pof operator
-(define-operand (name pof) (comment "pof: prefix") (attrs)
- (type h-sint)
- (index f-nil)
- (handlers (parse "pof") (print "pof"))
-)
-
-; define pag operator
-(define-operand (name pag) (comment "pag: prefix") (attrs)
- (type h-sint)
- (index f-nil)
- (handlers (parse "pag") (print "pag"))
-)
-
-; define sof operator
-(define-operand (name sof) (comment "sof: prefix") (attrs)
- (type h-sint)
- (index f-nil)
- (handlers (parse "sof") (print "sof"))
-)
-
-; define seg operator
-(define-operand (name segm) (comment "seg: prefix") (attrs)
- (type h-sint)
- (index f-nil)
- (handlers (parse "seg") (print "seg"))
-)
-
-; IDOC attribute for instruction documentation.
-(define-attr
- (for insn)
- (type enum)
- (name IDOC)
- (comment "insn kind for documentation")
- (attrs META)
- (values
- (MOVE - () "Data Movement")
- (ALU - () "Arithmatic & logical")
- (CMP - () "Compare")
- (JMP - () "Jump & Call")
- (MISC - () "Miscellaneous")
- (SYSC - () "System control")
- )
-)
-
-; Include the instruction set descriptions from their respective
-; source files.
-
-;Arithmatic insns
-;******************************************************************
-
-;add/sub register and immediate
-(define-pmacro (arithmetic16 name insn insn1 opc1 opc2 op1 op2 mode dir)
- (dni name
- (.str name "arithmetic" )
- ((PIPE OS) (IDOC ALU))
- (.str insn " $"op1 ",$"dir"$"op2)
- (+ opc1 opc2 op1 op2)
- (set mode op1 (insn1 mode op1 (mem HI op2)))
- ()
- )
-)
-(arithmetic16 addrpof add add OP1_0 OP2_2 reg8 upof16 HI "pof")
-(arithmetic16 subrpof sub sub OP1_2 OP2_2 reg8 upof16 HI "pof")
-(arithmetic16 addbrpof addb add OP1_0 OP2_3 regb8 upof16 QI "pof")
-(arithmetic16 subbrpof subb sub OP1_2 OP2_3 regb8 upof16 QI "pof")
-(arithmetic16 addrpag add add OP1_0 OP2_2 reg8 upag16 HI "pag")
-(arithmetic16 subrpag sub sub OP1_2 OP2_2 reg8 upag16 HI "pag")
-(arithmetic16 addbrpag addb add OP1_0 OP2_3 regb8 upag16 QI "pag")
-(arithmetic16 subbrpag subb sub OP1_2 OP2_3 regb8 upag16 QI "pag")
-
-;add/sub register and immediate
-(define-pmacro (arithmetic17 name insn insn1 opc1 opc2 op1 op2 mode dir)
- (dni name
- (.str name "arithmetic" )
- ((PIPE OS) (IDOC ALU))
- (.str insn " $"op1 ",$"dir"$"op2)
- (+ opc1 opc2 op1 op2)
- (set mode op1 (insn1 mode op1 (mem HI op2) cbit))
- ()
- )
-)
-(arithmetic17 addcrpof addc addc OP1_1 OP2_2 reg8 upof16 HI "pof")
-(arithmetic17 subcrpof subc subc OP1_3 OP2_2 reg8 upof16 HI "pof")
-(arithmetic17 addcbrpof addcb addc OP1_1 OP2_3 regb8 upof16 QI "pof")
-(arithmetic17 subcbrpof subcb subc OP1_3 OP2_3 regb8 upof16 QI "pof")
-(arithmetic17 addcrpag addc addc OP1_1 OP2_2 reg8 upag16 HI "pag")
-(arithmetic17 subcrpag subc subc OP1_3 OP2_2 reg8 upag16 HI "pag")
-(arithmetic17 addcbrpag addcb addc OP1_1 OP2_3 regb8 upag16 QI "pag")
-(arithmetic17 subcbrpag subcb subc OP1_3 OP2_3 regb8 upag16 QI "pag")
-
-;add/sub register and immediate
-(define-pmacro (arithmetic18 name insn insn1 opc1 opc2 op1 op2 mode dir)
- (dni name
- (.str name "arithmetic" )
- ((PIPE OS) (IDOC ALU))
- (.str insn " $"dir"$"op1 ",$"op2)
- (+ opc1 opc2 op2 op1)
- (set (mem HI op1) (insn1 (mem HI op1) op2 ))
- ()
- )
-)
-(arithmetic18 addrpofr add add OP1_0 OP2_4 upof16 reg8 HI "pof")
-(arithmetic18 subrpofr sub sub OP1_2 OP2_4 upof16 reg8 HI "pof")
-(arithmetic18 addbrpofr addb add OP1_0 OP2_5 upof16 regb8 QI "pof")
-(arithmetic18 subbrpofr subb sub OP1_2 OP2_5 upof16 regb8 QI "pof")
-
-;add/sub register and immediate
-(define-pmacro (arithmetic19 name insn insn1 opc1 opc2 op1 op2 mode dir)
- (dni name
- (.str name "arithmetic" )
- ((PIPE OS) (IDOC ALU))
- (.str insn " $"dir"$"op1 ",$"op2)
- (+ opc1 opc2 op2 op1)
- (set (mem HI op1) (insn1 mode (mem HI op1) op2 cbit))
- ()
- )
-)
-(arithmetic19 addcrpofr addc addc OP1_1 OP2_4 upof16 reg8 HI "pof")
-(arithmetic19 subcrpofr subc subc OP1_3 OP2_4 upof16 reg8 HI "pof")
-(arithmetic19 addcbrpofr addcb addc OP1_1 OP2_5 upof16 regb8 QI "pof")
-(arithmetic19 subcbrpofr subcb subc OP1_3 OP2_5 upof16 regb8 QI "pof")
-
-;add/sub register and immediate
-(define-pmacro (arithmetic20 name insn insn1 opc1 opc2 op1 op2 mode dir)
- (dni name
- (.str name "arithmetic" )
- ((PIPE OS) (IDOC ALU))
- (.str insn " $"op1 ",$hash$"dir"$"op2)
- (+ opc1 opc2 op1 op2)
- (set mode op1 (insn1 mode op1 op2))
- ()
- )
-)
-(arithmetic20 addrhpof add add OP1_0 OP2_6 reg8 uimm16 HI "pof")
-(arithmetic20 subrhpof sub sub OP1_2 OP2_6 reg8 uimm16 HI "pof")
-(arithmetic20 addbrhpof add add OP1_0 OP2_6 reg8 uimm16 HI "pag")
-(arithmetic20 subbrhpof sub sub OP1_2 OP2_6 reg8 uimm16 HI "pag")
-
-;add/sub register and immediate
-(define-pmacro (arithmetic21 name insn insn1 opc1 opc2 op1 op2 mode dir)
- (dni name
- (.str name "arithmetic" )
- ((PIPE OS) (IDOC ALU))
- (.str insn " $"op1 ",$hash$"dir"$"op2)
- (+ opc1 opc2 op1 (f-op-bit1 0) op2)
- (set mode op1 (insn1 mode op1 op2))
- ()
- )
-)
-(arithmetic21 addrhpof3 add add OP1_0 OP2_8 dr uimm3 HI "pof")
-(arithmetic21 subrhpof3 sub sub OP1_2 OP2_8 dr uimm3 HI "pof")
-(arithmetic21 addbrhpag3 addb add OP1_0 OP2_9 drb uimm3 QI "pag")
-(arithmetic21 subbrhpag3 subb sub OP1_2 OP2_9 drb uimm3 QI "pag")
-(arithmetic21 addrhpag3 add add OP1_0 OP2_8 dr uimm3 HI "pag")
-(arithmetic21 subrhpag3 sub sub OP1_2 OP2_8 dr uimm3 HI "pag")
-(arithmetic21 addbrhpof3 addb add OP1_0 OP2_9 drb uimm3 QI "pof")
-(arithmetic21 subbrhpof3 subb sub OP1_2 OP2_9 drb uimm3 QI "pof")
-
-;add/sub register and immediate
-(define-pmacro (arithmetic22 name insn insn1 opc1 opc2 op1 op2 mode dir)
- (dni name
- (.str name "arithmetic" )
- ((PIPE OS) (IDOC ALU))
- (.str insn " $"op1 ",$hash$"dir"$"op2)
- (+ opc1 opc2 op1 op2 (f-op-bit8 0))
- (set mode op1 (insn1 mode op1 op2))
- ()
- )
-)
-(arithmetic22 addrbhpof addb add OP1_0 OP2_7 regb8 uimm8 QI "pof")
-(arithmetic22 subrbhpof subb sub OP1_2 OP2_7 regb8 uimm8 QI "pof")
-(arithmetic22 addbrhpag addb add OP1_0 OP2_7 regb8 uimm8 QI "pag")
-(arithmetic22 subbrhpag subb sub OP1_2 OP2_7 regb8 uimm8 QI "pag")
-
-;add/sub register and immediate
-(define-pmacro (arithmetic23 name insn insn1 opc1 opc2 op1 op2 mode dir)
- (dni name
- (.str name "arithmetic" )
- ((PIPE OS) (IDOC ALU))
- (.str insn " $"op1 ",$hash$"dir"$"op2)
- (+ opc1 opc2 op1 op2)
- (set mode op1 (insn1 mode op1 op2 cbit))
- ()
- )
-)
-(arithmetic23 addcrhpof addc addc OP1_1 OP2_6 reg8 uimm16 HI "pof")
-(arithmetic23 subcrhpof subc subc OP1_3 OP2_6 reg8 uimm16 HI "pof")
-(arithmetic23 addcbrhpof addc addc OP1_1 OP2_6 reg8 uimm16 HI "pag")
-(arithmetic23 subcbrhpof subc subc OP1_3 OP2_6 reg8 uimm16 HI "pag")
-
-;add/sub register and immediate
-(define-pmacro (arithmetic24 name insn insn1 opc1 opc2 op1 op2 mode dir)
- (dni name
- (.str name "arithmetic" )
- ((PIPE OS) (IDOC ALU))
- (.str insn " $"op1 ",$hash$"dir"$"op2)
- (+ opc1 opc2 op1 (f-op-bit1 0) op2)
- (set mode op1 (insn1 mode op1 op2 cbit))
- ()
- )
-)
-(arithmetic24 addcrhpof3 addc addc OP1_1 OP2_8 dr uimm3 HI "pof")
-(arithmetic24 subcrhpof3 subc subc OP1_3 OP2_8 dr uimm3 HI "pof")
-(arithmetic24 addcbrhpag3 addcb addc OP1_1 OP2_9 drb uimm3 QI "pag")
-(arithmetic24 subcbrhpag3 subcb subc OP1_3 OP2_9 drb uimm3 QI "pag")
-(arithmetic24 addcrhpag3 addc addc OP1_1 OP2_8 dr uimm3 HI "pag")
-(arithmetic24 subcrhpag3 subc subc OP1_3 OP2_8 dr uimm3 HI "pag")
-(arithmetic24 addcbrhpof3 addcb addc OP1_1 OP2_9 drb uimm3 QI "pof")
-(arithmetic24 subcbrhpof3 subcb subc OP1_3 OP2_9 drb uimm3 QI "pof")
-
-;add/sub register and immediate
-(define-pmacro (arithmetic25 name insn insn1 opc1 opc2 op1 op2 mode dir)
- (dni name
- (.str name "arithmetic" )
- ((PIPE OS) (IDOC ALU))
- (.str insn " $"op1 ",$hash$"dir"$"op2)
- (+ opc1 opc2 op1 op2 (f-op-bit8 0))
- (set mode op1 (insn1 mode op1 op2 cbit))
- ()
- )
-)
-(arithmetic25 addcrbhpof addcb addc OP1_1 OP2_7 regb8 uimm8 QI "pof")
-(arithmetic25 subcrbhpof subcb subc OP1_3 OP2_7 regb8 uimm8 QI "pof")
-(arithmetic25 addcbrhpag addcb addc OP1_1 OP2_7 regb8 uimm8 QI "pag")
-(arithmetic25 subcbrhpag subcb subc OP1_3 OP2_7 regb8 uimm8 QI "pag")
-
-;add/sub register and immediate
-(define-pmacro (arithmetic10 name insn insn1 opc1 opc2 op1 op2 mode)
- (dni name
- (.str name "arithmetic" )
- ((PIPE OS) (IDOC ALU))
- (.str insn " $"op1 ",$hash$"op2)
- (+ opc1 opc2 op1 (f-op-bit1 0) op2)
- (set mode op1 (insn1 mode op1 op2))
- ()
- )
-)
-(arithmetic10 addri add add OP1_0 OP2_8 dr uimm3 HI)
-(arithmetic10 subri sub sub OP1_2 OP2_8 dr uimm3 HI)
-(arithmetic10 addbri addb add OP1_0 OP2_9 drb uimm3 QI)
-(arithmetic10 subbri subb sub OP1_2 OP2_9 drb uimm3 QI)
-
-;add/sub register and immediate
-(define-pmacro (arithmetic11 name insn insn1 opc1 opc2 op1 op2 mode)
- (dni name
- (.str name "arithmetic" )
- ((PIPE OS) (IDOC ALU))
- (.str insn " $"op1 ",$hash$"op2)
- (+ opc1 opc2 op1 op2)
- (set mode op1 (insn1 mode op1 op2))
- ()
- )
-)
-(arithmetic11 addrim add add OP1_0 OP2_6 reg8 uimm16 HI)
-(arithmetic11 subrim sub sub OP1_2 OP2_6 reg8 uimm16 HI)
-
-;add/sub register and immediate
-(define-pmacro (arithmetic12 name insn insn1 opc1 opc2 op1 op2 mode)
- (dni name
- (.str name "arithmetic" )
- ((PIPE OS) (IDOC ALU))
- (.str insn " $"op1 ",$hash$"op2)
- (+ opc1 opc2 op1 op2 (f-op-bit8 0))
- (set mode op1 (insn1 mode op1 op2))
- ()
- )
-)
-(arithmetic12 addbrim addb add OP1_0 OP2_7 regb8 uimm8 QI)
-(arithmetic12 subbrim subb sub OP1_2 OP2_7 regb8 uimm8 QI)
-
-;add/sub register and immediate with carry
-(define-pmacro (arithmetic13 name insn insn1 opc1 opc2 op1 op2 mode)
- (dni name
- (.str name "arithmetic" )
- ((PIPE OS) (IDOC ALU))
- (.str insn " $"op1 ",$hash$"op2)
- (+ opc1 opc2 op1 (f-op-bit1 0) op2)
- (set mode op1 (insn1 mode op1 op2 cbit))
- ()
- )
-)
-(arithmetic13 addcri addc addc OP1_1 OP2_8 dr uimm3 HI)
-(arithmetic13 subcri subc subc OP1_3 OP2_8 dr uimm3 HI)
-(arithmetic13 addcbri addcb addc OP1_1 OP2_9 drb uimm3 QI)
-(arithmetic13 subcbri subcb subc OP1_3 OP2_9 drb uimm3 QI)
-
-;add/sub register and immediate with carry
-(define-pmacro (arithmetic14 name insn insn1 opc1 opc2 op1 op2 mode)
- (dni name
- (.str name "arithmetic" )
- ((PIPE OS) (IDOC ALU))
- (.str insn " $"op1 ",$hash$"op2)
- (+ opc1 opc2 op1 op2)
- (set mode op1 (insn1 mode op1 op2 cbit))
- ()
- )
-)
-(arithmetic14 addcrim addc addc OP1_1 OP2_6 reg8 uimm16 HI)
-(arithmetic14 subcrim subc subc OP1_3 OP2_6 reg8 uimm16 HI)
-
-;add/sub register and immediate with carry
-(define-pmacro (arithmetic15 name insn insn1 opc1 opc2 op1 op2 mode)
- (dni name
- (.str name "arithmetic" )
- ((PIPE OS) (IDOC ALU))
- (.str insn " $"op1 ",$hash$"op2)
- (+ opc1 opc2 op1 op2 (f-op-bit8 0))
- (set mode op1 (insn1 mode op1 op2 cbit))
- ()
- )
-)
-(arithmetic15 addcbrim addcb addc OP1_1 OP2_7 regb8 uimm8 QI)
-(arithmetic15 subcbrim subcb subc OP1_3 OP2_7 regb8 uimm8 QI)
-
-
-;add/sub registers
-(define-pmacro (arithmetic name insn insn1 opc1 opc2 op1 op2 mode)
- (dni name
- (.str name "arithmetic" )
- ((PIPE OS) (IDOC ALU))
- (.str insn " $"op1 ",$"op2)
- (+ opc1 opc2 op1 op2)
- (set mode op1 (insn1 mode op1 op2))
- ()
- )
-)
-(arithmetic addr add add OP1_0 OP2_0 dr sr HI)
-(arithmetic subr sub sub OP1_2 OP2_0 dr sr HI)
-(arithmetic addbr addb add OP1_0 OP2_1 drb srb QI)
-(arithmetic subbr subb sub OP1_2 OP2_1 drb srb QI)
-
-;add/sub register and indirect memory
-(define-pmacro (arithmetic1 name insn insn1 opc1 opc2 op1 op2 mode)
- (dni name
- (.str name "arithmetic" )
- ((PIPE OS) (IDOC ALU))
- (.str insn " $"op1 ",[$"op2"]")
- (+ opc1 opc2 op1 (f-op-bit2 2) op2)
- (set mode op1 (insn1 mode op1 (mem HI op2)))
- ()
- )
-)
-(arithmetic1 add2 add add OP1_0 OP2_8 dr sr2 HI)
-(arithmetic1 sub2 sub sub OP1_2 OP2_8 dr sr2 HI)
-(arithmetic1 addb2 addb add OP1_0 OP2_9 drb sr2 QI)
-(arithmetic1 subb2 subb sub OP1_2 OP2_9 drb sr2 QI)
-
-;add/sub register and indirect memory post increment
-(define-pmacro (arithmetic2 name insn insn1 opc1 opc2 op1 op2 mode)
- (dni name
- (.str name "arithmetic" )
- ((PIPE OS) (IDOC ALU))
- (.str insn " $"op1 ",[$"op2"+]")
- (+ opc1 opc2 op1 (f-op-bit2 3) op2)
- (sequence ()
- (set mode op1 (insn1 mode op1 (mem HI op2)))
- (set HI op2 (add HI op2 (const 2)))
- )
- ()
- )
-)
-(arithmetic2 add2i add add OP1_0 OP2_8 dr sr2 HI)
-(arithmetic2 sub2i sub sub OP1_2 OP2_8 dr sr2 HI)
-(arithmetic2 addb2i addb add OP1_0 OP2_9 drb sr2 QI)
-(arithmetic2 subb2i subb sub OP1_2 OP2_9 drb sr2 QI)
-
-;add/sub registers with carry
-(define-pmacro (arithmetic3 name insn insn1 opc1 opc2 op1 op2 mode)
- (dni name
- (.str name "arithmetic" )
- ((PIPE OS) (IDOC ALU))
- (.str insn " $"op1 ",$"op2)
- (+ opc1 opc2 op1 op2)
- (set mode op1 (insn1 mode op1 op2 cbit))
- ()
- )
-)
-(arithmetic3 addcr addc addc OP1_1 OP2_0 dr sr HI)
-(arithmetic3 subcr subc subc OP1_3 OP2_0 dr sr HI)
-(arithmetic3 addbcr addcb addc OP1_1 OP2_1 drb srb QI)
-(arithmetic3 subbcr subcb subc OP1_3 OP2_1 drb srb QI)
-
-
-;add/sub register and indirect memory
-(define-pmacro (arithmetic4 name insn insn1 opc1 opc2 op1 op2 mode)
- (dni name
- (.str name "arithmetic" )
- ((PIPE OS) (IDOC ALU))
- (.str insn " $"op1 ",[$"op2"]")
- (+ opc1 opc2 op1 (f-op-bit2 2) op2)
- (set mode op1 (insn1 mode op1 (mem HI op2) cbit))
- ()
- )
-)
-(arithmetic4 addcr2 addc addc OP1_1 OP2_8 dr sr2 HI)
-(arithmetic4 subcr2 subc subc OP1_3 OP2_8 dr sr2 HI)
-(arithmetic4 addbcr2 addcb addc OP1_1 OP2_9 drb sr2 QI)
-(arithmetic4 subbcr2 subcb subc OP1_3 OP2_9 drb sr2 QI)
-
-;add/sub register and indirect memory post increment
-(define-pmacro (arithmetic5 name insn insn1 opc1 opc2 op1 op2 mode)
- (dni name
- (.str name "arithmetic" )
- ((PIPE OS) (IDOC ALU))
- (.str insn " $"op1 ",[$"op2"+]")
- (+ opc1 opc2 op1 (f-op-bit2 3) op2)
- (sequence ()
- (set mode op1 (insn1 mode op1 (mem HI op2) cbit))
- (set HI op2 (add HI op2 (const 2)))
- )
- ()
- )
-)
-(arithmetic5 addcr2i addc addc OP1_1 OP2_8 dr sr2 HI)
-(arithmetic5 subcr2i subc subc OP1_3 OP2_8 dr sr2 HI)
-(arithmetic5 addbcr2i addcb addc OP1_1 OP2_9 drb sr2 QI)
-(arithmetic5 subbcr2i subcb subc OP1_3 OP2_9 drb sr2 QI)
-
-;add/sub register and direct memory
-(define-pmacro (arithmetic6 name insn insn1 opc1 opc2 op1 op2 mode)
- (dni name
- (.str name "arithmetic" )
- ((PIPE OS) (IDOC ALU))
- (.str insn " $"op1 ",$"op2)
- (+ opc1 opc2 op1 op2)
- (set mode op1 (insn1 mode op1 op2))
- ()
- )
-)
-
-;add/sub register and direct memory
-(define-pmacro (arithmetic7 name insn insn1 opc1 opc2 op1 op2 mode)
- (dni name
- (.str name "arithmetic" )
- ((PIPE OS) (IDOC ALU))
- (.str insn " $"op1 ",$"op2)
- (+ opc1 opc2 op2 op1)
- (set (mem HI op1) (insn1 (mem HI op1) op2))
- ()
- )
-)
-(arithmetic6 addrm2 add add OP1_0 OP2_2 regmem8 memgr8 HI)
-(arithmetic7 addrm3 add add OP1_0 OP2_4 memgr8 regmem8 HI)
-(arithmetic6 addrm add add OP1_0 OP2_2 reg8 memory HI)
-(arithmetic7 addrm1 add add OP1_0 OP2_4 memory reg8 HI)
-(arithmetic6 subrm3 sub sub OP1_2 OP2_2 regmem8 memgr8 HI)
-(arithmetic7 subrm2 sub sub OP1_2 OP2_4 memgr8 regmem8 HI)
-(arithmetic6 subrm1 sub sub OP1_2 OP2_2 reg8 memory HI)
-(arithmetic7 subrm sub sub OP1_2 OP2_4 memory reg8 HI)
-(arithmetic6 addbrm2 addb add OP1_0 OP2_3 regbmem8 memgr8 QI)
-(arithmetic7 addbrm3 addb add OP1_0 OP2_5 memgr8 regbmem8 QI)
-(arithmetic6 addbrm addb add OP1_0 OP2_3 regb8 memory QI)
-(arithmetic7 addbrm1 addb add OP1_0 OP2_5 memory regb8 QI)
-(arithmetic6 subbrm3 subb sub OP1_2 OP2_3 regbmem8 memgr8 QI)
-(arithmetic7 subbrm2 subb sub OP1_2 OP2_5 memgr8 regbmem8 QI)
-(arithmetic6 subbrm1 subb sub OP1_2 OP2_3 regb8 memory QI)
-(arithmetic7 subbrm subb sub OP1_2 OP2_5 memory regb8 QI)
-
-;add/sub registers with carry
-(define-pmacro (arithmetic8 name insn insn1 opc1 opc2 op1 op2 mode)
- (dni name
- (.str name "arithmetic" )
- ((PIPE OS) (IDOC ALU))
- (.str insn " $"op1 ",$"op2)
- (+ opc1 opc2 op1 op2)
- (set mode op1 (insn1 mode op1 op2 cbit))
- ()
- )
-)
-
-;add/sub registers with carry
-(define-pmacro (arithmetic9 name insn insn1 opc1 opc2 op1 op2 mode)
- (dni name
- (.str name "arithmetic" )
- ((PIPE OS) (IDOC ALU))
- (.str insn " $"op1 ",$"op2)
- (+ opc1 opc2 op2 op1)
- (set (mem HI op1) (insn1 (mem HI op1) op2 cbit))
- ()
- )
-)
-(arithmetic8 addcrm2 addc addc OP1_1 OP2_2 regmem8 memgr8 HI)
-(arithmetic9 addcrm3 addc addc OP1_1 OP2_4 memgr8 regmem8 HI)
-(arithmetic8 addcrm addc addc OP1_1 OP2_2 reg8 memory HI)
-(arithmetic9 addcrm1 addc addc OP1_1 OP2_4 memory reg8 HI)
-(arithmetic8 subcrm3 subc subc OP1_3 OP2_2 regmem8 memgr8 HI)
-(arithmetic9 subcrm2 subc subc OP1_3 OP2_4 memgr8 regmem8 HI)
-(arithmetic8 subcrm1 subc subc OP1_3 OP2_2 reg8 memory HI)
-(arithmetic9 subcrm subc subc OP1_3 OP2_4 memory reg8 HI)
-(arithmetic8 addcbrm2 addcb addc OP1_1 OP2_3 regbmem8 memgr8 QI)
-(arithmetic9 addcbrm3 addcb addc OP1_1 OP2_5 memgr8 regbmem8 QI)
-(arithmetic8 addcbrm addcb addc OP1_1 OP2_3 regb8 memory QI)
-(arithmetic9 addcbrm1 addcb addc OP1_1 OP2_5 memory regb8 QI)
-(arithmetic8 subcbrm3 subcb subc OP1_3 OP2_3 regbmem8 memgr8 QI)
-(arithmetic9 subcbrm2 subcb subc OP1_3 OP2_5 memgr8 regbmem8 QI)
-(arithmetic8 subcbrm1 subcb subc OP1_3 OP2_3 regb8 memory QI)
-(arithmetic9 subcbrm subcb subc OP1_3 OP2_5 memory regb8 QI)
-
-; MUL Rwn,Rwm
-(dni muls "signed multiplication"
- ((PIPE OS) (IDOC ALU))
- "mul $src1,$src2"
- (+ OP1_0 OP2_11 src1 src2)
- (nop) ;; FIXME: (reg SI h-md 0)
- ()
-)
-; MULU Rwn,Rwm
-(dni mulu "unsigned multiplication"
- ((PIPE OS) (IDOC ALU))
- "mulu $src1,$src2"
- (+ OP1_1 OP2_11 src1 src2)
- (nop) ;; FIXME: (reg SI h-md 0)
- ()
-)
-; DIV Rwn
-(dni div "16-by-16 signed division"
- ((PIPE OS) (IDOC ALU))
- "div $srdiv"
- (+ OP1_4 OP2_11 srdiv )
- (sequence ()
- (set HI (reg HI h-cr 6) (div HI (reg HI h-cr 6) srdiv))
- (set HI (reg HI h-cr 7) (mod HI (reg HI h-cr 6) srdiv))
- )
- ()
-)
-; DIVL Rwn
-(dni divl "32-by16 signed division"
- ((PIPE OS) (IDOC ALU))
- "divl $srdiv"
- (+ OP1_6 OP2_11 srdiv )
- (sequence ()
- (set HI (reg HI h-cr 6) 0) ;; FIXME: (div SI (reg SI h-md 0) srdiv))
- (set HI (reg HI h-cr 7) 0) ;; FIXME: (mod SI (reg SI h-md 0) srdiv))
- )
- ()
-)
-; DIVLU Rwn
-(dni divlu "32-by16 unsigned division"
- ((PIPE OS) (IDOC ALU))
- "divlu $srdiv"
- (+ OP1_7 OP2_11 srdiv )
- (sequence ()
- (set HI (reg HI h-cr 6) 0) ;; FIXME: (udiv SI (reg SI h-md 0) srdiv))
- (set HI (reg HI h-cr 7) 0) ;; FIXME: (umod SI (reg SI h-md 0) srdiv))
- )
- ()
-)
-; DIVU Rwn
-(dni divu "16-by-16 unsigned division"
- ((PIPE OS) (IDOC ALU))
- "divu $srdiv"
- (+ OP1_5 OP2_11 srdiv )
- (sequence ()
- (set HI (reg HI h-cr 6) (udiv HI (reg HI h-cr 6) srdiv))
- (set HI (reg HI h-cr 7) (umod HI (reg HI h-cr 6) srdiv))
- )
- ()
-)
-
-;Integer one's complement
-; CPL Rwn
-(dni cpl "Integer Ones complement"
- ((PIPE OS) (IDOC MISC))
- "cpl $dr"
- (+ OP1_9 OP2_1 dr (f-op-bit4 0))
- (set dr (inv HI dr))
- ()
-)
-
-;Bytes one's complement
-; CPLB Rbn
-(dni cplb "Byte Ones complement"
- ((PIPE OS) (IDOC MISC))
- "cplb $drb"
- (+ OP1_11 OP2_1 drb (f-op-bit4 0))
- (set drb (inv QI drb))
- ()
-)
-;Integer two's complement
-; NEG Rwn
-(dni neg "Integer two's complement"
- ((PIPE OS) (IDOC MISC))
- "neg $dr"
- (+ OP1_8 OP2_1 dr (f-op-bit4 0))
- (set dr (neg HI dr))
- ()
-)
-;Bytes two's complement
-; NEGB Rbn
-(dni negb "byte twos complement"
- ((PIPE OS) (IDOC MISC))
- "negb $drb"
- (+ OP1_10 OP2_1 drb (f-op-bit4 0))
- (set drb (neg QI drb))
- ()
-)
-
-;****************************************************************
-;logical insn
-;****************************************************************
-;and/or/xor registers
-(define-pmacro (logical name insn insn1 opc1 opc2 op1 op2 mode)
- (dni name
- (.str name "logical" )
- ((PIPE OS) (IDOC ALU))
- (.str insn " $"op1 ",$"op2)
- (+ opc1 opc2 op1 op2)
- (set mode op1 (insn1 mode op1 op2))
- ()
- )
-)
-
-(logical andr and and OP1_6 OP2_0 dr sr HI)
-(logical orr or or OP1_7 OP2_0 dr sr HI)
-(logical xorr xor xor OP1_5 OP2_0 dr sr HI)
-(logical andbr andb and OP1_6 OP2_1 drb srb QI)
-(logical orbr orb or OP1_7 OP2_1 drb srb QI)
-(logical xorbr xorb xor OP1_5 OP2_1 drb srb QI)
-
-;and/or/xor register and immediate
-(define-pmacro (logical1 name insn insn1 opc1 opc2 op1 op2 mode)
- (dni name
- (.str name "logical" )
- ((PIPE OS) (IDOC ALU))
- (.str insn " $"op1 ",$hash$"op2)
- (+ opc1 opc2 op1 (f-op-bit1 0) op2)
- (set mode op1 (insn1 mode op1 op2))
- ()
- )
-)
-(logical1 andri and and OP1_6 OP2_8 dr uimm3 HI)
-(logical1 orri or or OP1_7 OP2_8 dr uimm3 HI)
-(logical1 xorri xor xor OP1_5 OP2_8 dr uimm3 HI)
-(logical1 andbri andb and OP1_6 OP2_9 drb uimm3 QI)
-(logical1 orbri orb or OP1_7 OP2_9 drb uimm3 QI)
-(logical1 xorbri xorb xor OP1_5 OP2_9 drb uimm3 QI)
-
-;and/or/xor register and immediate
-(define-pmacro (logical2 name insn insn1 opc1 opc2 op1 op2 mode)
- (dni name
- (.str name "logical" )
- ((PIPE OS) (IDOC ALU))
- (.str insn " $"op1 ",$hash$"op2)
- (+ opc1 opc2 op1 op2)
- (set mode op1 (insn1 mode op1 op2))
- ()
- )
-)
-(logical2 andrim and and OP1_6 OP2_6 reg8 uimm16 HI)
-(logical2 orrim or or OP1_7 OP2_6 reg8 uimm16 HI)
-(logical2 xorrim xor xor OP1_5 OP2_6 reg8 uimm16 HI)
-
-;and/or/xor register and immediate
-(define-pmacro (logical3 name insn insn1 opc1 opc2 op1 op2 mode)
- (dni name
- (.str name "logical" )
- ((PIPE OS) (IDOC ALU))
- (.str insn " $"op1 ",$hash$"op2)
- (+ opc1 opc2 op1 op2 (f-op-bit8 0))
- (set mode op1 (insn1 mode op1 op2))
- ()
- )
-)
-(logical3 andbrim andb and OP1_6 OP2_7 regb8 uimm8 QI)
-(logical3 orbrim orb or OP1_7 OP2_7 regb8 uimm8 QI)
-(logical3 xorbrim xorb xor OP1_5 OP2_7 regb8 uimm8 QI)
-
-;and/or/xor register and indirect memory
-(define-pmacro (logical4 name insn insn1 opc1 opc2 op1 op2 mode)
- (dni name
- (.str name "logical" )
- ((PIPE OS) (IDOC ALU))
- (.str insn " $"op1 ",[$"op2"]")
- (+ opc1 opc2 op1 (f-op-bit2 2) op2)
- (set mode op1 (insn1 mode op1 (mem HI op2)))
- ()
- )
-)
-(logical4 and2 and and OP1_6 OP2_8 dr sr2 HI)
-(logical4 or2 or or OP1_7 OP2_8 dr sr2 HI)
-(logical4 xor2 xor xor OP1_5 OP2_8 dr sr2 HI)
-(logical4 andb2 andb and OP1_6 OP2_9 drb sr2 QI)
-(logical4 orb2 orb or OP1_7 OP2_9 drb sr2 QI)
-(logical4 xorb2 xorb xor OP1_5 OP2_9 drb sr2 QI)
-
-;and/or/xor register and indirect memory post increment
-(define-pmacro (logical5 name insn insn1 opc1 opc2 op1 op2 mode)
- (dni name
- (.str name "logical" )
- ((PIPE OS) (IDOC ALU))
- (.str insn " $"op1 ",[$"op2"+]")
- (+ opc1 opc2 op1 (f-op-bit2 3) op2)
- (sequence ()
- (set mode op1 (insn1 mode op1 (mem HI op2)))
- (set HI op2 (add HI op2 (const 2)))
- )
- ()
- )
-)
-(logical5 and2i and and OP1_6 OP2_8 dr sr2 HI)
-(logical5 or2i or or OP1_7 OP2_8 dr sr2 HI)
-(logical5 xor2i xor xor OP1_5 OP2_8 dr sr2 HI)
-(logical5 andb2i andb and OP1_6 OP2_9 drb sr2 QI)
-(logical5 orb2i orb or OP1_7 OP2_9 drb sr2 QI)
-(logical5 xorb2i xorb xor OP1_5 OP2_9 drb sr2 QI)
-
-;add/sub register and immediate
-(define-pmacro (logical7 name insn insn1 opc1 opc2 op1 op2 mode dir)
- (dni name
- (.str name "arithmetic" )
- ((PIPE OS) (IDOC ALU))
- (.str insn " $"dir"$"op1 ",$"op2)
- (+ opc1 opc2 op1 op2)
- (set (mem HI op1) (insn1 (mem HI op1) op2 ))
- ()
- )
-)
-(logical7 andpofr and and OP1_6 OP2_2 reg8 upof16 HI "pof")
-(logical7 orpofr or or OP1_7 OP2_2 reg8 upof16 HI "pof")
-(logical7 xorpofr xor xor OP1_5 OP2_2 reg8 upof16 HI "pof")
-(logical7 andbpofr andb and OP1_6 OP2_3 regb8 upof16 QI "pof")
-(logical7 orbpofr orb or OP1_7 OP2_3 regb8 upof16 QI "pof")
-(logical7 xorbpofr xorb xor OP1_5 OP2_3 regb8 upof16 QI "pof")
-
-;add/sub register and immediate
-(define-pmacro (logical8 name insn insn1 opc1 opc2 op1 op2 mode dir)
- (dni name
- (.str name "arithmetic" )
- ((PIPE OS) (IDOC ALU))
- (.str insn " $"dir"$"op1 ",$"op2)
- (+ opc1 opc2 op1 op2)
- (set (mem HI op1) (insn1 (mem HI op1) op2 ))
- ()
- )
-)
-(logical8 andrpofr and and OP1_6 OP2_4 upof16 reg8 HI "pof")
-(logical8 orrpofr or or OP1_7 OP2_4 upof16 reg8 HI "pof")
-(logical8 xorrpofr xor xor OP1_5 OP2_4 upof16 reg8 HI "pof")
-(logical8 andbrpofr andb and OP1_6 OP2_5 upof16 regb8 QI "pof")
-(logical8 orbrpofr orb or OP1_7 OP2_5 upof16 regb8 QI "pof")
-(logical8 xorbrpofr xorb xor OP1_5 OP2_5 upof16 regb8 QI "pof")
-
-;and/or/xor register and direct memory
-(define-pmacro (logical6 name insn insn1 opc1 opc2 op1 op2 mode)
- (dni name
- (.str name "arithmetic" )
- ((PIPE OS) (IDOC ALU))
- (.str insn " $"op1 ",$"op2)
- (+ opc1 opc2 op1 op2)
- (set mode op1 (insn1 mode op1 op2))
- ()
- )
-)
-
-;and/or/xor register and direct memory
-(define-pmacro (logical7 name insn insn1 opc1 opc2 op1 op2 mode)
- (dni name
- (.str name "arithmetic" )
- ((PIPE OS) (IDOC ALU))
- (.str insn " $"op1 ",$"op2)
- (+ opc1 opc2 op2 op1)
- (set (mem HI op1) (insn1 (mem HI op1) op2))
- ()
- )
-)
-(logical6 andrm2 and and OP1_6 OP2_2 regmem8 memgr8 HI)
-(logical7 andrm3 and and OP1_6 OP2_4 memgr8 regmem8 HI)
-(logical6 andrm and and OP1_6 OP2_2 reg8 memory HI)
-(logical7 andrm1 and and OP1_6 OP2_4 memory reg8 HI)
-(logical6 orrm3 or or OP1_7 OP2_2 regmem8 memgr8 HI)
-(logical7 orrm2 or or OP1_7 OP2_4 memgr8 regmem8 HI)
-(logical6 orrm1 or or OP1_7 OP2_2 reg8 memory HI)
-(logical7 orrm or or OP1_7 OP2_4 memory reg8 HI)
-(logical6 xorrm3 xor xor OP1_5 OP2_2 regmem8 memgr8 HI)
-(logical7 xorrm2 xor xor OP1_5 OP2_4 memgr8 regmem8 HI)
-(logical6 xorrm1 xor xor OP1_5 OP2_2 reg8 memory HI)
-(logical7 xorrm xor xor OP1_5 OP2_4 memory reg8 HI)
-(logical6 andbrm2 andb and OP1_6 OP2_3 regbmem8 memgr8 QI)
-(logical7 andbrm3 andb and OP1_6 OP2_5 memgr8 regbmem8 QI)
-(logical6 andbrm andb and OP1_6 OP2_3 regb8 memory QI)
-(logical7 andbrm1 andb and OP1_6 OP2_5 memory regb8 QI)
-(logical6 orbrm3 orb or OP1_7 OP2_3 regbmem8 memgr8 QI)
-(logical7 orbrm2 orb or OP1_7 OP2_5 memgr8 regbmem8 QI)
-(logical6 orbrm1 orb or OP1_7 OP2_3 regb8 memory QI)
-(logical7 orbrm orb or OP1_7 OP2_5 memory regb8 QI)
-(logical6 xorbrm3 xorb xor OP1_5 OP2_3 regbmem8 memgr8 QI)
-(logical7 xorbrm2 xorb xor OP1_5 OP2_5 memgr8 regbmem8 QI)
-(logical6 xorbrm1 xorb xor OP1_5 OP2_3 regb8 memory QI)
-(logical7 xorbrm xorb xor OP1_5 OP2_5 memory regb8 QI)
-
-;****************************************************************
-;logical insn
-;****************************************************************
-;mov registers
-(define-pmacro (move name insn opc1 opc2 op1 op2 mode)
- (dni name
- (.str name "mov registers" )
- ((PIPE OS) (IDOC MOVE))
- (.str insn " $"op1 ",$"op2)
- (+ opc1 opc2 op1 op2)
- (set mode op1 op2)
- ()
- )
-)
-(move movr mov OP1_15 OP2_0 dr sr HI)
-(move movrb movb OP1_15 OP2_1 drb srb HI)
-
-;mov register and immediate
-(define-pmacro (move1 name insn opc1 opc2 op1 op2 mode)
- (dni name
- (.str name "move" )
- ((PIPE OS) (IDOC MOVE))
- (.str insn " $"op1 ",$hash$"op2)
- (+ opc1 opc2 op2 op1)
- (set mode op1 op2)
- ()
- )
-)
-(move1 movri mov OP1_14 OP2_0 dri u4 HI)
-(move1 movbri movb OP1_14 OP2_1 srb u4 QI)
-
-; MOV Rwn,#data16
-(dni movi "move immediate to register"
- ((PIPE OS) (IDOC MOVE))
- "mov $reg8,$hash$uimm16"
- (+ OP1_14 OP2_6 reg8 uimm16)
- (set HI reg8 uimm16)
- ()
-)
-
-; MOVB reg,#data8
-(dni movbi "move immediate to register"
- ((PIPE OS) (IDOC MOVE))
- "movb $regb8,$hash$uimm8"
- (+ OP1_14 OP2_7 regb8 uimm8 (f-op-bit8 0))
- (set QI regb8 uimm8)
- ()
-)
-
-;move and indirect memory
-(define-pmacro (mov2 name insn opc1 opc2 op1 op2 mode)
- (dni name
- (.str name "move" )
- ((PIPE OS) (IDOC MOVE))
- (.str insn " $"op1 ",[$"op2"]")
- (+ opc1 opc2 op1 op2)
- (set mode op1 (mem HI op2))
- ()
- )
-)
-(mov2 movr2 mov OP1_10 OP2_8 dr sr HI)
-(mov2 movbr2 movb OP1_10 OP2_9 drb sr QI)
-
-;move and indirect memory
-(define-pmacro (mov3 name insn opc1 opc2 op1 op2 mode)
- (dni name
- (.str name "move" )
- ((PIPE OS) (IDOC MOVE))
- (.str insn " [$"op2 "],$"op1)
- (+ opc1 opc2 op1 op2)
- (set mode op1 (mem HI op2))
- ()
- )
-)
-(mov3 movri2 mov OP1_11 OP2_8 dr sr HI)
-(mov3 movbri2 movb OP1_11 OP2_9 drb sr QI)
-
-;move and indirect memory
-(define-pmacro (mov4 name insn opc1 opc2 op1 op2 mode)
- (dni name
- (.str name "move" )
- ((PIPE OS) (IDOC MOVE))
- (.str insn " [-$"op2 "],$"op1)
- (+ opc1 opc2 op1 op2)
- (sequence ()
- (set op1 (sub op2 (const HI 2)))
- (set HI (mem HI op2) op1)
- )
- ()
- )
-)
-(mov4 movri3 mov OP1_8 OP2_8 dr sr HI)
-(mov4 movbri3 movb OP1_8 OP2_9 drb sr QI)
-
-;mov register and indirect memory post increment
-(define-pmacro (mov5 name insn opc1 opc2 op1 op2 mode)
- (dni name
- (.str name "move" )
- ((PIPE OS) (IDOC MOVE))
- (.str insn " $"op1 ",[$"op2"+]")
- (+ opc1 opc2 op1 op2)
- (sequence ()
- (set mode op1 (mem HI op2))
- (set HI op2 (add HI op2 (const 2)))
- )
- ()
- )
-)
-(mov5 mov2i mov OP1_9 OP2_8 dr sr HI)
-(mov5 movb2i movb OP1_9 OP2_9 drb sr HI)
-
-;mov indirect memory
-(define-pmacro (mov6 name insn opc1 opc2 op1 op2 mode)
- (dni name
- (.str name "move" )
- ((PIPE OS) (IDOC MOVE))
- (.str insn " [$"op1 "],[$"op2"]")
- (+ opc1 opc2 op1 op2)
- (set HI (mem HI op1) (mem HI op2))
- ()
- )
-)
-(mov6 mov6i mov OP1_12 OP2_8 dr sr HI)
-(mov6 movb6i movb OP1_12 OP2_9 dr sr HI)
-
-;mov indirect memory
-(define-pmacro (mov7 name insn opc1 opc2 op1 op2 mode)
- (dni name
- (.str name "move" )
- ((PIPE OS) (IDOC MOVE))
- (.str insn " [$"op1 "+],[$"op2"]")
- (+ opc1 opc2 op1 op2)
- (sequence ()
- (set mode (mem mode op1) (mem mode op2))
- (set mode op1 (add mode op1 (const mode 2)))
- )
- ()
- )
-)
-(mov7 mov7i mov OP1_13 OP2_8 dr sr HI)
-(mov7 movb7i movb OP1_13 OP2_9 dr sr HI)
-
-;mov indirect memory
-(define-pmacro (mov8 name insn opc1 opc2 op1 op2 mode)
- (dni name
- (.str name "move" )
- ((PIPE OS) (IDOC MOVE))
- (.str insn " [$"op1 "],[$"op2"+]")
- (+ opc1 opc2 op1 op2)
- (sequence ()
- (set mode (mem mode op1) (mem mode op2))
- (set mode op2 (add mode op2 (const mode 2)))
- )
- ()
- )
-)
-(mov8 mov8i mov OP1_14 OP2_8 dr sr HI)
-(mov8 movb8i movb OP1_14 OP2_9 dr sr HI)
-
-;mov indirect memory
-(define-pmacro (mov9 name insn opc1 opc2 op1 op2 mode)
- (dni name
- (.str name "move" )
- ((PIPE OS) (IDOC MOVE))
- (.str insn " $"op1 ",[$"op2"+$hash$"uimm16"]")
- (+ opc1 opc2 op1 op2 uimm16)
- (sequence ((mode tmp1))
- (set mode tmp1 (add HI op2 uimm16))
- (set mode op1 (mem HI tmp1))
- )
- ()
- )
-)
-(mov9 mov9i mov OP1_13 OP2_4 dr sr HI)
-(mov9 movb9i movb OP1_15 OP2_4 drb sr QI)
-
-;mov indirect memory
-(define-pmacro (mov10 name insn opc1 opc2 op1 op2 mode)
- (dni name
- (.str name "move" )
- ((PIPE OS) (IDOC MOVE))
- (.str insn " [$"op2"+$hash$"uimm16 "],$"op1)
- (+ opc1 opc2 op1 op2 uimm16)
- (sequence ((mode tmp1))
- (set mode tmp1 (add HI op1 uimm16))
- (set mode (mem HI tmp1) op1)
- )
- ()
- )
-)
-(mov10 mov10i mov OP1_12 OP2_4 dr sr HI)
-(mov10 movb10i movb OP1_14 OP2_4 drb sr QI)
-
-;move and indirect memory
-(define-pmacro (mov11 name insn opc1 opc2 op1 op2 mode)
- (dni name
- (.str name "move" )
- ((PIPE OS) (IDOC MOVE))
- (.str insn " [$"op1 "],$"op2)
- (+ opc1 opc2 (f-op-lbit4 0) op1 op2)
- (set (mem mode op1) (mem HI op2))
- ()
- )
-)
-(mov11 movri11 mov OP1_8 OP2_4 src2 memory HI)
-(mov11 movbri11 movb OP1_10 OP2_4 src2 memory HI)
-
-;move and indirect memory
-(define-pmacro (mov12 name insn opc1 opc2 op1 op2 mode)
- (dni name
- (.str name "move" )
- ((PIPE OS) (IDOC MOVE))
- (.str insn " $"op2 ",[$"op1"]")
- (+ opc1 opc2 (f-op-lbit4 0) op1 op2)
- (set (mem HI op2) (mem mode op1))
- ()
- )
-)
-(mov12 movri12 mov OP1_9 OP2_4 src2 memory HI)
-(mov12 movbri12 movb OP1_11 OP2_4 src2 memory HI)
-
-(define-pmacro (movemem3 name insn opc1 opc2 op1 op2 dir)
- (dni name
- (.str name "move" )
- ((PIPE OS) (IDOC MOVE))
- (.str insn " $"op1 ",$hash$"dir"$"op2)
- (+ opc1 opc2 op1 op2)
- (set HI op1 op2)
- ()
- )
-)
-(movemem3 movehm5 mov OP1_14 OP2_6 regoff8 upof16 "pof")
-(movemem3 movehm6 mov OP1_14 OP2_6 regoff8 upag16 "pag")
-(movemem3 movehm7 mov OP1_14 OP2_6 regoff8 useg16 "segm")
-(movemem3 movehm8 mov OP1_14 OP2_6 regoff8 usof16 "sof")
-
-(define-pmacro (movemem4 name insn opc1 opc2 op1 op2 dir)
- (dni name
- (.str name "move" )
- ((PIPE OS) (IDOC MOVE))
- (.str insn " $"op1 ",$hash$"dir"$"op2)
- (+ opc1 opc2 op1 op2 (f-op-bit8 0))
- (set QI op1 op2)
- ()
- )
-)
-(movemem4 movehm9 movb OP1_14 OP2_7 regb8 uimm8 "pof")
-(movemem4 movehm10 movb OP1_14 OP2_7 regoff8 uimm8 "pag")
-
-(define-pmacro (movemem name insn opc1 opc2 op1 op2 mode dir)
- (dni name
- (.str name "move" )
- ((PIPE OS) (IDOC MOVE))
- (.str insn " $"op1 ",$"dir"$"op2)
- (+ opc1 opc2 op1 op2)
- (set mode op1 (mem HI op2))
- ()
- )
-)
-(movemem movrmp mov OP1_15 OP2_2 regoff8 upof16 HI "pof")
-(movemem movrmp1 movb OP1_15 OP2_3 regb8 upof16 QI "pof")
-(movemem movrmp2 mov OP1_15 OP2_2 regoff8 upag16 HI "pag")
-(movemem movrmp3 movb OP1_15 OP2_3 regb8 upag16 QI "pag")
-
-(define-pmacro (movemem1 name insn opc1 opc2 op1 op2 dir)
- (dni name
- (.str name "move" )
- ((PIPE OS) (IDOC MOVE))
- (.str insn " $"dir"$"op1 ",$"op2)
- (+ opc1 opc2 op2 op1)
- (set (mem HI op1) op2 )
- ()
- )
-)
-(movemem1 movrmp4 mov OP1_15 OP2_6 upof16 regoff8 "pof")
-(movemem1 movrmp5 movb OP1_15 OP2_7 upof16 regb8 "pof")
-
-(define-pmacro (movemem2 name insn opc1 opc2 op1 op2 mode dir)
- (dni name
- (.str name "move" )
- ((PIPE OS) (IDOC MOVE))
- (.str insn " $"op1 ",$hash$"dir"$"op2)
- (+ opc1 opc2 op2 op1)
- (set mode op1 op2)
- ()
- )
-)
-(movemem2 movehm1 mov OP1_14 OP2_0 dri u4 HI "pof")
-(movemem2 movehm2 movb OP1_14 OP2_1 srb u4 QI "pof")
-(movemem2 movehm3 mov OP1_14 OP2_0 dri u4 HI "pag")
-(movemem2 movehm4 movb OP1_14 OP2_1 srb u4 QI "pag")
-
-;move register and direct memory
-(define-pmacro (move12 name insn opc1 opc2 op1 op2 mode)
- (dni name
- (.str name "move" )
- ((PIPE OS) (IDOC MOVE))
- (.str insn " $"op1 ",$"op2)
- (+ opc1 opc2 op1 op2)
- (set mode op1 (mem HI op2))
- ()
- )
-)
-
-;move register and direct memory
-(define-pmacro (move13 name insn opc1 opc2 op1 op2 mode)
- (dni name
- (.str name "move" )
- ((PIPE OS) (IDOC MOVE))
- (.str insn " $"op1 ",$"op2)
- (+ opc1 opc2 op2 op1)
- (set (mem HI op1) op2)
- ()
- )
-)
-(move12 mve12 mov OP1_15 OP2_2 regmem8 memgr8 HI)
-(move13 mve13 mov OP1_15 OP2_6 memgr8 regmem8 HI)
-(move12 mover12 mov OP1_15 OP2_2 reg8 memory HI)
-(move13 mvr13 mov OP1_15 OP2_6 memory reg8 HI)
-(move12 mver12 movb OP1_15 OP2_3 regbmem8 memgr8 QI)
-(move13 mver13 movb OP1_15 OP2_7 memgr8 regbmem8 QI)
-(move12 movr12 movb OP1_15 OP2_3 regb8 memory QI)
-(move13 movr13 movb OP1_15 OP2_7 memory regb8 QI)
-
-; MOVBS Rw,Rb
-(dni movbsrr "mov byte register with sign extension to word register"
- ((PIPE OS) (IDOC MOVE))
- "movbs $sr,$drb"
- (+ OP1_13 OP2_0 drb sr)
- (sequence ()
- (if (and QI drb (const 128))
- (set HI sr (or HI (const HI 65280) drb)))
- (set HI sr (and HI (const HI 255) drb))
- )
- ()
-)
-
-; MOVBZ Rw,Rb
-(dni movbzrr "mov byte register with zero extension to word register"
- ((PIPE OS) (IDOC MOVE))
- "movbz $sr,$drb"
- (+ OP1_12 OP2_0 drb sr)
- (set HI sr (and HI (const HI 255) drb))
- ()
-)
-
-; MOVBS reg,POF mem
-(dni movbsrpofm "mov memory to byte register"
- ((PIPE OS) (IDOC MOVE))
- "movbs $regmem8,$pof$upof16"
- (+ OP1_13 OP2_2 regmem8 upof16)
- (set QI regmem8 (mem HI upof16))
- ()
-)
-
-; MOVBS pof,reg
-(dni movbspofmr "mov memory to byte register"
- ((PIPE OS) (IDOC MOVE))
- "movbs $pof$upof16,$regbmem8"
- (+ OP1_13 OP2_5 upof16 regbmem8 )
- (set QI (mem HI upof16) regbmem8)
- ()
-)
-
-; MOVBZ reg,POF mem
-(dni movbzrpofm "mov memory to byte register"
- ((PIPE OS) (IDOC MOVE))
- "movbz $reg8,$pof$upof16"
- (+ OP1_12 OP2_2 reg8 upof16)
- (set QI reg8 (mem HI upof16))
- ()
-)
-
-; MOVBZ pof,reg
-(dni movbzpofmr "mov memory to byte register"
- ((PIPE OS) (IDOC MOVE))
- "movbz $pof$upof16,$regb8"
- (+ OP1_12 OP2_5 upof16 regb8 )
- (set QI (mem HI upof16) regb8)
- ()
-)
-
-;move register and direct memory
-(define-pmacro (move14 name insn opc1 opc2 op1 op2 )
- (dni name
- (.str name "move" )
- ((PIPE OS) (IDOC MOVE))
- (.str insn " $"op1 ",$"op2)
- (+ opc1 opc2 op1 op2)
- (set HI op1 (and HI (const HI 255) (mem QI op2)))
- ()
- )
-)
-
-;move register and direct memory
-(define-pmacro (move15 name insn opc1 opc2 op1 op2 )
- (dni name
- (.str name "move" )
- ((PIPE OS) (IDOC MOVE))
- (.str insn " $"op1 ",$"op2)
- (+ opc1 opc2 op2 op1)
- (set HI (mem HI op1) (and HI (const HI 255) op2))
- ()
- )
-)
-(move14 movebs14 movbs OP1_13 OP2_2 regmem8 memgr8 )
-(move15 movebs15 movbs OP1_13 OP2_5 memgr8 regbmem8 )
-(move14 moverbs14 movbs OP1_13 OP2_2 reg8 memory )
-(move15 movrbs15 movbs OP1_13 OP2_5 memory regb8 )
-(move14 movebz14 movbz OP1_12 OP2_2 regmem8 memgr8 )
-(move15 movebz15 movbz OP1_12 OP2_5 memgr8 regbmem8 )
-(move14 moverbz14 movbz OP1_12 OP2_2 reg8 memory )
-(move15 movrbz15 movbz OP1_12 OP2_5 memory regb8 )
-
-
-;mov registers
-(define-pmacro (moveb1 name insn opc1 opc2 op1 op2)
- (dni name
- (.str name "move" )
- ((PIPE OS) (IDOC MOVE))
- (.str insn " $"op2 ",$"op1)
- (+ opc1 opc2 op1 op2)
- (sequence ()
- (if (and QI op1 (const 128))
- (set HI op2 (or HI (const HI 65280) op1)))
- (set HI op2 (and HI (const HI 255) op1))
- )
- ()
- )
-)
-(moveb1 movrbs movbs OP1_13 OP2_0 drb sr )
-(moveb1 movrbz movbz OP1_12 OP2_0 drb sr )
-
-
-
-;jump and call insns
-;******************************************************************
-;Absolute conditional jump
-(define-pmacro (jmpabs name insn)
- (dni name
- (.str name "Absolute conditional jump" )
- ((PIPE OS) (IDOC JMP))
- (.str insn " $extcond,$caddr")
- (+ OP1_14 OP2_10 extcond (f-op-bitone 0) bitone bit01 caddr)
- (sequence ((HI tmp1) (HI tmp2))
- (set tmp1 (mem HI caddr))
- (set tmp2 (sub HI pc (mem HI caddr)))
- (if (gt tmp2 (const 0)) ;; FIXME: (lt tmp2 (const 32)) (eq tmp2 (const 32))
- (set bitone (const 1)))
- (if (lt tmp2 (const 0)) ;; FIXME: (eq tmp2 (const 0)) (gt tmp2 (const 32))
- (set bitone (const 0)))
- (if (eq extcond (const 1)) ;; FIXME: (ne extcond cc_Z))
- (set bit01 (const 0))
- (set HI pc (mem HI caddr)))
- (if (ne extcond (const 1)) ;; FIXME: (eq extcond cc_Z))
- (set bit01 (const 1))
- (set HI pc (add HI pc (const 2))))
- )
- ()
- )
-)
-
-(jmpabs jmpa0 jmpa+)
-(jmpabs jmpa1 jmpa)
-
-; JMPA- cc,caddr
-(dni jmpa- "Absolute conditional jump"
- (COND-CTI (PIPE OS) (IDOC JMP))
- "jmpa- $extcond,$caddr"
- (+ OP1_14 OP2_10 extcond (f-op-bitone 0) bitone (f-op-1bit 1) caddr)
- (sequence ((HI tmp1) (HI tmp2))
- (set tmp1 (mem HI caddr))
- (set tmp2 (sub HI pc (mem HI caddr)))
- (if (gt tmp2 (const 0)) ;; FIXME: (lt tmp2 (const 32)) (eq tmp2 (const 32))
- (set bitone (const 1)))
- (if (lt tmp2 (const 0)) ;; FIXME: (eq tmp2 (const 0)) (gt tmp2 (const 32))
- (set bitone (const 0)))
- (set HI pc (add HI pc (const 2)))
- )
- ()
-)
-
-; JMPI cc,[Rwn]
-(dni jmpi "Indirect conditional jump"
- (COND-CTI (PIPE OS) (IDOC JMP))
- "jmpi $icond,[$sr]"
- (+ OP1_9 OP2_12 icond sr)
- (sequence ()
- (if (eq icond (const 1))
- (set HI pc (mem HI sr)))
- (set HI pc (add HI pc (const 2)))
- )
- ()
-)
-
-(define-pmacro (jmprel name insn opc1)
- (dni name
- (.str name "conditional" )
- (COND-CTI (PIPE OS) (IDOC JMP))
- (.str insn " $cond,$rel")
- (+ opc1 OP2_13 rel)
- (sequence ()
- (if (eq cond (const 1))
- (sequence ()
- (if (lt QI rel (const 0))
- (sequence ()
- ;; FIXME: (neg QI rel)
- ;; FIXME: (add QI rel (const 1))
- ;; FIXME: (mul QI rel (const 2))
- (set HI pc (sub HI pc rel))
- ))
- (set HI pc (add HI pc (mul QI rel (const 2))))
- )
- )
- (set HI pc pc)
- )
- ()
- )
-)
-
-(jmprel jmpr_nenz jmpr COND_NE_NZ )
-(jmprel jmpr_sgt jmpr COND_SGT )
-(jmprel jmpr_z jmpr COND_Z )
-(jmprel jmpr_v jmpr COND_V )
-(jmprel jmpr_nv jmpr COND_NV )
-(jmprel jmpr_n jmpr COND_N )
-(jmprel jmpr_nn jmpr COND_NN )
-(jmprel jmpr_c jmpr COND_C )
-(jmprel jmpr_nc jmpr COND_NC )
-(jmprel jmpr_eq jmpr COND_EQ )
-(jmprel jmpr_ne jmpr COND_NE )
-(jmprel jmpr_ult jmpr COND_ULT )
-(jmprel jmpr_ule jmpr COND_ULE )
-(jmprel jmpr_uge jmpr COND_UGE )
-(jmprel jmpr_ugt jmpr COND_UGT )
-(jmprel jmpr_sle jmpr COND_SLE )
-(jmprel jmpr_sge jmpr COND_SGE )
-(jmprel jmpr_net jmpr COND_NET )
-(jmprel jmpr_uc jmpr COND_UC )
-(jmprel jmpr_slt jmpr COND_SLT )
-
-
-
-
-; JMPS seg,caddr
-(dni jmpseg "absolute inter-segment jump"
- (UNCOND-CTI(PIPE OS) (IDOC JMP))
- "jmps $hash$segm$useg8,$hash$sof$usof16"
- (+ OP1_15 OP2_10 seg usof16)
- (sequence ()
- (if (eq BI sgtdisbit (const BI 0))
- (set QI (reg h-cr 10) useg8))
- ;; FIXME: previous indentation suggested this nop was the `else'
- ;; clause of the previous `if'.
- (nop)
- (set HI pc usof16)
- )
- ()
-)
-
-; JMPS seg,caddr
-(dni jmps "absolute inter-segment jump"
- (UNCOND-CTI(PIPE OS) (IDOC JMP))
- "jmps $seg,$caddr"
- (+ OP1_15 OP2_10 seg caddr)
- (sequence ()
- (if (eq BI sgtdisbit (const BI 0))
- (set QI (reg h-cr 10) seg))
- ;; FIXME: previous indentation suggested this nop was the `else'
- ;; clause of the previous `if'.
- (nop)
- (set HI pc caddr)
- )
- ()
-)
-
-
-;relative jump if bit set
-;JB bitaddrQ.q,rel
-(dni jb "relative jump if bit set"
- ((PIPE OS) (IDOC JMP))
- "jb $genreg$dot$qlobit,$relhi"
- (+ OP1_8 OP2_10 genreg relhi qlobit (f-qhibit 0))
- (sequence ((HI tmp1) (HI tmp2))
- (set HI tmp1 genreg)
- (set HI tmp2 (const 1))
- ;;(sll HI tmp2 qlobit) - FIXME: missing (set ...)
- (set HI tmp2 (and tmp1 tmp2))
- (if (eq tmp2 (const 1)) ;; FIXME: (ne tmp2 0)?
- (sequence ()
- (if (lt QI relhi (const 0))
- (set HI pc (add HI pc (mul QI relhi (const 2)))))
- ))
- (set HI pc (add HI pc (const 4))) ;; FIXME: Is this right?
- )
- ()
-)
-
-;relative jump if bit set and clear bit
-;JBC bitaddrQ.q,rel
-(dni jbc "relative jump if bit set and clear bit"
- ((PIPE OS) (IDOC JMP))
- "jbc $genreg$dot$qlobit,$relhi"
- (+ OP1_10 OP2_10 genreg relhi qlobit (f-qhibit 0))
- (sequence ((HI tmp1) (HI tmp2))
- (set HI tmp1 genreg)
- (set HI tmp2 (const 1))
- ;;(sll HI tmp2 qlobit) - FIXME: missing (set ...)
- (set HI tmp2 (and tmp1 tmp2))
- (if (eq tmp2 (const 1)) ;; FIXME: (ne tmp2 0)?
- (sequence ()
- ;; FIXME: The `else' clause has several statements.
- (if (lt QI relhi (const 0))
- (set tmp2 (const 1))
- (set tmp1 genreg)
- ;; FIXME: (sll tmp2 qlobit)
- ;; FIXME: (inv tmp2)
- (set HI tmp1 (and tmp1 tmp2))
- (set HI genreg tmp1)
- (set HI pc (add HI pc (mul QI relhi (const 2)))))
- ))
- (set HI pc (add HI pc (const 4))) ;; FIXME: Is this right?
- )
- ()
-)
-
-;relative jump if bit set
-;JNB bitaddrQ.q,rel
-(dni jnb "relative jump if bit not set"
- ((PIPE OS) (IDOC JMP))
- "jnb $genreg$dot$qlobit,$relhi"
- (+ OP1_9 OP2_10 genreg relhi qlobit (f-qhibit 0))
- (sequence ((HI tmp1) (HI tmp2))
- (set HI tmp1 genreg)
- (set HI tmp2 (const 1))
- ;;(sll HI tmp2 qlobit) - FIXME: missing (set ...)
- (set HI tmp2 (and tmp1 tmp2))
- (if (eq tmp2 (const 0)) ;; FIXME: (ne tmp2 0)?
- (sequence ()
- (if (lt QI relhi (const 0))
- (set HI pc (add HI pc (mul QI relhi (const 2)))))
- ))
- (set HI pc (add HI pc (const 4))) ;; FIXME: Is this right?
- )
- ()
-)
-
-;relative jump if bit not set and set bit
-;JNBS bitaddrQ.q,rel
-(dni jnbs "relative jump if bit not set and set bit"
- ((PIPE OS) (IDOC JMP))
- "jnbs $genreg$dot$qlobit,$relhi"
- (+ OP1_11 OP2_10 genreg relhi qlobit (f-qhibit 0))
- (sequence ((HI tmp1) (HI tmp2))
- (set HI tmp1 genreg)
- (set HI tmp2 (const 1))
- ;;(sll HI tmp2 qlobit) - FIXME: missing (set ...)
- (set HI tmp2 (and tmp1 tmp2))
- (if (eq tmp2 (const 0))
- (sequence ()
- ;; FIXME: The `else' clause has several statements.
- (if (lt QI relhi (const 0))
- (set tmp2 (const 1))
- (set tmp1 reg8)
- ;; FIXME: (sll tmp2 qbit)
- (set BI tmp1(or tmp1 tmp2))
- (set HI reg8 tmp1)
- (set HI pc (add HI pc (mul QI relhi (const 2)))))
- ))
- (set HI pc (add HI pc (const 4))) ;; FIXME: Is this right?
- )
- ()
-)
-
-
-;Absolute conditional call
-(define-pmacro (callabs name insn)
- (dni name
- (.str name "Absolute conditional call" )
- ((PIPE OS) (IDOC JMP))
- (.str insn " $extcond,$caddr")
- (+ OP1_12 OP2_10 extcond (f-op-2bit 0) bit01 caddr)
- (sequence ()
- (if (eq extcond (const 1))
- (set bit01 (const 0))
- (set (reg h-cr 9) (sub HI (reg h-cr 9) (const 2)))
- (set HI (mem HI (reg h-cr 9)) pc)
- (set HI pc (mem HI caddr)))
- (if (ne extcond (const 1))
- (set bit01 (const 1))
- (set HI pc (add HI pc (const 2))))
- )
- ()
- )
-)
-
-(callabs calla0 calla+)
-(callabs calla1 calla)
-
-; CALLA- cc,caddr
-(dni calla- "Absolute conditional call"
- (COND-CTI (PIPE OS) (IDOC JMP))
- "calla- $extcond,$caddr"
- (+ OP1_12 OP2_10 extcond (f-op-bit3 1) caddr)
- (sequence ()
- (if (eq extcond (const 1))
- (set (reg h-cr 9) (sub HI (reg h-cr 9) (const 2)))
- (set HI (mem HI (reg h-cr 9)) pc)
- (set HI pc (mem HI caddr)))
- (set HI pc (add HI pc (const 2)))
- )
- ()
-)
-
-; CALLI cc,[Rwn]
-(dni calli "indirect subroutine call"
- (COND-CTI (PIPE OS) (IDOC JMP))
- "calli $icond,[$sr]"
- (+ OP1_10 OP2_11 icond sr)
- (sequence ()
- (if (eq icond (const 1))
- (sequence ()
- (set (reg h-cr 9) (sub HI (reg h-cr 9) (const 2)))
- (set HI (mem HI (reg h-cr 9)) pc)
- (set HI pc (mem HI sr))
- )
- )
- (set HI pc (add HI pc (const 2)))
- )
- ()
-)
-
-; CALLR rel
-(dni callr "Call subroutine with PC relative signed 8 bit offset"
- ( COND-CTI (PIPE OS) (IDOC JMP))
- "callr $rel"
- (+ OP1_11 OP2_11 rel)
- (sequence ()
- (set (reg h-cr 9) (sub HI (reg h-cr 9) (const 2)))
- (set HI (mem HI (reg h-cr 9)) pc)
- (sequence ()
- (if (lt QI rel (const 0))
- (sequence ()
- ;; FIXME: (neg QI rel)
- ;; FIXME: (add QI rel (const 1))
- ;; FIXME: (mul QI rel (const 2))
- (set HI pc (sub HI pc rel))
- ))
- (set HI pc (add HI pc (mul QI rel (const 2))))
- )
- )
- ()
-)
-
-
-; CALLS seg,caddr
-(dni callseg "call inter-segment subroutine"
- (UNCOND-CTI (PIPE OS) (IDOC JMP))
- "calls $hash$segm$useg8,$hash$sof$usof16"
- (+ OP1_13 OP2_10 useg8 usof16)
- (sequence ()
- (set (reg h-cr 9) (sub HI (reg h-cr 9) (const 2)))
- (set HI (mem HI (reg h-cr 9)) (reg h-cr 10))
- (set (reg h-cr 9) (sub HI (reg h-cr 9) (const 2)))
- (set HI (mem HI (reg h-cr 9)) pc)
- (if (eq BI sgtdisbit (const BI 0))
- (set QI (reg h-cr 10) useg8))
- ;; FIXME: previous indentation suggested this nop was the `else'
- ;; clause of the previous `if'.
- (nop)
- (set HI pc usof16)
- )
- ()
-)
-
-; CALLS seg,caddr
-(dni calls "call inter-segment subroutine"
- (UNCOND-CTI (PIPE OS) (IDOC JMP))
- "calls $seg,$caddr"
- (+ OP1_13 OP2_10 seg caddr)
- (sequence ()
- (set (reg h-cr 9) (sub HI (reg h-cr 9) (const 2)))
- (set HI (mem HI (reg h-cr 9)) (reg h-cr 10))
- (set (reg h-cr 9) (sub HI (reg h-cr 9) (const 2)))
- (set HI (mem HI (reg h-cr 9)) pc)
- (if (eq BI sgtdisbit (const BI 0))
- (set QI (reg h-cr 10) seg))
- ;; FIXME: previous indentation suggested this nop was the `else'
- ;; clause of the previous `if'.
- (nop)
- (set HI pc caddr)
- )
- ()
-)
-
-; PCALL reg,caddr
-(dni pcall "push word and call absolute subroutine"
- (UNCOND-CTI (PIPE OS) (IDOC JMP))
- "pcall $reg8,$caddr"
- (+ OP1_14 OP2_2 reg8 caddr)
- (sequence ((HI tmp1))
- (set HI tmp1 reg8)
- (set (reg h-cr 9) (sub HI (reg h-cr 9) (const 2)))
- (set HI (mem HI (reg h-cr 9)) tmp1)
- (set (reg h-cr 9) (sub HI (reg h-cr 9) (const 2)))
- (set HI (mem HI (reg h-cr 9)) pc)
- (set HI pc caddr)
- )
- ()
-)
-
-; TRAP #uimm7
-(dni trap "software trap"
- (UNCOND-CTI (PIPE OS) (IDOC JMP))
- "trap $hash$uimm7"
- (+ OP1_9 OP2_11 uimm7 (f-op-1bit 0))
- (sequence ()
- (set (reg h-cr 9) (sub HI (reg h-cr 9) (const 2)))
- (set HI (mem HI (reg h-cr 9)) (reg h-cr 4))
- (if (eq BI sgtdisbit (const BI 0))
- (set (reg h-cr 9) (sub HI (reg h-cr 9) (const 2)))
- (set HI (mem HI (reg h-cr 9)) (reg h-cr 10) )
- )
- (nop)
- (set HI (reg h-cr 10) (reg h-cr 11))
- (set (reg h-cr 9) (sub HI (reg h-cr 9) (const 2)))
- (set HI (mem HI (reg h-cr 9)) pc)
- (set HI pc (mul QI uimm7 (const 4)))
- )
- ()
-)
-
-;Return insns
-; RET
-(dni ret "return from subroutine"
- (UNCOND-CTI (PIPE OS) (IDOC JMP))
- "ret"
- (+ OP1_12 OP2_11 (f-op-bit8 0))
- (sequence ()
- (set HI pc (mem HI (reg h-cr 9)))
- (set (reg h-cr 9) (add HI (reg h-cr 9) (const 2)))
- )
- ()
-)
-
-; RETS
-(dni rets "return from inter-segment sunroutine"
- (UNCOND-CTI (PIPE OS) (IDOC JMP))
- "rets"
- (+ OP1_13 OP2_11 (f-op-bit8 0))
- (sequence ()
- (set HI pc (mem HI (reg h-cr 9)))
- (set (reg h-cr 9) (add HI (reg h-cr 9) (const 2)))
- (if (eq BI sgtdisbit (const BI 0))
- (set HI (reg h-cr 10) (mem HI (reg h-cr 9)))
- )
- (nop)
- (set (reg h-cr 9) (add HI (reg h-cr 9) (const 2)))
- )
- ()
-)
-
-; RETP reg
-(dni retp "return from subroutine and pop word register"
- (UNCOND-CTI (PIPE OS) (IDOC JMP))
- "retp $reg8"
- (+ OP1_14 OP2_11 reg8)
- (sequence ((HI tmp1))
- (set HI pc (mem HI (reg h-cr 9)))
- (set (reg h-cr 9) (add HI (reg h-cr 9) (const 2)))
- (set HI tmp1 (mem HI (reg h-cr 9)))
- (set (reg h-cr 9) (add HI (reg h-cr 9) (const 2)))
- (set HI reg8 tmp1)
- )
- ()
-)
-
-; RETI
-(dni reti "return from ISR"
- (UNCOND-CTI (PIPE OS) (IDOC JMP))
- "reti"
- (+ OP1_15 OP2_11 (f-op-lbit4 8) (f-op-bit4 8))
- (sequence ()
- (set HI pc (mem HI (reg h-cr 9)))
- (set (reg h-cr 9) (add HI (reg h-cr 9) (const 2)))
- (if (eq BI sgtdisbit (const BI 0))
- (sequence ()
- (set HI (reg h-cr 10) (mem HI (reg h-cr 9)))
- (set (reg h-cr 9) (add HI (reg h-cr 9) (const 2)))
- )
- )
- (nop)
- (set HI (reg h-cr 4) (mem HI (reg h-cr 9)))
- (set (reg h-cr 9) (add HI (reg h-cr 9) (const 2)))
- )
- ()
-)
-
-;stack operation insn
-;******************************************************************
-; POP reg
-(dni pop "restore register from system stack"
- ((PIPE OS) (IDOC MISC))
- "pop $reg8"
- (+ OP1_15 OP2_12 reg8)
- (sequence ((HI tmp1))
- (set HI tmp1 (mem HI (reg h-cr 9)))
- (set (reg h-cr 9) (add HI (reg h-cr 9) (const 2)))
- (set HI reg8 tmp1)
- )
- ()
-)
-
-; PUSH reg
-(dni push "save register on system stack"
- ((PIPE OS) (IDOC MISC))
- "push $reg8"
- (+ OP1_14 OP2_12 reg8)
- (sequence ((HI tmp1))
- (set HI tmp1 reg8)
- (set (reg h-cr 9) (sub HI (reg h-cr 9) (const 2)))
- (set HI (mem HI (reg h-cr 9)) tmp1)
- )
- ()
-)
-
-;context switching insns
-; SCXT reg,#data16
-(dni scxti "Push word register on stack and update same with immediate data"
- ((PIPE OS) (IDOC MISC))
- "scxt $reg8,$hash$uimm16"
- (+ OP1_12 OP2_6 reg8 uimm16)
- (sequence ((HI tmp1) (HI tmp2))
- (set HI tmp1 reg8)
- (set HI tmp2 uimm16)
- ;; FIXME: (sub HI (reg HI h-cr 9) (const 2))
- (set HI (reg HI h-cr 9) tmp1)
- (set HI reg8 tmp2)
- )
- ()
-)
-
-; SCXT reg,POF mem
-(dni scxtrpofm "mov memory to byte register"
- ((PIPE OS) (IDOC MOVE))
- "scxt $reg8,$pof$upof16"
- (+ OP1_13 OP2_6 reg8 upof16)
- (set QI reg8 (mem HI upof16))
- ()
-)
-
-; SCXT regmem8,memgr8
-(dni scxtmg "Push word register on stack and update same with direct memory"
- ((PIPE OS) (IDOC MISC))
- "scxt $regmem8,$memgr8"
- (+ OP1_13 OP2_6 regmem8 memgr8)
- (sequence ((HI tmp1) (HI tmp2))
- (set HI tmp1 regmem8)
- (set HI tmp2 memgr8)
- ;; FIXME: (sub HI (reg HI h-cr 9) (const 2))
- (set HI (reg HI h-cr 9) tmp1)
- (set HI regmem8 tmp2)
- )
- ()
-)
-
-; SCXT reg,mem
-(dni scxtm "Push word register on stack and update same with direct memory"
- ((PIPE OS) (IDOC MISC))
- "scxt $reg8,$memory"
- (+ OP1_13 OP2_6 reg8 memory)
- (sequence ((HI tmp1) (HI tmp2))
- (set HI tmp1 reg8)
- (set HI tmp2 memory)
- ;; FIXME: (sub HI (reg HI h-cr 9) (const 2))
- (set HI (reg HI h-cr 9) tmp1)
- (set HI reg8 tmp2)
- )
- ()
-)
-
-;No operation
-; NOP
-(dni nop "nop"
- ((PIPE OS) (IDOC MISC))
- "nop"
- (+ OP1_12 OP2_12 (f-op-bit8 0))
- ()
- ()
-)
-
-;*********system control instructions *********************/
-
-(define-pmacro (sysctrl name insn opc1 opc2 op1 op2 op3)
- (dni name
- (.str name "miscellaneous" )
- ((PIPE OS) (IDOC MISC))
- (.str insn )
- (+ opc1 opc2 (f-op-lbit4 op1) (f-op-bit4 op2) (f-data8 op3) (f-op-bit8 op3))
- ()
- ()
- )
-)
-(sysctrl srstm srst OP1_11 OP2_7 4 8 183 )
-(sysctrl idlem idle OP1_8 OP2_7 7 8 135)
-(sysctrl pwrdnm pwrdn OP1_9 OP2_7 6 8 151)
-(sysctrl diswdtm diswdt OP1_10 OP2_5 5 10 165)
-(sysctrl enwdtm enwdt OP1_8 OP2_5 7 10 133)
-(sysctrl einitm einit OP1_11 OP2_5 4 10 181)
-(sysctrl srvwdtm srvwdt OP1_10 OP2_7 5 8 167 )
-
-;s/w brk
-; SBRK
-(dni sbrk "sbrk"
- ((PIPE OS) (IDOC MISC))
- "sbrk"
- (+ OP1_8 OP2_12 (f-op-bit8 0))
- ()
- ()
-)
-
-; atomic sequence
-; ATOMIC #irang2
-(dni atomic "begin atomic sequence"
- ((PIPE OS) (IDOC SYSC))
- "atomic $hash$uimm2"
- (+ OP1_13 OP2_1 (f-op-lbit2 0) uimm2 (f-op-bit4 0))
- (sequence ((HI count))
- (set HI count uimm2)
- (cond
- ((ne HI count (const 0))
- (sequence ()
- (set HI pc (add HI pc (const 2)))
- (set HI count (sub HI count (const 1)))
- ))
- )
- (set HI count (const 0))
- )
- ()
-)
-
-;extended register sequence
-; EXTR #irang2
-(dni extr "begin extended register sequence"
- ((PIPE OS) (IDOC SYSC))
- "extr $hash$uimm2"
- (+ OP1_13 OP2_1 (f-op-lbit2 2) uimm2 (f-op-bit4 0))
- (sequence ((HI count))
- (set HI count uimm2)
- (cond
- ((ne HI count (const 0))
- (sequence ()
- (set HI pc (add HI pc (const 2)))
- (set HI count (sub HI count (const 1)))
- ))
- )
- (set HI count (const 0))
- )
- ()
-)
-
-;extended page sequence
-; EXTP Rw,#irang2
-(dni extp "begin extended page sequence"
- ((PIPE OS) (IDOC SYSC))
- "extp $sr,$hash$uimm2"
- (+ OP1_13 OP2_12 (f-op-lbit2 1) uimm2 sr)
- (sequence ((HI count))
- (set HI count uimm2)
- (cond
- ((ne HI count (const 0))
- (sequence ()
- (set HI pc (add HI pc (const 2)))
- (set HI count (sub HI count (const 1)))
- ))
- )
- (set HI count (const 0))
- )
- ()
-)
-
-;extended page sequence
-; EXTP #pag10,#irang2
-(dni extp1 "begin extended page sequence"
- ((PIPE OS) (IDOC SYSC))
- "extp $hash$pagenum,$hash$uimm2"
- (+ OP1_13 OP2_7 (f-op-lbit2 1) uimm2 (f-op-bit4 0) pagenum (f-qlobit 0) (f-qlobit2 0))
- (sequence ((HI count))
- (set HI count uimm2)
- (cond
- ((ne HI count (const 0))
- (sequence ()
- (set HI pc (add HI pc (const 2)))
- (set HI count (sub HI count (const 1)))
- ))
- )
- (set HI count (const 0))
- )
- ()
-)
-
-; EXTP #pag10,#irang2
-(dni extpg1 "begin extended page sequence"
- ((PIPE OS) (IDOC SYSC))
- "extp $hash$pag$upag16,$hash$uimm2"
- (+ OP1_13 OP2_7 (f-op-lbit2 1) uimm2 (f-op-bit4 0) upag16 )
- (sequence ((HI count))
- (set HI count uimm2)
- (cond
- ((ne HI count (const 0))
- (sequence ()
- (set HI pc (add HI pc (const 2)))
- (set HI count (sub HI count (const 1)))
- ))
- )
- (set HI count (const 0))
- )
- ()
-)
-
-;extended page and register sequence
-; EXTPR Rw,#irang2
-(dni extpr "begin extended page and register sequence"
- ((PIPE OS) (IDOC SYSC))
- "extpr $sr,$hash$uimm2"
- (+ OP1_13 OP2_12 (f-op-lbit2 3) uimm2 sr)
- (sequence ((HI count))
- (set HI count uimm2)
- (cond
- ((ne HI count (const 0))
- (sequence ()
- (set HI pc (add HI pc (const 2)))
- (set HI count (sub HI count (const 1)))
- ))
- )
- (set HI count (const 0))
- )
- ()
-)
-
-;extended page and register sequence
-; EXTPR #pag10,#irang2
-(dni extpr1 "begin extended page sequence"
- ((PIPE OS) (IDOC SYSC))
- "extpr $hash$pagenum,$hash$uimm2"
- (+ OP1_13 OP2_7 (f-op-lbit2 3) uimm2 (f-op-bit4 0) pagenum (f-qlobit 0) (f-qlobit2 0))
- (sequence ((HI count))
- (set HI count uimm2)
- (cond
- ((ne HI count (const 0))
- (sequence ()
- (set HI pc (add HI pc (const 2)))
- (set HI count (sub HI count (const 1)))
- ))
- )
- (set HI count (const 0))
- )
- ()
-)
-
-;extended segment sequence
-; EXTS Rw,#irang2
-(dni exts "begin extended segment sequence"
- ((PIPE OS) (IDOC SYSC))
- "exts $sr,$hash$uimm2"
- (+ OP1_13 OP2_12 (f-op-lbit2 0) uimm2 sr)
- (sequence ((HI count))
- (set HI count uimm2)
- (cond
- ((ne HI count (const 0))
- (sequence ()
- (set HI pc (add HI pc (const 2)))
- (set HI count (sub HI count (const 1)))
- ))
- )
- (set HI count (const 0))
- )
- ()
-)
-
-;extended segment sequence
-; EXTS #seg8,#irang2
-(dni exts1 "begin extended segment sequence"
- ((PIPE OS) (IDOC SYSC))
- "exts $hash$seghi8,$hash$uimm2"
- (+ OP1_13 OP2_7 (f-op-lbit2 0) uimm2 (f-op-bit4 0) seghi8 (f-op-bit8 0))
- (sequence ((HI count))
- (set HI count uimm2)
- (cond
- ((ne HI count (const 0))
- (sequence ()
- (set HI pc (add HI pc (const 2)))
- (set HI count (sub HI count (const 1)))
- ))
- )
- (set HI count (const 0))
- )
- ()
-)
-
-;extended segment register sequence
-; EXTSR Rwm,#irang2
-(dni extsr "begin extended segment and register sequence"
- ((PIPE OS) (IDOC SYSC))
- "extsr $sr,$hash$uimm2"
- (+ OP1_13 OP2_12 (f-op-lbit2 2) uimm2 sr)
- (sequence ((HI count))
- (set HI count uimm2)
- (cond
- ((ne HI count (const 0))
- (sequence ()
- (set HI pc (add HI pc (const 2)))
- (set HI count (sub HI count (const 1)))
- ))
- )
- (set HI count (const 0))
- )
- ()
-)
-
-;extended segment register sequence
-; EXTSR #pag10,#irang2
-(dni extsr1 "begin extended segment and register sequence"
- ((PIPE OS) (IDOC SYSC))
- "extsr $hash$seghi8,$hash$uimm2"
- (+ OP1_13 OP2_7 (f-op-lbit2 2) uimm2 (f-op-bit4 0) seghi8 (f-op-bit8 0))
- (sequence ((HI count))
- (set HI count uimm2)
- (cond
- ((ne HI count (const 0))
- (sequence ()
- (set HI pc (add HI pc (const 2)))
- (set HI count (sub HI count (const 1)))
- ))
- )
- (set HI count (const 0))
- )
- ()
-)
-
-;prioritize register
-;PRIOR Rwn,Rwm
-(dni prior "add registers"
- ((PIPE OS) (IDOC ALU))
- "prior $dr,$sr"
- (+ OP1_2 OP2_11 dr sr)
- (sequence ((HI count) (HI tmp1) (HI tmp2))
- (set HI count (const 0))
- (set HI tmp1 sr)
- (set HI tmp2 (and tmp1 (const 32768)))
- (cond
- ((ne HI tmp2 (const 1)) ;;(ne HI sr (const 0)) - FIXME: and? or?
- ;;(sll HI tmp1 (const 1)) - FIXME: missing (set ...)
- (set HI tmp2 (and tmp1 (const 32768)))
- (set HI count (add HI count (const 1)))
- )
- )
- (set HI dr count)
- )
- ()
-)
-
-
-;bit instructions
-;******************************************************************
-;bit clear
-(define-pmacro (bclear name insn opc1)
- (dni name
- (.str name "bit clear" )
- ((PIPE OS) (IDOC ALU))
- (.str insn " $reg8$dot$qbit")
- (+ opc1 OP2_14 reg8)
- (sequence ((HI tmp1) (HI tmp2))
- (set tmp2 (const 1))
- (set tmp1 reg8)
- ;; FIXME: (sll tmp2 qbit)
- ;; FIXME: (inv tmp2)
- (set BI tmp1(and tmp1 tmp2))
- (set HI reg8 tmp1))
- ()
- )
-)
-
-;clear direct bit
-(dni bclr18 "bit logical MOVN"
- ((PIPE OS) (IDOC ALU))
- "bclr $RegNam"
- (+ OP1_11 OP2_14 RegNam)
- (sequence ((HI tmp1) (HI tmp2))
- (set tmp2 (const 1))
- (set tmp1 reg8)
- ;; FIXME: (sll tmp2 qbit)
- ;; FIXME: (inv tmp2)
- (set BI tmp1(and tmp1 tmp2))
- (set HI reg8 tmp1))
- ()
-)
-
-
-(bclear bclr0 bclr QBIT_0 )
-(bclear bclr1 bclr QBIT_1 )
-(bclear bclr2 bclr QBIT_2 )
-(bclear bclr3 bclr QBIT_3 )
-(bclear bclr4 bclr QBIT_4 )
-(bclear bclr5 bclr QBIT_5 )
-(bclear bclr6 bclr QBIT_6 )
-(bclear bclr7 bclr QBIT_7 )
-(bclear bclr8 bclr QBIT_8 )
-(bclear bclr9 bclr QBIT_9 )
-(bclear bclr10 bclr QBIT_10 )
-(bclear bclr11 bclr QBIT_11 )
-(bclear bclr12 bclr QBIT_12 )
-(bclear bclr13 bclr QBIT_13 )
-(bclear bclr14 bclr QBIT_14 )
-(bclear bclr15 bclr QBIT_15 )
-
-;set direct bit
-(dni bset19 "bit logical MOVN"
- ((PIPE OS) (IDOC ALU))
- "bset $RegNam"
- (+ OP1_11 OP2_15 RegNam)
- (sequence ((HI tmp1) (HI tmp2))
- (set tmp2 (const 1))
- (set tmp1 reg8)
- ;; FIXME: (sll tmp2 qbit)
- (set BI tmp1(or tmp1 tmp2))
- (set HI reg8 tmp1))
- ()
-)
-
-;bit set
-(define-pmacro (bitset name insn opc1)
- (dni name
- (.str name "bit set" )
- ((PIPE OS) (IDOC ALU))
- (.str insn " $reg8$dot$qbit")
- (+ opc1 OP2_15 reg8)
- (sequence ((HI tmp1) (HI tmp2))
- (set tmp2 (const 1))
- (set tmp1 reg8)
- ;; FIXME: (sll tmp2 qbit)
- (set BI tmp1(or tmp1 tmp2))
- (set HI reg8 tmp1))
- ()
- )
-)
-
-
-(bitset bset0 bset QBIT_0 )
-(bitset bset1 bset QBIT_1 )
-(bitset bset2 bset QBIT_2 )
-(bitset bset3 bset QBIT_3 )
-(bitset bset4 bset QBIT_4 )
-(bitset bset5 bset QBIT_5 )
-(bitset bset6 bset QBIT_6 )
-(bitset bset7 bset QBIT_7 )
-(bitset bset8 bset QBIT_8 )
-(bitset bset9 bset QBIT_9 )
-(bitset bset10 bset QBIT_10 )
-(bitset bset11 bset QBIT_11 )
-(bitset bset12 bset QBIT_12 )
-(bitset bset13 bset QBIT_13 )
-(bitset bset14 bset QBIT_14 )
-(bitset bset15 bset QBIT_15 )
-
-;mov direct bit
-;BMOV bitaddrZ.z,bitaddrQ.q
-(dni bmov "bit logical MOV"
- ((PIPE OS) (IDOC ALU))
- "bmov $reghi8$dot$qhibit,$reg8$dot$qlobit"
- (+ OP1_4 OP2_10 reg8 reghi8 qhibit qlobit)
- (sequence ((HI tmp1) (HI tmp2) (HI tmp3) (HI tmp4))
- (set HI tmp1 reghi8)
- (set HI tmp2 reg8)
- (set tmp3 (const 1))
- (set tmp4 (const 1))
- ;; FIXME: (sll tmp3 qlobit)
- ;; FIXME: (sll tmp4 qhibit)
- ;; FIXME: (and tmp1 tmp3)
- ;; FIXME: (and tmp2 tmp4)
- (set BI tmp1 tmp2)
- (set HI reghi8 tmp1)
- (set HI reg8 tmp2))
- ()
-)
-
-;movn direct bit
-;BMOVN bitaddrZ.z,bitaddrQ.q
-(dni bmovn "bit logical MOVN"
- ((PIPE OS) (IDOC ALU))
- "bmovn $reghi8$dot$qhibit,$reg8$dot$qlobit"
- (+ OP1_3 OP2_10 reg8 reghi8 qhibit qlobit)
- (sequence ((HI tmp1) (HI tmp2) (HI tmp3) (HI tmp4))
- (set HI tmp1 reghi8)
- (set HI tmp2 reg8)
- (set tmp3 (const 1))
- (set tmp4 (const 1))
- ;; FIXME: (sll tmp3 qlobit)
- ;; FIXME: (sll tmp4 qhibit)
- ;; FIXME: (and tmp1 tmp3)
- ;; FIXME: (and tmp2 tmp4)
- ;; FIXME: (inv HI tmp2)
- (set BI tmp1 tmp2)
- (set HI reghi8 tmp1)
- (set HI reg8 tmp2))
- ()
-)
-
-;and direct bit
-;BAND bitaddrZ.z,bitaddrQ.q
-(dni band "bit logical AND"
- ((PIPE OS) (IDOC ALU))
- "band $reghi8$dot$qhibit,$reg8$dot$qlobit"
- (+ OP1_6 OP2_10 reg8 reghi8 qhibit qlobit)
- (sequence ((HI tmp1) (HI tmp2) (HI tmp3) (HI tmp4))
- (set HI tmp1 reghi8)
- (set HI tmp2 reg8)
- (set tmp3 (const 1))
- (set tmp4 (const 1))
- ;; FIXME: (sll tmp3 qlobit)
- ;; FIXME: (sll tmp4 qhibit)
- ;; FIXME: (and tmp1 tmp3)
- ;; FIXME: (and tmp2 tmp4)
- (set BI tmp1(and tmp1 tmp2))
- (set HI reghi8 tmp1)
- (set HI reg8 tmp2))
- ()
-)
-
-;or direct bit
-;BOR bitaddrZ.z,bitaddrQ.q
-(dni bor "bit logical OR"
- ((PIPE OS) (IDOC ALU))
- "bor $reghi8$dot$qhibit,$reg8$dot$qlobit"
- (+ OP1_5 OP2_10 reg8 reghi8 qhibit qlobit)
- (sequence ((HI tmp1) (HI tmp2) (HI tmp3) (HI tmp4))
- (set HI tmp1 reghi8)
- (set HI tmp2 reg8)
- (set tmp3 (const 1))
- (set tmp4 (const 1))
- ;; FIXME: (sll tmp3 qlobit)
- ;; FIXME: (sll tmp4 qhibit)
- ;; FIXME: (and tmp1 tmp3)
- ;; FIXME: (and tmp2 tmp4)
- (set BI tmp1(or tmp1 tmp2))
- (set HI reghi8 tmp1)
- (set HI reg8 tmp2))
- ()
-)
-
-;xor direct bit
-;BXOR bitaddrZ.z,bitaddrQ.q
-(dni bxor "bit logical XOR"
- ((PIPE OS) (IDOC ALU))
- "bxor $reghi8$dot$qhibit,$reg8$dot$qlobit"
- (+ OP1_7 OP2_10 reg8 reghi8 qhibit qlobit)
- (sequence ((HI tmp1) (HI tmp2) (HI tmp3) (HI tmp4))
- (set HI tmp1 reghi8)
- (set HI tmp2 reg8)
- (set tmp3 (const 1))
- (set tmp4 (const 1))
- ;; FIXME: (sll tmp3 qlobit)
- ;; FIXME: (sll tmp4 qhibit)
- ;; FIXME: (and tmp1 tmp3)
- ;; FIXME: (and tmp2 tmp4)
- (set BI tmp1(xor tmp1 tmp2))
- (set HI reghi8 tmp1)
- (set HI reg8 tmp2))
- ()
-)
-
-;cmp direct bit to bit
-;BCMP bitaddrZ.z,bitaddrQ.q
-(dni bcmp "bit to bit compare"
- ((PIPE OS) (IDOC ALU))
- "bcmp $reghi8$dot$qhibit,$reg8$dot$qlobit"
- (+ OP1_2 OP2_10 reg8 reghi8 qhibit qlobit)
- (sequence ((HI tmp1) (HI tmp2) (HI tmp3) (HI tmp4))
- (set HI tmp1 reghi8)
- (set HI tmp2 reg8)
- (set tmp3 (const 1))
- (set tmp4 (const 1))
- ;; FIXME: (sll tmp3 qlobit)
- ;; FIXME: (sll tmp4 qhibit)
- ;; FIXME: (and tmp1 tmp3)
- ;; FIXME: (and tmp2 tmp4)
- (set BI tmp1(xor tmp1 tmp2))
- (set HI reghi8 tmp1)
- (set HI reg8 tmp2))
- ()
-)
-
-;bit field low byte
-;BFLDL op1,op2,op3
-(dni bfldl "bit field low byte"
- ((PIPE OS) (IDOC MOVE))
- "bfldl $reg8,$hash$mask8,$hash$datahi8"
- (+ OP1_0 OP2_10 reg8 mask8 datahi8)
- (sequence ((HI tmp1) (QI tmp2) (QI tmp3))
- (set HI tmp1 reg8)
- (set QI tmp2 mask8)
- (set QI tmp3 datahi8)
- ;; FIXME: (inv QI tmp2)
- (set HI tmp1 (and tmp1 tmp2))
- (set HI tmp1 (or tmp1 tmp3))
- (set HI reg8 tmp1)
- )
- ()
-)
-
-;bit field high byte
-;BFLDH op1,op2,op3
-(dni bfldh "bit field high byte"
- ((PIPE OS) (IDOC MOVE))
- "bfldh $reg8,$hash$masklo8,$hash$data8"
- (+ OP1_1 OP2_10 reg8 masklo8 data8)
- (sequence ((HI tmp1) (HI tmp2) (HI tmp3))
- (set HI tmp1 reg8)
- (set QI tmp2 masklo8)
- (set HI tmp3 data8)
- ;; FIXME: (sll tmp2 (const 8))
- ;; FIXME: (inv HI tmp2)
- ;; FIXME: (sll tmp3 (const 8))
- (set HI tmp1 (and tmp1 tmp2))
- (set HI tmp1 (or tmp1 tmp3))
- (set HI reg8 tmp1)
- )
- ()
-)
-
-;/**********compare instructions******************
-
-;Compare register
-;CMP Rwn,Rwm
-(dni cmpr "compare two registers"
- ((PIPE OS) (IDOC CMP))
- "cmp $src1,$src2"
- (+ OP1_4 OP2_0 src1 src2)
- (set condbit (lt HI src1 src2))
- ()
-)
-
-;Compare byte register
-;CMPB Rbn,Rbm
-(dni cmpbr "compare two byte registers"
- ((PIPE OS) (IDOC CMP))
- "cmpb $drb,$srb"
- (+ OP1_4 OP2_1 drb srb)
- (set condbit (lt QI drb srb))
- ()
-)
-
-(define-pmacro (cmp1 name insn opc1 opc2 op1 op2 mode)
- (dni name
- (.str name "compare" )
- ((PIPE OS) (IDOC CMP))
- (.str insn " $"op1 ",$hash$"op2)
- (+ opc1 opc2 op1 (f-op-bit1 0) op2)
- (set condbit (lt mode op1 op2))
- ()
- )
-)
-(cmp1 cmpri cmp OP1_4 OP2_8 src1 uimm3 HI)
-(cmp1 cmpbri cmpb OP1_4 OP2_9 drb uimm3 QI)
-
-; CMP Rwn,#data16
-(dni cmpi "compare"
- ((PIPE OS) (IDOC CMP))
- "cmp $reg8,$hash$uimm16"
- (+ OP1_4 OP2_6 reg8 uimm16)
- (set condbit (lt HI reg8 uimm16))
- ()
-)
-
-; CMPB reg,#data8
-(dni cmpbi "compare"
- ((PIPE OS) (IDOC CMP))
- "cmpb $regb8,$hash$uimm8"
- (+ OP1_4 OP2_7 regb8 uimm8 (f-op-bit8 0))
- (set condbit (lt QI regb8 uimm8))
- ()
-)
-
-;compare reg and indirect memory
-(define-pmacro (cmp2 name insn opc1 opc2 op1 op2 mode)
- (dni name
- (.str name "compare" )
- ((PIPE OS) (IDOC CMP))
- (.str insn " $"op1 ",[$"op2"]")
- (+ opc1 opc2 op1 (f-op-bit2 2) op2)
- (set condbit (lt mode op1 op2))
- ()
- )
-)
-(cmp2 cmpr2 cmp OP1_4 OP2_8 dr sr2 HI)
-(cmp2 cmpbr2 cmpb OP1_4 OP2_9 drb sr2 QI)
-
-;compare register and indirect memory post increment
-(define-pmacro (cmp3 name insn opc1 opc2 op1 op2 mode)
- (dni name
- (.str name "compare" )
- ((PIPE OS) (IDOC CMP))
- (.str insn " $"op1 ",[$"op2"+]")
- (+ opc1 opc2 op1 (f-op-bit2 3) op2)
- (sequence ()
- (set condbit (lt mode op1 op2))
- (set HI op2 (add HI op2 (const 2)))
- )
- ()
- )
-)
-(cmp3 cmp2i cmp OP1_4 OP2_8 dr sr2 HI)
-(cmp3 cmpb2i cmpb OP1_4 OP2_9 drb sr2 QI)
-
-;compare register and direct memory
-(define-pmacro (cmp4 name insn opc1 opc2 op1 op2 mode)
- (dni name
- (.str name "compare" )
- ((PIPE OS) (IDOC CMP))
- (.str insn " $"op1 ",$pof$"op2)
- (+ opc1 opc2 op1 op2)
- (set condbit (lt HI op1 (mem HI op2)))
- ()
- )
-)
-(cmp4 cmp04 cmp OP1_4 OP2_2 reg8 upof16 HI)
-(cmp4 cmpb4 cmpb OP1_4 OP2_3 regb8 upof16 QI)
-
-;compare register and direct memory
-(define-pmacro (cmp4 name insn opc1 opc2 op1 op2 mode)
- (dni name
- (.str name "compare" )
- ((PIPE OS) (IDOC CMP))
- (.str insn " $"op1 ",$"op2)
- (+ opc1 opc2 op1 op2)
- (set condbit (lt HI op1 (mem HI op2)))
- ()
- )
-)
-(cmp4 cmp004 cmp OP1_4 OP2_2 regmem8 memgr8 HI)
-(cmp4 cmp0004 cmp OP1_4 OP2_2 reg8 memory HI)
-(cmp4 cmpb04 cmpb OP1_4 OP2_3 regbmem8 memgr8 QI)
-(cmp4 cmpb004 cmpb OP1_4 OP2_3 regb8 memory QI)
-
-;compare register and immediate
-(define-pmacro (cmp5 name insn opc1 opc2 op1 op2 mode)
- (dni name
- (.str name "compare" )
- ((PIPE OS) (IDOC CMP))
- (.str insn " $"op1 ",$hash$"op2)
- (+ opc1 opc2 op2 op1)
- (sequence ()
- (set condbit (lt HI op1 op2))
- (set mode op1 (sub HI op1 (const 1)))
- )
- ()
- )
-)
-(cmp5 cmpd1ri cmpd1 OP1_10 OP2_0 sr uimm4 HI)
-(cmp5 cmpd2ri cmpd2 OP1_11 OP2_0 sr uimm4 HI)
-(cmp5 cmpi1ri cmpi1 OP1_8 OP2_0 sr uimm4 HI)
-(cmp5 cmpi2ri cmpi2 OP1_9 OP2_0 sr uimm4 HI)
-(cmp5 cmpd1rim cmpd1 OP1_10 OP2_6 reg8 uimm16 HI)
-(cmp5 cmpd2rim cmpd2 OP1_11 OP2_6 reg8 uimm16 HI)
-(cmp5 cmpi1rim cmpi1 OP1_8 OP2_6 reg8 uimm16 HI)
-(cmp5 cmpi2rim cmpi2 OP1_9 OP2_6 reg8 uimm16 HI)
-
-;compare register and direct memory
-(define-pmacro (cmp6 name insn opc1 opc2 op1 op2 mode )
- (dni name
- (.str name "compare" )
- ((PIPE OS) (IDOC CMP))
- (.str insn " $"op1 ",$pof$"op2)
- (+ opc1 opc2 op1 op2)
- (sequence ()
- (set condbit (lt HI op1 (mem HI op2)))
- (set mode op1 (sub HI op1 (const 1)))
- )
- ()
- )
-)
-(cmp6 cmpd1rp cmpd1 OP1_10 OP2_2 reg8 upof16 HI )
-(cmp6 cmpd2rp cmpd2 OP1_11 OP2_2 reg8 upof16 HI )
-(cmp6 cmpi1rp cmpi1 OP1_8 OP2_2 reg8 upof16 HI )
-(cmp6 cmpi2rp cmpi2 OP1_9 OP2_2 reg8 upof16 HI )
-
-;compare register and direct memory
-(define-pmacro (cmp7 name insn opc1 opc2 op1 op2 mode)
- (dni name
- (.str name "compare" )
- ((PIPE OS) (IDOC CMP))
- (.str insn " $"op1 ",$"op2)
- (+ opc1 opc2 op1 op2)
- (sequence ()
- (set condbit (lt HI op1 (mem HI op2)))
- (set mode op1 (sub HI op1 (const 1)))
- )
- ()
- )
-)
-(cmp7 cmpd1rm cmpd1 OP1_10 OP2_2 regmem8 memgr8 HI)
-(cmp7 cmpd2rm cmpd2 OP1_11 OP2_2 regmem8 memgr8 HI)
-(cmp7 cmpi1rm cmpi1 OP1_8 OP2_2 regmem8 memgr8 HI)
-(cmp7 cmpi2rm cmpi2 OP1_9 OP2_2 regmem8 memgr8 HI)
-(cmp7 cmpd1rmi cmpd1 OP1_10 OP2_2 reg8 memory HI)
-(cmp7 cmpd2rmi cmpd2 OP1_11 OP2_2 reg8 memory HI)
-(cmp7 cmpi1rmi cmpi1 OP1_8 OP2_2 reg8 memory HI)
-(cmp7 cmpi2rmi cmpi2 OP1_9 OP2_2 reg8 memory HI)
-
-
-;Shift and rotate insns
-;****************************************************************
-(define-pmacro (shift name insn insn1 opc1 opc2 op1 op2 mode)
- (dni name
- (.str name "shift" )
- ((PIPE OS) (IDOC ALU))
- (.str insn " $"op1 ",$"op2)
- (+ opc1 opc2 op1 op2)
- (set mode op1 (insn1 mode op1 op2))
- ()
- )
-)
-(shift shlr shl sll OP1_4 OP2_12 dr sr HI)
-(shift shrr shr srl OP1_6 OP2_12 dr sr HI)
-(shift rolr rol rol OP1_0 OP2_12 dr sr HI)
-(shift rorr ror ror OP1_2 OP2_12 dr sr HI)
-(shift ashrr ashr sra OP1_10 OP2_12 dr sr HI)
-
-(define-pmacro (shift1 name insn insn1 opc1 opc2 op1 op2 mode)
- (dni name
- (.str name "shift" )
- ((PIPE OS) (IDOC ALU))
- (.str insn " $"op1 ",$hash$"op2)
- (+ opc1 opc2 op2 op1)
- (set mode op1 (insn1 mode op1 op2))
- ()
- )
-)
-(shift1 shlri shl sll OP1_5 OP2_12 sr uimm4 HI)
-(shift1 shrri shr srl OP1_7 OP2_12 sr uimm4 HI)
-(shift1 rolri rol rol OP1_1 OP2_12 sr uimm4 HI)
-(shift1 rorri ror ror OP1_3 OP2_12 sr uimm4 HI)
-(shift1 ashrri ashr sra OP1_11 OP2_12 sr uimm4 HI)
+++ /dev/null
-/* XC16X opcode support. -*- C -*-
-
- Copyright 2006, 2007, 2009 Free Software Foundation, Inc.
-
- Contributed by KPIT Cummins Infosystems Ltd.; developed under contract
- from Infineon Systems, GMBH , Germany.
-
- This file is part of the GNU Binutils.
-
- This program is free software; you can redistribute it and/or modify
- it under the terms of the GNU General Public License as published by
- the Free Software Foundation; either version 3 of the License, or
- (at your option) any later version.
-
- This program is distributed in the hope that it will be useful,
- but WITHOUT ANY WARRANTY; without even the implied warranty of
- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- GNU General Public License for more details.
-
- You should have received a copy of the GNU General Public License
- along with this program; if not, write to the Free Software
- Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
- 02110-1301, USA. */
-
-
-/* This file is an addendum to xc16x.cpu. Heavy use of C code isn't
- appropriate in .cpu files, so it resides here. This especially applies
- to assembly/disassembly where parsing/printing can be quite involved.
- Such things aren't really part of the specification of the cpu, per se,
- so .cpu files provide the general framework and .opc files handle the
- nitty-gritty details as necessary.
-
- Each section is delimited with start and end markers.
-
- <arch>-opc.h additions use: "-- opc.h"
- <arch>-opc.c additions use: "-- opc.c"
- <arch>-asm.c additions use: "-- asm.c"
- <arch>-dis.c additions use: "-- dis.c"
- <arch>-ibd.h additions use: "-- ibd.h" */
-\f
-/* -- opc.h */
-
-#define CGEN_DIS_HASH_SIZE 8
-#define CGEN_DIS_HASH(buf,value) (((* (unsigned char*) (buf)) >> 3) % CGEN_DIS_HASH_SIZE)
-
-/* -- */
-\f
-/* -- opc.c */
-
-/* -- */
-\f
-/* -- asm.c */
-/* Handle '#' prefixes (i.e. skip over them). */
-
-static const char *
-parse_hash (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
- const char **strp,
- int opindex ATTRIBUTE_UNUSED,
- long *valuep ATTRIBUTE_UNUSED)
-{
- if (**strp == '#')
- {
- ++*strp;
- return NULL;
- }
- return _("Missing '#' prefix");
-}
-
-/* Handle '.' prefixes (i.e. skip over them). */
-
-static const char *
-parse_dot (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
- const char **strp,
- int opindex ATTRIBUTE_UNUSED,
- long *valuep ATTRIBUTE_UNUSED)
-{
- if (**strp == '.')
- {
- ++*strp;
- return NULL;
- }
- return _("Missing '.' prefix");
-}
-
-/* Handle 'pof:' prefixes (i.e. skip over them). */
-
-static const char *
-parse_pof (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
- const char **strp,
- int opindex ATTRIBUTE_UNUSED,
- long *valuep ATTRIBUTE_UNUSED)
-{
- if (strncasecmp (*strp, "pof:", 4) == 0)
- {
- *strp += 4;
- return NULL;
- }
- return _("Missing 'pof:' prefix");
-}
-
-/* Handle 'pag:' prefixes (i.e. skip over them). */
-
-static const char *
-parse_pag (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
- const char **strp,
- int opindex ATTRIBUTE_UNUSED,
- long *valuep ATTRIBUTE_UNUSED)
-{
- if (strncasecmp (*strp, "pag:", 4) == 0)
- {
- *strp += 4;
- return NULL;
- }
- return _("Missing 'pag:' prefix");
-}
-
-/* Handle 'sof' prefixes (i.e. skip over them). */
-
-static const char *
-parse_sof (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
- const char **strp,
- int opindex ATTRIBUTE_UNUSED,
- long *valuep ATTRIBUTE_UNUSED)
-{
- if (strncasecmp (*strp, "sof:", 4) == 0)
- {
- *strp += 4;
- return NULL;
- }
- return _("Missing 'sof:' prefix");
-}
-
-/* Handle 'seg' prefixes (i.e. skip over them). */
-
-static const char *
-parse_seg (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
- const char **strp,
- int opindex ATTRIBUTE_UNUSED,
- long *valuep ATTRIBUTE_UNUSED)
-{
- if (strncasecmp (*strp, "seg:", 4) == 0)
- {
- *strp += 4;
- return NULL;
- }
- return _("Missing 'seg:' prefix");
-}
-/* -- */
-\f
-/* -- dis.c */
-
-/* Print an operand with a "." prefix.
- NOTE: This prints the operand in hex.
- ??? This exists to maintain disassembler compatibility with previous
- versions. Ideally we'd print the "." in print_dot. */
-
-static void
-print_with_dot_prefix (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
- void * dis_info,
- long value,
- unsigned attrs ATTRIBUTE_UNUSED,
- bfd_vma pc ATTRIBUTE_UNUSED,
- int length ATTRIBUTE_UNUSED)
-{
- disassemble_info *info = (disassemble_info *) dis_info;
-
- info->fprintf_func (info->stream, ".");
- info->fprintf_func (info->stream, "0x%lx", value);
-}
-
-/* Print an operand with a "#pof:" prefix.
- NOTE: This prints the operand as an address.
- ??? This exists to maintain disassembler compatibility with previous
- versions. Ideally we'd print "#pof:" in print_pof. */
-
-static void
-print_with_pof_prefix (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
- void * dis_info,
- bfd_vma value,
- unsigned attrs ATTRIBUTE_UNUSED,
- bfd_vma pc ATTRIBUTE_UNUSED,
- int length ATTRIBUTE_UNUSED)
-{
- disassemble_info *info = (disassemble_info *) dis_info;
-
- info->fprintf_func (info->stream, "#pof:");
- info->fprintf_func (info->stream, "0x%lx", (long) value);
-}
-
-/* Print an operand with a "#pag:" prefix.
- NOTE: This prints the operand in hex.
- ??? This exists to maintain disassembler compatibility with previous
- versions. Ideally we'd print "#pag:" in print_pag. */
-
-static void
-print_with_pag_prefix (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
- void * dis_info,
- long value,
- unsigned attrs ATTRIBUTE_UNUSED,
- bfd_vma pc ATTRIBUTE_UNUSED,
- int length ATTRIBUTE_UNUSED)
-{
- disassemble_info *info = (disassemble_info *) dis_info;
-
- info->fprintf_func (info->stream, "#pag:");
- info->fprintf_func (info->stream, "0x%lx", value);
-}
-
-/* Print a 'pof:' prefix to an operand. */
-
-static void
-print_pof (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
- void * dis_info ATTRIBUTE_UNUSED,
- long value ATTRIBUTE_UNUSED,
- unsigned int attrs ATTRIBUTE_UNUSED,
- bfd_vma pc ATTRIBUTE_UNUSED,
- int length ATTRIBUTE_UNUSED)
-{
-}
-
-/* Print a 'pag:' prefix to an operand. */
-
-static void
-print_pag (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
- void * dis_info ATTRIBUTE_UNUSED,
- long value ATTRIBUTE_UNUSED,
- unsigned int attrs ATTRIBUTE_UNUSED,
- bfd_vma pc ATTRIBUTE_UNUSED,
- int length ATTRIBUTE_UNUSED)
-{
-}
-
-/* Print a 'sof:' prefix to an operand. */
-
-static void
-print_sof (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
- void * dis_info,
- long value ATTRIBUTE_UNUSED,
- unsigned int attrs ATTRIBUTE_UNUSED,
- bfd_vma pc ATTRIBUTE_UNUSED,
- int length ATTRIBUTE_UNUSED)
-{
- disassemble_info *info = (disassemble_info *) dis_info;
-
- info->fprintf_func (info->stream, "sof:");
-}
-
-/* Print a 'seg:' prefix to an operand. */
-
-static void
-print_seg (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
- void * dis_info,
- long value ATTRIBUTE_UNUSED,
- unsigned int attrs ATTRIBUTE_UNUSED,
- bfd_vma pc ATTRIBUTE_UNUSED,
- int length ATTRIBUTE_UNUSED)
-{
- disassemble_info *info = (disassemble_info *) dis_info;
-
- info->fprintf_func (info->stream, "seg:");
-}
-
-/* Print a '#' prefix to an operand. */
-
-static void
-print_hash (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
- void * dis_info,
- long value ATTRIBUTE_UNUSED,
- unsigned int attrs ATTRIBUTE_UNUSED,
- bfd_vma pc ATTRIBUTE_UNUSED,
- int length ATTRIBUTE_UNUSED)
-{
- disassemble_info *info = (disassemble_info *) dis_info;
-
- info->fprintf_func (info->stream, "#");
-}
-
-/* Print a '.' prefix to an operand. */
-
-static void
-print_dot (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
- void * dis_info ATTRIBUTE_UNUSED,
- long value ATTRIBUTE_UNUSED,
- unsigned int attrs ATTRIBUTE_UNUSED,
- bfd_vma pc ATTRIBUTE_UNUSED,
- int length ATTRIBUTE_UNUSED)
-{
-}
-
-/* -- */
config/tc-visium.c \
config/tc-wasm32.c \
config/tc-xstormy16.c \
- config/tc-xc16x.c \
config/tc-xgate.c \
config/tc-xtensa.c \
config/tc-z80.c \
config/tc-visium.h \
config/tc-wasm32.h \
config/tc-xstormy16.h \
- config/tc-xc16x.h \
config/tc-xgate.h \
config/tc-xtensa.h \
config/tc-z80.h \
config/tc-visium.c \
config/tc-wasm32.c \
config/tc-xstormy16.c \
- config/tc-xc16x.c \
config/tc-xgate.c \
config/tc-xtensa.c \
config/tc-z80.c \
config/tc-visium.h \
config/tc-wasm32.h \
config/tc-xstormy16.h \
- config/tc-xc16x.h \
config/tc-xgate.h \
config/tc-xtensa.h \
config/tc-z80.h \
config/$(DEPDIR)/$(am__dirstamp)
config/tc-xstormy16.$(OBJEXT): config/$(am__dirstamp) \
config/$(DEPDIR)/$(am__dirstamp)
-config/tc-xc16x.$(OBJEXT): config/$(am__dirstamp) \
- config/$(DEPDIR)/$(am__dirstamp)
config/tc-xgate.$(OBJEXT): config/$(am__dirstamp) \
config/$(DEPDIR)/$(am__dirstamp)
config/tc-xtensa.$(OBJEXT): config/$(am__dirstamp) \
@AMDEP_TRUE@@am__include@ @am__quote@config/$(DEPDIR)/tc-vax.Po@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@config/$(DEPDIR)/tc-visium.Po@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@config/$(DEPDIR)/tc-wasm32.Po@am__quote@
-@AMDEP_TRUE@@am__include@ @am__quote@config/$(DEPDIR)/tc-xc16x.Po@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@config/$(DEPDIR)/tc-xgate.Po@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@config/$(DEPDIR)/tc-xstormy16.Po@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@config/$(DEPDIR)/tc-xtensa.Po@am__quote@
+++ /dev/null
-/* tc-xc16x.c -- Assembler for the Infineon XC16X.
- Copyright (C) 2006-2022 Free Software Foundation, Inc.
- Contributed by KPIT Cummins Infosystems
-
- This file is part of GAS, the GNU Assembler.
-
- GAS is free software; you can redistribute it and/or modify
- it under the terms of the GNU General Public License as published by
- the Free Software Foundation; either version 3, or (at your option)
- any later version.
-
- GAS is distributed in the hope that it will be useful,
- but WITHOUT ANY WARRANTY; without even the implied warranty of
- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- GNU General Public License for more details.
-
- You should have received a copy of the GNU General Public License
- along with GAS; see the file COPYING. If not, write to the Free
- Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
- 02110-1301, USA. */
-
-
-#include "as.h"
-#include "safe-ctype.h"
-#include "subsegs.h"
-#include "symcat.h"
-#include "opcodes/xc16x-desc.h"
-#include "opcodes/xc16x-opc.h"
-#include "cgen.h"
-#include "dwarf2dbg.h"
-
-
-#ifdef OBJ_ELF
-#include "elf/xc16x.h"
-#endif
-
-/* Structure to hold all of the different components describing
- an individual instruction. */
-typedef struct
-{
- const CGEN_INSN * insn;
- const CGEN_INSN * orig_insn;
- CGEN_FIELDS fields;
-#if CGEN_INT_INSN_P
- CGEN_INSN_INT buffer [1];
-#define INSN_VALUE(buf) (*(buf))
-#else
- unsigned char buffer [CGEN_MAX_INSN_SIZE];
-#define INSN_VALUE(buf) (buf)
-#endif
- char * addr;
- fragS * frag;
- int num_fixups;
- fixS * fixups [GAS_CGEN_MAX_FIXUPS];
- int indices [MAX_OPERAND_INSTANCES];
-}
-xc16x_insn;
-
-const char comment_chars[] = ";";
-const char line_comment_chars[] = "#";
-const char line_separator_chars[] = "";
-const char EXP_CHARS[] = "eE";
-const char FLT_CHARS[] = "dD";
-
-#define XC16X_SHORTOPTS ""
-const char * md_shortopts = XC16X_SHORTOPTS;
-
-struct option md_longopts[] =
-{
- {NULL, no_argument, NULL, 0}
-};
-size_t md_longopts_size = sizeof (md_longopts);
-
-static void
-xc16xlmode (int arg ATTRIBUTE_UNUSED)
-{
- if (stdoutput != NULL)
- if (!bfd_set_arch_mach (stdoutput, bfd_arch_xc16x, bfd_mach_xc16xl))
- as_warn (_("could not set architecture and machine"));
-}
-
-static void
-xc16xsmode (int arg ATTRIBUTE_UNUSED)
-{
- if (!bfd_set_arch_mach (stdoutput, bfd_arch_xc16x, bfd_mach_xc16xs))
- as_warn (_("could not set architecture and machine"));
-}
-
-static void
-xc16xmode (int arg ATTRIBUTE_UNUSED)
-{
- if (!bfd_set_arch_mach (stdoutput, bfd_arch_xc16x, bfd_mach_xc16x))
- as_warn (_("could not set architecture and machine"));
-}
-
-/* The target specific pseudo-ops which we support. */
-const pseudo_typeS md_pseudo_table[] =
-{
- { "word", cons, 2 },
- {"xc16xl", xc16xlmode, 0},
- {"xc16xs", xc16xsmode, 0},
- {"xc16x", xc16xmode, 0},
- { NULL, NULL, 0 }
-};
-
-void
-md_begin (void)
-{
- /* Initialize the `cgen' interface. */
-
- /* Set the machine number and endian. */
- gas_cgen_cpu_desc = xc16x_cgen_cpu_open (CGEN_CPU_OPEN_MACHS, 0,
- CGEN_CPU_OPEN_ENDIAN,
- CGEN_ENDIAN_LITTLE,
- CGEN_CPU_OPEN_END);
- xc16x_cgen_init_asm (gas_cgen_cpu_desc);
-
- /* This is a callback from cgen to gas to parse operands. */
- cgen_set_parse_operand_fn (gas_cgen_cpu_desc, gas_cgen_parse_operand);
-}
-
-void
-md_assemble (char *str)
-{
- xc16x_insn insn;
- char *errmsg;
-
- /* Initialize GAS's cgen interface for a new instruction. */
- gas_cgen_init_parse ();
-
- insn.insn = xc16x_cgen_assemble_insn
- (gas_cgen_cpu_desc, str, & insn.fields, insn.buffer, & errmsg);
-
- if (!insn.insn)
- {
- as_bad ("%s", errmsg);
- return;
- }
-
- /* Doesn't really matter what we pass for RELAX_P here. */
- gas_cgen_finish_insn (insn.insn, insn.buffer,
- CGEN_FIELDS_BITSIZE (& insn.fields), 1, NULL);
-}
-
-/* Return the bfd reloc type for OPERAND of INSN at fixup FIXP.
- Returns BFD_RELOC_NONE if no reloc type can be found.
- *FIXP may be modified if desired. */
-
-bfd_reloc_code_real_type
-md_cgen_lookup_reloc (const CGEN_INSN *insn ATTRIBUTE_UNUSED,
- const CGEN_OPERAND *operand,
- fixS *fixP)
-{
- switch (operand->type)
- {
- case XC16X_OPERAND_REL:
- /* ??? Adjust size? */
- fixP->fx_where += 1;
- fixP->fx_pcrel = 1;
- return BFD_RELOC_8_PCREL;
-
- case XC16X_OPERAND_CADDR:
- fixP->fx_size = 2;
- fixP->fx_where += 2;
- return BFD_RELOC_16;
-
- case XC16X_OPERAND_UIMM7:
- /* ??? Adjust size? */
- fixP->fx_where += 1;
- fixP->fx_pcrel = 1;
- return BFD_RELOC_8_PCREL;
-
- case XC16X_OPERAND_UIMM16:
- case XC16X_OPERAND_MEMORY:
- fixP->fx_size = 2;
- fixP->fx_where += 2;
- return BFD_RELOC_16;
-
- case XC16X_OPERAND_UPOF16:
- fixP->fx_size = 2;
- fixP->fx_where += 2;
- return BFD_RELOC_XC16X_POF;
-
- case XC16X_OPERAND_UPAG16:
- fixP->fx_size = 2;
- fixP->fx_where += 2;
- return BFD_RELOC_XC16X_PAG;
-
- case XC16X_OPERAND_USEG8:
- /* ??? This is an 8 bit field, why the 16 bit reloc? */
- fixP->fx_where += 1;
- return BFD_RELOC_XC16X_SEG;
-
- case XC16X_OPERAND_USEG16:
- case XC16X_OPERAND_USOF16:
- fixP->fx_size = 2;
- fixP->fx_where += 2;
- return BFD_RELOC_XC16X_SOF;
-
- default : /* Avoid -Wall warning. */
- break;
- }
-
- return BFD_RELOC_NONE;
-}
-
-/* Write a value out to the object file, using the appropriate endianness. */
-
-void
-md_number_to_chars (char * buf, valueT val, int n)
-{
- number_to_chars_littleendian (buf, val, n);
-}
-
-void
-md_show_usage (FILE * stream)
-{
- fprintf (stream, _(" XC16X specific command line options:\n"));
-}
-
-int
-md_parse_option (int c ATTRIBUTE_UNUSED,
- const char *arg ATTRIBUTE_UNUSED)
-{
- return 0;
-}
-
-const char *
-md_atof (int type, char *litP, int *sizeP)
-{
- return ieee_md_atof (type, litP, sizeP, false);
-}
-
-valueT
-md_section_align (segT segment, valueT size)
-{
- int align = bfd_section_alignment (segment);
- return ((size + (1 << align) - 1) & -(1 << align));
-}
-
-symbolS *
-md_undefined_symbol (char *name ATTRIBUTE_UNUSED)
-{
- return NULL;
-}
-
-int
-md_estimate_size_before_relax (fragS *fragP ATTRIBUTE_UNUSED,
- segT segment_type ATTRIBUTE_UNUSED)
-{
- printf (_("call to md_estimate_size_before_relax \n"));
- abort ();
-}
-
-
-long
-md_pcrel_from (fixS *fixP)
-{
- long temp_val;
- temp_val=fixP->fx_size + fixP->fx_where + fixP->fx_frag->fr_address;
-
- return temp_val;
-}
-
-long
-md_pcrel_from_section (fixS *fixP, segT sec)
-{
- if (fixP->fx_addsy != (symbolS *) NULL
- && (! S_IS_DEFINED (fixP->fx_addsy)
- || S_GET_SEGMENT (fixP->fx_addsy) != sec
- || S_IS_EXTERNAL (fixP->fx_addsy)
- || S_IS_WEAK (fixP->fx_addsy)))
- {
- return 0;
- }
-
- return md_pcrel_from (fixP);
-}
-
-arelent *
-tc_gen_reloc (asection *section ATTRIBUTE_UNUSED, fixS *fixp)
-{
- arelent *rel;
- bfd_reloc_code_real_type r_type;
-
- if (fixp->fx_subsy)
- {
- if ((S_GET_SEGMENT (fixp->fx_addsy) != S_GET_SEGMENT (fixp->fx_subsy))
- || S_GET_SEGMENT (fixp->fx_addsy) == undefined_section)
- {
- as_bad_subtract (fixp);
- return NULL;
- }
- }
-
- rel = XNEW (arelent);
- rel->sym_ptr_ptr = XNEW (asymbol *);
- *rel->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
- rel->address = fixp->fx_frag->fr_address + fixp->fx_where;
- rel->addend = fixp->fx_offset;
-
- r_type = fixp->fx_r_type;
-
-#define DEBUG 0
-#if DEBUG
- fprintf (stderr, "%s\n", bfd_get_reloc_code_name (r_type));
- fflush (stderr);
-#endif
-
- rel->howto = bfd_reloc_type_lookup (stdoutput, r_type);
- if (rel->howto == NULL)
- {
- as_bad_where (fixp->fx_file, fixp->fx_line,
- _("Cannot represent relocation type %s"),
- bfd_get_reloc_code_name (r_type));
- return NULL;
- }
-
- return rel;
-}
-
-void
-md_apply_fix (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED)
-{
- /* FIXME: This absolute nonsense apparently is to make relative
- jumps "work". Of course, it breaks any other type of fixup. */
- if (!strstr (seg->name,".debug"))
- {
- if (*valP < 128)
- *valP /= 2;
- if (*valP>268435455)
- {
- *valP = *valP * (-1);
- *valP /= 2;
- *valP = 256 - (*valP);
- }
- }
-
- gas_cgen_md_apply_fix (fixP, valP, seg);
- return;
-}
-
-void
-md_convert_frag (bfd *headers ATTRIBUTE_UNUSED,
- segT seg ATTRIBUTE_UNUSED,
- fragS *fragP ATTRIBUTE_UNUSED)
-{
- printf (_("call to md_convert_frag \n"));
- abort ();
-}
+++ /dev/null
-/* This file is tc-xc16x.h
- Copyright (C) 2006-2022 Free Software Foundation, Inc.
- Contributed by KPIT Cummins Infosystems
-
- This file is part of GAS, the GNU Assembler.
-
- GAS is free software; you can redistribute it and/or modify
- it under the terms of the GNU General Public License as published by
- the Free Software Foundation; either version 3, or (at your option)
- any later version.
-
- GAS is distributed in the hope that it will be useful,
- but WITHOUT ANY WARRANTY; without even the implied warranty of
- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- GNU General Public License for more details.
-
- You should have received a copy of the GNU General Public License
- along with GAS; see the file COPYING. If not, write to the Free
- Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
- 02110-1301, USA. */
-
-#define TC_XC16X
-
-#define TARGET_BYTES_BIG_ENDIAN 0
-
-#define TARGET_ARCH bfd_arch_xc16x
-
-#ifdef OBJ_ELF
-#define TARGET_FORMAT "elf32-xc16x"
-#define LOCAL_LABEL_PREFIX '.'
-#define LOCAL_LABEL(NAME) (NAME[0] == '.' && NAME[1] == 'L')
-#define FAKE_LABEL_NAME ".L0\001"
-#endif
-
-struct fix;
-struct internal_reloc;
-
-#define WORKING_DOT_WORD
-
-#define BFD_ARCH bfd_arch_xc16x
-#define TC_COUNT_RELOC(x) 1
-#define IGNORE_NONSTANDARD_ESCAPES
-
-#define TC_RELOC_MANGLE(s,a,b,c) tc_reloc_mangle(a,b,c)
-extern void tc_reloc_mangle (struct fix *, struct internal_reloc *, bfd_vma);
-
-/* No shared lib support, so we don't need to ensure externally
- visible symbols can be overridden. */
-#define EXTERN_FORCE_RELOC 0
-
-/* Minimum instruction is of 16 bits. */
-#define DWARF2_LINE_MIN_INSN_LENGTH 2
-
-#define DO_NOT_STRIP 0
-#define LISTING_HEADER "Infineon XC16X GAS "
-#define NEED_FX_R_TYPE 1
-#define MD_PCREL_FROM_SECTION(FIX, SEC) md_pcrel_from_section (FIX, SEC)
-
-#define md_operand(x)
using_cgen=yes
;;
- xc16x)
- using_cgen=yes
- ;;
-
xtensa)
f=config/xtensa-relax.o
case " $extra_objects " in
using_cgen=yes
;;
- xc16x)
- using_cgen=yes
- ;;
-
xtensa)
f=config/xtensa-relax.o
case " $extra_objects " in
@set LM32
@set M32C
@set M32R
-@set xc16x
@set M68HC11
@set S12Z
@set M680X0
+++ /dev/null
-@c Copyright (C) 2006-2022 Free Software Foundation, Inc.
-@c This is part of the GAS manual.
-@c For copying conditions, see the file as.texinfo.
-
-@page
-@node xc16x-Dependent
-@chapter Infineon xc16x Dependent Features
-
-@cindex xc16x support
-@menu
-* xc16x Directives:: xc16x Machine Directives
-* xc16x Syntax:: xc16x Syntax
-@end menu
-
-@node xc16x Directives
-@section xc16x Machine Directives
-
-The xc16x version of the assembler supports the following machine
-directives:
-
-@table @code
-@cindex @code{align} directive, xc16x
-@item .align
-This directive aligns the section program counter on the next 2-byte
-boundary.
-
-
-@cindex @code{byte} directive, xc16x
-@item .byte @var{expr}
-This directive assembles a half-word (8-bit) constant.
-
-@cindex @code{word} directive, xc16x
-@item .word @var{expr}
-This assembles a word (16-bit) constant.
-
-@cindex @code{ascii} directive, xc16x
-@item .ascii "@var{ascii}"
-This directive used for copying @var{str} into the object file.
-The string is terminated with a null byte.
-
-@cindex @code{set} directive, xc16x
-@item .set @var{symbol}, @var{value}
-This directive creates a symbol named @var{symbol} which is an alias for
-another symbol (possibly not yet defined). This should not be confused
-with the mnemonic @code{set}, which is a legitimate xc16x instruction.
-
-
-
-@cindex @code{bss} directive, xc16x
-@item .bss @var{symbol}, @var{length}
-Reserve @var{length} bytes in the bss section for a local @var{symbol},
-aligned to the power of two specified by @var{align}. @var{length} and
-@var{align} must be positive absolute expressions. This directive
-differs from @samp{.lcomm} only in that it permits you to specify
-an alignment.
-@end table
-
-@node xc16x Syntax
-@section xc16x Syntax
-@menu
-* xc16x-Chars:: Special Characters
-@end menu
-
-@node xc16x-Chars
-@subsection Special Characters
-
-@cindex line comment character, xc16x
-@cindex xc16c line comment character
-The presence of a @samp{;} appearing anywhere on a line indicates the
-start of a comment that extends to the end of that line.
-
-If a @samp{#} appears as the first character of a line then the whole
-line is treated as a comment, but in this case the line can also be a
-logical line number directive (@pxref{Comments}) or a preprocessor
-control command (@pxref{Preprocessing}).
-
-@cindex line separator, xc16x
-@cindex statement separator, xc16x
-@cindex xc16x line separator
-The XC16X assembler does not support a line separator character.
config/tc-visium.h
config/tc-wasm32.c
config/tc-wasm32.h
-config/tc-xc16x.c
-config/tc-xc16x.h
config/tc-xgate.c
config/tc-xgate.h
config/tc-xstormy16.c
+++ /dev/null
-.text
-xc16x_add:
-add r0,r1
-add r0,[r1]
-add r0,[r1+]
-add r0,#3
-add r0,#1234
-add r0,0xffed
-add 0xffed,r0
-
-
-
-
-
-
-
-
\ No newline at end of file
+++ /dev/null
-.text
-_start:
- add r0,r1
- add r0,r2
- add r0,r3
- add r0,r4
- add r0,r5
- add r0,r6
- add r0,r7
- add r0,r8
- add r0,r9
- add r0,r10
- add r0,r11
- add r0,r12
- add r0,r13
- add r0,r14
- add r0,r15
-
- add r1,r0
- add r1,r2
- add r1,r3
- add r1,r4
- add r1,r5
- add r1,r6
- add r1,r7
- add r1,r8
- add r1,r9
- add r1,r10
- add r1,r11
- add r1,r12
- add r1,r13
- add r1,r14
- add r1,r15
-
- add r2,r0
- add r2,r1
- add r2,r3
- add r2,r4
- add r2,r5
- add r2,r6
- add r2,r7
- add r2,r8
- add r2,r9
- add r2,r10
- add r2,r11
- add r2,r12
- add r2,r13
- add r2,r14
- add r2,r15
-
- add r3,r0
- add r3,r1
- add r3,r2
- add r3,r4
- add r3,r5
- add r3,r6
- add r3,r7
- add r3,r8
- add r3,r9
- add r3,r10
- add r3,r11
- add r3,r12
- add r3,r13
- add r3,r14
- add r3,r15
-
- add r0,[r1]
- add r0,[r1+]
- add r0,#3
- add r0,#0xffff
- add r0,0xffff
- add 0xffff,r0
-
- addb rl0,rh0
- addb rl0[r0]
- addb rl0,#3
- addb rl0,#0xff
- addb r0,0xff10
- addb 0xff10,r0
-
- addc r0,r1
- addc r0,[r1]
- addc r0,#3
- addc r0,#0xff12
- addc r0,#0xff12
- addc r0,0xff12
- addc 0xff12,r0
-
- addcb rl0,#3
- addcb rl0,#0xff
- addcb r0,0xff10
- addcb 0xff10,r0
\ No newline at end of file
+++ /dev/null
- .section .text
- .global _fun
-xc16x_add:
-
- addb rl0,rl1
- addb rl0,[r1]
- addb rl0,[r1+]
- addb rl0,#0x2
- addb rl0,#0x33
- addb rl0,0x2387
- addb 0x2387,rl0
+++ /dev/null
- .section .text
- .global _fun
-xc16x_add:
-
- addc r0,r1
- addc r0,[r1]
- addc r0,[r1+]
- addc r0,#0x34
- addc r0,#0x3456
- addc r0,0x2387
- addc 0x2387,r0
+++ /dev/null
- .section .text
- .global _fun
-xc16x_add:
-
- addcb rl0,rl1
- addcb rl0,[r1]
- addcb rl0,[r1+]
- addcb rl0,#0x02
- addcb rl0,#0x23
- addcb 0x2387,rl0
-
-
-
-
-
-
-
\ No newline at end of file
+++ /dev/null
-.section .text
-.global _fun
-
-xc16x_and:
-
- and r0,r1
- and r0,[r1]
- and r0,[r1+]
- and r0,#3
- and r0,#0xfcbe
- and r0,0x0230
- and 0x320,r0
-
-
\ No newline at end of file
+++ /dev/null
- .section .text
- .global _fun
-xc16x_andb:
- andb rl0,rl1
- andb rl0,[r1]
- andb rl0,[r1+]
- andb rl0,#3
- andb rl0,#0xbe
- andb rl0,0x0230
- andb 0x320,rl0
+++ /dev/null
- .text
- xc16x_bfldl:
- BFLDL r0,#0x87,#0x0e
- BFLDH r0,#0xff,#0x0e
+++ /dev/null
-.text
-xc16x_bit:
-bclr r0.1
-bset r0.1
-bmov r0.2,r0.1
-bmovn r0.3,r0.2
-band r0.1,r0.4
-bor r0.1,r0.2
-bxor r0.1,r0.2
-bcmp r0.1,r0.2
-
\ No newline at end of file
+++ /dev/null
-.text
-xc16x_calla:
-calla cc_uc,0xaaaa
-calla cc_z,0xaaaa
-calla cc_nz,0xaaaa
-calla cc_v,0xaaaa
-calla cc_nv,0xaaaa
-calla cc_n,0xaaaa
-calla cc_nn,0xaaaa
-calla cc_c,0xaaaa
-calla cc_nc,0xaaaa
-calla cc_eq,0xaaaa
-calla cc_ne,0xaaaa
-calla cc_ult,0xaaaa
-calla cc_ule,0xaaaa
-calla cc_uge,0xaaaa
-calla cc_ugt,0xaaaa
-calla cc_sle,0xaaaa
-calla cc_sge,0xaaaa
-calla cc_sgt,0xaaaa
-calla cc_net,0xaaaa
-calla cc_slt,0xaaaa
-
-
\ No newline at end of file
+++ /dev/null
-.text
-xc16x_calli:
-calli cc_uc,[r1]
-calli cc_z,[r1]
-calli cc_nz,[r1]
-calli cc_v,[r1]
-calli cc_nv,[r1]
-calli cc_n,[r1]
-calli cc_nn,[r1]
-calli cc_c,[r1]
-calli cc_nc,[r1]
-calli cc_eq,[r1]
-calli cc_ne,[r1]
-calli cc_ult,[r1]
-calli cc_ule,[r1]
-calli cc_uge,[r1]
-calli cc_ugt,[r1]
-calli cc_sle,[r1]
-calli cc_sge,[r1]
-calli cc_net,[r1]
-calli cc_slt,[r1]
+++ /dev/null
-.text
-xc16x_cmp:
-cmp r0,r1
-cmp r0,[r1]
-cmp r0,[r1+]
-cmp r0,#3
-cmp r0,#0x0234
-cmp r0,0x3452
-
\ No newline at end of file
+++ /dev/null
-.text
-cmp r0,r1
-cmp r0,[r1]
-cmp r0,[r1+]
-cmp r0,#3
-cmp r0,#0x0234
-cmp r0,0x3452
-
-cmp r0,r1
-cmp r0,[r1]
-cmp r0,[r1+]
-cmp r0,#3
-cmp r0,#0xcdef
-cmp r0,0xcdef
-
-cmpb rl0,rl1
-cmpb rl0,[r1]
-cmpb rl0,[r1+]
-cmpb rl0,#3
-cmpb rl0,#cd
-cmpb rl0,0x0234
-
-cmpb rl0,rl1
-cmpb rl0,[r1]
-cmpb rl0,[r1+]
-cmpb rl0,#3
-cmpb rl0,#cd
-cmpb rl0,0xcdef
-
-cmpd1 r0,#0x0f
-cmpd1 r0,#0x0fccb
-cmpd1 r0,0xffcb
-cmpd2 r0,#0x0f
-cmpd2 r0,#0x0fccb
-cmpd2 r0,0xffcb
-
-cmpi1 r0,#0x0f
-cmpi1 r0,#0x0fccb
-cmpi1 r0,0xffcb
-cmpi2 r0,#0x0f
-cmpi2 r0,#0x0fccb
-cmpi2 r0,0xffcb
-
-
-
+++ /dev/null
-.text
-xc16x_cmpb:
-cmpb rl0,rl1
-cmpb rl0,[r1]
-cmpb rl0,[r1+]
-cmpb rl0,#3
-cmpb rl0,#34
-cmpb rl0,0x0234
+++ /dev/null
-.section .text
-.global _fun
-
-xc16x_cmpd:
-
- cmpd1 r0,#0x0f
- cmpd1 r0,#0x0fccb
- cmpd1 r0,0xffcb
- cmpd2 r0,#0x0f
- cmpd2 r0,#0x0fccb
- cmpd2 r0,0xffcb
- cmpi1 r0,#0x0f
- cmpi1 r0,#0x0fccb
- cmpi1 r0,0xffcb
- cmpi2 r0,#0x0f
- cmpi2 r0,#0x0fccb
- cmpi2 r0,0xffcb
-
\ No newline at end of file
+++ /dev/null
- .section .text
- .global _fun
-
-xc16x_cpl_cplb:
-
- cpl r0
- cplb rl0
+++ /dev/null
- .section .text
- .global _fun
-xc16x_div:
-
- div r0
- divl r0
- divlu r0
- divu r0
+++ /dev/null
-.text
-xc16x_jmpa:
- jmpa cc_UC,0xaaaa
- jmpa cc_Z,0xaaaa
- jmpa cc_NZ,0xaaaa
- jmpa cc_V,0xaaaa
- jmpa cc_NV,0xaaaa
- jmpa cc_N,0xaaaa
- jmpa cc_NN,0xaaaa
- jmpa cc_ULT,0xaaaa
- jmpa cc_UGE,0xaaaa
- jmpa cc_Z,0xaaaa
- jmpa cc_NZ,0xaaaa
- jmpa cc_ULT,0xaaaa
- jmpa cc_ULE,0xaaaa
- jmpa cc_UGE,0xaaaa
- jmpa cc_UGT,0xaaaa
- jmpa cc_SLE,0xaaaa
- jmpa cc_SGE,0xaaaa
- jmpa cc_SGT,0xaaaa
- jmpa cc_NET,0xaaaa
-
-
+++ /dev/null
-.section .text
-.global _fun
-
-xc16x_jmpi:
-
- jmpi cc_UC, [r7]
- jmpi cc_z, [r7]
- jmpi cc_NZ, [r7]
- jmpi cc_V, [r7]
- jmpi cc_NV, [r7]
- jmpi cc_N, [r7]
- jmpi cc_NN, [r7]
- jmpi cc_C, [r7]
- jmpi cc_NC, [r7]
- jmpi cc_EQ, [r7]
- jmpi cc_NE, [r7]
- jmpi cc_ULT,[r7]
- jmpi cc_ULE,[r7]
- jmpi cc_UGE,[r7]
- jmpi cc_UGT,[r7]
- jmpi cc_SLE,[r7]
- jmpi cc_SGE,[r7]
- jmpi cc_SGT,[r7]
- jmpi cc_NET,[r7]
+++ /dev/null
- .section .text
- .global _fun
-
-xc16x_jmpr:
-
- jmpr cc_uc, xc16x_jmpr
- jmpr cc_z, xc16x_jmpr
- jmpr cc_nz, xc16x_jmpr
- jmpr cc_v, xc16x_jmpr
- jmpr cc_nv, xc16x_jmpr
- jmpr cc_n, xc16x_jmpr
- jmpr cc_nn, xc16x_jmpr
- jmpr cc_c, xc16x_jmpr
- jmpr cc_nc, xc16x_jmpr
- jmpr cc_eq, xc16x_jmpr
- jmpr cc_ne, xc16x_jmpr
- jmpr cc_ult,xc16x_jmpr
- jmpr cc_ule,xc16x_jmpr
- jmpr cc_uge,xc16x_jmpr
- jmpr cc_ugt,xc16x_jmpr
- jmpr cc_sle,xc16x_jmpr
- jmpr cc_sge,xc16x_jmpr
- jmpr cc_sgt,xc16x_jmpr
- jmpr cc_net,xc16x_jmpr
- jmpr cc_slt,xc16x_jmpr
+++ /dev/null
- .section .text
- .global _fun
-xc16x_mov:
-
- mov r0,r1
- mov r0,#02
- mov r0,#0xfcbe
- mov r0,[r1]
- mov r0,[r1+]
- mov [r0],r1
- mov [-r0],r1
- mov [r0],[r1]
- mov [r0+],[r1]
- mov [r0],[r1+]
- mov r0,[r0+#0xffcb]
- mov [r0+#0xffcb],r0
- mov [r0],0xffcb
- mov 0xffcb,[r0]
- mov r0,0xffcb
- mov 0xffcb,r0
+++ /dev/null
- .xc16x
- mov r0,r1
- mov r0,#02
- mov r0,#0x0001
- mov r0,[r1]
- mov r0,[r1+]
- mov [r0],r1
- mov [-r0],r1
- mov [r0],[r1]
- mov [r0+],[r1]
- mov [r0],[r1+]
- mov r0,[r0+#0x0001]
- mov [r0+#0x0001],r0
- mov [r0],0x0001
- mov 0x0001,[r0]
- mov r0,0x0001
- mov 0x0001,r0
-
- mov r0,r1
- mov r0,#02
- mov r0,#0xffff
- mov r0,[r1]
- mov r0,[r1+]
- mov [r0],r1
- mov [-r0],r1
- mov [r0],[r1]
- mov [r0+],[r1]
- mov [r0],[r1+]
- mov r0,[r0+#0xffff]
- mov [r0+#0xffff],r0
- mov [r0],0xffff
- mov 0xffff,[r0]
- mov r0,0xffff
- mov 0xffff,r0
-
- movb rl0,r2
- movb rl0,#0x12
- movb r3,[r2]
- movb rl0,[r2+]
- movb [-r2],rl0
- movb [r3],[r2+]
- movb [r3],[r2]
- movb [r2+],[r3]
- movb [r2],[r3+]
- movb rl0,[r3+#0x1234]
- movb [r3+#0x1234],rl0
- movb [r3],0x1234
- movb [r3],0x1234
- movb 0x1234,[r3]
- movb rl0,0x12
- movb 0x12,rl0
-
- movb rl0,r2
- movb rl0,#0xff
- movb r3,[r2]
- movb rl0,[r2+]
- movb [-r2],rl0
- movb [r3],[r2+]
- movb [r3],[r2]
- movb [r2+],[r3]
- movb [r2],[r3+]
- movb rl0,[r3+#0xffff]
- movb [r3+#0xffff],rl0
- movb [r3],0xffff
- movb [r3],0xffff
- movb 0xffff,[r3]
- movb rl0,0xff
- movb 0xff,rl0
-
- movbs r0,rl1
- movbs r0,0x12
- movbs 0x1234,rl0
-
- movbs r0,rl1
- movbs r0,0xff
- movbs 0xffff,rl0
-
- movbz r2,rl0
- movbz r0,0x1234
- movbz 0x1234,rl0
-
- movbz r2,rl0
- movbz r0,0xffff
- movbz 0xffff,rl0
-
\ No newline at end of file
+++ /dev/null
- .section .text
- .global _fun
-xc16x_movb:
-
- movb rl0,r2
- movb rl0,#0x12
- movb r3,[r2]
- movb rl0,[r2+]
- movb [-r2],rl0
- movb [r3],[r2+]
- movb [r3],[r2]
- movb [r2+],[r3]
- movb [r2],[r3+]
- movb rl0,[r3+#0x1234]
- movb [r3+#0x1234],rl0
- movb [r3],0x1234
- movb [r3],0xeeff
- movb 0x1234,[r3]
- movb rl0,0x12
- movb 0x12,rl0
-
-
-
-
-
-
\ No newline at end of file
+++ /dev/null
- .section .text
- .global _fun
-
-xc16x_movbs:
-
- movbs r0,rl1
- movbs r0,0xff
- movbs 0xffcb,rl0
+++ /dev/null
- .section .text
- .global _fun
-xc16x_movbz:
-
- movbz r2,rl0
- movbz r0,0x23dd
- movbz 0x23,rl0
-
-
\ No newline at end of file
+++ /dev/null
- .section .text
- .global _fun
-xc16x_mul:
-
- mul r0,r1
- mulu r0,r1
+++ /dev/null
- .section .text
- .global _fun
-xc16x_neg:
-
- neg r0
- negb rl0
+++ /dev/null
- .section .text
- .global _fun
-xc16x_nop:
- nop
- nop
-
+++ /dev/null
- .section .text
- .global _fun
-xc16x_or:
-
- or r0,r1
- or r0,[r1]
- or r0,[r1+]
- or r0,#3
- or r0,#0x0234
- or r0,0x4536
- or 0x4536,r0
+++ /dev/null
- .section .text
- .global _fun
-xc16x_or:
- orb rl0,rl1
- orb rl0,[r1]
- orb rl0,[r1+]
- orb rl0,#3
- orb rl0,#0x23
- orb rl0,0x0234
- orb 0x0234,rl0\v
+++ /dev/null
- .section .text
- .global _fun
-xc16x_prior:
-
- prior r0,r1
+++ /dev/null
- .section .text
- .global _fun
-xc16x_pushpop:
- pop r0
- push r0
+++ /dev/null
- .section .text
- .global _fun
-
-xc16x_ret:
- ret
- reti
- rets
- retp r5
-
+++ /dev/null
- .section .text
- .global _fun
-xc16x_scxt:
- scxt r0,#0xffff
- scxt r0,0xffff
-
+++ /dev/null
- .section .text
- .global _fun
-xc16x_shlrol:
-
- shl r0,r1
- shl r0,#4
- shr r0,r1
- shr r0,#4
- rol r0,r1
- rol r0,#4
- ror r0,r1
- ror r0,#4
- ashr r0,r1
- ashr r0,#4
+++ /dev/null
- .section .text
- .global _fun
-xc16x_sub:
-
- sub r0,r1
- sub r0,[r1]
- sub r0,[r1+]
- sub r0,#0x1
- sub r0,#0x7643
- sub r0,0x7643
- sub 0x7643,r0
-
-
-
-
-
-
-
-
\ No newline at end of file
+++ /dev/null
- .text
-_start:
- sub r0,r1
- sub r0,[r1]
- sub r0,[r1+]
- sub r0,#0x1
- sub r0,#0x7643
- sub r0,0x7643
- sub 0x7643,r0
-
- sub r1,r0
- sub r1,[r0]
- sub r1,[r0+]
- sub r1,#0x1
- sub r1,#0xCDEF
- sub r1,0xCDEF
- sub 0xCDEF,r1
-
-
- subb rl0,rl1
- subb rl0,[r1]
- subb rl0,[r1+]
- subb rl0,#0x1
- subb rl0,#0x43
- subb rl0,0x7643
- subb 0x7643,rl0
-
- subb rl1,rl0
- subb rl1,[r0]
- subb rl1,[r0+]
- subb rl1,#0x1
- subb rl1,#0xCD
- subb rl1,0xCDEF
- subb 0xCDEF,rl1
-
-
-
- subc r0,r1
- subc r0,[r1]
- subc r0,[r1+]
- subc r0,#0x2
- subc r0,#0x43
- subc r0,0x7643
- subc 0x7643,r0
-
- subc r1,r0
- subc r1,[r0]
- subc r1,[r0+]
- subc r1,#0xC
- subc r1,#0xCD
- subc r1,0xCDEF
- subc 0xCDEF,r1
-
- subcb rl0,rl1
- subcb rl0,[r1]
- subcb rl0,[r1+]
- subcb rl0,#0x2
- subcb rl0,#0x43
- subcb rl0,0x7643
- subcb 0x7643,rl0
-
- subcb rl0,rl1
- subcb rl0,[r1]
- subcb rl0,[r1+]
- subcb rl0,#0x2
- subcb rl0,#0x43
- subcb rl0,0x7643
- subcb 0x7643,rl0
-
-
\ No newline at end of file
+++ /dev/null
- .section .text
- .global _fun
-xc16x_subb:
-
- subb rl0,rl1
- subb rl0,[r1]
- subb rl0,[r1+]
- subb rl0,#0x1
- subb rl0,#0x43
- subb rl0,0x7643
- subb 0x7643,rl0
-
-
-
-
-
-
-
-
\ No newline at end of file
+++ /dev/null
- .section .text
- .global _fun
-xc16x_subc:
-
- subc r0,r1
- subc r0,[r1]
- subc r0,[r1+]
- subc r0,#0x2
- subc r0,#0x43
- subc r0,0x7643
- subc 0x7643,r0
-
-
-
-
-
-
-
-
\ No newline at end of file
+++ /dev/null
- .section .text
- .global _fun
-xc16x_subcb:
-
- subcb rl0,rl1
- subcb rl0,[r1]
- subcb rl0,[r1+]
- subcb rl0,#0x2
- subcb rl0,#0x43
- subcb rl0,0x7643
- subcb 0x7643,rl0
-
-
-
-
-
-
-
-
-
\ No newline at end of file
+++ /dev/null
- .section .text
- .global _fun
-xc16x_syscontrol:
- srst
- sbrk
- idle
- pwrdn
- srvwdt
- diswdt
- enwdt
- einit
-
+++ /dev/null
-.text
-xc16x_syscontrol2:
- extr #0x4
- extr #0x3
- extr #0x2
- extr #0x1
-
- atomic #0x4
- atomic #0x3
- atomic #0x2
- atomic #0x1
-
- extp r5,#0x4
- extp #0x3ff,#0x4
- extpr r5,#0x4
- extpr #0x3ff,#0x4
-
- exts r5,#0x4
- exts #0x1,#0x4
-
- extsr r5,#0x4
- extsr #0x1,#0x4
-
-
-
-
+++ /dev/null
- .section .text
- .global _fun
-
-xc16x_trap:
-
- trap #0x02
+++ /dev/null
-# Copyright (C) 2012-2022 Free Software Foundation, Inc.
-
-# This program is free software; you can redistribute it and/or modify
-# it under the terms of the GNU General Public License as published by
-# the Free Software Foundation; either version 3 of the License, or
-# (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.
-
-#
-# Some xc16x tests
-#
-proc do_xc16x_add {} {
- set testname "add.s: xc16x add word tests"
- set x 0
-
- gas_start "add.s" "-al"
-
- # Check each instruction bit pattern to verify it got
- # assembled correctly.
- while 1 {
- expect {
- -re " +\[0-9\]+ 0000 0001\[^\n\]*\n" { set x [expr $x+1] }
- -re " +\[0-9\]+ 0002 0809\[^\n\]*\n" { set x [expr $x+1] }
- -re " +\[0-9\]+ 0004 080D\[^\n\]*\n" { set x [expr $x+1] }
- -re " +\[0-9\]+ 0006 0803\[^\n\]*\n" { set x [expr $x+1] }
- -re " +\[0-9\]+ 0008 06F0D204\[^\n\]*\n" { set x [expr $x+1] }
- -re " +\[0-9\]+ 000c 02F0EDFF\[^\n\]*\n" { set x [expr $x+1] }
- -re " +\[0-9\]+ 0010 04F0EDFF\[^\n\]*\n" { set x [expr $x+1] }
- timeout { perror "timeout\n"; break }
- eof { break }
- }
- }
-
- # This was intended to do any cleanup necessary. It kinda looks like it
- # isn't needed, but just in case, please keep it in for now.
- gas_finish
-
- # Did we find what we were looking for? If not, flunk it.
- if [expr $x == 7] then { pass $testname } else { fail $testname }
-}
-
-proc do_xc16x_addb {} {
- set testname "addb.s: xc16x add byte tests"
- set x 0
-
- gas_start "addb.s" "-al"
-
- # Check each instruction bit pattern to verify it got
- # assembled correctly.
- while 1 {
- expect {
- -re " +\[0-9\]+ 0000 0102\[^\n\]*\n" { set x [expr $x+1] }
- -re " +\[0-9\]+ 0002 0909\[^\n\]*\n" { set x [expr $x+1] }
- -re " +\[0-9\]+ 0004 090D\[^\n\]*\n" { set x [expr $x+1] }
- -re " +\[0-9\]+ 0006 0902\[^\n\]*\n" { set x [expr $x+1] }
- -re " +\[0-9\]+ 0008 07F03300\[^\n\]*\n" { set x [expr $x+1] }
- -re " +\[0-9\]+ 000c 03F08723\[^\n\]*\n" { set x [expr $x+1] }
- -re " +\[0-9\]+ 0010 05F08723\[^\n\]*\n" { set x [expr $x+1] }
- timeout { perror "timeout\n"; break }
- eof { break }
- }
- }
-
- # This was intended to do any cleanup necessary. It kinda looks like it
- # isn't needed, but just in case, please keep it in for now.
- gas_finish
-
- # Did we find what we were looking for? If not, flunk it.
- if [expr $x == 7] then { pass $testname } else { fail $testname }
-}
-
-proc do_xc16x_addc {} {
- set testname "addc.s: xc16x add with carry tests"
- set x 0
-
- gas_start "addc.s" "-al"
-
- # Check each instruction bit pattern to verify it got
- # assembled correctly.
- while 1 {
- expect {
- -re " +\[0-9\]+ 0000 1001\[^\n\]*\n" { set x [expr $x+1] }
- -re " +\[0-9\]+ 0002 1809\[^\n\]*\n" { set x [expr $x+1] }
- -re " +\[0-9\]+ 0004 180D\[^\n\]*\n" { set x [expr $x+1] }
- -re " +\[0-9\]+ 0006 16F03400\[^\n\]*\n" { set x [expr $x+1] }
- -re " +\[0-9\]+ 000a 16F05634\[^\n\]*\n" { set x [expr $x+1] }
- -re " +\[0-9\]+ 000e 12F08723\[^\n\]*\n" { set x [expr $x+1] }
- -re " +\[0-9\]+ 0012 14F08723\[^\n\]*\n" { set x [expr $x+1] }
- timeout { perror "timeout\n"; break }
- eof { break }
- }
- }
-
- # This was intended to do any cleanup necessary. It kinda looks like it
- # isn't needed, but just in case, please keep it in for now.
- gas_finish
-
- # Did we find what we were looking for? If not, flunk it.
- if [expr $x == 7] then { pass $testname } else { fail $testname }
-}
-
-proc do_xc16x_addcb {} {
- set testname "addcb.s: xc16x add byte with carry tests"
- set x 0
-
- gas_start "addcb.s" "-al"
-
- # Check each instruction bit pattern to verify it got
- # assembled correctly.
- while 1 {
- expect {
- -re " +\[0-9\]+ 0000 1102\[^\n\]*\n" { set x [expr $x+1] }
- -re " +\[0-9\]+ 0002 1909\[^\n\]*\n" { set x [expr $x+1] }
- -re " +\[0-9\]+ 0004 190D\[^\n\]*\n" { set x [expr $x+1] }
- -re " +\[0-9\]+ 0006 17F00200\[^\n\]*\n" { set x [expr $x+1] }
- -re " +\[0-9\]+ 000a 17F02300\[^\n\]*\n" { set x [expr $x+1] }
- -re " +\[0-9\]+ 000e 15F08723\[^\n\]*\n" { set x [expr $x+1] }
- timeout { perror "timeout\n"; break }
- eof { break }
- }
- }
-
- # This was intended to do any cleanup necessary. It kinda looks like it
- # isn't needed, but just in case, please keep it in for now.
- gas_finish
-
- # Did we find what we were looking for? If not, flunk it.
- if [expr $x == 6] then { pass $testname } else { fail $testname }
-}
-
-proc do_xc16x_sub {} {
- set testname "sub.s: xc16x sub tests"
- set x 0
-
- gas_start "sub.s" "-al"
-
- # Check each instruction bit pattern to verify it got
- # assembled correctly.
- while 1 {
- expect {
- -re " +\[0-9\]+ 0000 2001\[^\n\]*\n" { set x [expr $x+1] }
- -re " +\[0-9\]+ 0002 2809\[^\n\]*\n" { set x [expr $x+1] }
- -re " +\[0-9\]+ 0004 280D\[^\n\]*\n" { set x [expr $x+1] }
- -re " +\[0-9\]+ 0006 2801\[^\n\]*\n" { set x [expr $x+1] }
- -re " +\[0-9\]+ 0008 26F04376\[^\n\]*\n" { set x [expr $x+1] }
- -re " +\[0-9\]+ 000c 22F04376\[^\n\]*\n" { set x [expr $x+1] }
- -re " +\[0-9\]+ 0010 24F04376\[^\n\]*\n" { set x [expr $x+1] }
- timeout { perror "timeout\n"; break }
- eof { break }
- }
- }
-
- # This was intended to do any cleanup necessary. It kinda looks like it
- # isn't needed, but just in case, please keep it in for now.
- gas_finish
-
- # Did we find what we were looking for? If not, flunk it.
- if [expr $x == 7] then { pass $testname } else { fail $testname }
-}
-
-proc do_xc16x_subb {} {
- set testname "subb.s: xc16x sub byte tests"
- set x 0
-
- gas_start "subb.s" "-al"
-
- # Check each instruction bit pattern to verify it got
- # assembled correctly.
- while 1 {
- expect {
- -re " +\[0-9\]+ 0000 2102\[^\n\]*\n" { set x [expr $x+1] }
- -re " +\[0-9\]+ 0002 2909\[^\n\]*\n" { set x [expr $x+1] }
- -re " +\[0-9\]+ 0004 290D\[^\n\]*\n" { set x [expr $x+1] }
- -re " +\[0-9\]+ 0006 2901\[^\n\]*\n" { set x [expr $x+1] }
- -re " +\[0-9\]+ 0008 27F04300\[^\n\]*\n" { set x [expr $x+1] }
- -re " +\[0-9\]+ 000c 23F04376\[^\n\]*\n" { set x [expr $x+1] }
- -re " +\[0-9\]+ 0010 25F04376\[^\n\]*\n" { set x [expr $x+1] }
- timeout { perror "timeout\n"; break }
- eof { break }
- }
- }
-
- # This was intended to do any cleanup necessary. It kinda looks like it
- # isn't needed, but just in case, please keep it in for now.
- gas_finish
-
- # Did we find what we were looking for? If not, flunk it.
- if [expr $x == 7] then { pass $testname } else { fail $testname }
-}
-
-proc do_xc16x_subc {} {
- set testname "subc.s: xc16x sub with carry tests"
- set x 0
-
- gas_start "subc.s" "-al"
-
- # Check each instruction bit pattern to verify it got
- # assembled correctly.
- while 1 {
- expect {
- -re " +\[0-9\]+ 0000 3001\[^\n\]*\n" { set x [expr $x+1] }
- -re " +\[0-9\]+ 0002 3809\[^\n\]*\n" { set x [expr $x+1] }
- -re " +\[0-9\]+ 0004 380D\[^\n\]*\n" { set x [expr $x+1] }
- -re " +\[0-9\]+ 0006 3802\[^\n\]*\n" { set x [expr $x+1] }
- -re " +\[0-9\]+ 0008 36F04300\[^\n\]*\n" { set x [expr $x+1] }
- -re " +\[0-9\]+ 000c 32F04376\[^\n\]*\n" { set x [expr $x+1] }
- -re " +\[0-9\]+ 0010 34F04376\[^\n\]*\n" { set x [expr $x+1] }
- timeout { perror "timeout\n"; break }
- eof { break }
- }
- }
-
- # This was intended to do any cleanup necessary. It kinda looks like it
- # isn't needed, but just in case, please keep it in for now.
- gas_finish
-
- # Did we find what we were looking for? If not, flunk it.
- if [expr $x == 7] then { pass $testname } else { fail $testname }
-}
-
-proc do_xc16x_subcb {} {
- set testname "subcb.s: xc16x sub byte with carry tests"
- set x 0
-
- gas_start "subcb.s" "-al"
-
- # Check each instruction bit pattern to verify it got
- # assembled correctly.
- while 1 {
- expect {
- -re " +\[0-9\]+ 0000 3102\[^\n\]*\n" { set x [expr $x+1] }
- -re " +\[0-9\]+ 0002 3909\[^\n\]*\n" { set x [expr $x+1] }
- -re " +\[0-9\]+ 0004 390D\[^\n\]*\n" { set x [expr $x+1] }
- -re " +\[0-9\]+ 0006 3902\[^\n\]*\n" { set x [expr $x+1] }
- -re " +\[0-9\]+ 0008 37F04300\[^\n\]*\n" { set x [expr $x+1] }
- -re " +\[0-9\]+ 000c 33F04376\[^\n\]*\n" { set x [expr $x+1] }
- -re " +\[0-9\]+ 0010 35F04376\[^\n\]*\n" { set x [expr $x+1] }
- timeout { perror "timeout\n"; break }
- eof { break }
- }
- }
-
- # This was intended to do any cleanup necessary. It kinda looks like it
- # isn't needed, but just in case, please keep it in for now.
- gas_finish
-
- # Did we find what we were looking for? If not, flunk it.
- if [expr $x == 7] then { pass $testname } else { fail $testname }
-}
-
-proc do_xc16x_and {} {
- set testname "and.s: xc16x and tests"
- set x 0
-
- gas_start "and.s" "-al"
-
- # Check each instruction bit pattern to verify it got
- # assembled correctly.
- while 1 {
- expect {
- -re " +\[0-9\]+ 0000 6001\[^\n\]*\n" { set x [expr $x+1] }
- -re " +\[0-9\]+ 0002 6809\[^\n\]*\n" { set x [expr $x+1] }
- -re " +\[0-9\]+ 0004 680D\[^\n\]*\n" { set x [expr $x+1] }
- -re " +\[0-9\]+ 0006 6803\[^\n\]*\n" { set x [expr $x+1] }
- -re " +\[0-9\]+ 0008 66F0BEFC\[^\n\]*\n" { set x [expr $x+1] }
- -re " +\[0-9\]+ 000c 62F03002\[^\n\]*\n" { set x [expr $x+1] }
- -re " +\[0-9\]+ 0010 64F02003\[^\n\]*\n" { set x [expr $x+1] }
- timeout { perror "timeout\n"; break }
- eof { break }
- }
- }
-
- # This was intended to do any cleanup necessary. It kinda looks like it
- # isn't needed, but just in case, please keep it in for now.
- gas_finish
-
- # Did we find what we were looking for? If not, flunk it.
- if [expr $x == 7] then { pass $testname } else { fail $testname }
-}
-
-proc do_xc16x_andb {} {
- set testname "andb.s: xc16x and byte tests"
- set x 0
-
- gas_start "andb.s" "-al"
-
- # Check each instruction bit pattern to verify it got
- # assembled correctly.
- while 1 {
- expect {
- -re " +\[0-9\]+ 0000 6102\[^\n\]*\n" { set x [expr $x+1] }
- -re " +\[0-9\]+ 0002 6909\[^\n\]*\n" { set x [expr $x+1] }
- -re " +\[0-9\]+ 0004 690D\[^\n\]*\n" { set x [expr $x+1] }
- -re " +\[0-9\]+ 0006 6903\[^\n\]*\n" { set x [expr $x+1] }
- -re " +\[0-9\]+ 0008 67F0BE00\[^\n\]*\n" { set x [expr $x+1] }
- -re " +\[0-9\]+ 000c 63F03002\[^\n\]*\n" { set x [expr $x+1] }
- -re " +\[0-9\]+ 0010 65F02003\[^\n\]*\n" { set x [expr $x+1] }
- timeout { perror "timeout\n"; break }
- eof { break }
- }
- }
-
- # This was intended to do any cleanup necessary. It kinda looks like it
- # isn't needed, but just in case, please keep it in for now.
- gas_finish
-
- # Did we find what we were looking for? If not, flunk it.
- if [expr $x == 7] then { pass $testname } else { fail $testname }
-}
-
-proc do_xc16x_or {} {
- set testname "or.s: xc16x or tests"
- set x 0
-
- gas_start "or.s" "-al"
-
- # Check each instruction bit pattern to verify it got
- # assembled correctly.
- while 1 {
- expect {
- -re " +\[0-9\]+ 0000 7001\[^\n\]*\n" { set x [expr $x+1] }
- -re " +\[0-9\]+ 0002 7809\[^\n\]*\n" { set x [expr $x+1] }
- -re " +\[0-9\]+ 0004 780D\[^\n\]*\n" { set x [expr $x+1] }
- -re " +\[0-9\]+ 0006 7803\[^\n\]*\n" { set x [expr $x+1] }
- -re " +\[0-9\]+ 0008 76F03402\[^\n\]*\n" { set x [expr $x+1] }
- -re " +\[0-9\]+ 000c 72F03645\[^\n\]*\n" { set x [expr $x+1] }
- -re " +\[0-9\]+ 0010 74F03645\[^\n\]*\n" { set x [expr $x+1] }
- timeout { perror "timeout\n"; break }
- eof { break }
- }
- }
-
- # This was intended to do any cleanup necessary. It kinda looks like it
- # isn't needed, but just in case, please keep it in for now.
- gas_finish
-
- # Did we find what we were looking for? If not, flunk it.
- if [expr $x == 7] then { pass $testname } else { fail $testname }
-}
-
-proc do_xc16x_xor {} {
- set testname "xor.s: xc16x xor tests"
- set x 0
-
- gas_start "xor.s" "-al"
-
- # Check each instruction bit pattern to verify it got
- # assembled correctly.
- while 1 {
- expect {
- -re " +\[0-9\]+ 0000 5001\[^\n\]*\n" { set x [expr $x+1] }
- -re " +\[0-9\]+ 0002 5809\[^\n\]*\n" { set x [expr $x+1] }
- -re " +\[0-9\]+ 0004 580D\[^\n\]*\n" { set x [expr $x+1] }
- -re " +\[0-9\]+ 0006 5803\[^\n\]*\n" { set x [expr $x+1] }
- -re " +\[0-9\]+ 0008 56F03402\[^\n\]*\n" { set x [expr $x+1] }
- -re " +\[0-9\]+ 000c 52F03402\[^\n\]*\n" { set x [expr $x+1] }
- -re " +\[0-9\]+ 0010 54F03402\[^\n\]*\n" { set x [expr $x+1] }
- timeout { perror "timeout\n"; break }
- eof { break }
- }
- }
-
- # This was intended to do any cleanup necessary. It kinda looks like it
- # isn't needed, but just in case, please keep it in for now.
- gas_finish
-
- # Did we find what we were looking for? If not, flunk it.
- if [expr $x == 7] then { pass $testname } else { fail $testname }
-}
-
-proc do_xc16x_xorb {} {
- set testname "xorb.s: xc16x xorb tests"
- set x 0
-
- gas_start "xorb.s" "-al"
-
- # Check each instruction bit pattern to verify it got
- # assembled correctly.
- while 1 {
- expect {
- -re " +\[0-9\]+ 0000 5102\[^\n\]*\n" { set x [expr $x+1] }
- -re " +\[0-9\]+ 0002 5909\[^\n\]*\n" { set x [expr $x+1] }
- -re " +\[0-9\]+ 0004 590D\[^\n\]*\n" { set x [expr $x+1] }
- -re " +\[0-9\]+ 0006 5903\[^\n\]*\n" { set x [expr $x+1] }
- -re " +\[0-9\]+ 0008 57F03400\[^\n\]*\n" { set x [expr $x+1] }
- -re " +\[0-9\]+ 000c 53F00324\[^\n\]*\n" { set x [expr $x+1] }
- -re " +\[0-9\]+ 0010 55F00324\[^\n\]*\n" { set x [expr $x+1] }
- timeout { perror "timeout\n"; break }
- eof { break }
- }
- }
-
- # This was intended to do any cleanup necessary. It kinda looks like it
- # isn't needed, but just in case, please keep it in for now.
- gas_finish
-
- # Did we find what we were looking for? If not, flunk it.
- if [expr $x == 7] then { pass $testname } else { fail $testname }
-
-}
-
-proc do_xc16x_mov {} {
- set testname "mov.s: xc16x mov tests"
- set x 0
-
- gas_start "mov.s" "-al"
-
- # Check each instruction bit pattern to verify it got
- # assembled correctly.
- while 1 {
- expect {
- -re " +\[0-9\]+ 0000 F001\[^\n\]*\n" { set x [expr $x+1] }
- -re " +\[0-9\]+ 0002 E6F00200\[^\n\]*\n" { set x [expr $x+1] }
- -re " +\[0-9\]+ 0006 E6F0BEFC\[^\n\]*\n" { set x [expr $x+1] }
- -re " +\[0-9\]+ 000a A801\[^\n\]*\n" { set x [expr $x+1] }
- -re " +\[0-9\]+ 000c 9801\[^\n\]*\n" { set x [expr $x+1] }
- -re " +\[0-9\]+ 000e B810\[^\n\]*\n" { set x [expr $x+1] }
- -re " +\[0-9\]+ 0010 8810\[^\n\]*\n" { set x [expr $x+1] }
- -re " +\[0-9\]+ 0012 C801\[^\n\]*\n" { set x [expr $x+1] }
- -re " +\[0-9\]+ 0014 D801\[^\n\]*\n" { set x [expr $x+1] }
- -re " +\[0-9\]+ 0016 E801\[^\n\]*\n" { set x [expr $x+1] }
- -re " +\[0-9\]+ 0018 D400CBFF\[^\n\]*\n" { set x [expr $x+1] }
- -re " +\[0-9\]+ 001c C400CBFF\[^\n\]*\n" { set x [expr $x+1] }
- -re " +\[0-9\]+ 0020 8400CBFF\[^\n\]*\n" { set x [expr $x+1] }
- -re " +\[0-9\]+ 0024 9400CBFF\[^\n\]*\n" { set x [expr $x+1] }
- -re " +\[0-9\]+ 0028 F2F0CBFF\[^\n\]*\n" { set x [expr $x+1] }
- -re " +\[0-9\]+ 002c F6F0CBFF\[^\n\]*\n" { set x [expr $x+1] }
- timeout { perror "timeout\n"; break }
- eof { break }
- }
- }
-
- # This was intended to do any cleanup necessary. It kinda looks like it
- # isn't needed, but just in case, please keep it in for now.
- gas_finish
-
- # Did we find what we were looking for? If not, flunk it.
- if [expr $x == 16] then { pass $testname } else { fail $testname }
-}
-
-proc do_xc16x_movb {} {
- set testname "movb.s: xc16x movb tests"
- set x 0
-
- gas_start "movb.s" "-al"
-
- # Check each instruction bit pattern to verify it got
- # assembled correctly.
- while 1 {
- expect {
- -re " +\[0-9\]+ 0000 F3F00000\[^\n\]*\n" { set x [expr $x+1] }
- -re " +\[0-9\]+ 0004 E7F01200\[^\n\]*\n" { set x [expr $x+1] }
- -re " +\[0-9\]+ 0008 B4020000\[^\n\]*\n" { set x [expr $x+1] }
- -re " +\[0-9\]+ 000c 9902\[^\n\]*\n" { set x [expr $x+1] }
- -re " +\[0-9\]+ 000e 8902\[^\n\]*\n" { set x [expr $x+1] }
- -re " +\[0-9\]+ 0010 E932\[^\n\]*\n" { set x [expr $x+1] }
- -re " +\[0-9\]+ 0012 C932\[^\n\]*\n" { set x [expr $x+1] }
- -re " +\[0-9\]+ 0014 D923\[^\n\]*\n" { set x [expr $x+1] }
- -re " +\[0-9\]+ 0016 E923\[^\n\]*\n" { set x [expr $x+1] }
- -re " +\[0-9\]+ 0018 F4033412\[^\n\]*\n" { set x [expr $x+1] }
- -re " +\[0-9\]+ 001c E4033412\[^\n\]*\n" { set x [expr $x+1] }
- -re " +\[0-9\]+ 0020 A4033412\[^\n\]*\n" { set x [expr $x+1] }
- -re " +\[0-9\]+ 0024 A403FFEE\[^\n\]*\n" { set x [expr $x+1] }
- -re " +\[0-9\]+ 0028 B4033412\[^\n\]*\n" { set x [expr $x+1] }
- -re " +\[0-9\]+ 002c F3F01200\[^\n\]*\n" { set x [expr $x+1] }
- -re " +\[0-9\]+ 0030 F7F01200\[^\n\]*\n" { set x [expr $x+1] }
- timeout { perror "timeout\n"; break }
- eof { break }
- }
- }
-
- # This was intended to do any cleanup necessary. It kinda looks like it
- # isn't needed, but just in case, please keep it in for now.
- gas_finish
-
- # Did we find what we were looking for? If not, flunk it.
- if [expr $x == 16] then { pass $testname } else { fail $testname }
-}
-
-proc do_xc16x_movbs {} {
- set testname "movbs.s: xc16x mov byte tests"
- set x 0
-
- gas_start "movbs.s" "-al"
-
- # Check each instruction bit pattern to verify it got
- # assembled correctly.
- while 1 {
- expect {
- -re " +\[0-9\]+ 0000 D020\[^\n\]*\n" { set x [expr $x+1] }
- -re " +\[0-9\]+ 0002 D2F0FF00\[^\n\]*\n" { set x [expr $x+1] }
- -re " +\[0-9\]+ 0006 D5F0CBFF\[^\n\]*\n" { set x [expr $x+1] }
- timeout { perror "timeout\n"; break }
- eof { break }
- }
- }
-
- # This was intended to do any cleanup necessary. It kinda looks like it
- # isn't needed, but just in case, please keep it in for now.
- gas_finish
-
- # Did we find what we were looking for? If not, flunk it.
- if [expr $x == 3] then { pass $testname } else { fail $testname }
-}
-
-proc do_xc16x_movbz {} {
- set testname "movbz.s: xc16x movbz tests"
- set x 0
-
- gas_start "movbz.s" "-al"
-
- # Check each instruction bit pattern to verify it got
- # assembled correctly.
- while 1 {
- expect {
- -re " +\[0-9\]+ 0000 C002\[^\n\]*\n" { set x [expr $x+1] }
- -re " +\[0-9\]+ 0002 C2F0DD23\[^\n\]*\n" { set x [expr $x+1] }
- -re " +\[0-9\]+ 0006 C5F02300\[^\n\]*\n" { set x [expr $x+1] }
- timeout { perror "timeout\n"; break }
- eof { break }
- }
- }
-
- # This was intended to do any cleanup necessary. It kinda looks like it
- # isn't needed, but just in case, please keep it in for now.
- gas_finish
-
- # Did we find what we were looking for? If not, flunk it.
- if [expr $x == 3] then { pass $testname } else { fail $testname }
-}
-
-proc do_xc16x_pushpop {} {
- set testname "pushpop.s: xc16x push/pop tests"
- set x 0
-
- gas_start "pushpop.s" "-al"
-
- # Check each instruction bit pattern to verify it got
- # assembled correctly.
- while 1 {
- expect {
- -re " +\[0-9\]+ 0000 FCF0\[^\n\]*\n" { set x [expr $x+1] }
- -re " +\[0-9\]+ 0002 ECF0\[^\n\]*\n" { set x [expr $x+1] }
- timeout { perror "timeout\n"; break }
- eof { break }
- }
- }
-
- # This was intended to do any cleanup necessary. It kinda looks like it
- # isn't needed, but just in case, please keep it in for now.
- gas_finish
-
- # Did we find what we were looking for? If not, flunk it.
- if [expr $x == 2] then { pass $testname } else { fail $testname }
-}
-
-proc do_xc16x_shlrol {} {
- set testname "shlrol.s: xc16x shift and rotate tests"
- set x 0
-
- gas_start "shlrol.s" "-al"
-
- # Check each instruction bit pattern to verify it got
- # assembled correctly.
- while 1 {
- expect {
- -re " +\[0-9\]+ 0000 4C01\[^\n\]*\n" { set x [expr $x+1] }
- -re " +\[0-9\]+ 0002 5C40\[^\n\]*\n" { set x [expr $x+1] }
- -re " +\[0-9\]+ 0004 6C01\[^\n\]*\n" { set x [expr $x+1] }
- -re " +\[0-9\]+ 0006 7C40\[^\n\]*\n" { set x [expr $x+1] }
- -re " +\[0-9\]+ 0008 0C01\[^\n\]*\n" { set x [expr $x+1] }
- -re " +\[0-9\]+ 000a 1C40\[^\n\]*\n" { set x [expr $x+1] }
- -re " +\[0-9\]+ 000c 2C01\[^\n\]*\n" { set x [expr $x+1] }
- -re " +\[0-9\]+ 000e 3C40\[^\n\]*\n" { set x [expr $x+1] }
- -re " +\[0-9\]+ 0010 AC01\[^\n\]*\n" { set x [expr $x+1] }
- -re " +\[0-9\]+ 0012 BC40\[^\n\]*\n" { set x [expr $x+1] }
- timeout { perror "timeout\n"; break }
- eof { break }
- }
- }
-
- # This was intended to do any cleanup necessary. It kinda looks like it
- # isn't needed, but just in case, please keep it in for now.
- gas_finish
-
- # Did we find what we were looking for? If not, flunk it.
- if [expr $x == 10] then { pass $testname } else { fail $testname }
-}
-
-proc do_xc16x_neg {} {
- set testname "neg.s: xc16x neg tests"
- set x 0
-
- gas_start "neg.s" "-al"
-
- # Check each instruction bit pattern to verify it got
- # assembled correctly.
- while 1 {
- expect {
- -re " +\[0-9\]+ 0000 8100\[^\n\]*\n" { set x [expr $x+1] }
- -re " +\[0-9\]+ 0002 A100\[^\n\]*\n" { set x [expr $x+1] }
- timeout { perror "timeout\n"; break }
- eof { break }
- }
- }
-
- # This was intended to do any cleanup necessary. It kinda looks like it
- # isn't needed, but just in case, please keep it in for now.
- gas_finish
-
- # Did we find what we were looking for? If not, flunk it.
- if [expr $x == 2] then { pass $testname } else { fail $testname }
-}
-proc do_xc16x_mul {} {
- set testname "mul.s: xc16x multiply tests"
- set x 0
-
- gas_start "mul.s" "-al"
-
- # Check each instruction bit pattern to verify it got
- # assembled correctly.
- while 1 {
- expect {
- -re " +\[0-9\]+ 0000 0B01\[^\n\]*\n" { set x [expr $x+1] }
- -re " +\[0-9\]+ 0002 1B01\[^\n\]*\n" { set x [expr $x+1] }
- timeout { perror "timeout\n"; break }
- eof { break }
- }
- }
-
- # This was intended to do any cleanup necessary. It kinda looks like it
- # isn't needed, but just in case, please keep it in for now.
- gas_finish
-
- # Did we find what we were looking for? If not, flunk it.
- if [expr $x == 2] then { pass $testname } else { fail $testname }
-}
-
-proc do_xc16x_div {} {
- set testname "div.s: xc16x division tests"
- set x 0
-
- gas_start "div.s" "-al"
-
- # Check each instruction bit pattern to verify it got
- # assembled correctly.
- while 1 {
- expect {
- -re " +\[0-9\]+ 0000 4B00\[^\n\]*\n" { set x [expr $x+1] }
- -re " +\[0-9\]+ 0002 6B00\[^\n\]*\n" { set x [expr $x+1] }
- -re " +\[0-9\]+ 0004 7B00\[^\n\]*\n" { set x [expr $x+1] }
- -re " +\[0-9\]+ 0006 5B00\[^\n\]*\n" { set x [expr $x+1] }
- timeout { perror "timeout\n"; break }
- eof { break }
- }
- }
-
- # This was intended to do any cleanup necessary. It kinda looks like it
- # isn't needed, but just in case, please keep it in for now.
- gas_finish
-
- # Did we find what we were looking for? If not, flunk it.
- if [expr $x == 4] then { pass $testname } else { fail $testname }
-}
-
-proc do_xc16x_jmpa {} {
- set testname "jmpa.s: xc16x jump absolute test"
- set x 0
-
- gas_start "jmpa.s" "-al"
-
- # Check each instruction bit pattern to verify it got
- # assembled correctly.
- while 1 {
- expect {
- -re " +\[0-9\]+ 0000 EA00AAAA\[^\n\]*\n" { set x [expr $x+1] }
- -re " +\[0-9\]+ 0004 EA20AAAA\[^\n\]*\n" { set x [expr $x+1] }
- -re " +\[0-9\]+ 0008 EA30AAAA\[^\n\]*\n" { set x [expr $x+1] }
- -re " +\[0-9\]+ 000c EA40AAAA\[^\n\]*\n" { set x [expr $x+1] }
- -re " +\[0-9\]+ 0010 EA50AAAA\[^\n\]*\n" { set x [expr $x+1] }
- -re " +\[0-9\]+ 0014 EA60AAAA\[^\n\]*\n" { set x [expr $x+1] }
- -re " +\[0-9\]+ 0018 EA70AAAA\[^\n\]*\n" { set x [expr $x+1] }
- -re " +\[0-9\]+ 001c EA80AAAA\[^\n\]*\n" { set x [expr $x+1] }
- -re " +\[0-9\]+ 0020 EA90AAAA\[^\n\]*\n" { set x [expr $x+1] }
- -re " +\[0-9\]+ 0024 EA20AAAA\[^\n\]*\n" { set x [expr $x+1] }
- -re " +\[0-9\]+ 0028 EA30AAAA\[^\n\]*\n" { set x [expr $x+1] }
- -re " +\[0-9\]+ 002c EA80AAAA\[^\n\]*\n" { set x [expr $x+1] }
- -re " +\[0-9\]+ 0030 EAF0AAAA\[^\n\]*\n" { set x [expr $x+1] }
- -re " +\[0-9\]+ 0034 EA90AAAA\[^\n\]*\n" { set x [expr $x+1] }
- -re " +\[0-9\]+ 0038 EAE0AAAA\[^\n\]*\n" { set x [expr $x+1] }
- -re " +\[0-9\]+ 003c EAB0AAAA\[^\n\]*\n" { set x [expr $x+1] }
- -re " +\[0-9\]+ 0040 EAD0AAAA\[^\n\]*\n" { set x [expr $x+1] }
- -re " +\[0-9\]+ 0044 EAA0AAAA\[^\n\]*\n" { set x [expr $x+1] }
- -re " +\[0-9\]+ 0048 EA10AAAA\[^\n\]*\n" { set x [expr $x+1] }
- timeout { perror "timeout\n"; break }
- eof { break }
- }
- }
-
- # This was intended to do any cleanup necessary. It kinda looks like it
- # isn't needed, but just in case, please keep it in for now.
- gas_finish
-
- # Did we find what we were looking for? If not, flunk it.
- if [expr $x == 19] then { pass $testname } else { fail $testname }
-}
-
-proc do_xc16x_jmpi {} {
- set testname "jmpi.s: xc16x jmp immidiate tests "
- set x 0
-
- gas_start "jmpi.s" "-al"
-
- # Check each instruction bit pattern to verify it got
- # assembled correctly.
- while 1 {
- expect {
- -re " +\[0-9\]+ 0000 9C07\[^\n\]*\n" { set x [expr $x+1] }
- -re " +\[0-9\]+ 0002 9C27\[^\n\]*\n" { set x [expr $x+1] }
- -re " +\[0-9\]+ 0004 9C37\[^\n\]*\n" { set x [expr $x+1] }
- -re " +\[0-9\]+ 0006 9C47\[^\n\]*\n" { set x [expr $x+1] }
- -re " +\[0-9\]+ 0008 9C57\[^\n\]*\n" { set x [expr $x+1] }
- -re " +\[0-9\]+ 000a 9C67\[^\n\]*\n" { set x [expr $x+1] }
- -re " +\[0-9\]+ 000c 9C77\[^\n\]*\n" { set x [expr $x+1] }
- -re " +\[0-9\]+ 000e 9C87\[^\n\]*\n" { set x [expr $x+1] }
- -re " +\[0-9\]+ 0010 9C97\[^\n\]*\n" { set x [expr $x+1] }
- -re " +\[0-9\]+ 0012 9C27\[^\n\]*\n" { set x [expr $x+1] }
- -re " +\[0-9\]+ 0014 9C37\[^\n\]*\n" { set x [expr $x+1] }
- -re " +\[0-9\]+ 0016 9C87\[^\n\]*\n" { set x [expr $x+1] }
- -re " +\[0-9\]+ 0018 9CF7\[^\n\]*\n" { set x [expr $x+1] }
- -re " +\[0-9\]+ 001a 9C97\[^\n\]*\n" { set x [expr $x+1] }
- -re " +\[0-9\]+ 001c 9CE7\[^\n\]*\n" { set x [expr $x+1] }
- -re " +\[0-9\]+ 001e 9CB7\[^\n\]*\n" { set x [expr $x+1] }
- -re " +\[0-9\]+ 0020 9CD7\[^\n\]*\n" { set x [expr $x+1] }
- -re " +\[0-9\]+ 0022 9CA7\[^\n\]*\n" { set x [expr $x+1] }
- -re " +\[0-9\]+ 0024 9C17\[^\n\]*\n" { set x [expr $x+1] }
- timeout { perror "timeout\n"; break }
- eof { break }
- }
- }
-
- # This was intended to do any cleanup necessary. It kinda looks like it
- # isn't needed, but just in case, please keep it in for now.
- gas_finish
-
- # Did we find what we were looking for? If not, flunk it.
- if [expr $x == 19] then { pass $testname } else { fail $testname }
-}
-
-
-proc do_xc16x_jmpr {} {
- set testname "jmpr.s: xc16x jump relative tests"
- set x 0
-
- gas_start "jmpr.s" "-al"
-
- # Check each instruction bit pattern to verify it got
- # assembled correctly.
- while 1 {
- expect {
- -re " +\[0-9\]+ 0000 0DFF\[^\n\]*\n" { set x [expr $x+1] }
- -re " +\[0-9\]+ 0002 2DFE\[^\n\]*\n" { set x [expr $x+1] }
- -re " +\[0-9\]+ 0004 3DFD\[^\n\]*\n" { set x [expr $x+1] }
- -re " +\[0-9\]+ 0006 4DFC\[^\n\]*\n" { set x [expr $x+1] }
- -re " +\[0-9\]+ 0008 5DFB\[^\n\]*\n" { set x [expr $x+1] }
- -re " +\[0-9\]+ 000a 6DFA\[^\n\]*\n" { set x [expr $x+1] }
- -re " +\[0-9\]+ 000c 7DF9\[^\n\]*\n" { set x [expr $x+1] }
- -re " +\[0-9\]+ 000e 8DF8\[^\n\]*\n" { set x [expr $x+1] }
- -re " +\[0-9\]+ 0010 9DF7\[^\n\]*\n" { set x [expr $x+1] }
- -re " +\[0-9\]+ 0012 2DF6\[^\n\]*\n" { set x [expr $x+1] }
- -re " +\[0-9\]+ 0014 3DF5\[^\n\]*\n" { set x [expr $x+1] }
- -re " +\[0-9\]+ 0016 8DF4\[^\n\]*\n" { set x [expr $x+1] }
- -re " +\[0-9\]+ 0018 FDF3\[^\n\]*\n" { set x [expr $x+1] }
- -re " +\[0-9\]+ 001a 9DF2\[^\n\]*\n" { set x [expr $x+1] }
- -re " +\[0-9\]+ 001c EDF1\[^\n\]*\n" { set x [expr $x+1] }
- -re " +\[0-9\]+ 001e BDF0\[^\n\]*\n" { set x [expr $x+1] }
- -re " +\[0-9\]+ 0020 DDEF\[^\n\]*\n" { set x [expr $x+1] }
- -re " +\[0-9\]+ 0022 ADEE\[^\n\]*\n" { set x [expr $x+1] }
- -re " +\[0-9\]+ 0024 1DED\[^\n\]*\n" { set x [expr $x+1] }
- -re " +\[0-9\]+ 0026 CDEC\[^\n\]*\n" { set x [expr $x+1] }
- timeout { perror "timeout\n"; break }
- eof { break }
- }
- }
-
- # This was intended to do any cleanup necessary. It kinda looks like it
- # isn't needed, but just in case, please keep it in for now.
- gas_finish
-
- # Did we find what we were looking for? If not, flunk it.
- if [expr $x == 20] then { pass $testname } else { fail $testname }
-}
-
-proc do_xc16x_syscontrol1 {} {
- set testname "syscontrol1.s: xc16x system control insrutions tests"
- set x 0
-
- gas_start "syscontrol1.s" "-al"
-
- # Check each instruction bit pattern to verify it got
- # assembled correctly.
- while 1 {
- expect {
- -re " +\[0-9\]+ 0000 B748B7B7\[^\n\]*\n" { set x [expr $x+1] }
- -re " +\[0-9\]+ 0004 8C00\[^\n\]*\n" { set x [expr $x+1] }
- -re " +\[0-9\]+ 0006 87788787\[^\n\]*\n" { set x [expr $x+1] }
- -re " +\[0-9\]+ 000a 97689797\[^\n\]*\n" { set x [expr $x+1] }
- -re " +\[0-9\]+ 000e A758A7A7\[^\n\]*\n" { set x [expr $x+1] }
- -re " +\[0-9\]+ 0012 A55AA5A5\[^\n\]*\n" { set x [expr $x+1] }
- -re " +\[0-9\]+ 0016 857A8585\[^\n\]*\n" { set x [expr $x+1] }
- -re " +\[0-9\]+ 001a B54AB5B5\[^\n\]*\n" { set x [expr $x+1] }
- timeout { perror "timeout\n"; break }
- eof { break }
- }
- }
-
- # This was intended to do any cleanup necessary. It kinda looks like it
- # isn't needed, but just in case, please keep it in for now.
- gas_finish
-
- # Did we find what we were looking for? If not, flunk it.
- if [expr $x == 8] then { pass $testname } else { fail $testname }
-}
-
-proc do_xc16x_syscontrol2 {} {
- set testname "syscontrol2.s: xc16x syscontrol2 tests"
- set x 0
-
- gas_start "syscontrol2.s" "-al"
-
- # Check each instruction bit pattern to verify it got
- # assembled correctly.
- while 1 {
- expect {
- -re " +\[0-9\]+ 0000 D1B0\[^\n\]*\n" { set x [expr $x+1] }
- -re " +\[0-9\]+ 0002 D1A0\[^\n\]*\n" { set x [expr $x+1] }
- -re " +\[0-9\]+ 0004 D190\[^\n\]*\n" { set x [expr $x+1] }
- -re " +\[0-9\]+ 0006 D180\[^\n\]*\n" { set x [expr $x+1] }
- -re " +\[0-9\]+ 0008 D130\[^\n\]*\n" { set x [expr $x+1] }
- -re " +\[0-9\]+ 000a D120\[^\n\]*\n" { set x [expr $x+1] }
- -re " +\[0-9\]+ 000c D110\[^\n\]*\n" { set x [expr $x+1] }
- -re " +\[0-9\]+ 000e D100\[^\n\]*\n" { set x [expr $x+1] }
- -re " +\[0-9\]+ 0010 DC75\[^\n\]*\n" { set x [expr $x+1] }
- -re " +\[0-9\]+ 0012 D770FF03\[^\n\]*\n" { set x [expr $x+1] }
- -re " +\[0-9\]+ 0016 DCF5\[^\n\]*\n" { set x [expr $x+1] }
- -re " +\[0-9\]+ 0018 D7F0FF03\[^\n\]*\n" { set x [expr $x+1] }
- -re " +\[0-9\]+ 001c DC35\[^\n\]*\n" { set x [expr $x+1] }
- -re " +\[0-9\]+ 001e D7300100\[^\n\]*\n" { set x [expr $x+1] }
- -re " +\[0-9\]+ 0022 DCB5\[^\n\]*\n" { set x [expr $x+1] }
- -re " +\[0-9\]+ 0024 D7B00100\[^\n\]*\n" { set x [expr $x+1] }
- timeout { perror "timeout\n"; break }
- eof { break }
- }
- }
-
- # This was intended to do any cleanup necessary. It kinda looks like it
- # isn't needed, but just in case, please keep it in for now.
- gas_finish
-
- # Did we find what we were looking for? If not, flunk it.
- if [expr $x == 16] then { pass $testname } else { fail $testname }
-}
-
-proc do_xc16x_cpl {} {
- set testname "cpl.s: xc16x compliment tests"
- set x 0
-
- gas_start "cpl.s" "-al"
-
- # Check each instruction bit pattern to verify it got
- # assembled correctly.
- while 1 {
- expect {
- -re " +\[0-9\]+ 0000 9100\[^\n\]*\n" { set x [expr $x+1] }
- -re " +\[0-9\]+ 0002 B100\[^\n\]*\n" { set x [expr $x+1] }
- timeout { perror "timeout\n"; break }
- eof { break }
- }
- }
-
- # This was intended to do any cleanup necessary. It kinda looks like it
- # isn't needed, but just in case, please keep it in for now.
- gas_finish
-
- # Did we find what we were looking for? If not, flunk it.
- if [expr $x == 2] then { pass $testname } else { fail $testname }
-}
-
-proc do_xc16x_cmp {} {
- set testname "cmp.s: xc16x misc tests"
- set x 0
-
- gas_start "cmp.s" "-al"
-
- # Check each instruction bit pattern to verify it got
- # assembled correctly.
- while 1 {
- expect {
- -re " +\[0-9\]+ 0000 4001\[^\n\]*\n" { set x [expr $x+1] }
- -re " +\[0-9\]+ 0002 4809\[^\n\]*\n" { set x [expr $x+1] }
- -re " +\[0-9\]+ 0004 480D\[^\n\]*\n" { set x [expr $x+1] }
- -re " +\[0-9\]+ 0006 4803\[^\n\]*\n" { set x [expr $x+1] }
- -re " +\[0-9\]+ 0008 46F03402\[^\n\]*\n" { set x [expr $x+1] }
- -re " +\[0-9\]+ 000c 42F05234\[^\n\]*\n" { set x [expr $x+1] }
- timeout { perror "timeout\n"; break }
- eof { break }
- }
- }
-
- # This was intended to do any cleanup necessary. It kinda looks like it
- # isn't needed, but just in case, please keep it in for now.
- gas_finish
-
- # Did we find what we were looking for? If not, flunk it.
- if [expr $x == 6] then { pass $testname } else { fail $testname }
-}
-
-proc do_xc16x_cmpb {} {
- set testname "cmpb.s: xc16x cmp byte tests"
- set x 0
-
- gas_start "cmpb.s" "-al"
-
- # Check each instruction bit pattern to verify it got
- # assembled correctly.
- while 1 {
- expect {
- -re " +\[0-9\]+ 0000 4102\[^\n\]*\n" { set x [expr $x+1] }
- -re " +\[0-9\]+ 0002 4909\[^\n\]*\n" { set x [expr $x+1] }
- -re " +\[0-9\]+ 0004 490D\[^\n\]*\n" { set x [expr $x+1] }
- -re " +\[0-9\]+ 0006 4903\[^\n\]*\n" { set x [expr $x+1] }
- -re " +\[0-9\]+ 0008 47F02200\[^\n\]*\n" { set x [expr $x+1] }
- -re " +\[0-9\]+ 000c 43F03402\[^\n\]*\n" { set x [expr $x+1] }
- timeout { perror "timeout\n"; break }
- eof { break }
- }
- }
-
- # This was intended to do any cleanup necessary. It kinda looks like it
- # isn't needed, but just in case, please keep it in for now.
- gas_finish
-
- # Did we find what we were looking for? If not, flunk it.
- if [expr $x == 6] then { pass $testname } else { fail $testname }
-}
-
-proc do_xc16x_cmpi {} {
- set testname "cmpi.s: xc16x cmpi tests"
- set x 0
-
- gas_start "cmpi.s" "-al"
-
- # Check each instruction bit pattern to verify it got
- # assembled correctly.
- while 1 {
- expect {
- -re " +\[0-9\]+ 0000 A0F0\[^\n\]*\n" { set x [expr $x+1] }
- -re " +\[0-9\]+ 0002 A6F0CBFC\[^\n\]*\n" { set x [expr $x+1] }
- -re " +\[0-9\]+ 0006 A2F0CBFF\[^\n\]*\n" { set x [expr $x+1] }
- -re " +\[0-9\]+ 000a B0F0\[^\n\]*\n" { set x [expr $x+1] }
- -re " +\[0-9\]+ 000c B6F0CBFC\[^\n\]*\n" { set x [expr $x+1] }
- -re " +\[0-9\]+ 0010 B2F0CBFF\[^\n\]*\n" { set x [expr $x+1] }
- -re " +\[0-9\]+ 0014 80F0\[^\n\]*\n" { set x [expr $x+1] }
- -re " +\[0-9\]+ 0016 86F0CBFC\[^\n\]*\n" { set x [expr $x+1] }
- -re " +\[0-9\]+ 001a 82F0CBFF\[^\n\]*\n" { set x [expr $x+1] }
- -re " +\[0-9\]+ 001e 90F0\[^\n\]*\n" { set x [expr $x+1] }
- -re " +\[0-9\]+ 0020 96F0CBFC\[^\n\]*\n" { set x [expr $x+1] }
- -re " +\[0-9\]+ 0024 92F0CBFF\[^\n\]*\n" { set x [expr $x+1] }
- timeout { perror "timeout\n"; break }
- eof { break }
- }
- }
-
- # This was intended to do any cleanup necessary. It kinda looks like it
- # isn't needed, but just in case, please keep it in for now.
- gas_finish
-
- # Did we find what we were looking for? If not, flunk it.
- if [expr $x == 12] then { pass $testname } else { fail $testname }
-}
-
-proc do_xc16x_calli {} {
- set testname "calli.s: xc16x call tests"
- set x 0
-
- gas_start "calli.s" "-al"
-
- # Check each instruction bit pattern to verify it got
- # assembled correctly.
- while 1 {
- expect {
- -re " +\[0-9\]+ 0000 AB01\[^\n\]*\n" { set x [expr $x+1] }
- -re " +\[0-9\]+ 0002 AB21\[^\n\]*\n" { set x [expr $x+1] }
- -re " +\[0-9\]+ 0004 AB31\[^\n\]*\n" { set x [expr $x+1] }
- -re " +\[0-9\]+ 0006 AB41\[^\n\]*\n" { set x [expr $x+1] }
- -re " +\[0-9\]+ 0008 AB51\[^\n\]*\n" { set x [expr $x+1] }
- -re " +\[0-9\]+ 000a AB61\[^\n\]*\n" { set x [expr $x+1] }
- -re " +\[0-9\]+ 000c AB71\[^\n\]*\n" { set x [expr $x+1] }
- -re " +\[0-9\]+ 000e AB81\[^\n\]*\n" { set x [expr $x+1] }
- -re " +\[0-9\]+ 0010 AB91\[^\n\]*\n" { set x [expr $x+1] }
- -re " +\[0-9\]+ 0012 AB21\[^\n\]*\n" { set x [expr $x+1] }
- -re " +\[0-9\]+ 0014 AB31\[^\n\]*\n" { set x [expr $x+1] }
- -re " +\[0-9\]+ 0016 AB81\[^\n\]*\n" { set x [expr $x+1] }
- -re " +\[0-9\]+ 0018 ABF1\[^\n\]*\n" { set x [expr $x+1] }
- -re " +\[0-9\]+ 001a AB91\[^\n\]*\n" { set x [expr $x+1] }
- -re " +\[0-9\]+ 001c ABE1\[^\n\]*\n" { set x [expr $x+1] }
- -re " +\[0-9\]+ 001e ABB1\[^\n\]*\n" { set x [expr $x+1] }
- -re " +\[0-9\]+ 0020 ABD1\[^\n\]*\n" { set x [expr $x+1] }
- -re " +\[0-9\]+ 0022 AB11\[^\n\]*\n" { set x [expr $x+1] }
- -re " +\[0-9\]+ 0024 ABC1\[^\n\]*\n" { set x [expr $x+1] }
- timeout { perror "timeout\n"; break }
- eof { break }
- }
- }
-
- # This was intended to do any cleanup necessary. It kinda looks like it
- # isn't needed, but just in case, please keep it in for now.
- gas_finish
-
- # Did we find what we were looking for? If not, flunk it.
- if [expr $x == 19] then { pass $testname } else { fail $testname }
-}
-
-proc do_xc16x_calla {} {
- set testname "calla.s: xc16x call tests"
- set x 0
-
- gas_start "calla.s" "-al"
-
- # Check each instruction bit pattern to verify it got
- # assembled correctly.
- while 1 {
- expect {
- -re " +\[0-9\]+ 0000 CA00AAAA\[^\n\]*\n" { set x [expr $x+1] }
- -re " +\[0-9\]+ 0004 CA20AAAA\[^\n\]*\n" { set x [expr $x+1] }
- -re " +\[0-9\]+ 0008 CA30AAAA\[^\n\]*\n" { set x [expr $x+1] }
- -re " +\[0-9\]+ 000c CA40AAAA\[^\n\]*\n" { set x [expr $x+1] }
- -re " +\[0-9\]+ 0010 CA50AAAA\[^\n\]*\n" { set x [expr $x+1] }
- -re " +\[0-9\]+ 0014 CA60AAAA\[^\n\]*\n" { set x [expr $x+1] }
- -re " +\[0-9\]+ 0018 CA70AAAA\[^\n\]*\n" { set x [expr $x+1] }
- -re " +\[0-9\]+ 001c CA80AAAA\[^\n\]*\n" { set x [expr $x+1] }
- -re " +\[0-9\]+ 0020 CA90AAAA\[^\n\]*\n" { set x [expr $x+1] }
- -re " +\[0-9\]+ 0024 CA20AAAA\[^\n\]*\n" { set x [expr $x+1] }
- -re " +\[0-9\]+ 0028 CA30AAAA\[^\n\]*\n" { set x [expr $x+1] }
- -re " +\[0-9\]+ 002c CA80AAAA\[^\n\]*\n" { set x [expr $x+1] }
- -re " +\[0-9\]+ 0030 CAF0AAAA\[^\n\]*\n" { set x [expr $x+1] }
- -re " +\[0-9\]+ 0034 CA90AAAA\[^\n\]*\n" { set x [expr $x+1] }
- -re " +\[0-9\]+ 0038 CAE0AAAA\[^\n\]*\n" { set x [expr $x+1] }
- -re " +\[0-9\]+ 003c CAB0AAAA\[^\n\]*\n" { set x [expr $x+1] }
- -re " +\[0-9\]+ 0040 CAD0AAAA\[^\n\]*\n" { set x [expr $x+1] }
- -re " +\[0-9\]+ 0044 CAA0AAAA\[^\n\]*\n" { set x [expr $x+1] }
- -re " +\[0-9\]+ 0048 CA10AAAA\[^\n\]*\n" { set x [expr $x+1] }
- -re " +\[0-9\]+ 004c CAC0AAAA\[^\n\]*\n" { set x [expr $x+1] }
- timeout { perror "timeout\n"; break }
- eof { break }
- }
- }
-
- # This was intended to do any cleanup necessary. It kinda looks like it
- # isn't needed, but just in case, please keep it in for now.
- gas_finish
-
- # Did we find what we were looking for? If not, flunk it.
- if [expr $x == 20] then { pass $testname } else { fail $testname }
-}
-
-
-proc do_xc16x_bit {} {
- set testname "bit.s: xc16x bit manipulation tests"
- set x 0
-
- gas_start "bit.s" "-al"
-
- # Check each instruction bit pattern to verify it got
- # assembled correctly.
- while 1 {
- expect {
- -re " +\[0-9\]+ 0000 1EF0\[^\n\]*\n" { set x [expr $x+1] }
- -re " +\[0-9\]+ 0002 1FF0\[^\n\]*\n" { set x [expr $x+1] }
- -re " +\[0-9\]+ 0004 4AF0F012\[^\n\]*\n" { set x [expr $x+1] }
- -re " +\[0-9\]+ 0008 3AF0F023\[^\n\]*\n" { set x [expr $x+1] }
- -re " +\[0-9\]+ 000c 6AF0F041\[^\n\]*\n" { set x [expr $x+1] }
- -re " +\[0-9\]+ 0010 5AF0F021\[^\n\]*\n" { set x [expr $x+1] }
- -re " +\[0-9\]+ 0014 7AF0F021\[^\n\]*\n" { set x [expr $x+1] }
- -re " +\[0-9\]+ 0018 2AF0F021\[^\n\]*\n" { set x [expr $x+1] }
- timeout { perror "timeout\n"; break }
- eof { break }
- }
- }
-
- # This was intended to do any cleanup necessary. It kinda looks like it
- # isn't needed, but just in case, please keep it in for now.
- gas_finish
-
- # Did we find what we were looking for? If not, flunk it.
- if [expr $x == 8] then { pass $testname } else { fail $testname }
-}
-
-proc do_xc16x_bfldl {} {
- set testname "bfldl.s: xc16x bitwise modify masked data tests"
- set x 0
-
- gas_start "bfldl.s" "-al"
-
- # Check each instruction bit pattern to verify it got
- # assembled correctly.
- while 1 {
- expect {
- -re " +\[0-9\]+ 0000 0AF0870E\[^\n\]*\n" { set x [expr $x+1] }
- -re " +\[0-9\]+ 0004 1AF00EFF\[^\n\]*\n" { set x [expr $x+1] }
- timeout { perror "timeout\n"; break }
- eof { break }
- }
- }
-
- # This was intended to do any cleanup necessary. It kinda looks like it
- # isn't needed, but just in case, please keep it in for now.
- gas_finish
-
- # Did we find what we were looking for? If not, flunk it.
- if [expr $x == 2] then { pass $testname } else { fail $testname }
-}
-
-proc do_xc16x_ret {} {
- set testname "ret.s: xc16x ret tests"
- set x 0
-
- gas_start "ret.s" "-al"
-
- # Check each instruction bit pattern to verify it got
- # assembled correctly.
- while 1 {
- expect {
- -re " +\[0-9\]+ 0000 CB00\[^\n\]*\n" { set x [expr $x+1] }
- -re " +\[0-9\]+ 0002 FB88\[^\n\]*\n" { set x [expr $x+1] }
- -re " +\[0-9\]+ 0004 DB00\[^\n\]*\n" { set x [expr $x+1] }
- -re " +\[0-9\]+ 0006 EBF5\[^\n\]*\n" { set x [expr $x+1] }
- timeout { perror "timeout\n"; break }
- eof { break }
- }
- }
-
- # This was intended to do any cleanup necessary. It kinda looks like it
- # isn't needed, but just in case, please keep it in for now.
- gas_finish
-
- # Did we find what we were looking for? If not, flunk it.
- if [expr $x == 4] then { pass $testname } else { fail $testname }
-}
-
-proc do_xc16x_trap {} {
- set testname "trap.s: xc16x add/sub tests"
- set x 0
-
- gas_start "trap.s" "-al"
-
- # Check each instruction bit pattern to verify it got
- # assembled correctly.
- while 1 {
- expect {
- -re " +\[0-9\]+ 0000 9B04\[^\n\]*\n" { set x [expr $x+1] }
- timeout { perror "timeout\n"; break }
- eof { break }
- }
- }
-
- # This was intended to do any cleanup necessary. It kinda looks like it
- # isn't needed, but just in case, please keep it in for now.
- gas_finish
-
- # Did we find what we were looking for? If not, flunk it.
- if [expr $x == 1] then { pass $testname } else { fail $testname }
-}
-
-proc do_xc16x_orb {} {
- set testname "orb.s: xc16x or byte instructions tests"
- set x 0
-
- gas_start "orb.s" "-al"
-
- # Check each instruction bit pattern to verify it got
- # assembled correctly.
- while 1 {
- expect {
- -re " +\[0-9\]+ 0000 7102\[^\n\]*\n" { set x [expr $x+1] }
- -re " +\[0-9\]+ 0002 7909\[^\n\]*\n" { set x [expr $x+1] }
- -re " +\[0-9\]+ 0004 790D\[^\n\]*\n" { set x [expr $x+1] }
- -re " +\[0-9\]+ 0006 7903\[^\n\]*\n" { set x [expr $x+1] }
- -re " +\[0-9\]+ 0008 77F02300\[^\n\]*\n" { set x [expr $x+1] }
- -re " +\[0-9\]+ 000c 73F03402\[^\n\]*\n" { set x [expr $x+1] }
- -re " +\[0-9\]+ 0010 75F03402\[^\n\]*\n" { set x [expr $x+1] }
- timeout { perror "timeout\n"; break }
- eof { break }
- }
- }
-
- # This was intended to do any cleanup necessary. It kinda looks like it
- # isn't needed, but just in case, please keep it in for now.
- gas_finish
-
- # Did we find what we were looking for? If not, flunk it.
- if [expr $x == 7] then { pass $testname } else { fail $testname }
-}
-
-
-proc do_xc16x_prior {} {
- set testname "prior.s: Determine no shift cycles tests"
- set x 0
-
- gas_start "prior.s" "-al"
-
- # Check each instruction bit pattern to verify it got
- # assembled correctly.
- while 1 {
- expect {
- -re " +\[0-9\]+ 0000 2B01\[^\n\]*\n" { set x [expr $x+1] }
- timeout { perror "timeout\n"; break }
- eof { break }
- }
- }
-
- # This was intended to do any cleanup necessary. It kinda looks like it
- # isn't needed, but just in case, please keep it in for now.
- gas_finish
-
- # Did we find what we were looking for? If not, flunk it.
- if [expr $x == 1] then { pass $testname } else { fail $testname }
-}
-
-proc do_xc16x_nop {} {
- set testname "nop.s: no operation nop tests"
- set x 0
-
- gas_start "nop.s" "-al"
-
- # Check each instruction bit pattern to verify it got
- # assembled correctly.
- while 1 {
- expect {
- -re " +\[0-9\]+ 0000 CC00\[^\n\]*\n" { set x [expr $x+1] }
- -re " +\[0-9\]+ 0002 CC00\[^\n\]*\n" { set x [expr $x+1] }
- timeout { perror "timeout\n"; break }
- eof { break }
- }
- }
-
- # This was intended to do any cleanup necessary. It kinda looks like it
- # isn't needed, but just in case, please keep it in for now.
- gas_finish
-
- # Did we find what we were looking for? If not, flunk it.
- if [expr $x == 2] then { pass $testname } else { fail $testname }
-}
-
-
-proc do_xc16x_scxt {} {
- set testname "scxt.s: push direct word to system stack tests"
- set x 0
-
- gas_start "scxt.s" "-al"
-
- # Check each instruction bit pattern to verify it got
- # assembled correctly.
- while 1 {
- expect {
- -re " +\[0-9\]+ 0000 C6F0FFFF\[^\n\]*\n" { set x [expr $x+1] }
- -re " +\[0-9\]+ 0004 D6F0FFFF\[^\n\]*\n" { set x [expr $x+1] }
- timeout { perror "timeout\n"; break }
- eof { break }
- }
- }
-
- # This was intended to do any cleanup necessary. It kinda looks like it
- # isn't needed, but just in case, please keep it in for now.
- gas_finish
-
- # Did we find what we were looking for? If not, flunk it.
- if [expr $x == 2] then { pass $testname } else { fail $testname }
-}
-
-
-if [istarget xc16x*-*-*] then {
- # Test the basic xc16x instruction parser
- do_xc16x_add
- do_xc16x_addb
- do_xc16x_addc
- do_xc16x_addcb
- do_xc16x_sub
- do_xc16x_subb
- do_xc16x_subc
- do_xc16x_subcb
- do_xc16x_and
- do_xc16x_andb
- do_xc16x_or
- do_xc16x_xor
- do_xc16x_xorb
- do_xc16x_mov
- do_xc16x_movb
- do_xc16x_movbs
- do_xc16x_movbz
- do_xc16x_shlrol
- do_xc16x_neg
- do_xc16x_mul
- do_xc16x_div
- do_xc16x_jmpa
- do_xc16x_jmpi
- do_xc16x_jmpr
- do_xc16x_syscontrol1
- do_xc16x_syscontrol2
- do_xc16x_cpl
- do_xc16x_cmp
- do_xc16x_cmpb
- do_xc16x_cmpi
- do_xc16x_calla
- do_xc16x_calli
- do_xc16x_bit
- do_xc16x_bfldl
- do_xc16x_ret
- do_xc16x_trap
- do_xc16x_orb
- do_xc16x_prior
- do_xc16x_nop
- do_xc16x_scxt
-
-}
+++ /dev/null
- .section .text
- .global _fun
-xc16x_or:
- xor r0,r1
- xor r0,[r1]
- xor r0,[r1+]
- xor r0,#3
- xor r0,#0x0234
- xor r0,0x0234
- xor 0x0234,r0
+++ /dev/null
- .section .text
- .global _fun
-xc16x_xorb:
- xorb rl0,rl1
- xorb rl0,[r1]
- xorb rl0,[r1+]
- xorb rl0,#3
- xorb rl0,#0x34
- xorb rl0,0x2403
- xorb 0x2403,rl0
+++ /dev/null
-/* Infineon XC16X ELF support for BFD.
- Copyright (C) 2006-2022 Free Software Foundation, Inc.
- Contributed by KPIT Cummins Infosystems
-
- This file is part of BFD, the Binary File Descriptor library.
-
- This program is free software; you can redistribute it and/or modify
- it under the terms of the GNU General Public License as published by
- the Free Software Foundation; either version 3 of the License, or
- (at your option) any later version.
-
- This program is distributed in the hope that it will be useful,
- but WITHOUT ANY WARRANTY; without even the implied warranty of
- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- GNU General Public License for more details.
-
- You should have received a copy of the GNU General Public License
- along with this program; if not, write to the Free Software Foundation,
- Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */
-
-#ifndef _ELF_XC16X_H
-#define _ELF_XC16X_H
-
-#include "elf/reloc-macros.h"
-
-/* Relocations. */
-START_RELOC_NUMBERS (elf_xc16x_reloc_type)
- RELOC_NUMBER (R_XC16X_NONE, 0)
- RELOC_NUMBER (R_XC16X_ABS_8, 1)
- RELOC_NUMBER (R_XC16X_ABS_16, 2)
- RELOC_NUMBER (R_XC16X_ABS_32, 3)
- RELOC_NUMBER (R_XC16X_8_PCREL, 4)
- RELOC_NUMBER (R_XC16X_PAG, 5)
- RELOC_NUMBER (R_XC16X_POF, 6)
- RELOC_NUMBER (R_XC16X_SEG, 7)
- RELOC_NUMBER (R_XC16X_SOF, 8)
-
-END_RELOC_NUMBERS (R_XC16X_max)
-
-#endif /* _ELF_XC16X_H */
eelf32tilepro.c \
eelf32vax.c \
eelf32visium.c \
- eelf32xc16x.c \
- eelf32xc16xl.c \
- eelf32xc16xs.c \
eelf32xstormy16.c \
eelf32xtensa.c \
eelf32z80.c \
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf32tilepro.Pc@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf32vax.Pc@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf32visium.Pc@am__quote@
-@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf32xc16x.Pc@am__quote@
-@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf32xc16xl.Pc@am__quote@
-@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf32xc16xs.Pc@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf32xstormy16.Pc@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf32xtensa.Pc@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf32z80.Pc@am__quote@
eelf32tilepro.c \
eelf32vax.c \
eelf32visium.c \
- eelf32xc16x.c \
- eelf32xc16xl.c \
- eelf32xc16xs.c \
eelf32xstormy16.c \
eelf32xtensa.c \
eelf32z80.c \
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf32tilepro.Po@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf32vax.Po@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf32visium.Po@am__quote@
-@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf32xc16x.Po@am__quote@
-@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf32xc16xl.Po@am__quote@
-@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf32xc16xs.Po@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf32xstormy16.Po@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf32xtensa.Po@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf32z80.Po@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf32tilepro.Pc@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf32vax.Pc@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf32visium.Pc@am__quote@
-@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf32xc16x.Pc@am__quote@
-@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf32xc16xl.Pc@am__quote@
-@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf32xc16xs.Pc@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf32xstormy16.Pc@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf32xtensa.Pc@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf32z80.Pc@am__quote@
targ_extra_emuls=i386pe
targ_extra_ofiles="deffilep.o pep-dll.o pe-dll.o"
;;
-xc16x-*-elf) targ_emul=elf32xc16x
- targ_extra_emuls="elf32xc16xl elf32xc16xs"
- ;;
xgate-*-*) targ_emul=xgateelf
targ_extra_ofiles=ldelfgen.o
;;
+++ /dev/null
-SCRIPT_NAME=elf32xc16x
-TEMPLATE_NAME=elf
-OUTPUT_FORMAT="elf32-xc16x"
-TEXT_START_ADDR=0x00400
-ARCH=xc16x
-MAXPAGESIZE="CONSTANT (MAXPAGESIZE)"
-ENTRY=_start
-EMBEDDED=yes
+++ /dev/null
-SCRIPT_NAME=elf32xc16xl
-TEMPLATE_NAME=elf
-OUTPUT_FORMAT="elf32-xc16x"
-TEXT_START_ADDR=0xc00300
-ARCH=xc16x:xc16xl
-MAXPAGESIZE="CONSTANT (MAXPAGESIZE)"
-ENTRY=_start
-EMBEDDED=yes
+++ /dev/null
-SCRIPT_NAME=elf32xc16xs
-TEMPLATE_NAME=elf
-OUTPUT_FORMAT="elf32-xc16x"
-TEXT_START_ADDR=0xc00300
-ARCH=xc16x:xc16xs
-MAXPAGESIZE="CONSTANT (MAXPAGESIZE)"
-ENTRY=_start
-EMBEDDED=yes
eelf32tilepro.c
eelf32vax.c
eelf32visium.c
-eelf32xc16x.c
-eelf32xc16xl.c
-eelf32xc16xs.c
eelf32xstormy16.c
eelf32xtensa.c
eelf32z80.c
+++ /dev/null
-# Copyright (C) 2014-2022 Free Software Foundation, Inc.
-#
-# Copying and distribution of this file, with or without modification,
-# are permitted in any medium without royalty provided the copyright
-# notice and this notice are preserved.
-
-cat <<EOF
-/* Copyright (C) 2014-2022 Free Software Foundation, Inc.
-
- Copying and distribution of this script, with or without modification,
- are permitted in any medium without royalty provided the copyright
- notice and this notice are preserved. */
-
-OUTPUT_FORMAT("${OUTPUT_FORMAT}")
-OUTPUT_ARCH(${ARCH})
-EOF
-
-test -n "${RELOCATING}" && cat <<EOF
-ENTRY ("_start")
-MEMORY
-{
-
- vectarea : o =0x00000, l = 0x0300
-
- introm : o = 0x00400, l = 0x16000
- /* The stack starts at the top of main ram. */
-
- dram : o = 0x8000 , l = 0xffff
- /* At the very top of the address space is the 8-bit area. */
-
- ldata : o =0x4000 ,l = 0x0200
-}
-
-EOF
-
-cat <<EOF
-SECTIONS
-{
-.init :
- {
- KEEP (*(SORT_NONE(.init)))
- ${RELOCATING+KEEP (*(SORT_NONE(.fini)))}
- } ${RELOCATING+ >introm}
-
-.text :
- {
- ${RELOCATING+*(.rodata)}
- ${RELOCATING+*(.text.*)}
- *(.text)
- ${RELOCATING+ _etext = . ; }
- } ${RELOCATING+ > introm}
-.data :
- {
- *(.data)
- ${RELOCATING+*(.data.*)}
-
- ${RELOCATING+ _edata = . ; }
- } ${RELOCATING+ > dram}
-
-.bss :
- {
- ${RELOCATING+ _bss_start = . ;}
- *(.bss)
- ${RELOCATING+*(COMMON)}
- ${RELOCATING+ _end = . ; }
- } ${RELOCATING+ > dram}
-
-.ldata :
- {
- *(.ldata)
- } ${RELOCATING+ > ldata}
-
-
-.vects :
- {
- *(.vects)
- } ${RELOCATING+ > vectarea}
-
-}
-EOF
+++ /dev/null
-# Copyright (C) 2014-2022 Free Software Foundation, Inc.
-#
-# Copying and distribution of this file, with or without modification,
-# are permitted in any medium without royalty provided the copyright
-# notice and this notice are preserved.
-
-cat <<EOF
-/* Copyright (C) 2014-2022 Free Software Foundation, Inc.
-
- Copying and distribution of this script, with or without modification,
- are permitted in any medium without royalty provided the copyright
- notice and this notice are preserved. */
-
-OUTPUT_FORMAT("${OUTPUT_FORMAT}")
-OUTPUT_ARCH(${ARCH})
-EOF
-
-test -n "${RELOCATING}" && cat <<EOF
-ENTRY ("_start")
-MEMORY
-{
- vectarea : o =0xc00000, l = 0x0300
-
- introm : o = 0xc00300, l = 0x16000
- /* The stack starts at the top of main ram. */
-
- dram : o = 0x8000 , l = 0xffff
- /* At the very top of the address space is the 8-bit area. */
-
- ldata : o =0x4000 ,l = 0x0200
-}
-EOF
-
-cat <<EOF
-SECTIONS
-{
-/*.vects :
- {
- *(.vects)
- } ${RELOCATING+ > vectarea} */
-.init :
- {
- KEEP (*(SORT_NONE(.init)))
- ${RELOCATING+KEEP (*(SORT_NONE(.fini)))}
- } ${RELOCATING+ >introm}
-
-.text :
- {
- ${RELOCATING+*(.rodata)}
- ${RELOCATING+*(.text.*)}
- *(.text)
- ${RELOCATING+ _etext = . ; }
- } ${RELOCATING+ > introm}
-.data :
- {
- *(.data)
- ${RELOCATING+*(.data.*)}
-
- ${RELOCATING+ _edata = . ; }
- } ${RELOCATING+ > dram}
-
-.bss :
- {
- ${RELOCATING+ _bss_start = . ;}
- *(.bss)
- ${RELOCATING+*(COMMON)}
- ${RELOCATING+ _end = . ; }
- } ${RELOCATING+ > dram}
-
-.ldata :
- {
- *(.ldata)
- } ${RELOCATING+ > ldata}
-
-.vects :
- {
- *(.vects)
- } ${RELOCATING+ > vectarea}
-}
-EOF
+++ /dev/null
-# Copyright (C) 2014-2022 Free Software Foundation, Inc.
-#
-# Copying and distribution of this file, with or without modification,
-# are permitted in any medium without royalty provided the copyright
-# notice and this notice are preserved.
-
-cat <<EOF
-/* Copyright (C) 2014-2022 Free Software Foundation, Inc.
-
- Copying and distribution of this script, with or without modification,
- are permitted in any medium without royalty provided the copyright
- notice and this notice are preserved. */
-
-OUTPUT_FORMAT("${OUTPUT_FORMAT}")
-OUTPUT_ARCH(${ARCH})
-EOF
-
-test -n "${RELOCATING}" && cat <<EOF
-ENTRY ("_start")
-MEMORY
-{
- vectarea : o =0xc00000, l = 0x0300
-
- introm : o = 0xc00300, l = 0x16000
- /* The stack starts at the top of main ram. */
-
- dram : o = 0x8000 , l = 0xffff
- /* At the very top of the address space is the 8-bit area. */
-
- ldata : o =0x4000 ,l = 0x0200
-}
-
-EOF
-
-cat <<EOF
-SECTIONS
-{
-/*.vects :
- {
- *(.vects)
- } ${RELOCATING+ > vectarea} */
-.init :
- {
- KEEP (*(SORT_NONE(.init)))
- ${RELOCATING+KEEP (*(SORT_NONE(.fini)))}
- } ${RELOCATING+ >introm}
-
-.text :
- {
- ${RELOCATING+*(.rodata)}
- ${RELOCATING+*(.text.*)}
- *(.text)
- ${RELOCATING+ _etext = . ; }
- } ${RELOCATING+ > introm}
-.data :
- {
- *(.data)
- ${RELOCATING+*(.data.*)}
-
- ${RELOCATING+ _edata = . ; }
- } ${RELOCATING+ > dram}
-
-.bss :
- {
- ${RELOCATING+ _bss_start = . ;}
- *(.bss)
- ${RELOCATING+*(COMMON)}
- ${RELOCATING+ _end = . ; }
- } ${RELOCATING+ > dram}
-
-.ldata :
- {
- *(.ldata)
- } ${RELOCATING+ > ldata}
-
-.vects :
- {
- *(.vects)
- } ${RELOCATING+ > vectarea}
-}
-EOF
|| [istarget h8300-*-*]
|| [istarget ip2k-*-*]
|| [istarget m68hc11-*]
- || [istarget "xc16x-*"]
|| [istarget "z80-*-*"] } {
set pr25490_2_exp "pr25490-2-16.rd"
set pr25490_3_exp "pr25490-3-16.rd"
#source: pr22450.s
#readelf: --notes --wide
#ld: -r
-#xfail: avr-*-* crx-*-* h8300-*-* ip2k-*-* m68hc11-*-* xc16x-*-* z80-*-*
+#xfail: avr-*-* crx-*-* h8300-*-* ip2k-*-* m68hc11-*-* z80-*-*
# Fails on H8300 because it does not generate the correct relocs for the size fields.
-# Fails on AVR, IP2K, M68HC11, XC16C because the assembler does not calculate the correct values for the differences of local symbols.
+# Fails on AVR, IP2K, and M68HC11 because the assembler does not calculate the correct values for the differences of local symbols.
# Fails on CRX because readelf does not know how to apply CRX reloc number 20 (R_CRX_SWITCH32).
#...
#xfail: [uses_genelf]
#xfail: m68hc12-*
# The following targets don't support --build-id.
-#xfail: cr16-* crx-* visium-* xc16x-*
+#xfail: cr16-* crx-* visium-*
# The following targets place .note.gnu.build-id in unusual places.
#xfail: pru-*
+++ /dev/null
-
-.*: file format elf32-xc16x
-
-Disassembly of section .text:
-
-00000400 <_start>:
- 400: e0 f5 mov r5,#0xf
- 402: e0 f6 mov r6,#0xf
-
-00000404 <.12>:
- 404: f2 f5 1c 04 mov r5,0x41c
- 408: e0 d6 mov r6,#0xd
- 40a: f2 f7 1c 04 mov r7,0x41c
- 40e: e0 d8 mov r8,#0xd
-
-00000410 <.13>:
- 410: f2 f5 1c 04 mov r5,0x41c
- 414: e0 f6 mov r6,#0xf
- 416: f2 f7 1c 04 mov r7,0x41c
- 41a: e0 f8 mov r8,#0xf
-
-0000041c <.end>:
-.*: ca 09 04 04 calla- cc_nusr0,404 <.12>
-.*: ca 19 04 04 calla- cc_nusr1,404 <.12>
-.*: ca 29 04 04 calla- cc_usr0,404 <.12>
-.*: ea 09 04 04 jmpa- cc_nusr0,404 <.12>
-.*: ea 19 04 04 jmpa- cc_nusr1,404 <.12>
-.*: ea 29 04 04 jmpa- cc_usr0,404 <.12>
+++ /dev/null
- .global _start
-_start:
- mov r5,#0xf
- mov r6,#0xf
-
-.12:
- mov r5,.end
- mov r6,#0xd
- mov r7,.end
- mov r8,#0xd
-.13:
- mov r5,.end
- mov r6,#0xf
- mov r7,.end
- mov r8,#0xf
-.end:
- ;calla cc_UC,.13
- ;calla cc_usr1,.12
-
- ;calla+ cc_UGT,.12
- calla- cc_nusr0,.12
- calla- cc_nusr1,.12
- calla- cc_usr0,.12
-
- ;jmpa cc_UGT,.end
- ;jmpa cc_nusr0,.end
-
- ;jmpa+ cc_UGT,.12
- jmpa- cc_nusr0,.12
- jmpa- cc_nusr1,.12
- jmpa- cc_usr0,.12
+++ /dev/null
-
-.*: file format elf32-xc16x
-
-Disassembly of section .text:
-
-00000400 <_start>:
- 400: e0 f8 mov r8,#0xf
- 402: fa 00 08 04 jmps #seg:0x0,#sof:0x408
- 406: e0 f9 mov r9,#0xf
-
-00000408 <.12>:
- 408: e0 f5 mov r5,#0xf
- 40a: e0 f7 mov r7,#0xf
- 40c: da 00 10 04 calls #seg:0x0,#sof:0x410
-
-00000410 <.13>:
- 410: e0 f6 mov r6,#0xf
- 412: e0 f8 mov r8,#0xf
+++ /dev/null
- .global _start
-_start:
- mov r8,#0xf
- jmps #seg:.12,#sof:.12
- mov r9,#0xf
-.12:
- mov r5,#0xf
- mov r7,#0xf
- calls #seg:.13,#sof:.13
-.13:
- mov r6,#0xf
- mov r8,#0xf
-
\ No newline at end of file
+++ /dev/null
-
-.*: file format elf32-xc16x
-
-Disassembly of section .text:
-
-00000400 <_start>:
- 400: e0 f5 mov r5,#0xf
- 402: e0 f6 mov r6,#0xf
- 404: e0 f7 mov r7,#0xf
- 406: e0 f8 mov r8,#0xf
- 408: e0 f9 mov r9,#0xf
- 40a: e0 fa mov r10,#0xf
- 40c: e0 fb mov r11,#0xf
- 40e: e0 fc mov r12,#0xf
-
-00000410 <.12>:
- 410: 2d 07 jmpr cc_Z,7
- 412: 3d fe jmpr cc_NZ,254
- 414: 8d fd jmpr cc_ULT,253
- 416: 8d 45 jmpr cc_ULT,69
- 418: 9d 06 jmpr cc_UGE,6
- 41a: 0d 05 jmpr cc_UC,5
- 41c: 2d 04 jmpr cc_Z,4
- 41e: 3d 03 jmpr cc_NZ,3
-
-00000420 <.13>:
- 420: fd 02 jmpr cc_ULE,2
- 422: dd 01 jmpr cc_SGE,1
- 424: bd 00 jmpr cc_SLE,0
-
-00000426 <.end>:
- 426: 1d f4 jmpr cc_NET,244
- 428: bb fe callr 254
- 42a: bb fd callr 253
+++ /dev/null
- .global _start
-_start:
- mov r5,#0xf
- mov r6,#0xf
- mov r7,#0xf
- mov r8,#0xf
- mov r9,#0xf
- mov r10,#0xf
- mov r11,#0xf
- mov r12,#0xf
-.12:
- jmpr cc_Z,.13
- jmpr cc_NZ,.12
- jmpr cc_C,.12
- jmpr cc_C,0x45
- jmpr cc_NC,.end
- jmpr cc_UC,.end
- jmpr cc_EQ,.end
- jmpr cc_NE,.end
-.13:
- jmpr cc_ULE,.end
- jmpr cc_SGE,.end
- jmpr cc_SLE,.end
-.end:
- jmpr cc_NET,.12
- callr .end
- callr .end
+++ /dev/null
-
-.*: file format elf32-xc16x
-
-Disassembly of section .text:
-
-00c00300 <_start>:
- c00300: e0 f5 mov r5,#0xf
- c00302: e0 f6 mov r6,#0xf
- c00304: e0 f7 mov r7,#0xf
- c00306: e0 f8 mov r8,#0xf
- c00308: e0 f9 mov r9,#0xf
- c0030a: e0 fa mov r10,#0xf
- c0030c: e0 fb mov r11,#0xf
- c0030e: e0 fc mov r12,#0xf
-
-00c00310 <.12>:
- c00310: 2d 07 jmpr cc_Z,7
- c00312: 3d fe jmpr cc_NZ,254
- c00314: 8d fd jmpr cc_ULT,253
- c00316: 8d 45 jmpr cc_ULT,69
- c00318: 9d 06 jmpr cc_UGE,6
- c0031a: 0d 05 jmpr cc_UC,5
- c0031c: 2d 04 jmpr cc_Z,4
- c0031e: 3d 03 jmpr cc_NZ,3
-
-00c00320 <.13>:
- c00320: fd 02 jmpr cc_ULE,2
- c00322: dd 01 jmpr cc_SGE,1
- c00324: bd 00 jmpr cc_SLE,0
-
-00c00326 <.end>:
- c00326: 1d f4 jmpr cc_NET,244
- c00328: bb fe callr 254
- c0032a: bb fd callr 253
+++ /dev/null
-# Expect script for ld-xstormy16 tests
-# Copyright (C) 2003-2022 Free Software Foundation, Inc.
-#
-# This file is part of the GNU Binutils.
-#
-# This program is free software; you can redistribute it and/or modify
-# it under the terms of the GNU General Public License as published by
-# the Free Software Foundation; either version 3 of the License, or
-# (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
-# MA 02110-1301, USA.
-#
-
-# Test xc16x linking of pc-relative relocs. This tests the assembler and
-# tools like objdump as well as the linker.
-
-if {!([istarget "xc16x*-*-*"]) } {
- return
-}
-
-# Set up a list as described in ld-lib.exp
-
-set xc16x_tests {
- {
- "xc16x pc-relative relocs linker test"
- "" ""
- ""
- { "pcreloc.s" }
- { {objdump -Dz pcreloc.d} }
- "pcreloc"
- }
-}
-
-set xc16xabs_tests {
- {
- "xc16x absolute relative address linker test"
- "" ""
- ""
- { "absrel.s" }
- { {objdump -Dz absrel.d} }
- "absrel"
- }
-}
-
-set xc16xoffset_tests {
- {
- "xc16x offset linker test"
- "" ""
- ""
- { "offset.s" }
- { {objdump -Dz offset.d} }
- "offset"
- }
-}
-
- run_ld_link_tests $xc16x_tests
- run_ld_link_tests $xc16xabs_tests
- run_ld_link_tests $xc16xoffset_tests
-
-
score-opc.h \
sh-opc.h \
sysdep.h \
- xc16x-desc.h xc16x-opc.h \
xstormy16-desc.h xstormy16-opc.h \
z8k-opc.h
visium-dis.c \
visium-opc.c \
wasm32-dis.c \
- xc16x-asm.c \
- xc16x-desc.c \
- xc16x-dis.c \
- xc16x-ibld.c \
- xc16x-opc.c \
xstormy16-asm.c \
xstormy16-desc.c \
xstormy16-dis.c \
CLEANFILES = \
stamp-epiphany stamp-fr30 stamp-frv stamp-ip2k stamp-iq2000 stamp-lm32 \
- stamp-m32c stamp-m32r stamp-mep stamp-mt \
- stamp-or1k stamp-xc16x stamp-xstormy16 \
+ stamp-m32c stamp-m32r stamp-mep stamp-mt stamp-or1k stamp-xstormy16 \
libopcodes.a stamp-lib
$(CGENDIR)/opc-opinst.scm \
cgen-asm.in cgen-dis.in cgen-ibld.in
-CGEN_CPUS = cris epiphany fr30 frv ip2k iq2000 lm32 m32c m32r mep mt or1k xc16x xstormy16
+CGEN_CPUS = cris epiphany fr30 frv ip2k iq2000 lm32 m32c m32r mep mt or1k xstormy16
if CGEN_MAINT
BPF_DEPS = stamp-bpf
MEP_DEPS = stamp-mep
MT_DEPS = stamp-mt
OR1K_DEPS = stamp-or1k
-XC16X_DEPS = stamp-xc16x
XSTORMY16_DEPS = stamp-xstormy16
else
BPF_DEPS =
MEP_DEPS =
MT_DEPS =
OR1K_DEPS =
-XC16X_DEPS =
XSTORMY16_DEPS =
endif
$(MAKE) run-cgen arch=or1k prefix=or1k options=opinst \
archfile=$(CPUDIR)/or1k.cpu opcfile=$(CPUDIR)/or1k.opc extrafiles=opinst
-$(srcdir)/xc16x-desc.h $(srcdir)/xc16x-desc.c $(srcdir)/xc16x-opc.h $(srcdir)/xc16x-opc.c $(srcdir)/xc16x-ibld.c $(srcdir)/xc16x-asm.c $(srcdir)/xc16x-dis.c: $(XC16X_DEPS)
- @true
-stamp-xc16x: $(CGENDEPS) $(CPUDIR)/xc16x.cpu $(CPUDIR)/xc16x.opc
- $(MAKE) run-cgen arch=xc16x prefix=xc16x options= \
- archfile=$(CPUDIR)/xc16x.cpu \
- opcfile=$(CPUDIR)/xc16x.opc \
- extrafiles=
-
$(srcdir)/xstormy16-desc.h $(srcdir)/xstormy16-desc.c $(srcdir)/xstormy16-opc.h $(srcdir)/xstormy16-opc.c $(srcdir)/xstormy16-ibld.c $(srcdir)/xstormy16-asm.c $(srcdir)/xstormy16-dis.c: $(XSTORMY16_DEPS)
@true
stamp-xstormy16: $(CGENDEPS) $(CPUDIR)/xstormy16.cpu $(CPUDIR)/xstormy16.opc
score-opc.h \
sh-opc.h \
sysdep.h \
- xc16x-desc.h xc16x-opc.h \
xstormy16-desc.h xstormy16-opc.h \
z8k-opc.h
visium-dis.c \
visium-opc.c \
wasm32-dis.c \
- xc16x-asm.c \
- xc16x-desc.c \
- xc16x-dis.c \
- xc16x-ibld.c \
- xc16x-opc.c \
xstormy16-asm.c \
xstormy16-desc.c \
xstormy16-dis.c \
POTFILES = $(HFILES) $(CFILES)
CLEANFILES = \
stamp-epiphany stamp-fr30 stamp-frv stamp-ip2k stamp-iq2000 stamp-lm32 \
- stamp-m32c stamp-m32r stamp-mep stamp-mt \
- stamp-or1k stamp-xc16x stamp-xstormy16 \
+ stamp-m32c stamp-m32r stamp-mep stamp-mt stamp-or1k stamp-xstormy16 \
libopcodes.a stamp-lib
CGENDIR = @cgendir@
$(CGENDIR)/opc-opinst.scm \
cgen-asm.in cgen-dis.in cgen-ibld.in
-CGEN_CPUS = cris epiphany fr30 frv ip2k iq2000 lm32 m32c m32r mep mt or1k xc16x xstormy16
+CGEN_CPUS = cris epiphany fr30 frv ip2k iq2000 lm32 m32c m32r mep mt or1k xstormy16
@CGEN_MAINT_FALSE@BPF_DEPS =
@CGEN_MAINT_TRUE@BPF_DEPS = stamp-bpf
@CGEN_MAINT_FALSE@CRIS_DEPS =
@CGEN_MAINT_TRUE@MT_DEPS = stamp-mt
@CGEN_MAINT_FALSE@OR1K_DEPS =
@CGEN_MAINT_TRUE@OR1K_DEPS = stamp-or1k
-@CGEN_MAINT_FALSE@XC16X_DEPS =
-@CGEN_MAINT_TRUE@XC16X_DEPS = stamp-xc16x
@CGEN_MAINT_FALSE@XSTORMY16_DEPS =
@CGEN_MAINT_TRUE@XSTORMY16_DEPS = stamp-xstormy16
MOSTLYCLEANFILES = aarch64-gen$(EXEEXT_FOR_BUILD) i386-gen$(EXEEXT_FOR_BUILD) \
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/visium-dis.Plo@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/visium-opc.Plo@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/wasm32-dis.Plo@am__quote@
-@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/xc16x-asm.Plo@am__quote@
-@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/xc16x-desc.Plo@am__quote@
-@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/xc16x-dis.Plo@am__quote@
-@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/xc16x-ibld.Plo@am__quote@
-@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/xc16x-opc.Plo@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/xgate-dis.Plo@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/xgate-opc.Plo@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/xstormy16-asm.Plo@am__quote@
$(MAKE) run-cgen arch=or1k prefix=or1k options=opinst \
archfile=$(CPUDIR)/or1k.cpu opcfile=$(CPUDIR)/or1k.opc extrafiles=opinst
-$(srcdir)/xc16x-desc.h $(srcdir)/xc16x-desc.c $(srcdir)/xc16x-opc.h $(srcdir)/xc16x-opc.c $(srcdir)/xc16x-ibld.c $(srcdir)/xc16x-asm.c $(srcdir)/xc16x-dis.c: $(XC16X_DEPS)
- @true
-stamp-xc16x: $(CGENDEPS) $(CPUDIR)/xc16x.cpu $(CPUDIR)/xc16x.opc
- $(MAKE) run-cgen arch=xc16x prefix=xc16x options= \
- archfile=$(CPUDIR)/xc16x.cpu \
- opcfile=$(CPUDIR)/xc16x.opc \
- extrafiles=
-
$(srcdir)/xstormy16-desc.h $(srcdir)/xstormy16-desc.c $(srcdir)/xstormy16-opc.h $(srcdir)/xstormy16-opc.c $(srcdir)/xstormy16-ibld.c $(srcdir)/xstormy16-asm.c $(srcdir)/xstormy16-dis.c: $(XSTORMY16_DEPS)
@true
stamp-xstormy16: $(CGENDEPS) $(CPUDIR)/xstormy16.cpu $(CPUDIR)/xstormy16.opc
bfd_vax_arch) ta="$ta vax-dis.lo" ;;
bfd_visium_arch) ta="$ta visium-dis.lo visium-opc.lo" ;;
bfd_wasm32_arch) ta="$ta wasm32-dis.lo" ;;
- bfd_xc16x_arch) ta="$ta xc16x-asm.lo xc16x-desc.lo xc16x-dis.lo xc16x-ibld.lo xc16x-opc.lo" using_cgen=yes ;;
bfd_xgate_arch) ta="$ta xgate-dis.lo xgate-opc.lo" ;;
bfd_xstormy16_arch) ta="$ta xstormy16-asm.lo xstormy16-desc.lo xstormy16-dis.lo xstormy16-ibld.lo xstormy16-opc.lo" using_cgen=yes ;;
bfd_xtensa_arch) ta="$ta xtensa-dis.lo" ;;
bfd_vax_arch) ta="$ta vax-dis.lo" ;;
bfd_visium_arch) ta="$ta visium-dis.lo visium-opc.lo" ;;
bfd_wasm32_arch) ta="$ta wasm32-dis.lo" ;;
- bfd_xc16x_arch) ta="$ta xc16x-asm.lo xc16x-desc.lo xc16x-dis.lo xc16x-ibld.lo xc16x-opc.lo" using_cgen=yes ;;
bfd_xgate_arch) ta="$ta xgate-dis.lo xgate-opc.lo" ;;
bfd_xstormy16_arch) ta="$ta xstormy16-asm.lo xstormy16-desc.lo xstormy16-dis.lo xstormy16-ibld.lo xstormy16-opc.lo" using_cgen=yes ;;
bfd_xtensa_arch) ta="$ta xtensa-dis.lo" ;;
#define ARCH_visium
#define ARCH_wasm32
#define ARCH_xstormy16
-#define ARCH_xc16x
#define ARCH_xgate
#define ARCH_xtensa
#define ARCH_z80
disassemble = print_insn_xstormy16;
break;
#endif
-#ifdef ARCH_xc16x
- case bfd_arch_xc16x:
- disassemble = print_insn_xc16x;
- break;
-#endif
#ifdef ARCH_xtensa
case bfd_arch_xtensa:
disassemble = print_insn_xtensa;
extern int print_insn_vax (bfd_vma, disassemble_info *);
extern int print_insn_visium (bfd_vma, disassemble_info *);
extern int print_insn_wasm32 (bfd_vma, disassemble_info *);
-extern int print_insn_xc16x (bfd_vma, disassemble_info *);
extern int print_insn_xgate (bfd_vma, disassemble_info *);
extern int print_insn_xstormy16 (bfd_vma, disassemble_info *);
extern int print_insn_xtensa (bfd_vma, disassemble_info *);
visium-dis.c
visium-opc.c
wasm32-dis.c
-xc16x-asm.c
-xc16x-desc.c
-xc16x-desc.h
-xc16x-dis.c
-xc16x-ibld.c
-xc16x-opc.c
-xc16x-opc.h
xgate-dis.c
xgate-opc.c
xstormy16-asm.c
+++ /dev/null
-/* DO NOT EDIT! -*- buffer-read-only: t -*- vi:set ro: */
-/* Assembler interface for targets using CGEN. -*- C -*-
- CGEN: Cpu tools GENerator
-
- THIS FILE IS MACHINE GENERATED WITH CGEN.
- - the resultant file is machine generated, cgen-asm.in isn't
-
- Copyright (C) 1996-2022 Free Software Foundation, Inc.
-
- This file is part of libopcodes.
-
- This library is free software; you can redistribute it and/or modify
- it under the terms of the GNU General Public License as published by
- the Free Software Foundation; either version 3, or (at your option)
- any later version.
-
- It is distributed in the hope that it will be useful, but WITHOUT
- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
- License for more details.
-
- You should have received a copy of the GNU General Public License
- along with this program; if not, write to the Free Software Foundation, Inc.,
- 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */
-
-
-/* ??? Eventually more and more of this stuff can go to cpu-independent files.
- Keep that in mind. */
-
-#include "sysdep.h"
-#include <stdio.h>
-#include "ansidecl.h"
-#include "bfd.h"
-#include "symcat.h"
-#include "xc16x-desc.h"
-#include "xc16x-opc.h"
-#include "opintl.h"
-#include "xregex.h"
-#include "libiberty.h"
-#include "safe-ctype.h"
-
-#undef min
-#define min(a,b) ((a) < (b) ? (a) : (b))
-#undef max
-#define max(a,b) ((a) > (b) ? (a) : (b))
-
-static const char * parse_insn_normal
- (CGEN_CPU_DESC, const CGEN_INSN *, const char **, CGEN_FIELDS *);
-\f
-/* -- assembler routines inserted here. */
-
-/* -- asm.c */
-/* Handle '#' prefixes (i.e. skip over them). */
-
-static const char *
-parse_hash (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
- const char **strp,
- int opindex ATTRIBUTE_UNUSED,
- long *valuep ATTRIBUTE_UNUSED)
-{
- if (**strp == '#')
- {
- ++*strp;
- return NULL;
- }
- return _("Missing '#' prefix");
-}
-
-/* Handle '.' prefixes (i.e. skip over them). */
-
-static const char *
-parse_dot (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
- const char **strp,
- int opindex ATTRIBUTE_UNUSED,
- long *valuep ATTRIBUTE_UNUSED)
-{
- if (**strp == '.')
- {
- ++*strp;
- return NULL;
- }
- return _("Missing '.' prefix");
-}
-
-/* Handle 'pof:' prefixes (i.e. skip over them). */
-
-static const char *
-parse_pof (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
- const char **strp,
- int opindex ATTRIBUTE_UNUSED,
- long *valuep ATTRIBUTE_UNUSED)
-{
- if (strncasecmp (*strp, "pof:", 4) == 0)
- {
- *strp += 4;
- return NULL;
- }
- return _("Missing 'pof:' prefix");
-}
-
-/* Handle 'pag:' prefixes (i.e. skip over them). */
-
-static const char *
-parse_pag (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
- const char **strp,
- int opindex ATTRIBUTE_UNUSED,
- long *valuep ATTRIBUTE_UNUSED)
-{
- if (strncasecmp (*strp, "pag:", 4) == 0)
- {
- *strp += 4;
- return NULL;
- }
- return _("Missing 'pag:' prefix");
-}
-
-/* Handle 'sof' prefixes (i.e. skip over them). */
-
-static const char *
-parse_sof (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
- const char **strp,
- int opindex ATTRIBUTE_UNUSED,
- long *valuep ATTRIBUTE_UNUSED)
-{
- if (strncasecmp (*strp, "sof:", 4) == 0)
- {
- *strp += 4;
- return NULL;
- }
- return _("Missing 'sof:' prefix");
-}
-
-/* Handle 'seg' prefixes (i.e. skip over them). */
-
-static const char *
-parse_seg (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
- const char **strp,
- int opindex ATTRIBUTE_UNUSED,
- long *valuep ATTRIBUTE_UNUSED)
-{
- if (strncasecmp (*strp, "seg:", 4) == 0)
- {
- *strp += 4;
- return NULL;
- }
- return _("Missing 'seg:' prefix");
-}
-/* -- */
-
-const char * xc16x_cgen_parse_operand
- (CGEN_CPU_DESC, int, const char **, CGEN_FIELDS *);
-
-/* Main entry point for operand parsing.
-
- This function is basically just a big switch statement. Earlier versions
- used tables to look up the function to use, but
- - if the table contains both assembler and disassembler functions then
- the disassembler contains much of the assembler and vice-versa,
- - there's a lot of inlining possibilities as things grow,
- - using a switch statement avoids the function call overhead.
-
- This function could be moved into `parse_insn_normal', but keeping it
- separate makes clear the interface between `parse_insn_normal' and each of
- the handlers. */
-
-const char *
-xc16x_cgen_parse_operand (CGEN_CPU_DESC cd,
- int opindex,
- const char ** strp,
- CGEN_FIELDS * fields)
-{
- const char * errmsg = NULL;
- /* Used by scalar operands that still need to be parsed. */
- long junk ATTRIBUTE_UNUSED;
-
- switch (opindex)
- {
- case XC16X_OPERAND_REGNAM :
- errmsg = cgen_parse_keyword (cd, strp, & xc16x_cgen_opval_psw_names, & fields->f_reg8);
- break;
- case XC16X_OPERAND_BIT01 :
- errmsg = cgen_parse_unsigned_integer (cd, strp, XC16X_OPERAND_BIT01, (unsigned long *) (& fields->f_op_1bit));
- break;
- case XC16X_OPERAND_BIT1 :
- errmsg = cgen_parse_unsigned_integer (cd, strp, XC16X_OPERAND_BIT1, (unsigned long *) (& fields->f_op_bit1));
- break;
- case XC16X_OPERAND_BIT2 :
- errmsg = cgen_parse_unsigned_integer (cd, strp, XC16X_OPERAND_BIT2, (unsigned long *) (& fields->f_op_bit2));
- break;
- case XC16X_OPERAND_BIT4 :
- errmsg = cgen_parse_unsigned_integer (cd, strp, XC16X_OPERAND_BIT4, (unsigned long *) (& fields->f_op_bit4));
- break;
- case XC16X_OPERAND_BIT8 :
- errmsg = cgen_parse_unsigned_integer (cd, strp, XC16X_OPERAND_BIT8, (unsigned long *) (& fields->f_op_bit8));
- break;
- case XC16X_OPERAND_BITONE :
- errmsg = cgen_parse_unsigned_integer (cd, strp, XC16X_OPERAND_BITONE, (unsigned long *) (& fields->f_op_onebit));
- break;
- case XC16X_OPERAND_CADDR :
- {
- bfd_vma value = 0;
- errmsg = cgen_parse_address (cd, strp, XC16X_OPERAND_CADDR, 0, NULL, & value);
- fields->f_offset16 = value;
- }
- break;
- case XC16X_OPERAND_COND :
- errmsg = cgen_parse_keyword (cd, strp, & xc16x_cgen_opval_conditioncode_names, & fields->f_condcode);
- break;
- case XC16X_OPERAND_DATA8 :
- errmsg = cgen_parse_unsigned_integer (cd, strp, XC16X_OPERAND_DATA8, (unsigned long *) (& fields->f_data8));
- break;
- case XC16X_OPERAND_DATAHI8 :
- errmsg = cgen_parse_unsigned_integer (cd, strp, XC16X_OPERAND_DATAHI8, (unsigned long *) (& fields->f_datahi8));
- break;
- case XC16X_OPERAND_DOT :
- errmsg = parse_dot (cd, strp, XC16X_OPERAND_DOT, (long *) (& junk));
- break;
- case XC16X_OPERAND_DR :
- errmsg = cgen_parse_keyword (cd, strp, & xc16x_cgen_opval_gr_names, & fields->f_r1);
- break;
- case XC16X_OPERAND_DRB :
- errmsg = cgen_parse_keyword (cd, strp, & xc16x_cgen_opval_grb_names, & fields->f_r1);
- break;
- case XC16X_OPERAND_DRI :
- errmsg = cgen_parse_keyword (cd, strp, & xc16x_cgen_opval_gr_names, & fields->f_r4);
- break;
- case XC16X_OPERAND_EXTCOND :
- errmsg = cgen_parse_keyword (cd, strp, & xc16x_cgen_opval_extconditioncode_names, & fields->f_extccode);
- break;
- case XC16X_OPERAND_GENREG :
- errmsg = cgen_parse_keyword (cd, strp, & xc16x_cgen_opval_r8_names, & fields->f_regb8);
- break;
- case XC16X_OPERAND_HASH :
- errmsg = parse_hash (cd, strp, XC16X_OPERAND_HASH, (long *) (& junk));
- break;
- case XC16X_OPERAND_ICOND :
- errmsg = cgen_parse_keyword (cd, strp, & xc16x_cgen_opval_conditioncode_names, & fields->f_icondcode);
- break;
- case XC16X_OPERAND_LBIT2 :
- errmsg = cgen_parse_unsigned_integer (cd, strp, XC16X_OPERAND_LBIT2, (unsigned long *) (& fields->f_op_lbit2));
- break;
- case XC16X_OPERAND_LBIT4 :
- errmsg = cgen_parse_unsigned_integer (cd, strp, XC16X_OPERAND_LBIT4, (unsigned long *) (& fields->f_op_lbit4));
- break;
- case XC16X_OPERAND_MASK8 :
- errmsg = cgen_parse_unsigned_integer (cd, strp, XC16X_OPERAND_MASK8, (unsigned long *) (& fields->f_mask8));
- break;
- case XC16X_OPERAND_MASKLO8 :
- errmsg = cgen_parse_unsigned_integer (cd, strp, XC16X_OPERAND_MASKLO8, (unsigned long *) (& fields->f_datahi8));
- break;
- case XC16X_OPERAND_MEMGR8 :
- errmsg = cgen_parse_keyword (cd, strp, & xc16x_cgen_opval_memgr8_names, & fields->f_memgr8);
- break;
- case XC16X_OPERAND_MEMORY :
- {
- bfd_vma value = 0;
- errmsg = cgen_parse_address (cd, strp, XC16X_OPERAND_MEMORY, 0, NULL, & value);
- fields->f_memory = value;
- }
- break;
- case XC16X_OPERAND_PAG :
- errmsg = parse_pag (cd, strp, XC16X_OPERAND_PAG, (long *) (& junk));
- break;
- case XC16X_OPERAND_PAGENUM :
- errmsg = cgen_parse_unsigned_integer (cd, strp, XC16X_OPERAND_PAGENUM, (unsigned long *) (& fields->f_pagenum));
- break;
- case XC16X_OPERAND_POF :
- errmsg = parse_pof (cd, strp, XC16X_OPERAND_POF, (long *) (& junk));
- break;
- case XC16X_OPERAND_QBIT :
- errmsg = cgen_parse_unsigned_integer (cd, strp, XC16X_OPERAND_QBIT, (unsigned long *) (& fields->f_qbit));
- break;
- case XC16X_OPERAND_QHIBIT :
- errmsg = cgen_parse_unsigned_integer (cd, strp, XC16X_OPERAND_QHIBIT, (unsigned long *) (& fields->f_qhibit));
- break;
- case XC16X_OPERAND_QLOBIT :
- errmsg = cgen_parse_unsigned_integer (cd, strp, XC16X_OPERAND_QLOBIT, (unsigned long *) (& fields->f_qlobit));
- break;
- case XC16X_OPERAND_REG8 :
- errmsg = cgen_parse_keyword (cd, strp, & xc16x_cgen_opval_r8_names, & fields->f_reg8);
- break;
- case XC16X_OPERAND_REGB8 :
- errmsg = cgen_parse_keyword (cd, strp, & xc16x_cgen_opval_grb8_names, & fields->f_regb8);
- break;
- case XC16X_OPERAND_REGBMEM8 :
- errmsg = cgen_parse_keyword (cd, strp, & xc16x_cgen_opval_regbmem8_names, & fields->f_regmem8);
- break;
- case XC16X_OPERAND_REGHI8 :
- errmsg = cgen_parse_keyword (cd, strp, & xc16x_cgen_opval_r8_names, & fields->f_reghi8);
- break;
- case XC16X_OPERAND_REGMEM8 :
- errmsg = cgen_parse_keyword (cd, strp, & xc16x_cgen_opval_regmem8_names, & fields->f_regmem8);
- break;
- case XC16X_OPERAND_REGOFF8 :
- errmsg = cgen_parse_keyword (cd, strp, & xc16x_cgen_opval_r8_names, & fields->f_regoff8);
- break;
- case XC16X_OPERAND_REL :
- errmsg = cgen_parse_signed_integer (cd, strp, XC16X_OPERAND_REL, (long *) (& fields->f_rel8));
- break;
- case XC16X_OPERAND_RELHI :
- errmsg = cgen_parse_signed_integer (cd, strp, XC16X_OPERAND_RELHI, (long *) (& fields->f_relhi8));
- break;
- case XC16X_OPERAND_SEG :
- errmsg = cgen_parse_unsigned_integer (cd, strp, XC16X_OPERAND_SEG, (unsigned long *) (& fields->f_seg8));
- break;
- case XC16X_OPERAND_SEGHI8 :
- errmsg = cgen_parse_unsigned_integer (cd, strp, XC16X_OPERAND_SEGHI8, (unsigned long *) (& fields->f_segnum8));
- break;
- case XC16X_OPERAND_SEGM :
- errmsg = parse_seg (cd, strp, XC16X_OPERAND_SEGM, (long *) (& junk));
- break;
- case XC16X_OPERAND_SOF :
- errmsg = parse_sof (cd, strp, XC16X_OPERAND_SOF, (long *) (& junk));
- break;
- case XC16X_OPERAND_SR :
- errmsg = cgen_parse_keyword (cd, strp, & xc16x_cgen_opval_gr_names, & fields->f_r2);
- break;
- case XC16X_OPERAND_SR2 :
- errmsg = cgen_parse_keyword (cd, strp, & xc16x_cgen_opval_gr_names, & fields->f_r0);
- break;
- case XC16X_OPERAND_SRB :
- errmsg = cgen_parse_keyword (cd, strp, & xc16x_cgen_opval_grb_names, & fields->f_r2);
- break;
- case XC16X_OPERAND_SRC1 :
- errmsg = cgen_parse_keyword (cd, strp, & xc16x_cgen_opval_gr_names, & fields->f_r1);
- break;
- case XC16X_OPERAND_SRC2 :
- errmsg = cgen_parse_keyword (cd, strp, & xc16x_cgen_opval_gr_names, & fields->f_r2);
- break;
- case XC16X_OPERAND_SRDIV :
- errmsg = cgen_parse_keyword (cd, strp, & xc16x_cgen_opval_regdiv8_names, & fields->f_reg8);
- break;
- case XC16X_OPERAND_U4 :
- errmsg = cgen_parse_keyword (cd, strp, & xc16x_cgen_opval_reg0_name, & fields->f_uimm4);
- break;
- case XC16X_OPERAND_UIMM16 :
- errmsg = cgen_parse_unsigned_integer (cd, strp, XC16X_OPERAND_UIMM16, (unsigned long *) (& fields->f_uimm16));
- break;
- case XC16X_OPERAND_UIMM2 :
- errmsg = cgen_parse_keyword (cd, strp, & xc16x_cgen_opval_ext_names, & fields->f_uimm2);
- break;
- case XC16X_OPERAND_UIMM3 :
- errmsg = cgen_parse_keyword (cd, strp, & xc16x_cgen_opval_reg0_name1, & fields->f_uimm3);
- break;
- case XC16X_OPERAND_UIMM4 :
- errmsg = cgen_parse_unsigned_integer (cd, strp, XC16X_OPERAND_UIMM4, (unsigned long *) (& fields->f_uimm4));
- break;
- case XC16X_OPERAND_UIMM7 :
- errmsg = cgen_parse_unsigned_integer (cd, strp, XC16X_OPERAND_UIMM7, (unsigned long *) (& fields->f_uimm7));
- break;
- case XC16X_OPERAND_UIMM8 :
- errmsg = cgen_parse_unsigned_integer (cd, strp, XC16X_OPERAND_UIMM8, (unsigned long *) (& fields->f_uimm8));
- break;
- case XC16X_OPERAND_UPAG16 :
- errmsg = cgen_parse_unsigned_integer (cd, strp, XC16X_OPERAND_UPAG16, (unsigned long *) (& fields->f_uimm16));
- break;
- case XC16X_OPERAND_UPOF16 :
- {
- bfd_vma value = 0;
- errmsg = cgen_parse_address (cd, strp, XC16X_OPERAND_UPOF16, 0, NULL, & value);
- fields->f_memory = value;
- }
- break;
- case XC16X_OPERAND_USEG16 :
- errmsg = cgen_parse_unsigned_integer (cd, strp, XC16X_OPERAND_USEG16, (unsigned long *) (& fields->f_offset16));
- break;
- case XC16X_OPERAND_USEG8 :
- errmsg = cgen_parse_unsigned_integer (cd, strp, XC16X_OPERAND_USEG8, (unsigned long *) (& fields->f_seg8));
- break;
- case XC16X_OPERAND_USOF16 :
- errmsg = cgen_parse_unsigned_integer (cd, strp, XC16X_OPERAND_USOF16, (unsigned long *) (& fields->f_offset16));
- break;
-
- default :
- /* xgettext:c-format */
- opcodes_error_handler
- (_("internal error: unrecognized field %d while parsing"),
- opindex);
- abort ();
- }
-
- return errmsg;
-}
-
-cgen_parse_fn * const xc16x_cgen_parse_handlers[] =
-{
- parse_insn_normal,
-};
-
-void
-xc16x_cgen_init_asm (CGEN_CPU_DESC cd)
-{
- xc16x_cgen_init_opcode_table (cd);
- xc16x_cgen_init_ibld_table (cd);
- cd->parse_handlers = & xc16x_cgen_parse_handlers[0];
- cd->parse_operand = xc16x_cgen_parse_operand;
-#ifdef CGEN_ASM_INIT_HOOK
-CGEN_ASM_INIT_HOOK
-#endif
-}
-
-\f
-
-/* Regex construction routine.
-
- This translates an opcode syntax string into a regex string,
- by replacing any non-character syntax element (such as an
- opcode) with the pattern '.*'
-
- It then compiles the regex and stores it in the opcode, for
- later use by xc16x_cgen_assemble_insn
-
- Returns NULL for success, an error message for failure. */
-
-char *
-xc16x_cgen_build_insn_regex (CGEN_INSN *insn)
-{
- CGEN_OPCODE *opc = (CGEN_OPCODE *) CGEN_INSN_OPCODE (insn);
- const char *mnem = CGEN_INSN_MNEMONIC (insn);
- char rxbuf[CGEN_MAX_RX_ELEMENTS];
- char *rx = rxbuf;
- const CGEN_SYNTAX_CHAR_TYPE *syn;
- int reg_err;
-
- syn = CGEN_SYNTAX_STRING (CGEN_OPCODE_SYNTAX (opc));
-
- /* Mnemonics come first in the syntax string. */
- if (! CGEN_SYNTAX_MNEMONIC_P (* syn))
- return _("missing mnemonic in syntax string");
- ++syn;
-
- /* Generate a case sensitive regular expression that emulates case
- insensitive matching in the "C" locale. We cannot generate a case
- insensitive regular expression because in Turkish locales, 'i' and 'I'
- are not equal modulo case conversion. */
-
- /* Copy the literal mnemonic out of the insn. */
- for (; *mnem; mnem++)
- {
- char c = *mnem;
-
- if (ISALPHA (c))
- {
- *rx++ = '[';
- *rx++ = TOLOWER (c);
- *rx++ = TOUPPER (c);
- *rx++ = ']';
- }
- else
- *rx++ = c;
- }
-
- /* Copy any remaining literals from the syntax string into the rx. */
- for(; * syn != 0 && rx <= rxbuf + (CGEN_MAX_RX_ELEMENTS - 7 - 4); ++syn)
- {
- if (CGEN_SYNTAX_CHAR_P (* syn))
- {
- char c = CGEN_SYNTAX_CHAR (* syn);
-
- switch (c)
- {
- /* Escape any regex metacharacters in the syntax. */
- case '.': case '[': case '\\':
- case '*': case '^': case '$':
-
-#ifdef CGEN_ESCAPE_EXTENDED_REGEX
- case '?': case '{': case '}':
- case '(': case ')': case '*':
- case '|': case '+': case ']':
-#endif
- *rx++ = '\\';
- *rx++ = c;
- break;
-
- default:
- if (ISALPHA (c))
- {
- *rx++ = '[';
- *rx++ = TOLOWER (c);
- *rx++ = TOUPPER (c);
- *rx++ = ']';
- }
- else
- *rx++ = c;
- break;
- }
- }
- else
- {
- /* Replace non-syntax fields with globs. */
- *rx++ = '.';
- *rx++ = '*';
- }
- }
-
- /* Trailing whitespace ok. */
- * rx++ = '[';
- * rx++ = ' ';
- * rx++ = '\t';
- * rx++ = ']';
- * rx++ = '*';
-
- /* But anchor it after that. */
- * rx++ = '$';
- * rx = '\0';
-
- CGEN_INSN_RX (insn) = xmalloc (sizeof (regex_t));
- reg_err = regcomp ((regex_t *) CGEN_INSN_RX (insn), rxbuf, REG_NOSUB);
-
- if (reg_err == 0)
- return NULL;
- else
- {
- static char msg[80];
-
- regerror (reg_err, (regex_t *) CGEN_INSN_RX (insn), msg, 80);
- regfree ((regex_t *) CGEN_INSN_RX (insn));
- free (CGEN_INSN_RX (insn));
- (CGEN_INSN_RX (insn)) = NULL;
- return msg;
- }
-}
-
-\f
-/* Default insn parser.
-
- The syntax string is scanned and operands are parsed and stored in FIELDS.
- Relocs are queued as we go via other callbacks.
-
- ??? Note that this is currently an all-or-nothing parser. If we fail to
- parse the instruction, we return 0 and the caller will start over from
- the beginning. Backtracking will be necessary in parsing subexpressions,
- but that can be handled there. Not handling backtracking here may get
- expensive in the case of the m68k. Deal with later.
-
- Returns NULL for success, an error message for failure. */
-
-static const char *
-parse_insn_normal (CGEN_CPU_DESC cd,
- const CGEN_INSN *insn,
- const char **strp,
- CGEN_FIELDS *fields)
-{
- /* ??? Runtime added insns not handled yet. */
- const CGEN_SYNTAX *syntax = CGEN_INSN_SYNTAX (insn);
- const char *str = *strp;
- const char *errmsg;
- const char *p;
- const CGEN_SYNTAX_CHAR_TYPE * syn;
-#ifdef CGEN_MNEMONIC_OPERANDS
- /* FIXME: wip */
- int past_opcode_p;
-#endif
-
- /* For now we assume the mnemonic is first (there are no leading operands).
- We can parse it without needing to set up operand parsing.
- GAS's input scrubber will ensure mnemonics are lowercase, but we may
- not be called from GAS. */
- p = CGEN_INSN_MNEMONIC (insn);
- while (*p && TOLOWER (*p) == TOLOWER (*str))
- ++p, ++str;
-
- if (* p)
- return _("unrecognized instruction");
-
-#ifndef CGEN_MNEMONIC_OPERANDS
- if (* str && ! ISSPACE (* str))
- return _("unrecognized instruction");
-#endif
-
- CGEN_INIT_PARSE (cd);
- cgen_init_parse_operand (cd);
-#ifdef CGEN_MNEMONIC_OPERANDS
- past_opcode_p = 0;
-#endif
-
- /* We don't check for (*str != '\0') here because we want to parse
- any trailing fake arguments in the syntax string. */
- syn = CGEN_SYNTAX_STRING (syntax);
-
- /* Mnemonics come first for now, ensure valid string. */
- if (! CGEN_SYNTAX_MNEMONIC_P (* syn))
- abort ();
-
- ++syn;
-
- while (* syn != 0)
- {
- /* Non operand chars must match exactly. */
- if (CGEN_SYNTAX_CHAR_P (* syn))
- {
- /* FIXME: While we allow for non-GAS callers above, we assume the
- first char after the mnemonic part is a space. */
- /* FIXME: We also take inappropriate advantage of the fact that
- GAS's input scrubber will remove extraneous blanks. */
- if (TOLOWER (*str) == TOLOWER (CGEN_SYNTAX_CHAR (* syn)))
- {
-#ifdef CGEN_MNEMONIC_OPERANDS
- if (CGEN_SYNTAX_CHAR(* syn) == ' ')
- past_opcode_p = 1;
-#endif
- ++ syn;
- ++ str;
- }
- else if (*str)
- {
- /* Syntax char didn't match. Can't be this insn. */
- static char msg [80];
-
- /* xgettext:c-format */
- sprintf (msg, _("syntax error (expected char `%c', found `%c')"),
- CGEN_SYNTAX_CHAR(*syn), *str);
- return msg;
- }
- else
- {
- /* Ran out of input. */
- static char msg [80];
-
- /* xgettext:c-format */
- sprintf (msg, _("syntax error (expected char `%c', found end of instruction)"),
- CGEN_SYNTAX_CHAR(*syn));
- return msg;
- }
- continue;
- }
-
-#ifdef CGEN_MNEMONIC_OPERANDS
- (void) past_opcode_p;
-#endif
- /* We have an operand of some sort. */
- errmsg = cd->parse_operand (cd, CGEN_SYNTAX_FIELD (*syn), &str, fields);
- if (errmsg)
- return errmsg;
-
- /* Done with this operand, continue with next one. */
- ++ syn;
- }
-
- /* If we're at the end of the syntax string, we're done. */
- if (* syn == 0)
- {
- /* FIXME: For the moment we assume a valid `str' can only contain
- blanks now. IE: We needn't try again with a longer version of
- the insn and it is assumed that longer versions of insns appear
- before shorter ones (eg: lsr r2,r3,1 vs lsr r2,r3). */
- while (ISSPACE (* str))
- ++ str;
-
- if (* str != '\0')
- return _("junk at end of line"); /* FIXME: would like to include `str' */
-
- return NULL;
- }
-
- /* We couldn't parse it. */
- return _("unrecognized instruction");
-}
-\f
-/* Main entry point.
- This routine is called for each instruction to be assembled.
- STR points to the insn to be assembled.
- We assume all necessary tables have been initialized.
- The assembled instruction, less any fixups, is stored in BUF.
- Remember that if CGEN_INT_INSN_P then BUF is an int and thus the value
- still needs to be converted to target byte order, otherwise BUF is an array
- of bytes in target byte order.
- The result is a pointer to the insn's entry in the opcode table,
- or NULL if an error occured (an error message will have already been
- printed).
-
- Note that when processing (non-alias) macro-insns,
- this function recurses.
-
- ??? It's possible to make this cpu-independent.
- One would have to deal with a few minor things.
- At this point in time doing so would be more of a curiosity than useful
- [for example this file isn't _that_ big], but keeping the possibility in
- mind helps keep the design clean. */
-
-const CGEN_INSN *
-xc16x_cgen_assemble_insn (CGEN_CPU_DESC cd,
- const char *str,
- CGEN_FIELDS *fields,
- CGEN_INSN_BYTES_PTR buf,
- char **errmsg)
-{
- const char *start;
- CGEN_INSN_LIST *ilist;
- const char *parse_errmsg = NULL;
- const char *insert_errmsg = NULL;
- int recognized_mnemonic = 0;
-
- /* Skip leading white space. */
- while (ISSPACE (* str))
- ++ str;
-
- /* The instructions are stored in hashed lists.
- Get the first in the list. */
- ilist = CGEN_ASM_LOOKUP_INSN (cd, str);
-
- /* Keep looking until we find a match. */
- start = str;
- for ( ; ilist != NULL ; ilist = CGEN_ASM_NEXT_INSN (ilist))
- {
- const CGEN_INSN *insn = ilist->insn;
- recognized_mnemonic = 1;
-
-#ifdef CGEN_VALIDATE_INSN_SUPPORTED
- /* Not usually needed as unsupported opcodes
- shouldn't be in the hash lists. */
- /* Is this insn supported by the selected cpu? */
- if (! xc16x_cgen_insn_supported (cd, insn))
- continue;
-#endif
- /* If the RELAXED attribute is set, this is an insn that shouldn't be
- chosen immediately. Instead, it is used during assembler/linker
- relaxation if possible. */
- if (CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_RELAXED) != 0)
- continue;
-
- str = start;
-
- /* Skip this insn if str doesn't look right lexically. */
- if (CGEN_INSN_RX (insn) != NULL &&
- regexec ((regex_t *) CGEN_INSN_RX (insn), str, 0, NULL, 0) == REG_NOMATCH)
- continue;
-
- /* Allow parse/insert handlers to obtain length of insn. */
- CGEN_FIELDS_BITSIZE (fields) = CGEN_INSN_BITSIZE (insn);
-
- parse_errmsg = CGEN_PARSE_FN (cd, insn) (cd, insn, & str, fields);
- if (parse_errmsg != NULL)
- continue;
-
- /* ??? 0 is passed for `pc'. */
- insert_errmsg = CGEN_INSERT_FN (cd, insn) (cd, insn, fields, buf,
- (bfd_vma) 0);
- if (insert_errmsg != NULL)
- continue;
-
- /* It is up to the caller to actually output the insn and any
- queued relocs. */
- return insn;
- }
-
- {
- static char errbuf[150];
- const char *tmp_errmsg;
-#ifdef CGEN_VERBOSE_ASSEMBLER_ERRORS
-#define be_verbose 1
-#else
-#define be_verbose 0
-#endif
-
- if (be_verbose)
- {
- /* If requesting verbose error messages, use insert_errmsg.
- Failing that, use parse_errmsg. */
- tmp_errmsg = (insert_errmsg ? insert_errmsg :
- parse_errmsg ? parse_errmsg :
- recognized_mnemonic ?
- _("unrecognized form of instruction") :
- _("unrecognized instruction"));
-
- if (strlen (start) > 50)
- /* xgettext:c-format */
- sprintf (errbuf, "%s `%.50s...'", tmp_errmsg, start);
- else
- /* xgettext:c-format */
- sprintf (errbuf, "%s `%.50s'", tmp_errmsg, start);
- }
- else
- {
- if (strlen (start) > 50)
- /* xgettext:c-format */
- sprintf (errbuf, _("bad instruction `%.50s...'"), start);
- else
- /* xgettext:c-format */
- sprintf (errbuf, _("bad instruction `%.50s'"), start);
- }
-
- *errmsg = errbuf;
- return NULL;
- }
-}
+++ /dev/null
-/* DO NOT EDIT! -*- buffer-read-only: t -*- vi:set ro: */
-/* CPU data for xc16x.
-
-THIS FILE IS MACHINE GENERATED WITH CGEN.
-
-Copyright (C) 1996-2022 Free Software Foundation, Inc.
-
-This file is part of the GNU Binutils and/or GDB, the GNU debugger.
-
- This file is free software; you can redistribute it and/or modify
- it under the terms of the GNU General Public License as published by
- the Free Software Foundation; either version 3, or (at your option)
- any later version.
-
- It is distributed in the hope that it will be useful, but WITHOUT
- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
- License for more details.
-
- You should have received a copy of the GNU General Public License along
- with this program; if not, write to the Free Software Foundation, Inc.,
- 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.
-
-*/
-
-#include "sysdep.h"
-#include <stdio.h>
-#include <stdarg.h>
-#include <stdlib.h>
-#include "ansidecl.h"
-#include "bfd.h"
-#include "symcat.h"
-#include "xc16x-desc.h"
-#include "xc16x-opc.h"
-#include "opintl.h"
-#include "libiberty.h"
-#include "xregex.h"
-
-/* Attributes. */
-
-static const CGEN_ATTR_ENTRY bool_attr[] =
-{
- { "#f", 0 },
- { "#t", 1 },
- { 0, 0 }
-};
-
-static const CGEN_ATTR_ENTRY MACH_attr[] ATTRIBUTE_UNUSED =
-{
- { "base", MACH_BASE },
- { "xc16x", MACH_XC16X },
- { "max", MACH_MAX },
- { 0, 0 }
-};
-
-static const CGEN_ATTR_ENTRY ISA_attr[] ATTRIBUTE_UNUSED =
-{
- { "xc16x", ISA_XC16X },
- { "max", ISA_MAX },
- { 0, 0 }
-};
-
-static const CGEN_ATTR_ENTRY PIPE_attr[] ATTRIBUTE_UNUSED =
-{
- { "NONE", PIPE_NONE },
- { "OS", PIPE_OS },
- { 0, 0 }
-};
-
-const CGEN_ATTR_TABLE xc16x_cgen_ifield_attr_table[] =
-{
- { "MACH", & MACH_attr[0], & MACH_attr[0] },
- { "VIRTUAL", &bool_attr[0], &bool_attr[0] },
- { "PCREL-ADDR", &bool_attr[0], &bool_attr[0] },
- { "ABS-ADDR", &bool_attr[0], &bool_attr[0] },
- { "RESERVED", &bool_attr[0], &bool_attr[0] },
- { "SIGN-OPT", &bool_attr[0], &bool_attr[0] },
- { "SIGNED", &bool_attr[0], &bool_attr[0] },
- { "RELOC", &bool_attr[0], &bool_attr[0] },
- { 0, 0, 0 }
-};
-
-const CGEN_ATTR_TABLE xc16x_cgen_hardware_attr_table[] =
-{
- { "MACH", & MACH_attr[0], & MACH_attr[0] },
- { "VIRTUAL", &bool_attr[0], &bool_attr[0] },
- { "CACHE-ADDR", &bool_attr[0], &bool_attr[0] },
- { "PC", &bool_attr[0], &bool_attr[0] },
- { "PROFILE", &bool_attr[0], &bool_attr[0] },
- { 0, 0, 0 }
-};
-
-const CGEN_ATTR_TABLE xc16x_cgen_operand_attr_table[] =
-{
- { "MACH", & MACH_attr[0], & MACH_attr[0] },
- { "VIRTUAL", &bool_attr[0], &bool_attr[0] },
- { "PCREL-ADDR", &bool_attr[0], &bool_attr[0] },
- { "ABS-ADDR", &bool_attr[0], &bool_attr[0] },
- { "SIGN-OPT", &bool_attr[0], &bool_attr[0] },
- { "SIGNED", &bool_attr[0], &bool_attr[0] },
- { "NEGATIVE", &bool_attr[0], &bool_attr[0] },
- { "RELAX", &bool_attr[0], &bool_attr[0] },
- { "SEM-ONLY", &bool_attr[0], &bool_attr[0] },
- { "RELOC", &bool_attr[0], &bool_attr[0] },
- { "HASH-PREFIX", &bool_attr[0], &bool_attr[0] },
- { "DOT-PREFIX", &bool_attr[0], &bool_attr[0] },
- { "POF-PREFIX", &bool_attr[0], &bool_attr[0] },
- { "PAG-PREFIX", &bool_attr[0], &bool_attr[0] },
- { "SOF-PREFIX", &bool_attr[0], &bool_attr[0] },
- { "SEG-PREFIX", &bool_attr[0], &bool_attr[0] },
- { 0, 0, 0 }
-};
-
-const CGEN_ATTR_TABLE xc16x_cgen_insn_attr_table[] =
-{
- { "MACH", & MACH_attr[0], & MACH_attr[0] },
- { "PIPE", & PIPE_attr[0], & PIPE_attr[0] },
- { "ALIAS", &bool_attr[0], &bool_attr[0] },
- { "VIRTUAL", &bool_attr[0], &bool_attr[0] },
- { "UNCOND-CTI", &bool_attr[0], &bool_attr[0] },
- { "COND-CTI", &bool_attr[0], &bool_attr[0] },
- { "SKIP-CTI", &bool_attr[0], &bool_attr[0] },
- { "DELAY-SLOT", &bool_attr[0], &bool_attr[0] },
- { "RELAXABLE", &bool_attr[0], &bool_attr[0] },
- { "RELAXED", &bool_attr[0], &bool_attr[0] },
- { "NO-DIS", &bool_attr[0], &bool_attr[0] },
- { "PBB", &bool_attr[0], &bool_attr[0] },
- { 0, 0, 0 }
-};
-
-/* Instruction set variants. */
-
-static const CGEN_ISA xc16x_cgen_isa_table[] = {
- { "xc16x", 16, 32, 16, 32 },
- { 0, 0, 0, 0, 0 }
-};
-
-/* Machine variants. */
-
-static const CGEN_MACH xc16x_cgen_mach_table[] = {
- { "xc16x", "xc16x", MACH_XC16X, 32 },
- { 0, 0, 0, 0 }
-};
-
-static CGEN_KEYWORD_ENTRY xc16x_cgen_opval_gr_names_entries[] =
-{
- { "r0", 0, {0, {{{0, 0}}}}, 0, 0 },
- { "r1", 1, {0, {{{0, 0}}}}, 0, 0 },
- { "r2", 2, {0, {{{0, 0}}}}, 0, 0 },
- { "r3", 3, {0, {{{0, 0}}}}, 0, 0 },
- { "r4", 4, {0, {{{0, 0}}}}, 0, 0 },
- { "r5", 5, {0, {{{0, 0}}}}, 0, 0 },
- { "r6", 6, {0, {{{0, 0}}}}, 0, 0 },
- { "r7", 7, {0, {{{0, 0}}}}, 0, 0 },
- { "r8", 8, {0, {{{0, 0}}}}, 0, 0 },
- { "r9", 9, {0, {{{0, 0}}}}, 0, 0 },
- { "r10", 10, {0, {{{0, 0}}}}, 0, 0 },
- { "r11", 11, {0, {{{0, 0}}}}, 0, 0 },
- { "r12", 12, {0, {{{0, 0}}}}, 0, 0 },
- { "r13", 13, {0, {{{0, 0}}}}, 0, 0 },
- { "r14", 14, {0, {{{0, 0}}}}, 0, 0 },
- { "r15", 15, {0, {{{0, 0}}}}, 0, 0 }
-};
-
-CGEN_KEYWORD xc16x_cgen_opval_gr_names =
-{
- & xc16x_cgen_opval_gr_names_entries[0],
- 16,
- 0, 0, 0, 0, ""
-};
-
-static CGEN_KEYWORD_ENTRY xc16x_cgen_opval_ext_names_entries[] =
-{
- { "0x1", 0, {0, {{{0, 0}}}}, 0, 0 },
- { "0x2", 1, {0, {{{0, 0}}}}, 0, 0 },
- { "0x3", 2, {0, {{{0, 0}}}}, 0, 0 },
- { "0x4", 3, {0, {{{0, 0}}}}, 0, 0 },
- { "1", 0, {0, {{{0, 0}}}}, 0, 0 },
- { "2", 1, {0, {{{0, 0}}}}, 0, 0 },
- { "3", 2, {0, {{{0, 0}}}}, 0, 0 },
- { "4", 3, {0, {{{0, 0}}}}, 0, 0 }
-};
-
-CGEN_KEYWORD xc16x_cgen_opval_ext_names =
-{
- & xc16x_cgen_opval_ext_names_entries[0],
- 8,
- 0, 0, 0, 0, ""
-};
-
-static CGEN_KEYWORD_ENTRY xc16x_cgen_opval_psw_names_entries[] =
-{
- { "IEN", 136, {0, {{{0, 0}}}}, 0, 0 },
- { "r0.11", 240, {0, {{{0, 0}}}}, 0, 0 },
- { "r1.11", 241, {0, {{{0, 0}}}}, 0, 0 },
- { "r2.11", 242, {0, {{{0, 0}}}}, 0, 0 },
- { "r3.11", 243, {0, {{{0, 0}}}}, 0, 0 },
- { "r4.11", 244, {0, {{{0, 0}}}}, 0, 0 },
- { "r5.11", 245, {0, {{{0, 0}}}}, 0, 0 },
- { "r6.11", 246, {0, {{{0, 0}}}}, 0, 0 },
- { "r7.11", 247, {0, {{{0, 0}}}}, 0, 0 },
- { "r8.11", 248, {0, {{{0, 0}}}}, 0, 0 },
- { "r9.11", 249, {0, {{{0, 0}}}}, 0, 0 },
- { "r10.11", 250, {0, {{{0, 0}}}}, 0, 0 },
- { "r11.11", 251, {0, {{{0, 0}}}}, 0, 0 },
- { "r12.11", 252, {0, {{{0, 0}}}}, 0, 0 },
- { "r13.11", 253, {0, {{{0, 0}}}}, 0, 0 },
- { "r14.11", 254, {0, {{{0, 0}}}}, 0, 0 },
- { "r15.11", 255, {0, {{{0, 0}}}}, 0, 0 }
-};
-
-CGEN_KEYWORD xc16x_cgen_opval_psw_names =
-{
- & xc16x_cgen_opval_psw_names_entries[0],
- 17,
- 0, 0, 0, 0, ""
-};
-
-static CGEN_KEYWORD_ENTRY xc16x_cgen_opval_grb_names_entries[] =
-{
- { "rl0", 0, {0, {{{0, 0}}}}, 0, 0 },
- { "rh0", 1, {0, {{{0, 0}}}}, 0, 0 },
- { "rl1", 2, {0, {{{0, 0}}}}, 0, 0 },
- { "rh1", 3, {0, {{{0, 0}}}}, 0, 0 },
- { "rl2", 4, {0, {{{0, 0}}}}, 0, 0 },
- { "rh2", 5, {0, {{{0, 0}}}}, 0, 0 },
- { "rl3", 6, {0, {{{0, 0}}}}, 0, 0 },
- { "rh3", 7, {0, {{{0, 0}}}}, 0, 0 },
- { "rl4", 8, {0, {{{0, 0}}}}, 0, 0 },
- { "rh4", 9, {0, {{{0, 0}}}}, 0, 0 },
- { "rl5", 10, {0, {{{0, 0}}}}, 0, 0 },
- { "rh5", 11, {0, {{{0, 0}}}}, 0, 0 },
- { "rl6", 12, {0, {{{0, 0}}}}, 0, 0 },
- { "rh6", 13, {0, {{{0, 0}}}}, 0, 0 },
- { "rl7", 14, {0, {{{0, 0}}}}, 0, 0 },
- { "rh7", 15, {0, {{{0, 0}}}}, 0, 0 }
-};
-
-CGEN_KEYWORD xc16x_cgen_opval_grb_names =
-{
- & xc16x_cgen_opval_grb_names_entries[0],
- 16,
- 0, 0, 0, 0, ""
-};
-
-static CGEN_KEYWORD_ENTRY xc16x_cgen_opval_conditioncode_names_entries[] =
-{
- { "cc_UC", 0, {0, {{{0, 0}}}}, 0, 0 },
- { "cc_NET", 1, {0, {{{0, 0}}}}, 0, 0 },
- { "cc_Z", 2, {0, {{{0, 0}}}}, 0, 0 },
- { "cc_EQ", 2, {0, {{{0, 0}}}}, 0, 0 },
- { "cc_NZ", 3, {0, {{{0, 0}}}}, 0, 0 },
- { "cc_NE", 3, {0, {{{0, 0}}}}, 0, 0 },
- { "cc_V", 4, {0, {{{0, 0}}}}, 0, 0 },
- { "cc_NV", 5, {0, {{{0, 0}}}}, 0, 0 },
- { "cc_N", 6, {0, {{{0, 0}}}}, 0, 0 },
- { "cc_NN", 7, {0, {{{0, 0}}}}, 0, 0 },
- { "cc_ULT", 8, {0, {{{0, 0}}}}, 0, 0 },
- { "cc_UGE", 9, {0, {{{0, 0}}}}, 0, 0 },
- { "cc_C", 8, {0, {{{0, 0}}}}, 0, 0 },
- { "cc_NC", 9, {0, {{{0, 0}}}}, 0, 0 },
- { "cc_SGT", 10, {0, {{{0, 0}}}}, 0, 0 },
- { "cc_SLE", 11, {0, {{{0, 0}}}}, 0, 0 },
- { "cc_SLT", 12, {0, {{{0, 0}}}}, 0, 0 },
- { "cc_SGE", 13, {0, {{{0, 0}}}}, 0, 0 },
- { "cc_UGT", 14, {0, {{{0, 0}}}}, 0, 0 },
- { "cc_ULE", 15, {0, {{{0, 0}}}}, 0, 0 }
-};
-
-CGEN_KEYWORD xc16x_cgen_opval_conditioncode_names =
-{
- & xc16x_cgen_opval_conditioncode_names_entries[0],
- 20,
- 0, 0, 0, 0, ""
-};
-
-static CGEN_KEYWORD_ENTRY xc16x_cgen_opval_extconditioncode_names_entries[] =
-{
- { "cc_UC", 0, {0, {{{0, 0}}}}, 0, 0 },
- { "cc_NET", 2, {0, {{{0, 0}}}}, 0, 0 },
- { "cc_Z", 4, {0, {{{0, 0}}}}, 0, 0 },
- { "cc_EQ", 4, {0, {{{0, 0}}}}, 0, 0 },
- { "cc_NZ", 6, {0, {{{0, 0}}}}, 0, 0 },
- { "cc_NE", 6, {0, {{{0, 0}}}}, 0, 0 },
- { "cc_V", 8, {0, {{{0, 0}}}}, 0, 0 },
- { "cc_NV", 10, {0, {{{0, 0}}}}, 0, 0 },
- { "cc_N", 12, {0, {{{0, 0}}}}, 0, 0 },
- { "cc_NN", 14, {0, {{{0, 0}}}}, 0, 0 },
- { "cc_ULT", 16, {0, {{{0, 0}}}}, 0, 0 },
- { "cc_UGE", 18, {0, {{{0, 0}}}}, 0, 0 },
- { "cc_C", 16, {0, {{{0, 0}}}}, 0, 0 },
- { "cc_NC", 18, {0, {{{0, 0}}}}, 0, 0 },
- { "cc_SGT", 20, {0, {{{0, 0}}}}, 0, 0 },
- { "cc_SLE", 22, {0, {{{0, 0}}}}, 0, 0 },
- { "cc_SLT", 24, {0, {{{0, 0}}}}, 0, 0 },
- { "cc_SGE", 26, {0, {{{0, 0}}}}, 0, 0 },
- { "cc_UGT", 28, {0, {{{0, 0}}}}, 0, 0 },
- { "cc_ULE", 30, {0, {{{0, 0}}}}, 0, 0 },
- { "cc_nusr0", 1, {0, {{{0, 0}}}}, 0, 0 },
- { "cc_nusr1", 3, {0, {{{0, 0}}}}, 0, 0 },
- { "cc_usr0", 5, {0, {{{0, 0}}}}, 0, 0 },
- { "cc_usr1", 7, {0, {{{0, 0}}}}, 0, 0 }
-};
-
-CGEN_KEYWORD xc16x_cgen_opval_extconditioncode_names =
-{
- & xc16x_cgen_opval_extconditioncode_names_entries[0],
- 24,
- 0, 0, 0, 0, ""
-};
-
-static CGEN_KEYWORD_ENTRY xc16x_cgen_opval_grb8_names_entries[] =
-{
- { "dpp0", 0, {0, {{{0, 0}}}}, 0, 0 },
- { "dpp1", 1, {0, {{{0, 0}}}}, 0, 0 },
- { "dpp2", 2, {0, {{{0, 0}}}}, 0, 0 },
- { "dpp3", 3, {0, {{{0, 0}}}}, 0, 0 },
- { "psw", 136, {0, {{{0, 0}}}}, 0, 0 },
- { "cp", 8, {0, {{{0, 0}}}}, 0, 0 },
- { "mdl", 7, {0, {{{0, 0}}}}, 0, 0 },
- { "mdh", 6, {0, {{{0, 0}}}}, 0, 0 },
- { "mdc", 135, {0, {{{0, 0}}}}, 0, 0 },
- { "sp", 9, {0, {{{0, 0}}}}, 0, 0 },
- { "csp", 4, {0, {{{0, 0}}}}, 0, 0 },
- { "vecseg", 137, {0, {{{0, 0}}}}, 0, 0 },
- { "stkov", 10, {0, {{{0, 0}}}}, 0, 0 },
- { "stkun", 11, {0, {{{0, 0}}}}, 0, 0 },
- { "cpucon1", 12, {0, {{{0, 0}}}}, 0, 0 },
- { "cpucon2", 13, {0, {{{0, 0}}}}, 0, 0 },
- { "zeros", 142, {0, {{{0, 0}}}}, 0, 0 },
- { "ones", 143, {0, {{{0, 0}}}}, 0, 0 },
- { "spseg", 134, {0, {{{0, 0}}}}, 0, 0 },
- { "tfr", 214, {0, {{{0, 0}}}}, 0, 0 },
- { "rl0", 240, {0, {{{0, 0}}}}, 0, 0 },
- { "rh0", 241, {0, {{{0, 0}}}}, 0, 0 },
- { "rl1", 242, {0, {{{0, 0}}}}, 0, 0 },
- { "rh1", 243, {0, {{{0, 0}}}}, 0, 0 },
- { "rl2", 244, {0, {{{0, 0}}}}, 0, 0 },
- { "rh2", 245, {0, {{{0, 0}}}}, 0, 0 },
- { "rl3", 246, {0, {{{0, 0}}}}, 0, 0 },
- { "rh3", 247, {0, {{{0, 0}}}}, 0, 0 },
- { "rl4", 248, {0, {{{0, 0}}}}, 0, 0 },
- { "rh4", 249, {0, {{{0, 0}}}}, 0, 0 },
- { "rl5", 250, {0, {{{0, 0}}}}, 0, 0 },
- { "rh5", 251, {0, {{{0, 0}}}}, 0, 0 },
- { "rl6", 252, {0, {{{0, 0}}}}, 0, 0 },
- { "rh6", 253, {0, {{{0, 0}}}}, 0, 0 },
- { "rl7", 254, {0, {{{0, 0}}}}, 0, 0 },
- { "rh7", 255, {0, {{{0, 0}}}}, 0, 0 }
-};
-
-CGEN_KEYWORD xc16x_cgen_opval_grb8_names =
-{
- & xc16x_cgen_opval_grb8_names_entries[0],
- 36,
- 0, 0, 0, 0, ""
-};
-
-static CGEN_KEYWORD_ENTRY xc16x_cgen_opval_r8_names_entries[] =
-{
- { "dpp0", 0, {0, {{{0, 0}}}}, 0, 0 },
- { "dpp1", 1, {0, {{{0, 0}}}}, 0, 0 },
- { "dpp2", 2, {0, {{{0, 0}}}}, 0, 0 },
- { "dpp3", 3, {0, {{{0, 0}}}}, 0, 0 },
- { "psw", 136, {0, {{{0, 0}}}}, 0, 0 },
- { "cp", 8, {0, {{{0, 0}}}}, 0, 0 },
- { "mdl", 7, {0, {{{0, 0}}}}, 0, 0 },
- { "mdh", 6, {0, {{{0, 0}}}}, 0, 0 },
- { "mdc", 135, {0, {{{0, 0}}}}, 0, 0 },
- { "sp", 9, {0, {{{0, 0}}}}, 0, 0 },
- { "csp", 4, {0, {{{0, 0}}}}, 0, 0 },
- { "vecseg", 137, {0, {{{0, 0}}}}, 0, 0 },
- { "stkov", 10, {0, {{{0, 0}}}}, 0, 0 },
- { "stkun", 11, {0, {{{0, 0}}}}, 0, 0 },
- { "cpucon1", 12, {0, {{{0, 0}}}}, 0, 0 },
- { "cpucon2", 13, {0, {{{0, 0}}}}, 0, 0 },
- { "zeros", 142, {0, {{{0, 0}}}}, 0, 0 },
- { "ones", 143, {0, {{{0, 0}}}}, 0, 0 },
- { "spseg", 134, {0, {{{0, 0}}}}, 0, 0 },
- { "tfr", 214, {0, {{{0, 0}}}}, 0, 0 },
- { "r0", 240, {0, {{{0, 0}}}}, 0, 0 },
- { "r1", 241, {0, {{{0, 0}}}}, 0, 0 },
- { "r2", 242, {0, {{{0, 0}}}}, 0, 0 },
- { "r3", 243, {0, {{{0, 0}}}}, 0, 0 },
- { "r4", 244, {0, {{{0, 0}}}}, 0, 0 },
- { "r5", 245, {0, {{{0, 0}}}}, 0, 0 },
- { "r6", 246, {0, {{{0, 0}}}}, 0, 0 },
- { "r7", 247, {0, {{{0, 0}}}}, 0, 0 },
- { "r8", 248, {0, {{{0, 0}}}}, 0, 0 },
- { "r9", 249, {0, {{{0, 0}}}}, 0, 0 },
- { "r10", 250, {0, {{{0, 0}}}}, 0, 0 },
- { "r11", 251, {0, {{{0, 0}}}}, 0, 0 },
- { "r12", 252, {0, {{{0, 0}}}}, 0, 0 },
- { "r13", 253, {0, {{{0, 0}}}}, 0, 0 },
- { "r14", 254, {0, {{{0, 0}}}}, 0, 0 },
- { "r15", 255, {0, {{{0, 0}}}}, 0, 0 }
-};
-
-CGEN_KEYWORD xc16x_cgen_opval_r8_names =
-{
- & xc16x_cgen_opval_r8_names_entries[0],
- 36,
- 0, 0, 0, 0, ""
-};
-
-static CGEN_KEYWORD_ENTRY xc16x_cgen_opval_regmem8_names_entries[] =
-{
- { "dpp0", 0, {0, {{{0, 0}}}}, 0, 0 },
- { "dpp1", 1, {0, {{{0, 0}}}}, 0, 0 },
- { "dpp2", 2, {0, {{{0, 0}}}}, 0, 0 },
- { "dpp3", 3, {0, {{{0, 0}}}}, 0, 0 },
- { "psw", 136, {0, {{{0, 0}}}}, 0, 0 },
- { "cp", 8, {0, {{{0, 0}}}}, 0, 0 },
- { "mdl", 7, {0, {{{0, 0}}}}, 0, 0 },
- { "mdh", 6, {0, {{{0, 0}}}}, 0, 0 },
- { "mdc", 135, {0, {{{0, 0}}}}, 0, 0 },
- { "sp", 9, {0, {{{0, 0}}}}, 0, 0 },
- { "csp", 4, {0, {{{0, 0}}}}, 0, 0 },
- { "vecseg", 137, {0, {{{0, 0}}}}, 0, 0 },
- { "stkov", 10, {0, {{{0, 0}}}}, 0, 0 },
- { "stkun", 11, {0, {{{0, 0}}}}, 0, 0 },
- { "cpucon1", 12, {0, {{{0, 0}}}}, 0, 0 },
- { "cpucon2", 13, {0, {{{0, 0}}}}, 0, 0 },
- { "zeros", 142, {0, {{{0, 0}}}}, 0, 0 },
- { "ones", 143, {0, {{{0, 0}}}}, 0, 0 },
- { "spseg", 134, {0, {{{0, 0}}}}, 0, 0 },
- { "tfr", 214, {0, {{{0, 0}}}}, 0, 0 },
- { "r0", 240, {0, {{{0, 0}}}}, 0, 0 },
- { "r1", 241, {0, {{{0, 0}}}}, 0, 0 },
- { "r2", 242, {0, {{{0, 0}}}}, 0, 0 },
- { "r3", 243, {0, {{{0, 0}}}}, 0, 0 },
- { "r4", 244, {0, {{{0, 0}}}}, 0, 0 },
- { "r5", 245, {0, {{{0, 0}}}}, 0, 0 },
- { "r6", 246, {0, {{{0, 0}}}}, 0, 0 },
- { "r7", 247, {0, {{{0, 0}}}}, 0, 0 },
- { "r8", 248, {0, {{{0, 0}}}}, 0, 0 },
- { "r9", 249, {0, {{{0, 0}}}}, 0, 0 },
- { "r10", 250, {0, {{{0, 0}}}}, 0, 0 },
- { "r11", 251, {0, {{{0, 0}}}}, 0, 0 },
- { "r12", 252, {0, {{{0, 0}}}}, 0, 0 },
- { "r13", 253, {0, {{{0, 0}}}}, 0, 0 },
- { "r14", 254, {0, {{{0, 0}}}}, 0, 0 },
- { "r15", 255, {0, {{{0, 0}}}}, 0, 0 }
-};
-
-CGEN_KEYWORD xc16x_cgen_opval_regmem8_names =
-{
- & xc16x_cgen_opval_regmem8_names_entries[0],
- 36,
- 0, 0, 0, 0, ""
-};
-
-static CGEN_KEYWORD_ENTRY xc16x_cgen_opval_regdiv8_names_entries[] =
-{
- { "r0", 0, {0, {{{0, 0}}}}, 0, 0 },
- { "r1", 17, {0, {{{0, 0}}}}, 0, 0 },
- { "r2", 34, {0, {{{0, 0}}}}, 0, 0 },
- { "r3", 51, {0, {{{0, 0}}}}, 0, 0 },
- { "r4", 68, {0, {{{0, 0}}}}, 0, 0 },
- { "r5", 85, {0, {{{0, 0}}}}, 0, 0 },
- { "r6", 102, {0, {{{0, 0}}}}, 0, 0 },
- { "r7", 119, {0, {{{0, 0}}}}, 0, 0 },
- { "r8", 136, {0, {{{0, 0}}}}, 0, 0 },
- { "r9", 153, {0, {{{0, 0}}}}, 0, 0 },
- { "r10", 170, {0, {{{0, 0}}}}, 0, 0 },
- { "r11", 187, {0, {{{0, 0}}}}, 0, 0 },
- { "r12", 204, {0, {{{0, 0}}}}, 0, 0 },
- { "r13", 221, {0, {{{0, 0}}}}, 0, 0 },
- { "r14", 238, {0, {{{0, 0}}}}, 0, 0 },
- { "r15", 255, {0, {{{0, 0}}}}, 0, 0 }
-};
-
-CGEN_KEYWORD xc16x_cgen_opval_regdiv8_names =
-{
- & xc16x_cgen_opval_regdiv8_names_entries[0],
- 16,
- 0, 0, 0, 0, ""
-};
-
-static CGEN_KEYWORD_ENTRY xc16x_cgen_opval_reg0_name_entries[] =
-{
- { "0x1", 1, {0, {{{0, 0}}}}, 0, 0 },
- { "0x2", 2, {0, {{{0, 0}}}}, 0, 0 },
- { "0x3", 3, {0, {{{0, 0}}}}, 0, 0 },
- { "0x4", 4, {0, {{{0, 0}}}}, 0, 0 },
- { "0x5", 5, {0, {{{0, 0}}}}, 0, 0 },
- { "0x6", 6, {0, {{{0, 0}}}}, 0, 0 },
- { "0x7", 7, {0, {{{0, 0}}}}, 0, 0 },
- { "0x8", 8, {0, {{{0, 0}}}}, 0, 0 },
- { "0x9", 9, {0, {{{0, 0}}}}, 0, 0 },
- { "0xa", 10, {0, {{{0, 0}}}}, 0, 0 },
- { "0xb", 11, {0, {{{0, 0}}}}, 0, 0 },
- { "0xc", 12, {0, {{{0, 0}}}}, 0, 0 },
- { "0xd", 13, {0, {{{0, 0}}}}, 0, 0 },
- { "0xe", 14, {0, {{{0, 0}}}}, 0, 0 },
- { "0xf", 15, {0, {{{0, 0}}}}, 0, 0 },
- { "1", 1, {0, {{{0, 0}}}}, 0, 0 },
- { "2", 2, {0, {{{0, 0}}}}, 0, 0 },
- { "3", 3, {0, {{{0, 0}}}}, 0, 0 },
- { "4", 4, {0, {{{0, 0}}}}, 0, 0 },
- { "5", 5, {0, {{{0, 0}}}}, 0, 0 },
- { "6", 6, {0, {{{0, 0}}}}, 0, 0 },
- { "7", 7, {0, {{{0, 0}}}}, 0, 0 },
- { "8", 8, {0, {{{0, 0}}}}, 0, 0 },
- { "9", 9, {0, {{{0, 0}}}}, 0, 0 },
- { "10", 10, {0, {{{0, 0}}}}, 0, 0 },
- { "11", 11, {0, {{{0, 0}}}}, 0, 0 },
- { "12", 12, {0, {{{0, 0}}}}, 0, 0 },
- { "13", 13, {0, {{{0, 0}}}}, 0, 0 },
- { "14", 14, {0, {{{0, 0}}}}, 0, 0 },
- { "15", 15, {0, {{{0, 0}}}}, 0, 0 }
-};
-
-CGEN_KEYWORD xc16x_cgen_opval_reg0_name =
-{
- & xc16x_cgen_opval_reg0_name_entries[0],
- 30,
- 0, 0, 0, 0, ""
-};
-
-static CGEN_KEYWORD_ENTRY xc16x_cgen_opval_reg0_name1_entries[] =
-{
- { "0x1", 1, {0, {{{0, 0}}}}, 0, 0 },
- { "0x2", 2, {0, {{{0, 0}}}}, 0, 0 },
- { "0x3", 3, {0, {{{0, 0}}}}, 0, 0 },
- { "0x4", 4, {0, {{{0, 0}}}}, 0, 0 },
- { "0x5", 5, {0, {{{0, 0}}}}, 0, 0 },
- { "0x6", 6, {0, {{{0, 0}}}}, 0, 0 },
- { "0x7", 7, {0, {{{0, 0}}}}, 0, 0 },
- { "1", 1, {0, {{{0, 0}}}}, 0, 0 },
- { "2", 2, {0, {{{0, 0}}}}, 0, 0 },
- { "3", 3, {0, {{{0, 0}}}}, 0, 0 },
- { "4", 4, {0, {{{0, 0}}}}, 0, 0 },
- { "5", 5, {0, {{{0, 0}}}}, 0, 0 },
- { "6", 6, {0, {{{0, 0}}}}, 0, 0 },
- { "7", 7, {0, {{{0, 0}}}}, 0, 0 }
-};
-
-CGEN_KEYWORD xc16x_cgen_opval_reg0_name1 =
-{
- & xc16x_cgen_opval_reg0_name1_entries[0],
- 14,
- 0, 0, 0, 0, ""
-};
-
-static CGEN_KEYWORD_ENTRY xc16x_cgen_opval_regbmem8_names_entries[] =
-{
- { "dpp0", 0, {0, {{{0, 0}}}}, 0, 0 },
- { "dpp1", 1, {0, {{{0, 0}}}}, 0, 0 },
- { "dpp2", 2, {0, {{{0, 0}}}}, 0, 0 },
- { "dpp3", 3, {0, {{{0, 0}}}}, 0, 0 },
- { "psw", 136, {0, {{{0, 0}}}}, 0, 0 },
- { "cp", 8, {0, {{{0, 0}}}}, 0, 0 },
- { "mdl", 7, {0, {{{0, 0}}}}, 0, 0 },
- { "mdh", 6, {0, {{{0, 0}}}}, 0, 0 },
- { "mdc", 135, {0, {{{0, 0}}}}, 0, 0 },
- { "sp", 9, {0, {{{0, 0}}}}, 0, 0 },
- { "csp", 4, {0, {{{0, 0}}}}, 0, 0 },
- { "vecseg", 137, {0, {{{0, 0}}}}, 0, 0 },
- { "stkov", 10, {0, {{{0, 0}}}}, 0, 0 },
- { "stkun", 11, {0, {{{0, 0}}}}, 0, 0 },
- { "cpucon1", 12, {0, {{{0, 0}}}}, 0, 0 },
- { "cpucon2", 13, {0, {{{0, 0}}}}, 0, 0 },
- { "zeros", 142, {0, {{{0, 0}}}}, 0, 0 },
- { "ones", 143, {0, {{{0, 0}}}}, 0, 0 },
- { "spseg", 134, {0, {{{0, 0}}}}, 0, 0 },
- { "tfr", 214, {0, {{{0, 0}}}}, 0, 0 },
- { "rl0", 240, {0, {{{0, 0}}}}, 0, 0 },
- { "rh0", 241, {0, {{{0, 0}}}}, 0, 0 },
- { "rl1", 242, {0, {{{0, 0}}}}, 0, 0 },
- { "rh1", 243, {0, {{{0, 0}}}}, 0, 0 },
- { "rl2", 244, {0, {{{0, 0}}}}, 0, 0 },
- { "rh2", 245, {0, {{{0, 0}}}}, 0, 0 },
- { "rl3", 246, {0, {{{0, 0}}}}, 0, 0 },
- { "rh3", 247, {0, {{{0, 0}}}}, 0, 0 },
- { "rl4", 248, {0, {{{0, 0}}}}, 0, 0 },
- { "rh4", 249, {0, {{{0, 0}}}}, 0, 0 },
- { "rl5", 250, {0, {{{0, 0}}}}, 0, 0 },
- { "rh5", 251, {0, {{{0, 0}}}}, 0, 0 },
- { "rl6", 252, {0, {{{0, 0}}}}, 0, 0 },
- { "rh6", 253, {0, {{{0, 0}}}}, 0, 0 },
- { "rl7", 254, {0, {{{0, 0}}}}, 0, 0 },
- { "rh7", 255, {0, {{{0, 0}}}}, 0, 0 }
-};
-
-CGEN_KEYWORD xc16x_cgen_opval_regbmem8_names =
-{
- & xc16x_cgen_opval_regbmem8_names_entries[0],
- 36,
- 0, 0, 0, 0, ""
-};
-
-static CGEN_KEYWORD_ENTRY xc16x_cgen_opval_memgr8_names_entries[] =
-{
- { "dpp0", 65024, {0, {{{0, 0}}}}, 0, 0 },
- { "dpp1", 65026, {0, {{{0, 0}}}}, 0, 0 },
- { "dpp2", 65028, {0, {{{0, 0}}}}, 0, 0 },
- { "dpp3", 65030, {0, {{{0, 0}}}}, 0, 0 },
- { "psw", 65296, {0, {{{0, 0}}}}, 0, 0 },
- { "cp", 65040, {0, {{{0, 0}}}}, 0, 0 },
- { "mdl", 65038, {0, {{{0, 0}}}}, 0, 0 },
- { "mdh", 65036, {0, {{{0, 0}}}}, 0, 0 },
- { "mdc", 65294, {0, {{{0, 0}}}}, 0, 0 },
- { "sp", 65042, {0, {{{0, 0}}}}, 0, 0 },
- { "csp", 65032, {0, {{{0, 0}}}}, 0, 0 },
- { "vecseg", 65298, {0, {{{0, 0}}}}, 0, 0 },
- { "stkov", 65044, {0, {{{0, 0}}}}, 0, 0 },
- { "stkun", 65046, {0, {{{0, 0}}}}, 0, 0 },
- { "cpucon1", 65048, {0, {{{0, 0}}}}, 0, 0 },
- { "cpucon2", 65050, {0, {{{0, 0}}}}, 0, 0 },
- { "zeros", 65308, {0, {{{0, 0}}}}, 0, 0 },
- { "ones", 65310, {0, {{{0, 0}}}}, 0, 0 },
- { "spseg", 65292, {0, {{{0, 0}}}}, 0, 0 },
- { "tfr", 65452, {0, {{{0, 0}}}}, 0, 0 }
-};
-
-CGEN_KEYWORD xc16x_cgen_opval_memgr8_names =
-{
- & xc16x_cgen_opval_memgr8_names_entries[0],
- 20,
- 0, 0, 0, 0, ""
-};
-
-
-/* The hardware table. */
-
-#define A(a) (1 << CGEN_HW_##a)
-
-const CGEN_HW_ENTRY xc16x_cgen_hw_table[] =
-{
- { "h-memory", HW_H_MEMORY, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
- { "h-sint", HW_H_SINT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
- { "h-uint", HW_H_UINT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
- { "h-addr", HW_H_ADDR, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
- { "h-iaddr", HW_H_IADDR, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
- { "h-pc", HW_H_PC, CGEN_ASM_NONE, 0, { 0|A(PC), { { { (1<<MACH_BASE), 0 } } } } },
- { "h-gr", HW_H_GR, CGEN_ASM_KEYWORD, & xc16x_cgen_opval_gr_names, { 0|A(CACHE_ADDR)|A(PROFILE), { { { (1<<MACH_BASE), 0 } } } } },
- { "h-cr", HW_H_CR, CGEN_ASM_KEYWORD, & xc16x_cgen_opval_gr_names, { 0|A(CACHE_ADDR)|A(PROFILE), { { { (1<<MACH_BASE), 0 } } } } },
- { "h-ext", HW_H_EXT, CGEN_ASM_KEYWORD, & xc16x_cgen_opval_ext_names, { 0|A(CACHE_ADDR)|A(PROFILE), { { { (1<<MACH_BASE), 0 } } } } },
- { "h-psw", HW_H_PSW, CGEN_ASM_KEYWORD, & xc16x_cgen_opval_psw_names, { 0|A(CACHE_ADDR)|A(PROFILE), { { { (1<<MACH_BASE), 0 } } } } },
- { "h-grb", HW_H_GRB, CGEN_ASM_KEYWORD, & xc16x_cgen_opval_grb_names, { 0|A(CACHE_ADDR)|A(PROFILE), { { { (1<<MACH_BASE), 0 } } } } },
- { "h-cc", HW_H_CC, CGEN_ASM_KEYWORD, & xc16x_cgen_opval_conditioncode_names, { 0|A(CACHE_ADDR)|A(PROFILE), { { { (1<<MACH_BASE), 0 } } } } },
- { "h-ecc", HW_H_ECC, CGEN_ASM_KEYWORD, & xc16x_cgen_opval_extconditioncode_names, { 0|A(CACHE_ADDR)|A(PROFILE), { { { (1<<MACH_BASE), 0 } } } } },
- { "h-grb8", HW_H_GRB8, CGEN_ASM_KEYWORD, & xc16x_cgen_opval_grb8_names, { 0|A(CACHE_ADDR)|A(PROFILE), { { { (1<<MACH_BASE), 0 } } } } },
- { "h-r8", HW_H_R8, CGEN_ASM_KEYWORD, & xc16x_cgen_opval_r8_names, { 0|A(CACHE_ADDR)|A(PROFILE), { { { (1<<MACH_BASE), 0 } } } } },
- { "h-regmem8", HW_H_REGMEM8, CGEN_ASM_KEYWORD, & xc16x_cgen_opval_regmem8_names, { 0, { { { (1<<MACH_BASE), 0 } } } } },
- { "h-regdiv8", HW_H_REGDIV8, CGEN_ASM_KEYWORD, & xc16x_cgen_opval_regdiv8_names, { 0|A(CACHE_ADDR)|A(PROFILE), { { { (1<<MACH_BASE), 0 } } } } },
- { "h-r0", HW_H_R0, CGEN_ASM_KEYWORD, & xc16x_cgen_opval_reg0_name, { 0|A(CACHE_ADDR)|A(PROFILE), { { { (1<<MACH_BASE), 0 } } } } },
- { "h-r01", HW_H_R01, CGEN_ASM_KEYWORD, & xc16x_cgen_opval_reg0_name1, { 0|A(CACHE_ADDR)|A(PROFILE), { { { (1<<MACH_BASE), 0 } } } } },
- { "h-regbmem8", HW_H_REGBMEM8, CGEN_ASM_KEYWORD, & xc16x_cgen_opval_regbmem8_names, { 0|A(CACHE_ADDR)|A(PROFILE), { { { (1<<MACH_BASE), 0 } } } } },
- { "h-memgr8", HW_H_MEMGR8, CGEN_ASM_KEYWORD, & xc16x_cgen_opval_memgr8_names, { 0, { { { (1<<MACH_BASE), 0 } } } } },
- { "h-cond", HW_H_COND, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
- { "h-cbit", HW_H_CBIT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
- { "h-sgtdis", HW_H_SGTDIS, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
- { 0, 0, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } }
-};
-
-#undef A
-
-
-/* The instruction field table. */
-
-#define A(a) (1 << CGEN_IFLD_##a)
-
-const CGEN_IFLD xc16x_cgen_ifld_table[] =
-{
- { XC16X_F_NIL, "f-nil", 0, 0, 0, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
- { XC16X_F_ANYOF, "f-anyof", 0, 0, 0, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
- { XC16X_F_OP1, "f-op1", 0, 32, 7, 4, { 0, { { { (1<<MACH_BASE), 0 } } } } },
- { XC16X_F_OP2, "f-op2", 0, 32, 3, 4, { 0, { { { (1<<MACH_BASE), 0 } } } } },
- { XC16X_F_CONDCODE, "f-condcode", 0, 32, 7, 4, { 0, { { { (1<<MACH_BASE), 0 } } } } },
- { XC16X_F_ICONDCODE, "f-icondcode", 0, 32, 15, 4, { 0, { { { (1<<MACH_BASE), 0 } } } } },
- { XC16X_F_RCOND, "f-rcond", 0, 32, 7, 4, { 0, { { { (1<<MACH_BASE), 0 } } } } },
- { XC16X_F_QCOND, "f-qcond", 0, 32, 7, 4, { 0, { { { (1<<MACH_BASE), 0 } } } } },
- { XC16X_F_EXTCCODE, "f-extccode", 0, 32, 15, 5, { 0, { { { (1<<MACH_BASE), 0 } } } } },
- { XC16X_F_R0, "f-r0", 0, 32, 9, 2, { 0, { { { (1<<MACH_BASE), 0 } } } } },
- { XC16X_F_R1, "f-r1", 0, 32, 15, 4, { 0, { { { (1<<MACH_BASE), 0 } } } } },
- { XC16X_F_R2, "f-r2", 0, 32, 11, 4, { 0, { { { (1<<MACH_BASE), 0 } } } } },
- { XC16X_F_R3, "f-r3", 0, 32, 12, 4, { 0, { { { (1<<MACH_BASE), 0 } } } } },
- { XC16X_F_R4, "f-r4", 0, 32, 11, 4, { 0, { { { (1<<MACH_BASE), 0 } } } } },
- { XC16X_F_UIMM2, "f-uimm2", 0, 32, 13, 2, { 0, { { { (1<<MACH_BASE), 0 } } } } },
- { XC16X_F_UIMM3, "f-uimm3", 0, 32, 10, 3, { 0, { { { (1<<MACH_BASE), 0 } } } } },
- { XC16X_F_UIMM4, "f-uimm4", 0, 32, 15, 4, { 0, { { { (1<<MACH_BASE), 0 } } } } },
- { XC16X_F_UIMM7, "f-uimm7", 0, 32, 15, 7, { 0|A(RELOC)|A(PCREL_ADDR), { { { (1<<MACH_BASE), 0 } } } } },
- { XC16X_F_UIMM8, "f-uimm8", 0, 32, 23, 8, { 0, { { { (1<<MACH_BASE), 0 } } } } },
- { XC16X_F_UIMM16, "f-uimm16", 0, 32, 31, 16, { 0, { { { (1<<MACH_BASE), 0 } } } } },
- { XC16X_F_MEMORY, "f-memory", 0, 32, 31, 16, { 0, { { { (1<<MACH_BASE), 0 } } } } },
- { XC16X_F_MEMGR8, "f-memgr8", 0, 32, 31, 16, { 0, { { { (1<<MACH_BASE), 0 } } } } },
- { XC16X_F_REL8, "f-rel8", 0, 32, 15, 8, { 0|A(RELOC)|A(PCREL_ADDR), { { { (1<<MACH_BASE), 0 } } } } },
- { XC16X_F_RELHI8, "f-relhi8", 0, 32, 23, 8, { 0|A(RELOC)|A(PCREL_ADDR), { { { (1<<MACH_BASE), 0 } } } } },
- { XC16X_F_REG8, "f-reg8", 0, 32, 15, 8, { 0, { { { (1<<MACH_BASE), 0 } } } } },
- { XC16X_F_REGMEM8, "f-regmem8", 0, 32, 15, 8, { 0, { { { (1<<MACH_BASE), 0 } } } } },
- { XC16X_F_REGOFF8, "f-regoff8", 0, 32, 15, 8, { 0, { { { (1<<MACH_BASE), 0 } } } } },
- { XC16X_F_REGHI8, "f-reghi8", 0, 32, 23, 8, { 0, { { { (1<<MACH_BASE), 0 } } } } },
- { XC16X_F_REGB8, "f-regb8", 0, 32, 15, 8, { 0, { { { (1<<MACH_BASE), 0 } } } } },
- { XC16X_F_SEG8, "f-seg8", 0, 32, 15, 8, { 0, { { { (1<<MACH_BASE), 0 } } } } },
- { XC16X_F_SEGNUM8, "f-segnum8", 0, 32, 23, 8, { 0, { { { (1<<MACH_BASE), 0 } } } } },
- { XC16X_F_MASK8, "f-mask8", 0, 32, 23, 8, { 0, { { { (1<<MACH_BASE), 0 } } } } },
- { XC16X_F_PAGENUM, "f-pagenum", 0, 32, 25, 10, { 0, { { { (1<<MACH_BASE), 0 } } } } },
- { XC16X_F_DATAHI8, "f-datahi8", 0, 32, 31, 8, { 0, { { { (1<<MACH_BASE), 0 } } } } },
- { XC16X_F_DATA8, "f-data8", 0, 32, 23, 8, { 0, { { { (1<<MACH_BASE), 0 } } } } },
- { XC16X_F_OFFSET16, "f-offset16", 0, 32, 31, 16, { 0|A(RELOC)|A(ABS_ADDR), { { { (1<<MACH_BASE), 0 } } } } },
- { XC16X_F_OP_BIT1, "f-op-bit1", 0, 32, 11, 1, { 0, { { { (1<<MACH_BASE), 0 } } } } },
- { XC16X_F_OP_BIT2, "f-op-bit2", 0, 32, 11, 2, { 0, { { { (1<<MACH_BASE), 0 } } } } },
- { XC16X_F_OP_BIT4, "f-op-bit4", 0, 32, 11, 4, { 0, { { { (1<<MACH_BASE), 0 } } } } },
- { XC16X_F_OP_BIT3, "f-op-bit3", 0, 32, 10, 3, { 0, { { { (1<<MACH_BASE), 0 } } } } },
- { XC16X_F_OP_2BIT, "f-op-2bit", 0, 32, 10, 2, { 0, { { { (1<<MACH_BASE), 0 } } } } },
- { XC16X_F_OP_BITONE, "f-op-bitone", 0, 32, 10, 1, { 0, { { { (1<<MACH_BASE), 0 } } } } },
- { XC16X_F_OP_ONEBIT, "f-op-onebit", 0, 32, 9, 1, { 0, { { { (1<<MACH_BASE), 0 } } } } },
- { XC16X_F_OP_1BIT, "f-op-1bit", 0, 32, 8, 1, { 0, { { { (1<<MACH_BASE), 0 } } } } },
- { XC16X_F_OP_LBIT4, "f-op-lbit4", 0, 32, 15, 4, { 0, { { { (1<<MACH_BASE), 0 } } } } },
- { XC16X_F_OP_LBIT2, "f-op-lbit2", 0, 32, 15, 2, { 0, { { { (1<<MACH_BASE), 0 } } } } },
- { XC16X_F_OP_BIT8, "f-op-bit8", 0, 32, 31, 8, { 0, { { { (1<<MACH_BASE), 0 } } } } },
- { XC16X_F_OP_BIT16, "f-op-bit16", 0, 32, 31, 16, { 0, { { { (1<<MACH_BASE), 0 } } } } },
- { XC16X_F_QBIT, "f-qbit", 0, 32, 7, 4, { 0, { { { (1<<MACH_BASE), 0 } } } } },
- { XC16X_F_QLOBIT, "f-qlobit", 0, 32, 31, 4, { 0, { { { (1<<MACH_BASE), 0 } } } } },
- { XC16X_F_QHIBIT, "f-qhibit", 0, 32, 27, 4, { 0, { { { (1<<MACH_BASE), 0 } } } } },
- { XC16X_F_QLOBIT2, "f-qlobit2", 0, 32, 27, 2, { 0, { { { (1<<MACH_BASE), 0 } } } } },
- { XC16X_F_POF, "f-pof", 0, 32, 31, 16, { 0, { { { (1<<MACH_BASE), 0 } } } } },
- { 0, 0, 0, 0, 0, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } }
-};
-
-#undef A
-
-
-
-/* multi ifield declarations */
-
-
-
-/* multi ifield definitions */
-
-
-/* The operand table. */
-
-#define A(a) (1 << CGEN_OPERAND_##a)
-#define OPERAND(op) XC16X_OPERAND_##op
-
-const CGEN_OPERAND xc16x_cgen_operand_table[] =
-{
-/* pc: program counter */
- { "pc", XC16X_OPERAND_PC, HW_H_PC, 0, 0,
- { 0, { &xc16x_cgen_ifld_table[XC16X_F_NIL] } },
- { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
-/* sr: source register */
- { "sr", XC16X_OPERAND_SR, HW_H_GR, 11, 4,
- { 0, { &xc16x_cgen_ifld_table[XC16X_F_R2] } },
- { 0, { { { (1<<MACH_BASE), 0 } } } } },
-/* dr: destination register */
- { "dr", XC16X_OPERAND_DR, HW_H_GR, 15, 4,
- { 0, { &xc16x_cgen_ifld_table[XC16X_F_R1] } },
- { 0, { { { (1<<MACH_BASE), 0 } } } } },
-/* dri: destination register */
- { "dri", XC16X_OPERAND_DRI, HW_H_GR, 11, 4,
- { 0, { &xc16x_cgen_ifld_table[XC16X_F_R4] } },
- { 0, { { { (1<<MACH_BASE), 0 } } } } },
-/* srb: source register */
- { "srb", XC16X_OPERAND_SRB, HW_H_GRB, 11, 4,
- { 0, { &xc16x_cgen_ifld_table[XC16X_F_R2] } },
- { 0, { { { (1<<MACH_BASE), 0 } } } } },
-/* drb: destination register */
- { "drb", XC16X_OPERAND_DRB, HW_H_GRB, 15, 4,
- { 0, { &xc16x_cgen_ifld_table[XC16X_F_R1] } },
- { 0, { { { (1<<MACH_BASE), 0 } } } } },
-/* sr2: 2 bit source register */
- { "sr2", XC16X_OPERAND_SR2, HW_H_GR, 9, 2,
- { 0, { &xc16x_cgen_ifld_table[XC16X_F_R0] } },
- { 0, { { { (1<<MACH_BASE), 0 } } } } },
-/* src1: source register 1 */
- { "src1", XC16X_OPERAND_SRC1, HW_H_GR, 15, 4,
- { 0, { &xc16x_cgen_ifld_table[XC16X_F_R1] } },
- { 0, { { { (1<<MACH_BASE), 0 } } } } },
-/* src2: source register 2 */
- { "src2", XC16X_OPERAND_SRC2, HW_H_GR, 11, 4,
- { 0, { &xc16x_cgen_ifld_table[XC16X_F_R2] } },
- { 0, { { { (1<<MACH_BASE), 0 } } } } },
-/* srdiv: source register 2 */
- { "srdiv", XC16X_OPERAND_SRDIV, HW_H_REGDIV8, 15, 8,
- { 0, { &xc16x_cgen_ifld_table[XC16X_F_REG8] } },
- { 0, { { { (1<<MACH_BASE), 0 } } } } },
-/* RegNam: PSW bits */
- { "RegNam", XC16X_OPERAND_REGNAM, HW_H_PSW, 15, 8,
- { 0, { &xc16x_cgen_ifld_table[XC16X_F_REG8] } },
- { 0, { { { (1<<MACH_BASE), 0 } } } } },
-/* uimm2: 2 bit unsigned number */
- { "uimm2", XC16X_OPERAND_UIMM2, HW_H_EXT, 13, 2,
- { 0, { &xc16x_cgen_ifld_table[XC16X_F_UIMM2] } },
- { 0|A(HASH_PREFIX), { { { (1<<MACH_BASE), 0 } } } } },
-/* uimm3: 3 bit unsigned number */
- { "uimm3", XC16X_OPERAND_UIMM3, HW_H_R01, 10, 3,
- { 0, { &xc16x_cgen_ifld_table[XC16X_F_UIMM3] } },
- { 0|A(HASH_PREFIX), { { { (1<<MACH_BASE), 0 } } } } },
-/* uimm4: 4 bit unsigned number */
- { "uimm4", XC16X_OPERAND_UIMM4, HW_H_UINT, 15, 4,
- { 0, { &xc16x_cgen_ifld_table[XC16X_F_UIMM4] } },
- { 0|A(HASH_PREFIX), { { { (1<<MACH_BASE), 0 } } } } },
-/* uimm7: 7 bit trap number */
- { "uimm7", XC16X_OPERAND_UIMM7, HW_H_UINT, 15, 7,
- { 0, { &xc16x_cgen_ifld_table[XC16X_F_UIMM7] } },
- { 0|A(HASH_PREFIX)|A(RELOC)|A(PCREL_ADDR), { { { (1<<MACH_BASE), 0 } } } } },
-/* uimm8: 8 bit unsigned immediate */
- { "uimm8", XC16X_OPERAND_UIMM8, HW_H_UINT, 23, 8,
- { 0, { &xc16x_cgen_ifld_table[XC16X_F_UIMM8] } },
- { 0|A(HASH_PREFIX), { { { (1<<MACH_BASE), 0 } } } } },
-/* uimm16: 16 bit unsigned immediate */
- { "uimm16", XC16X_OPERAND_UIMM16, HW_H_UINT, 31, 16,
- { 0, { &xc16x_cgen_ifld_table[XC16X_F_UIMM16] } },
- { 0|A(HASH_PREFIX), { { { (1<<MACH_BASE), 0 } } } } },
-/* upof16: 16 bit unsigned immediate */
- { "upof16", XC16X_OPERAND_UPOF16, HW_H_ADDR, 31, 16,
- { 0, { &xc16x_cgen_ifld_table[XC16X_F_MEMORY] } },
- { 0|A(POF_PREFIX), { { { (1<<MACH_BASE), 0 } } } } },
-/* reg8: 8 bit word register number */
- { "reg8", XC16X_OPERAND_REG8, HW_H_R8, 15, 8,
- { 0, { &xc16x_cgen_ifld_table[XC16X_F_REG8] } },
- { 0, { { { (1<<MACH_BASE), 0 } } } } },
-/* regmem8: 8 bit word register number */
- { "regmem8", XC16X_OPERAND_REGMEM8, HW_H_REGMEM8, 15, 8,
- { 0, { &xc16x_cgen_ifld_table[XC16X_F_REGMEM8] } },
- { 0, { { { (1<<MACH_BASE), 0 } } } } },
-/* regbmem8: 8 bit byte register number */
- { "regbmem8", XC16X_OPERAND_REGBMEM8, HW_H_REGBMEM8, 15, 8,
- { 0, { &xc16x_cgen_ifld_table[XC16X_F_REGMEM8] } },
- { 0, { { { (1<<MACH_BASE), 0 } } } } },
-/* regoff8: 8 bit word register number */
- { "regoff8", XC16X_OPERAND_REGOFF8, HW_H_R8, 15, 8,
- { 0, { &xc16x_cgen_ifld_table[XC16X_F_REGOFF8] } },
- { 0, { { { (1<<MACH_BASE), 0 } } } } },
-/* reghi8: 8 bit word register number */
- { "reghi8", XC16X_OPERAND_REGHI8, HW_H_R8, 23, 8,
- { 0, { &xc16x_cgen_ifld_table[XC16X_F_REGHI8] } },
- { 0, { { { (1<<MACH_BASE), 0 } } } } },
-/* regb8: 8 bit byte register number */
- { "regb8", XC16X_OPERAND_REGB8, HW_H_GRB8, 15, 8,
- { 0, { &xc16x_cgen_ifld_table[XC16X_F_REGB8] } },
- { 0, { { { (1<<MACH_BASE), 0 } } } } },
-/* genreg: 8 bit word register number */
- { "genreg", XC16X_OPERAND_GENREG, HW_H_R8, 15, 8,
- { 0, { &xc16x_cgen_ifld_table[XC16X_F_REGB8] } },
- { 0, { { { (1<<MACH_BASE), 0 } } } } },
-/* seg: 8 bit segment number */
- { "seg", XC16X_OPERAND_SEG, HW_H_UINT, 15, 8,
- { 0, { &xc16x_cgen_ifld_table[XC16X_F_SEG8] } },
- { 0, { { { (1<<MACH_BASE), 0 } } } } },
-/* seghi8: 8 bit hi segment number */
- { "seghi8", XC16X_OPERAND_SEGHI8, HW_H_UINT, 23, 8,
- { 0, { &xc16x_cgen_ifld_table[XC16X_F_SEGNUM8] } },
- { 0, { { { (1<<MACH_BASE), 0 } } } } },
-/* caddr: 16 bit address offset */
- { "caddr", XC16X_OPERAND_CADDR, HW_H_ADDR, 31, 16,
- { 0, { &xc16x_cgen_ifld_table[XC16X_F_OFFSET16] } },
- { 0|A(RELOC)|A(ABS_ADDR), { { { (1<<MACH_BASE), 0 } } } } },
-/* rel: 8 bit signed relative offset */
- { "rel", XC16X_OPERAND_REL, HW_H_SINT, 15, 8,
- { 0, { &xc16x_cgen_ifld_table[XC16X_F_REL8] } },
- { 0|A(RELOC)|A(PCREL_ADDR), { { { (1<<MACH_BASE), 0 } } } } },
-/* relhi: hi 8 bit signed relative offset */
- { "relhi", XC16X_OPERAND_RELHI, HW_H_SINT, 23, 8,
- { 0, { &xc16x_cgen_ifld_table[XC16X_F_RELHI8] } },
- { 0|A(RELOC)|A(PCREL_ADDR), { { { (1<<MACH_BASE), 0 } } } } },
-/* condbit: condition bit */
- { "condbit", XC16X_OPERAND_CONDBIT, HW_H_COND, 0, 0,
- { 0, { 0 } },
- { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
-/* bit1: gap of 1 bit */
- { "bit1", XC16X_OPERAND_BIT1, HW_H_UINT, 11, 1,
- { 0, { &xc16x_cgen_ifld_table[XC16X_F_OP_BIT1] } },
- { 0, { { { (1<<MACH_BASE), 0 } } } } },
-/* bit2: gap of 2 bits */
- { "bit2", XC16X_OPERAND_BIT2, HW_H_UINT, 11, 2,
- { 0, { &xc16x_cgen_ifld_table[XC16X_F_OP_BIT2] } },
- { 0, { { { (1<<MACH_BASE), 0 } } } } },
-/* bit4: gap of 4 bits */
- { "bit4", XC16X_OPERAND_BIT4, HW_H_UINT, 11, 4,
- { 0, { &xc16x_cgen_ifld_table[XC16X_F_OP_BIT4] } },
- { 0, { { { (1<<MACH_BASE), 0 } } } } },
-/* lbit4: gap of 4 bits */
- { "lbit4", XC16X_OPERAND_LBIT4, HW_H_UINT, 15, 4,
- { 0, { &xc16x_cgen_ifld_table[XC16X_F_OP_LBIT4] } },
- { 0, { { { (1<<MACH_BASE), 0 } } } } },
-/* lbit2: gap of 2 bits */
- { "lbit2", XC16X_OPERAND_LBIT2, HW_H_UINT, 15, 2,
- { 0, { &xc16x_cgen_ifld_table[XC16X_F_OP_LBIT2] } },
- { 0, { { { (1<<MACH_BASE), 0 } } } } },
-/* bit8: gap of 8 bits */
- { "bit8", XC16X_OPERAND_BIT8, HW_H_UINT, 31, 8,
- { 0, { &xc16x_cgen_ifld_table[XC16X_F_OP_BIT8] } },
- { 0, { { { (1<<MACH_BASE), 0 } } } } },
-/* u4: gap of 4 bits */
- { "u4", XC16X_OPERAND_U4, HW_H_R0, 15, 4,
- { 0, { &xc16x_cgen_ifld_table[XC16X_F_UIMM4] } },
- { 0, { { { (1<<MACH_BASE), 0 } } } } },
-/* bitone: field of 1 bit */
- { "bitone", XC16X_OPERAND_BITONE, HW_H_UINT, 9, 1,
- { 0, { &xc16x_cgen_ifld_table[XC16X_F_OP_ONEBIT] } },
- { 0, { { { (1<<MACH_BASE), 0 } } } } },
-/* bit01: field of 1 bit */
- { "bit01", XC16X_OPERAND_BIT01, HW_H_UINT, 8, 1,
- { 0, { &xc16x_cgen_ifld_table[XC16X_F_OP_1BIT] } },
- { 0, { { { (1<<MACH_BASE), 0 } } } } },
-/* cond: condition code */
- { "cond", XC16X_OPERAND_COND, HW_H_CC, 7, 4,
- { 0, { &xc16x_cgen_ifld_table[XC16X_F_CONDCODE] } },
- { 0, { { { (1<<MACH_BASE), 0 } } } } },
-/* icond: indirect condition code */
- { "icond", XC16X_OPERAND_ICOND, HW_H_CC, 15, 4,
- { 0, { &xc16x_cgen_ifld_table[XC16X_F_ICONDCODE] } },
- { 0, { { { (1<<MACH_BASE), 0 } } } } },
-/* extcond: extended condition code */
- { "extcond", XC16X_OPERAND_EXTCOND, HW_H_ECC, 15, 5,
- { 0, { &xc16x_cgen_ifld_table[XC16X_F_EXTCCODE] } },
- { 0, { { { (1<<MACH_BASE), 0 } } } } },
-/* memory: 16 bit memory */
- { "memory", XC16X_OPERAND_MEMORY, HW_H_ADDR, 31, 16,
- { 0, { &xc16x_cgen_ifld_table[XC16X_F_MEMORY] } },
- { 0, { { { (1<<MACH_BASE), 0 } } } } },
-/* memgr8: 16 bit memory */
- { "memgr8", XC16X_OPERAND_MEMGR8, HW_H_MEMGR8, 31, 16,
- { 0, { &xc16x_cgen_ifld_table[XC16X_F_MEMGR8] } },
- { 0, { { { (1<<MACH_BASE), 0 } } } } },
-/* cbit: carry bit */
- { "cbit", XC16X_OPERAND_CBIT, HW_H_CBIT, 0, 0,
- { 0, { 0 } },
- { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
-/* qbit: bit addr */
- { "qbit", XC16X_OPERAND_QBIT, HW_H_UINT, 7, 4,
- { 0, { &xc16x_cgen_ifld_table[XC16X_F_QBIT] } },
- { 0|A(DOT_PREFIX), { { { (1<<MACH_BASE), 0 } } } } },
-/* qlobit: bit addr */
- { "qlobit", XC16X_OPERAND_QLOBIT, HW_H_UINT, 31, 4,
- { 0, { &xc16x_cgen_ifld_table[XC16X_F_QLOBIT] } },
- { 0|A(DOT_PREFIX), { { { (1<<MACH_BASE), 0 } } } } },
-/* qhibit: bit addr */
- { "qhibit", XC16X_OPERAND_QHIBIT, HW_H_UINT, 27, 4,
- { 0, { &xc16x_cgen_ifld_table[XC16X_F_QHIBIT] } },
- { 0|A(DOT_PREFIX), { { { (1<<MACH_BASE), 0 } } } } },
-/* mask8: 8 bit mask */
- { "mask8", XC16X_OPERAND_MASK8, HW_H_UINT, 23, 8,
- { 0, { &xc16x_cgen_ifld_table[XC16X_F_MASK8] } },
- { 0|A(HASH_PREFIX), { { { (1<<MACH_BASE), 0 } } } } },
-/* masklo8: 8 bit mask */
- { "masklo8", XC16X_OPERAND_MASKLO8, HW_H_UINT, 31, 8,
- { 0, { &xc16x_cgen_ifld_table[XC16X_F_DATAHI8] } },
- { 0|A(HASH_PREFIX), { { { (1<<MACH_BASE), 0 } } } } },
-/* pagenum: 10 bit page number */
- { "pagenum", XC16X_OPERAND_PAGENUM, HW_H_UINT, 25, 10,
- { 0, { &xc16x_cgen_ifld_table[XC16X_F_PAGENUM] } },
- { 0|A(HASH_PREFIX), { { { (1<<MACH_BASE), 0 } } } } },
-/* data8: 8 bit data */
- { "data8", XC16X_OPERAND_DATA8, HW_H_UINT, 23, 8,
- { 0, { &xc16x_cgen_ifld_table[XC16X_F_DATA8] } },
- { 0|A(HASH_PREFIX), { { { (1<<MACH_BASE), 0 } } } } },
-/* datahi8: 8 bit data */
- { "datahi8", XC16X_OPERAND_DATAHI8, HW_H_UINT, 31, 8,
- { 0, { &xc16x_cgen_ifld_table[XC16X_F_DATAHI8] } },
- { 0|A(HASH_PREFIX), { { { (1<<MACH_BASE), 0 } } } } },
-/* sgtdisbit: segmentation enable bit */
- { "sgtdisbit", XC16X_OPERAND_SGTDISBIT, HW_H_SGTDIS, 0, 0,
- { 0, { 0 } },
- { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
-/* upag16: 16 bit unsigned immediate */
- { "upag16", XC16X_OPERAND_UPAG16, HW_H_UINT, 31, 16,
- { 0, { &xc16x_cgen_ifld_table[XC16X_F_UIMM16] } },
- { 0|A(PAG_PREFIX), { { { (1<<MACH_BASE), 0 } } } } },
-/* useg8: 8 bit segment */
- { "useg8", XC16X_OPERAND_USEG8, HW_H_UINT, 15, 8,
- { 0, { &xc16x_cgen_ifld_table[XC16X_F_SEG8] } },
- { 0|A(SEG_PREFIX), { { { (1<<MACH_BASE), 0 } } } } },
-/* useg16: 16 bit address offset */
- { "useg16", XC16X_OPERAND_USEG16, HW_H_UINT, 31, 16,
- { 0, { &xc16x_cgen_ifld_table[XC16X_F_OFFSET16] } },
- { 0|A(SEG_PREFIX)|A(RELOC)|A(ABS_ADDR), { { { (1<<MACH_BASE), 0 } } } } },
-/* usof16: 16 bit address offset */
- { "usof16", XC16X_OPERAND_USOF16, HW_H_UINT, 31, 16,
- { 0, { &xc16x_cgen_ifld_table[XC16X_F_OFFSET16] } },
- { 0|A(SOF_PREFIX)|A(RELOC)|A(ABS_ADDR), { { { (1<<MACH_BASE), 0 } } } } },
-/* hash: # prefix */
- { "hash", XC16X_OPERAND_HASH, HW_H_SINT, 0, 0,
- { 0, { 0 } },
- { 0, { { { (1<<MACH_BASE), 0 } } } } },
-/* dot: . prefix */
- { "dot", XC16X_OPERAND_DOT, HW_H_SINT, 0, 0,
- { 0, { 0 } },
- { 0, { { { (1<<MACH_BASE), 0 } } } } },
-/* pof: pof: prefix */
- { "pof", XC16X_OPERAND_POF, HW_H_SINT, 0, 0,
- { 0, { 0 } },
- { 0, { { { (1<<MACH_BASE), 0 } } } } },
-/* pag: pag: prefix */
- { "pag", XC16X_OPERAND_PAG, HW_H_SINT, 0, 0,
- { 0, { 0 } },
- { 0, { { { (1<<MACH_BASE), 0 } } } } },
-/* sof: sof: prefix */
- { "sof", XC16X_OPERAND_SOF, HW_H_SINT, 0, 0,
- { 0, { 0 } },
- { 0, { { { (1<<MACH_BASE), 0 } } } } },
-/* segm: seg: prefix */
- { "segm", XC16X_OPERAND_SEGM, HW_H_SINT, 0, 0,
- { 0, { 0 } },
- { 0, { { { (1<<MACH_BASE), 0 } } } } },
-/* sentinel */
- { 0, 0, 0, 0, 0,
- { 0, { 0 } },
- { 0, { { { (1<<MACH_BASE), 0 } } } } }
-};
-
-#undef A
-
-
-/* The instruction table. */
-
-#define OP(field) CGEN_SYNTAX_MAKE_FIELD (OPERAND (field))
-#define A(a) (1 << CGEN_INSN_##a)
-
-static const CGEN_IBASE xc16x_cgen_insn_table[MAX_INSNS] =
-{
- /* Special null first entry.
- A `num' value of zero is thus invalid.
- Also, the special `invalid' insn resides here. */
- { 0, 0, 0, 0, { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_NONE, 0 } } } } },
-/* add $reg8,$pof$upof16 */
- {
- XC16X_INSN_ADDRPOF, "addrpof", "add", 32,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
- },
-/* sub $reg8,$pof$upof16 */
- {
- XC16X_INSN_SUBRPOF, "subrpof", "sub", 32,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
- },
-/* addb $regb8,$pof$upof16 */
- {
- XC16X_INSN_ADDBRPOF, "addbrpof", "addb", 32,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
- },
-/* subb $regb8,$pof$upof16 */
- {
- XC16X_INSN_SUBBRPOF, "subbrpof", "subb", 32,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
- },
-/* add $reg8,$pag$upag16 */
- {
- XC16X_INSN_ADDRPAG, "addrpag", "add", 32,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
- },
-/* sub $reg8,$pag$upag16 */
- {
- XC16X_INSN_SUBRPAG, "subrpag", "sub", 32,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
- },
-/* addb $regb8,$pag$upag16 */
- {
- XC16X_INSN_ADDBRPAG, "addbrpag", "addb", 32,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
- },
-/* subb $regb8,$pag$upag16 */
- {
- XC16X_INSN_SUBBRPAG, "subbrpag", "subb", 32,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
- },
-/* addc $reg8,$pof$upof16 */
- {
- XC16X_INSN_ADDCRPOF, "addcrpof", "addc", 32,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
- },
-/* subc $reg8,$pof$upof16 */
- {
- XC16X_INSN_SUBCRPOF, "subcrpof", "subc", 32,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
- },
-/* addcb $regb8,$pof$upof16 */
- {
- XC16X_INSN_ADDCBRPOF, "addcbrpof", "addcb", 32,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
- },
-/* subcb $regb8,$pof$upof16 */
- {
- XC16X_INSN_SUBCBRPOF, "subcbrpof", "subcb", 32,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
- },
-/* addc $reg8,$pag$upag16 */
- {
- XC16X_INSN_ADDCRPAG, "addcrpag", "addc", 32,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
- },
-/* subc $reg8,$pag$upag16 */
- {
- XC16X_INSN_SUBCRPAG, "subcrpag", "subc", 32,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
- },
-/* addcb $regb8,$pag$upag16 */
- {
- XC16X_INSN_ADDCBRPAG, "addcbrpag", "addcb", 32,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
- },
-/* subcb $regb8,$pag$upag16 */
- {
- XC16X_INSN_SUBCBRPAG, "subcbrpag", "subcb", 32,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
- },
-/* add $pof$upof16,$reg8 */
- {
- XC16X_INSN_ADDRPOFR, "addrpofr", "add", 32,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
- },
-/* sub $pof$upof16,$reg8 */
- {
- XC16X_INSN_SUBRPOFR, "subrpofr", "sub", 32,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
- },
-/* addb $pof$upof16,$regb8 */
- {
- XC16X_INSN_ADDBRPOFR, "addbrpofr", "addb", 32,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
- },
-/* subb $pof$upof16,$regb8 */
- {
- XC16X_INSN_SUBBRPOFR, "subbrpofr", "subb", 32,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
- },
-/* addc $pof$upof16,$reg8 */
- {
- XC16X_INSN_ADDCRPOFR, "addcrpofr", "addc", 32,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
- },
-/* subc $pof$upof16,$reg8 */
- {
- XC16X_INSN_SUBCRPOFR, "subcrpofr", "subc", 32,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
- },
-/* addcb $pof$upof16,$regb8 */
- {
- XC16X_INSN_ADDCBRPOFR, "addcbrpofr", "addcb", 32,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
- },
-/* subcb $pof$upof16,$regb8 */
- {
- XC16X_INSN_SUBCBRPOFR, "subcbrpofr", "subcb", 32,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
- },
-/* add $reg8,$hash$pof$uimm16 */
- {
- XC16X_INSN_ADDRHPOF, "addrhpof", "add", 32,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
- },
-/* sub $reg8,$hash$pof$uimm16 */
- {
- XC16X_INSN_SUBRHPOF, "subrhpof", "sub", 32,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
- },
-/* add $reg8,$hash$pag$uimm16 */
- {
- XC16X_INSN_ADDBRHPOF, "addbrhpof", "add", 32,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
- },
-/* sub $reg8,$hash$pag$uimm16 */
- {
- XC16X_INSN_SUBBRHPOF, "subbrhpof", "sub", 32,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
- },
-/* add $dr,$hash$pof$uimm3 */
- {
- XC16X_INSN_ADDRHPOF3, "addrhpof3", "add", 16,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
- },
-/* sub $dr,$hash$pof$uimm3 */
- {
- XC16X_INSN_SUBRHPOF3, "subrhpof3", "sub", 16,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
- },
-/* addb $drb,$hash$pag$uimm3 */
- {
- XC16X_INSN_ADDBRHPAG3, "addbrhpag3", "addb", 16,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
- },
-/* subb $drb,$hash$pag$uimm3 */
- {
- XC16X_INSN_SUBBRHPAG3, "subbrhpag3", "subb", 16,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
- },
-/* add $dr,$hash$pag$uimm3 */
- {
- XC16X_INSN_ADDRHPAG3, "addrhpag3", "add", 16,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
- },
-/* sub $dr,$hash$pag$uimm3 */
- {
- XC16X_INSN_SUBRHPAG3, "subrhpag3", "sub", 16,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
- },
-/* addb $drb,$hash$pof$uimm3 */
- {
- XC16X_INSN_ADDBRHPOF3, "addbrhpof3", "addb", 16,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
- },
-/* subb $drb,$hash$pof$uimm3 */
- {
- XC16X_INSN_SUBBRHPOF3, "subbrhpof3", "subb", 16,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
- },
-/* addb $regb8,$hash$pof$uimm8 */
- {
- XC16X_INSN_ADDRBHPOF, "addrbhpof", "addb", 32,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
- },
-/* subb $regb8,$hash$pof$uimm8 */
- {
- XC16X_INSN_SUBRBHPOF, "subrbhpof", "subb", 32,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
- },
-/* addb $regb8,$hash$pag$uimm8 */
- {
- XC16X_INSN_ADDBRHPAG, "addbrhpag", "addb", 32,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
- },
-/* subb $regb8,$hash$pag$uimm8 */
- {
- XC16X_INSN_SUBBRHPAG, "subbrhpag", "subb", 32,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
- },
-/* addc $reg8,$hash$pof$uimm16 */
- {
- XC16X_INSN_ADDCRHPOF, "addcrhpof", "addc", 32,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
- },
-/* subc $reg8,$hash$pof$uimm16 */
- {
- XC16X_INSN_SUBCRHPOF, "subcrhpof", "subc", 32,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
- },
-/* addc $reg8,$hash$pag$uimm16 */
- {
- XC16X_INSN_ADDCBRHPOF, "addcbrhpof", "addc", 32,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
- },
-/* subc $reg8,$hash$pag$uimm16 */
- {
- XC16X_INSN_SUBCBRHPOF, "subcbrhpof", "subc", 32,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
- },
-/* addc $dr,$hash$pof$uimm3 */
- {
- XC16X_INSN_ADDCRHPOF3, "addcrhpof3", "addc", 16,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
- },
-/* subc $dr,$hash$pof$uimm3 */
- {
- XC16X_INSN_SUBCRHPOF3, "subcrhpof3", "subc", 16,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
- },
-/* addcb $drb,$hash$pag$uimm3 */
- {
- XC16X_INSN_ADDCBRHPAG3, "addcbrhpag3", "addcb", 16,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
- },
-/* subcb $drb,$hash$pag$uimm3 */
- {
- XC16X_INSN_SUBCBRHPAG3, "subcbrhpag3", "subcb", 16,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
- },
-/* addc $dr,$hash$pag$uimm3 */
- {
- XC16X_INSN_ADDCRHPAG3, "addcrhpag3", "addc", 16,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
- },
-/* subc $dr,$hash$pag$uimm3 */
- {
- XC16X_INSN_SUBCRHPAG3, "subcrhpag3", "subc", 16,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
- },
-/* addcb $drb,$hash$pof$uimm3 */
- {
- XC16X_INSN_ADDCBRHPOF3, "addcbrhpof3", "addcb", 16,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
- },
-/* subcb $drb,$hash$pof$uimm3 */
- {
- XC16X_INSN_SUBCBRHPOF3, "subcbrhpof3", "subcb", 16,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
- },
-/* addcb $regb8,$hash$pof$uimm8 */
- {
- XC16X_INSN_ADDCRBHPOF, "addcrbhpof", "addcb", 32,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
- },
-/* subcb $regb8,$hash$pof$uimm8 */
- {
- XC16X_INSN_SUBCRBHPOF, "subcrbhpof", "subcb", 32,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
- },
-/* addcb $regb8,$hash$pag$uimm8 */
- {
- XC16X_INSN_ADDCBRHPAG, "addcbrhpag", "addcb", 32,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
- },
-/* subcb $regb8,$hash$pag$uimm8 */
- {
- XC16X_INSN_SUBCBRHPAG, "subcbrhpag", "subcb", 32,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
- },
-/* add $dr,$hash$uimm3 */
- {
- XC16X_INSN_ADDRI, "addri", "add", 16,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
- },
-/* sub $dr,$hash$uimm3 */
- {
- XC16X_INSN_SUBRI, "subri", "sub", 16,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
- },
-/* addb $drb,$hash$uimm3 */
- {
- XC16X_INSN_ADDBRI, "addbri", "addb", 16,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
- },
-/* subb $drb,$hash$uimm3 */
- {
- XC16X_INSN_SUBBRI, "subbri", "subb", 16,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
- },
-/* add $reg8,$hash$uimm16 */
- {
- XC16X_INSN_ADDRIM, "addrim", "add", 32,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
- },
-/* sub $reg8,$hash$uimm16 */
- {
- XC16X_INSN_SUBRIM, "subrim", "sub", 32,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
- },
-/* addb $regb8,$hash$uimm8 */
- {
- XC16X_INSN_ADDBRIM, "addbrim", "addb", 32,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
- },
-/* subb $regb8,$hash$uimm8 */
- {
- XC16X_INSN_SUBBRIM, "subbrim", "subb", 32,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
- },
-/* addc $dr,$hash$uimm3 */
- {
- XC16X_INSN_ADDCRI, "addcri", "addc", 16,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
- },
-/* subc $dr,$hash$uimm3 */
- {
- XC16X_INSN_SUBCRI, "subcri", "subc", 16,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
- },
-/* addcb $drb,$hash$uimm3 */
- {
- XC16X_INSN_ADDCBRI, "addcbri", "addcb", 16,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
- },
-/* subcb $drb,$hash$uimm3 */
- {
- XC16X_INSN_SUBCBRI, "subcbri", "subcb", 16,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
- },
-/* addc $reg8,$hash$uimm16 */
- {
- XC16X_INSN_ADDCRIM, "addcrim", "addc", 32,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
- },
-/* subc $reg8,$hash$uimm16 */
- {
- XC16X_INSN_SUBCRIM, "subcrim", "subc", 32,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
- },
-/* addcb $regb8,$hash$uimm8 */
- {
- XC16X_INSN_ADDCBRIM, "addcbrim", "addcb", 32,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
- },
-/* subcb $regb8,$hash$uimm8 */
- {
- XC16X_INSN_SUBCBRIM, "subcbrim", "subcb", 32,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
- },
-/* add $dr,$sr */
- {
- XC16X_INSN_ADDR, "addr", "add", 16,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
- },
-/* sub $dr,$sr */
- {
- XC16X_INSN_SUBR, "subr", "sub", 16,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
- },
-/* addb $drb,$srb */
- {
- XC16X_INSN_ADDBR, "addbr", "addb", 16,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
- },
-/* subb $drb,$srb */
- {
- XC16X_INSN_SUBBR, "subbr", "subb", 16,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
- },
-/* add $dr,[$sr2] */
- {
- XC16X_INSN_ADD2, "add2", "add", 16,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
- },
-/* sub $dr,[$sr2] */
- {
- XC16X_INSN_SUB2, "sub2", "sub", 16,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
- },
-/* addb $drb,[$sr2] */
- {
- XC16X_INSN_ADDB2, "addb2", "addb", 16,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
- },
-/* subb $drb,[$sr2] */
- {
- XC16X_INSN_SUBB2, "subb2", "subb", 16,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
- },
-/* add $dr,[$sr2+] */
- {
- XC16X_INSN_ADD2I, "add2i", "add", 16,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
- },
-/* sub $dr,[$sr2+] */
- {
- XC16X_INSN_SUB2I, "sub2i", "sub", 16,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
- },
-/* addb $drb,[$sr2+] */
- {
- XC16X_INSN_ADDB2I, "addb2i", "addb", 16,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
- },
-/* subb $drb,[$sr2+] */
- {
- XC16X_INSN_SUBB2I, "subb2i", "subb", 16,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
- },
-/* addc $dr,$sr */
- {
- XC16X_INSN_ADDCR, "addcr", "addc", 16,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
- },
-/* subc $dr,$sr */
- {
- XC16X_INSN_SUBCR, "subcr", "subc", 16,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
- },
-/* addcb $drb,$srb */
- {
- XC16X_INSN_ADDBCR, "addbcr", "addcb", 16,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
- },
-/* subcb $drb,$srb */
- {
- XC16X_INSN_SUBBCR, "subbcr", "subcb", 16,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
- },
-/* addc $dr,[$sr2] */
- {
- XC16X_INSN_ADDCR2, "addcr2", "addc", 16,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
- },
-/* subc $dr,[$sr2] */
- {
- XC16X_INSN_SUBCR2, "subcr2", "subc", 16,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
- },
-/* addcb $drb,[$sr2] */
- {
- XC16X_INSN_ADDBCR2, "addbcr2", "addcb", 16,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
- },
-/* subcb $drb,[$sr2] */
- {
- XC16X_INSN_SUBBCR2, "subbcr2", "subcb", 16,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
- },
-/* addc $dr,[$sr2+] */
- {
- XC16X_INSN_ADDCR2I, "addcr2i", "addc", 16,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
- },
-/* subc $dr,[$sr2+] */
- {
- XC16X_INSN_SUBCR2I, "subcr2i", "subc", 16,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
- },
-/* addcb $drb,[$sr2+] */
- {
- XC16X_INSN_ADDBCR2I, "addbcr2i", "addcb", 16,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
- },
-/* subcb $drb,[$sr2+] */
- {
- XC16X_INSN_SUBBCR2I, "subbcr2i", "subcb", 16,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
- },
-/* add $regmem8,$memgr8 */
- {
- XC16X_INSN_ADDRM2, "addrm2", "add", 32,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
- },
-/* add $memgr8,$regmem8 */
- {
- XC16X_INSN_ADDRM3, "addrm3", "add", 32,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
- },
-/* add $reg8,$memory */
- {
- XC16X_INSN_ADDRM, "addrm", "add", 32,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
- },
-/* add $memory,$reg8 */
- {
- XC16X_INSN_ADDRM1, "addrm1", "add", 32,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
- },
-/* sub $regmem8,$memgr8 */
- {
- XC16X_INSN_SUBRM3, "subrm3", "sub", 32,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
- },
-/* sub $memgr8,$regmem8 */
- {
- XC16X_INSN_SUBRM2, "subrm2", "sub", 32,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
- },
-/* sub $reg8,$memory */
- {
- XC16X_INSN_SUBRM1, "subrm1", "sub", 32,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
- },
-/* sub $memory,$reg8 */
- {
- XC16X_INSN_SUBRM, "subrm", "sub", 32,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
- },
-/* addb $regbmem8,$memgr8 */
- {
- XC16X_INSN_ADDBRM2, "addbrm2", "addb", 32,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
- },
-/* addb $memgr8,$regbmem8 */
- {
- XC16X_INSN_ADDBRM3, "addbrm3", "addb", 32,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
- },
-/* addb $regb8,$memory */
- {
- XC16X_INSN_ADDBRM, "addbrm", "addb", 32,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
- },
-/* addb $memory,$regb8 */
- {
- XC16X_INSN_ADDBRM1, "addbrm1", "addb", 32,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
- },
-/* subb $regbmem8,$memgr8 */
- {
- XC16X_INSN_SUBBRM3, "subbrm3", "subb", 32,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
- },
-/* subb $memgr8,$regbmem8 */
- {
- XC16X_INSN_SUBBRM2, "subbrm2", "subb", 32,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
- },
-/* subb $regb8,$memory */
- {
- XC16X_INSN_SUBBRM1, "subbrm1", "subb", 32,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
- },
-/* subb $memory,$regb8 */
- {
- XC16X_INSN_SUBBRM, "subbrm", "subb", 32,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
- },
-/* addc $regmem8,$memgr8 */
- {
- XC16X_INSN_ADDCRM2, "addcrm2", "addc", 32,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
- },
-/* addc $memgr8,$regmem8 */
- {
- XC16X_INSN_ADDCRM3, "addcrm3", "addc", 32,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
- },
-/* addc $reg8,$memory */
- {
- XC16X_INSN_ADDCRM, "addcrm", "addc", 32,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
- },
-/* addc $memory,$reg8 */
- {
- XC16X_INSN_ADDCRM1, "addcrm1", "addc", 32,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
- },
-/* subc $regmem8,$memgr8 */
- {
- XC16X_INSN_SUBCRM3, "subcrm3", "subc", 32,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
- },
-/* subc $memgr8,$regmem8 */
- {
- XC16X_INSN_SUBCRM2, "subcrm2", "subc", 32,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
- },
-/* subc $reg8,$memory */
- {
- XC16X_INSN_SUBCRM1, "subcrm1", "subc", 32,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
- },
-/* subc $memory,$reg8 */
- {
- XC16X_INSN_SUBCRM, "subcrm", "subc", 32,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
- },
-/* addcb $regbmem8,$memgr8 */
- {
- XC16X_INSN_ADDCBRM2, "addcbrm2", "addcb", 32,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
- },
-/* addcb $memgr8,$regbmem8 */
- {
- XC16X_INSN_ADDCBRM3, "addcbrm3", "addcb", 32,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
- },
-/* addcb $regb8,$memory */
- {
- XC16X_INSN_ADDCBRM, "addcbrm", "addcb", 32,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
- },
-/* addcb $memory,$regb8 */
- {
- XC16X_INSN_ADDCBRM1, "addcbrm1", "addcb", 32,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
- },
-/* subcb $regbmem8,$memgr8 */
- {
- XC16X_INSN_SUBCBRM3, "subcbrm3", "subcb", 32,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
- },
-/* subcb $memgr8,$regbmem8 */
- {
- XC16X_INSN_SUBCBRM2, "subcbrm2", "subcb", 32,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
- },
-/* subcb $regb8,$memory */
- {
- XC16X_INSN_SUBCBRM1, "subcbrm1", "subcb", 32,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
- },
-/* subcb $memory,$regb8 */
- {
- XC16X_INSN_SUBCBRM, "subcbrm", "subcb", 32,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
- },
-/* mul $src1,$src2 */
- {
- XC16X_INSN_MULS, "muls", "mul", 16,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
- },
-/* mulu $src1,$src2 */
- {
- XC16X_INSN_MULU, "mulu", "mulu", 16,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
- },
-/* div $srdiv */
- {
- XC16X_INSN_DIV, "div", "div", 16,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
- },
-/* divl $srdiv */
- {
- XC16X_INSN_DIVL, "divl", "divl", 16,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
- },
-/* divlu $srdiv */
- {
- XC16X_INSN_DIVLU, "divlu", "divlu", 16,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
- },
-/* divu $srdiv */
- {
- XC16X_INSN_DIVU, "divu", "divu", 16,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
- },
-/* cpl $dr */
- {
- XC16X_INSN_CPL, "cpl", "cpl", 16,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
- },
-/* cplb $drb */
- {
- XC16X_INSN_CPLB, "cplb", "cplb", 16,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
- },
-/* neg $dr */
- {
- XC16X_INSN_NEG, "neg", "neg", 16,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
- },
-/* negb $drb */
- {
- XC16X_INSN_NEGB, "negb", "negb", 16,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
- },
-/* and $dr,$sr */
- {
- XC16X_INSN_ANDR, "andr", "and", 16,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
- },
-/* or $dr,$sr */
- {
- XC16X_INSN_ORR, "orr", "or", 16,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
- },
-/* xor $dr,$sr */
- {
- XC16X_INSN_XORR, "xorr", "xor", 16,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
- },
-/* andb $drb,$srb */
- {
- XC16X_INSN_ANDBR, "andbr", "andb", 16,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
- },
-/* orb $drb,$srb */
- {
- XC16X_INSN_ORBR, "orbr", "orb", 16,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
- },
-/* xorb $drb,$srb */
- {
- XC16X_INSN_XORBR, "xorbr", "xorb", 16,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
- },
-/* and $dr,$hash$uimm3 */
- {
- XC16X_INSN_ANDRI, "andri", "and", 16,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
- },
-/* or $dr,$hash$uimm3 */
- {
- XC16X_INSN_ORRI, "orri", "or", 16,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
- },
-/* xor $dr,$hash$uimm3 */
- {
- XC16X_INSN_XORRI, "xorri", "xor", 16,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
- },
-/* andb $drb,$hash$uimm3 */
- {
- XC16X_INSN_ANDBRI, "andbri", "andb", 16,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
- },
-/* orb $drb,$hash$uimm3 */
- {
- XC16X_INSN_ORBRI, "orbri", "orb", 16,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
- },
-/* xorb $drb,$hash$uimm3 */
- {
- XC16X_INSN_XORBRI, "xorbri", "xorb", 16,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
- },
-/* and $reg8,$hash$uimm16 */
- {
- XC16X_INSN_ANDRIM, "andrim", "and", 32,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
- },
-/* or $reg8,$hash$uimm16 */
- {
- XC16X_INSN_ORRIM, "orrim", "or", 32,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
- },
-/* xor $reg8,$hash$uimm16 */
- {
- XC16X_INSN_XORRIM, "xorrim", "xor", 32,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
- },
-/* andb $regb8,$hash$uimm8 */
- {
- XC16X_INSN_ANDBRIM, "andbrim", "andb", 32,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
- },
-/* orb $regb8,$hash$uimm8 */
- {
- XC16X_INSN_ORBRIM, "orbrim", "orb", 32,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
- },
-/* xorb $regb8,$hash$uimm8 */
- {
- XC16X_INSN_XORBRIM, "xorbrim", "xorb", 32,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
- },
-/* and $dr,[$sr2] */
- {
- XC16X_INSN_AND2, "and2", "and", 16,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
- },
-/* or $dr,[$sr2] */
- {
- XC16X_INSN_OR2, "or2", "or", 16,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
- },
-/* xor $dr,[$sr2] */
- {
- XC16X_INSN_XOR2, "xor2", "xor", 16,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
- },
-/* andb $drb,[$sr2] */
- {
- XC16X_INSN_ANDB2, "andb2", "andb", 16,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
- },
-/* orb $drb,[$sr2] */
- {
- XC16X_INSN_ORB2, "orb2", "orb", 16,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
- },
-/* xorb $drb,[$sr2] */
- {
- XC16X_INSN_XORB2, "xorb2", "xorb", 16,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
- },
-/* and $dr,[$sr2+] */
- {
- XC16X_INSN_AND2I, "and2i", "and", 16,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
- },
-/* or $dr,[$sr2+] */
- {
- XC16X_INSN_OR2I, "or2i", "or", 16,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
- },
-/* xor $dr,[$sr2+] */
- {
- XC16X_INSN_XOR2I, "xor2i", "xor", 16,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
- },
-/* andb $drb,[$sr2+] */
- {
- XC16X_INSN_ANDB2I, "andb2i", "andb", 16,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
- },
-/* orb $drb,[$sr2+] */
- {
- XC16X_INSN_ORB2I, "orb2i", "orb", 16,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
- },
-/* xorb $drb,[$sr2+] */
- {
- XC16X_INSN_XORB2I, "xorb2i", "xorb", 16,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
- },
-/* and $pof$reg8,$upof16 */
- {
- XC16X_INSN_ANDPOFR, "andpofr", "and", 32,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
- },
-/* or $pof$reg8,$upof16 */
- {
- XC16X_INSN_ORPOFR, "orpofr", "or", 32,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
- },
-/* xor $pof$reg8,$upof16 */
- {
- XC16X_INSN_XORPOFR, "xorpofr", "xor", 32,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
- },
-/* andb $pof$regb8,$upof16 */
- {
- XC16X_INSN_ANDBPOFR, "andbpofr", "andb", 32,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
- },
-/* orb $pof$regb8,$upof16 */
- {
- XC16X_INSN_ORBPOFR, "orbpofr", "orb", 32,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
- },
-/* xorb $pof$regb8,$upof16 */
- {
- XC16X_INSN_XORBPOFR, "xorbpofr", "xorb", 32,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
- },
-/* and $pof$upof16,$reg8 */
- {
- XC16X_INSN_ANDRPOFR, "andrpofr", "and", 32,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
- },
-/* or $pof$upof16,$reg8 */
- {
- XC16X_INSN_ORRPOFR, "orrpofr", "or", 32,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
- },
-/* xor $pof$upof16,$reg8 */
- {
- XC16X_INSN_XORRPOFR, "xorrpofr", "xor", 32,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
- },
-/* andb $pof$upof16,$regb8 */
- {
- XC16X_INSN_ANDBRPOFR, "andbrpofr", "andb", 32,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
- },
-/* orb $pof$upof16,$regb8 */
- {
- XC16X_INSN_ORBRPOFR, "orbrpofr", "orb", 32,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
- },
-/* xorb $pof$upof16,$regb8 */
- {
- XC16X_INSN_XORBRPOFR, "xorbrpofr", "xorb", 32,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
- },
-/* and $regmem8,$memgr8 */
- {
- XC16X_INSN_ANDRM2, "andrm2", "and", 32,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
- },
-/* and $memgr8,$regmem8 */
- {
- XC16X_INSN_ANDRM3, "andrm3", "and", 32,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
- },
-/* and $reg8,$memory */
- {
- XC16X_INSN_ANDRM, "andrm", "and", 32,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
- },
-/* and $memory,$reg8 */
- {
- XC16X_INSN_ANDRM1, "andrm1", "and", 32,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
- },
-/* or $regmem8,$memgr8 */
- {
- XC16X_INSN_ORRM3, "orrm3", "or", 32,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
- },
-/* or $memgr8,$regmem8 */
- {
- XC16X_INSN_ORRM2, "orrm2", "or", 32,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
- },
-/* or $reg8,$memory */
- {
- XC16X_INSN_ORRM1, "orrm1", "or", 32,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
- },
-/* or $memory,$reg8 */
- {
- XC16X_INSN_ORRM, "orrm", "or", 32,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
- },
-/* xor $regmem8,$memgr8 */
- {
- XC16X_INSN_XORRM3, "xorrm3", "xor", 32,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
- },
-/* xor $memgr8,$regmem8 */
- {
- XC16X_INSN_XORRM2, "xorrm2", "xor", 32,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
- },
-/* xor $reg8,$memory */
- {
- XC16X_INSN_XORRM1, "xorrm1", "xor", 32,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
- },
-/* xor $memory,$reg8 */
- {
- XC16X_INSN_XORRM, "xorrm", "xor", 32,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
- },
-/* andb $regbmem8,$memgr8 */
- {
- XC16X_INSN_ANDBRM2, "andbrm2", "andb", 32,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
- },
-/* andb $memgr8,$regbmem8 */
- {
- XC16X_INSN_ANDBRM3, "andbrm3", "andb", 32,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
- },
-/* andb $regb8,$memory */
- {
- XC16X_INSN_ANDBRM, "andbrm", "andb", 32,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
- },
-/* andb $memory,$regb8 */
- {
- XC16X_INSN_ANDBRM1, "andbrm1", "andb", 32,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
- },
-/* orb $regbmem8,$memgr8 */
- {
- XC16X_INSN_ORBRM3, "orbrm3", "orb", 32,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
- },
-/* orb $memgr8,$regbmem8 */
- {
- XC16X_INSN_ORBRM2, "orbrm2", "orb", 32,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
- },
-/* orb $regb8,$memory */
- {
- XC16X_INSN_ORBRM1, "orbrm1", "orb", 32,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
- },
-/* orb $memory,$regb8 */
- {
- XC16X_INSN_ORBRM, "orbrm", "orb", 32,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
- },
-/* xorb $regbmem8,$memgr8 */
- {
- XC16X_INSN_XORBRM3, "xorbrm3", "xorb", 32,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
- },
-/* xorb $memgr8,$regbmem8 */
- {
- XC16X_INSN_XORBRM2, "xorbrm2", "xorb", 32,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
- },
-/* xorb $regb8,$memory */
- {
- XC16X_INSN_XORBRM1, "xorbrm1", "xorb", 32,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
- },
-/* xorb $memory,$regb8 */
- {
- XC16X_INSN_XORBRM, "xorbrm", "xorb", 32,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
- },
-/* mov $dr,$sr */
- {
- XC16X_INSN_MOVR, "movr", "mov", 16,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
- },
-/* movb $drb,$srb */
- {
- XC16X_INSN_MOVRB, "movrb", "movb", 16,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
- },
-/* mov $dri,$hash$u4 */
- {
- XC16X_INSN_MOVRI, "movri", "mov", 16,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
- },
-/* movb $srb,$hash$u4 */
- {
- XC16X_INSN_MOVBRI, "movbri", "movb", 16,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
- },
-/* mov $reg8,$hash$uimm16 */
- {
- XC16X_INSN_MOVI, "movi", "mov", 32,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
- },
-/* movb $regb8,$hash$uimm8 */
- {
- XC16X_INSN_MOVBI, "movbi", "movb", 32,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
- },
-/* mov $dr,[$sr] */
- {
- XC16X_INSN_MOVR2, "movr2", "mov", 16,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
- },
-/* movb $drb,[$sr] */
- {
- XC16X_INSN_MOVBR2, "movbr2", "movb", 16,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
- },
-/* mov [$sr],$dr */
- {
- XC16X_INSN_MOVRI2, "movri2", "mov", 16,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
- },
-/* movb [$sr],$drb */
- {
- XC16X_INSN_MOVBRI2, "movbri2", "movb", 16,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
- },
-/* mov [-$sr],$dr */
- {
- XC16X_INSN_MOVRI3, "movri3", "mov", 16,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
- },
-/* movb [-$sr],$drb */
- {
- XC16X_INSN_MOVBRI3, "movbri3", "movb", 16,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
- },
-/* mov $dr,[$sr+] */
- {
- XC16X_INSN_MOV2I, "mov2i", "mov", 16,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
- },
-/* movb $drb,[$sr+] */
- {
- XC16X_INSN_MOVB2I, "movb2i", "movb", 16,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
- },
-/* mov [$dr],[$sr] */
- {
- XC16X_INSN_MOV6I, "mov6i", "mov", 16,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
- },
-/* movb [$dr],[$sr] */
- {
- XC16X_INSN_MOVB6I, "movb6i", "movb", 16,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
- },
-/* mov [$dr+],[$sr] */
- {
- XC16X_INSN_MOV7I, "mov7i", "mov", 16,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
- },
-/* movb [$dr+],[$sr] */
- {
- XC16X_INSN_MOVB7I, "movb7i", "movb", 16,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
- },
-/* mov [$dr],[$sr+] */
- {
- XC16X_INSN_MOV8I, "mov8i", "mov", 16,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
- },
-/* movb [$dr],[$sr+] */
- {
- XC16X_INSN_MOVB8I, "movb8i", "movb", 16,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
- },
-/* mov $dr,[$sr+$hash$uimm16] */
- {
- XC16X_INSN_MOV9I, "mov9i", "mov", 32,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
- },
-/* movb $drb,[$sr+$hash$uimm16] */
- {
- XC16X_INSN_MOVB9I, "movb9i", "movb", 32,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
- },
-/* mov [$sr+$hash$uimm16],$dr */
- {
- XC16X_INSN_MOV10I, "mov10i", "mov", 32,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
- },
-/* movb [$sr+$hash$uimm16],$drb */
- {
- XC16X_INSN_MOVB10I, "movb10i", "movb", 32,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
- },
-/* mov [$src2],$memory */
- {
- XC16X_INSN_MOVRI11, "movri11", "mov", 32,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
- },
-/* movb [$src2],$memory */
- {
- XC16X_INSN_MOVBRI11, "movbri11", "movb", 32,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
- },
-/* mov $memory,[$src2] */
- {
- XC16X_INSN_MOVRI12, "movri12", "mov", 32,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
- },
-/* movb $memory,[$src2] */
- {
- XC16X_INSN_MOVBRI12, "movbri12", "movb", 32,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
- },
-/* mov $regoff8,$hash$pof$upof16 */
- {
- XC16X_INSN_MOVEHM5, "movehm5", "mov", 32,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
- },
-/* mov $regoff8,$hash$pag$upag16 */
- {
- XC16X_INSN_MOVEHM6, "movehm6", "mov", 32,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
- },
-/* mov $regoff8,$hash$segm$useg16 */
- {
- XC16X_INSN_MOVEHM7, "movehm7", "mov", 32,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
- },
-/* mov $regoff8,$hash$sof$usof16 */
- {
- XC16X_INSN_MOVEHM8, "movehm8", "mov", 32,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
- },
-/* movb $regb8,$hash$pof$uimm8 */
- {
- XC16X_INSN_MOVEHM9, "movehm9", "movb", 32,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
- },
-/* movb $regoff8,$hash$pag$uimm8 */
- {
- XC16X_INSN_MOVEHM10, "movehm10", "movb", 32,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
- },
-/* mov $regoff8,$pof$upof16 */
- {
- XC16X_INSN_MOVRMP, "movrmp", "mov", 32,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
- },
-/* movb $regb8,$pof$upof16 */
- {
- XC16X_INSN_MOVRMP1, "movrmp1", "movb", 32,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
- },
-/* mov $regoff8,$pag$upag16 */
- {
- XC16X_INSN_MOVRMP2, "movrmp2", "mov", 32,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
- },
-/* movb $regb8,$pag$upag16 */
- {
- XC16X_INSN_MOVRMP3, "movrmp3", "movb", 32,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
- },
-/* mov $pof$upof16,$regoff8 */
- {
- XC16X_INSN_MOVRMP4, "movrmp4", "mov", 32,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
- },
-/* movb $pof$upof16,$regb8 */
- {
- XC16X_INSN_MOVRMP5, "movrmp5", "movb", 32,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
- },
-/* mov $dri,$hash$pof$u4 */
- {
- XC16X_INSN_MOVEHM1, "movehm1", "mov", 16,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
- },
-/* movb $srb,$hash$pof$u4 */
- {
- XC16X_INSN_MOVEHM2, "movehm2", "movb", 16,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
- },
-/* mov $dri,$hash$pag$u4 */
- {
- XC16X_INSN_MOVEHM3, "movehm3", "mov", 16,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
- },
-/* movb $srb,$hash$pag$u4 */
- {
- XC16X_INSN_MOVEHM4, "movehm4", "movb", 16,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
- },
-/* mov $regmem8,$memgr8 */
- {
- XC16X_INSN_MVE12, "mve12", "mov", 32,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
- },
-/* mov $memgr8,$regmem8 */
- {
- XC16X_INSN_MVE13, "mve13", "mov", 32,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
- },
-/* mov $reg8,$memory */
- {
- XC16X_INSN_MOVER12, "mover12", "mov", 32,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
- },
-/* mov $memory,$reg8 */
- {
- XC16X_INSN_MVR13, "mvr13", "mov", 32,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
- },
-/* movb $regbmem8,$memgr8 */
- {
- XC16X_INSN_MVER12, "mver12", "movb", 32,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
- },
-/* movb $memgr8,$regbmem8 */
- {
- XC16X_INSN_MVER13, "mver13", "movb", 32,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
- },
-/* movb $regb8,$memory */
- {
- XC16X_INSN_MOVR12, "movr12", "movb", 32,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
- },
-/* movb $memory,$regb8 */
- {
- XC16X_INSN_MOVR13, "movr13", "movb", 32,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
- },
-/* movbs $sr,$drb */
- {
- XC16X_INSN_MOVBSRR, "movbsrr", "movbs", 16,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
- },
-/* movbz $sr,$drb */
- {
- XC16X_INSN_MOVBZRR, "movbzrr", "movbz", 16,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
- },
-/* movbs $regmem8,$pof$upof16 */
- {
- XC16X_INSN_MOVBSRPOFM, "movbsrpofm", "movbs", 32,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
- },
-/* movbs $pof$upof16,$regbmem8 */
- {
- XC16X_INSN_MOVBSPOFMR, "movbspofmr", "movbs", 32,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
- },
-/* movbz $reg8,$pof$upof16 */
- {
- XC16X_INSN_MOVBZRPOFM, "movbzrpofm", "movbz", 32,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
- },
-/* movbz $pof$upof16,$regb8 */
- {
- XC16X_INSN_MOVBZPOFMR, "movbzpofmr", "movbz", 32,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
- },
-/* movbs $regmem8,$memgr8 */
- {
- XC16X_INSN_MOVEBS14, "movebs14", "movbs", 32,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
- },
-/* movbs $memgr8,$regbmem8 */
- {
- XC16X_INSN_MOVEBS15, "movebs15", "movbs", 32,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
- },
-/* movbs $reg8,$memory */
- {
- XC16X_INSN_MOVERBS14, "moverbs14", "movbs", 32,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
- },
-/* movbs $memory,$regb8 */
- {
- XC16X_INSN_MOVRBS15, "movrbs15", "movbs", 32,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
- },
-/* movbz $regmem8,$memgr8 */
- {
- XC16X_INSN_MOVEBZ14, "movebz14", "movbz", 32,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
- },
-/* movbz $memgr8,$regbmem8 */
- {
- XC16X_INSN_MOVEBZ15, "movebz15", "movbz", 32,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
- },
-/* movbz $reg8,$memory */
- {
- XC16X_INSN_MOVERBZ14, "moverbz14", "movbz", 32,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
- },
-/* movbz $memory,$regb8 */
- {
- XC16X_INSN_MOVRBZ15, "movrbz15", "movbz", 32,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
- },
-/* movbs $sr,$drb */
- {
- XC16X_INSN_MOVRBS, "movrbs", "movbs", 16,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
- },
-/* movbz $sr,$drb */
- {
- XC16X_INSN_MOVRBZ, "movrbz", "movbz", 16,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
- },
-/* jmpa+ $extcond,$caddr */
- {
- XC16X_INSN_JMPA0, "jmpa0", "jmpa+", 32,
- { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
- },
-/* jmpa $extcond,$caddr */
- {
- XC16X_INSN_JMPA1, "jmpa1", "jmpa", 32,
- { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
- },
-/* jmpa- $extcond,$caddr */
- {
- XC16X_INSN_JMPA_, "jmpa-", "jmpa-", 32,
- { 0|A(COND_CTI)|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
- },
-/* jmpi $icond,[$sr] */
- {
- XC16X_INSN_JMPI, "jmpi", "jmpi", 16,
- { 0|A(COND_CTI)|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
- },
-/* jmpr $cond,$rel */
- {
- XC16X_INSN_JMPR_NENZ, "jmpr_nenz", "jmpr", 16,
- { 0|A(COND_CTI)|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
- },
-/* jmpr $cond,$rel */
- {
- XC16X_INSN_JMPR_SGT, "jmpr_sgt", "jmpr", 16,
- { 0|A(COND_CTI)|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
- },
-/* jmpr $cond,$rel */
- {
- XC16X_INSN_JMPR_Z, "jmpr_z", "jmpr", 16,
- { 0|A(COND_CTI)|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
- },
-/* jmpr $cond,$rel */
- {
- XC16X_INSN_JMPR_V, "jmpr_v", "jmpr", 16,
- { 0|A(COND_CTI)|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
- },
-/* jmpr $cond,$rel */
- {
- XC16X_INSN_JMPR_NV, "jmpr_nv", "jmpr", 16,
- { 0|A(COND_CTI)|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
- },
-/* jmpr $cond,$rel */
- {
- XC16X_INSN_JMPR_N, "jmpr_n", "jmpr", 16,
- { 0|A(COND_CTI)|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
- },
-/* jmpr $cond,$rel */
- {
- XC16X_INSN_JMPR_NN, "jmpr_nn", "jmpr", 16,
- { 0|A(COND_CTI)|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
- },
-/* jmpr $cond,$rel */
- {
- XC16X_INSN_JMPR_C, "jmpr_c", "jmpr", 16,
- { 0|A(COND_CTI)|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
- },
-/* jmpr $cond,$rel */
- {
- XC16X_INSN_JMPR_NC, "jmpr_nc", "jmpr", 16,
- { 0|A(COND_CTI)|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
- },
-/* jmpr $cond,$rel */
- {
- XC16X_INSN_JMPR_EQ, "jmpr_eq", "jmpr", 16,
- { 0|A(COND_CTI)|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
- },
-/* jmpr $cond,$rel */
- {
- XC16X_INSN_JMPR_NE, "jmpr_ne", "jmpr", 16,
- { 0|A(COND_CTI)|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
- },
-/* jmpr $cond,$rel */
- {
- XC16X_INSN_JMPR_ULT, "jmpr_ult", "jmpr", 16,
- { 0|A(COND_CTI)|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
- },
-/* jmpr $cond,$rel */
- {
- XC16X_INSN_JMPR_ULE, "jmpr_ule", "jmpr", 16,
- { 0|A(COND_CTI)|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
- },
-/* jmpr $cond,$rel */
- {
- XC16X_INSN_JMPR_UGE, "jmpr_uge", "jmpr", 16,
- { 0|A(COND_CTI)|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
- },
-/* jmpr $cond,$rel */
- {
- XC16X_INSN_JMPR_UGT, "jmpr_ugt", "jmpr", 16,
- { 0|A(COND_CTI)|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
- },
-/* jmpr $cond,$rel */
- {
- XC16X_INSN_JMPR_SLE, "jmpr_sle", "jmpr", 16,
- { 0|A(COND_CTI)|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
- },
-/* jmpr $cond,$rel */
- {
- XC16X_INSN_JMPR_SGE, "jmpr_sge", "jmpr", 16,
- { 0|A(COND_CTI)|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
- },
-/* jmpr $cond,$rel */
- {
- XC16X_INSN_JMPR_NET, "jmpr_net", "jmpr", 16,
- { 0|A(COND_CTI)|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
- },
-/* jmpr $cond,$rel */
- {
- XC16X_INSN_JMPR_UC, "jmpr_uc", "jmpr", 16,
- { 0|A(COND_CTI)|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
- },
-/* jmpr $cond,$rel */
- {
- XC16X_INSN_JMPR_SLT, "jmpr_slt", "jmpr", 16,
- { 0|A(COND_CTI)|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
- },
-/* jmps $hash$segm$useg8,$hash$sof$usof16 */
- {
- XC16X_INSN_JMPSEG, "jmpseg", "jmps", 32,
- { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
- },
-/* jmps $seg,$caddr */
- {
- XC16X_INSN_JMPS, "jmps", "jmps", 32,
- { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
- },
-/* jb $genreg$dot$qlobit,$relhi */
- {
- XC16X_INSN_JB, "jb", "jb", 32,
- { 0|A(UNCOND_CTI)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
- },
-/* jbc $genreg$dot$qlobit,$relhi */
- {
- XC16X_INSN_JBC, "jbc", "jbc", 32,
- { 0|A(UNCOND_CTI)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
- },
-/* jnb $genreg$dot$qlobit,$relhi */
- {
- XC16X_INSN_JNB, "jnb", "jnb", 32,
- { 0|A(UNCOND_CTI)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
- },
-/* jnbs $genreg$dot$qlobit,$relhi */
- {
- XC16X_INSN_JNBS, "jnbs", "jnbs", 32,
- { 0|A(UNCOND_CTI)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
- },
-/* calla+ $extcond,$caddr */
- {
- XC16X_INSN_CALLA0, "calla0", "calla+", 32,
- { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
- },
-/* calla $extcond,$caddr */
- {
- XC16X_INSN_CALLA1, "calla1", "calla", 32,
- { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
- },
-/* calla- $extcond,$caddr */
- {
- XC16X_INSN_CALLA_, "calla-", "calla-", 32,
- { 0|A(COND_CTI)|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
- },
-/* calli $icond,[$sr] */
- {
- XC16X_INSN_CALLI, "calli", "calli", 16,
- { 0|A(COND_CTI)|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
- },
-/* callr $rel */
- {
- XC16X_INSN_CALLR, "callr", "callr", 16,
- { 0|A(COND_CTI)|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
- },
-/* calls $hash$segm$useg8,$hash$sof$usof16 */
- {
- XC16X_INSN_CALLSEG, "callseg", "calls", 32,
- { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
- },
-/* calls $seg,$caddr */
- {
- XC16X_INSN_CALLS, "calls", "calls", 32,
- { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
- },
-/* pcall $reg8,$caddr */
- {
- XC16X_INSN_PCALL, "pcall", "pcall", 32,
- { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
- },
-/* trap $hash$uimm7 */
- {
- XC16X_INSN_TRAP, "trap", "trap", 16,
- { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
- },
-/* ret */
- {
- XC16X_INSN_RET, "ret", "ret", 16,
- { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
- },
-/* rets */
- {
- XC16X_INSN_RETS, "rets", "rets", 16,
- { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
- },
-/* retp $reg8 */
- {
- XC16X_INSN_RETP, "retp", "retp", 16,
- { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
- },
-/* reti */
- {
- XC16X_INSN_RETI, "reti", "reti", 16,
- { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
- },
-/* pop $reg8 */
- {
- XC16X_INSN_POP, "pop", "pop", 16,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
- },
-/* push $reg8 */
- {
- XC16X_INSN_PUSH, "push", "push", 16,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
- },
-/* scxt $reg8,$hash$uimm16 */
- {
- XC16X_INSN_SCXTI, "scxti", "scxt", 32,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
- },
-/* scxt $reg8,$pof$upof16 */
- {
- XC16X_INSN_SCXTRPOFM, "scxtrpofm", "scxt", 32,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
- },
-/* scxt $regmem8,$memgr8 */
- {
- XC16X_INSN_SCXTMG, "scxtmg", "scxt", 32,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
- },
-/* scxt $reg8,$memory */
- {
- XC16X_INSN_SCXTM, "scxtm", "scxt", 32,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
- },
-/* nop */
- {
- XC16X_INSN_NOP, "nop", "nop", 16,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
- },
-/* srst */
- {
- XC16X_INSN_SRSTM, "srstm", "srst", 32,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
- },
-/* idle */
- {
- XC16X_INSN_IDLEM, "idlem", "idle", 32,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
- },
-/* pwrdn */
- {
- XC16X_INSN_PWRDNM, "pwrdnm", "pwrdn", 32,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
- },
-/* diswdt */
- {
- XC16X_INSN_DISWDTM, "diswdtm", "diswdt", 32,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
- },
-/* enwdt */
- {
- XC16X_INSN_ENWDTM, "enwdtm", "enwdt", 32,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
- },
-/* einit */
- {
- XC16X_INSN_EINITM, "einitm", "einit", 32,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
- },
-/* srvwdt */
- {
- XC16X_INSN_SRVWDTM, "srvwdtm", "srvwdt", 32,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
- },
-/* sbrk */
- {
- XC16X_INSN_SBRK, "sbrk", "sbrk", 16,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
- },
-/* atomic $hash$uimm2 */
- {
- XC16X_INSN_ATOMIC, "atomic", "atomic", 16,
- { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
- },
-/* extr $hash$uimm2 */
- {
- XC16X_INSN_EXTR, "extr", "extr", 16,
- { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
- },
-/* extp $sr,$hash$uimm2 */
- {
- XC16X_INSN_EXTP, "extp", "extp", 16,
- { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
- },
-/* extp $hash$pagenum,$hash$uimm2 */
- {
- XC16X_INSN_EXTP1, "extp1", "extp", 32,
- { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
- },
-/* extp $hash$pag$upag16,$hash$uimm2 */
- {
- XC16X_INSN_EXTPG1, "extpg1", "extp", 32,
- { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
- },
-/* extpr $sr,$hash$uimm2 */
- {
- XC16X_INSN_EXTPR, "extpr", "extpr", 16,
- { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
- },
-/* extpr $hash$pagenum,$hash$uimm2 */
- {
- XC16X_INSN_EXTPR1, "extpr1", "extpr", 32,
- { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
- },
-/* exts $sr,$hash$uimm2 */
- {
- XC16X_INSN_EXTS, "exts", "exts", 16,
- { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
- },
-/* exts $hash$seghi8,$hash$uimm2 */
- {
- XC16X_INSN_EXTS1, "exts1", "exts", 32,
- { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
- },
-/* extsr $sr,$hash$uimm2 */
- {
- XC16X_INSN_EXTSR, "extsr", "extsr", 16,
- { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
- },
-/* extsr $hash$seghi8,$hash$uimm2 */
- {
- XC16X_INSN_EXTSR1, "extsr1", "extsr", 32,
- { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
- },
-/* prior $dr,$sr */
- {
- XC16X_INSN_PRIOR, "prior", "prior", 16,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
- },
-/* bclr $RegNam */
- {
- XC16X_INSN_BCLR18, "bclr18", "bclr", 16,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
- },
-/* bclr $reg8$dot$qbit */
- {
- XC16X_INSN_BCLR0, "bclr0", "bclr", 16,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
- },
-/* bclr $reg8$dot$qbit */
- {
- XC16X_INSN_BCLR1, "bclr1", "bclr", 16,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
- },
-/* bclr $reg8$dot$qbit */
- {
- XC16X_INSN_BCLR2, "bclr2", "bclr", 16,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
- },
-/* bclr $reg8$dot$qbit */
- {
- XC16X_INSN_BCLR3, "bclr3", "bclr", 16,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
- },
-/* bclr $reg8$dot$qbit */
- {
- XC16X_INSN_BCLR4, "bclr4", "bclr", 16,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
- },
-/* bclr $reg8$dot$qbit */
- {
- XC16X_INSN_BCLR5, "bclr5", "bclr", 16,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
- },
-/* bclr $reg8$dot$qbit */
- {
- XC16X_INSN_BCLR6, "bclr6", "bclr", 16,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
- },
-/* bclr $reg8$dot$qbit */
- {
- XC16X_INSN_BCLR7, "bclr7", "bclr", 16,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
- },
-/* bclr $reg8$dot$qbit */
- {
- XC16X_INSN_BCLR8, "bclr8", "bclr", 16,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
- },
-/* bclr $reg8$dot$qbit */
- {
- XC16X_INSN_BCLR9, "bclr9", "bclr", 16,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
- },
-/* bclr $reg8$dot$qbit */
- {
- XC16X_INSN_BCLR10, "bclr10", "bclr", 16,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
- },
-/* bclr $reg8$dot$qbit */
- {
- XC16X_INSN_BCLR11, "bclr11", "bclr", 16,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
- },
-/* bclr $reg8$dot$qbit */
- {
- XC16X_INSN_BCLR12, "bclr12", "bclr", 16,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
- },
-/* bclr $reg8$dot$qbit */
- {
- XC16X_INSN_BCLR13, "bclr13", "bclr", 16,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
- },
-/* bclr $reg8$dot$qbit */
- {
- XC16X_INSN_BCLR14, "bclr14", "bclr", 16,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
- },
-/* bclr $reg8$dot$qbit */
- {
- XC16X_INSN_BCLR15, "bclr15", "bclr", 16,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
- },
-/* bset $RegNam */
- {
- XC16X_INSN_BSET19, "bset19", "bset", 16,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
- },
-/* bset $reg8$dot$qbit */
- {
- XC16X_INSN_BSET0, "bset0", "bset", 16,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
- },
-/* bset $reg8$dot$qbit */
- {
- XC16X_INSN_BSET1, "bset1", "bset", 16,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
- },
-/* bset $reg8$dot$qbit */
- {
- XC16X_INSN_BSET2, "bset2", "bset", 16,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
- },
-/* bset $reg8$dot$qbit */
- {
- XC16X_INSN_BSET3, "bset3", "bset", 16,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
- },
-/* bset $reg8$dot$qbit */
- {
- XC16X_INSN_BSET4, "bset4", "bset", 16,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
- },
-/* bset $reg8$dot$qbit */
- {
- XC16X_INSN_BSET5, "bset5", "bset", 16,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
- },
-/* bset $reg8$dot$qbit */
- {
- XC16X_INSN_BSET6, "bset6", "bset", 16,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
- },
-/* bset $reg8$dot$qbit */
- {
- XC16X_INSN_BSET7, "bset7", "bset", 16,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
- },
-/* bset $reg8$dot$qbit */
- {
- XC16X_INSN_BSET8, "bset8", "bset", 16,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
- },
-/* bset $reg8$dot$qbit */
- {
- XC16X_INSN_BSET9, "bset9", "bset", 16,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
- },
-/* bset $reg8$dot$qbit */
- {
- XC16X_INSN_BSET10, "bset10", "bset", 16,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
- },
-/* bset $reg8$dot$qbit */
- {
- XC16X_INSN_BSET11, "bset11", "bset", 16,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
- },
-/* bset $reg8$dot$qbit */
- {
- XC16X_INSN_BSET12, "bset12", "bset", 16,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
- },
-/* bset $reg8$dot$qbit */
- {
- XC16X_INSN_BSET13, "bset13", "bset", 16,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
- },
-/* bset $reg8$dot$qbit */
- {
- XC16X_INSN_BSET14, "bset14", "bset", 16,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
- },
-/* bset $reg8$dot$qbit */
- {
- XC16X_INSN_BSET15, "bset15", "bset", 16,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
- },
-/* bmov $reghi8$dot$qhibit,$reg8$dot$qlobit */
- {
- XC16X_INSN_BMOV, "bmov", "bmov", 32,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
- },
-/* bmovn $reghi8$dot$qhibit,$reg8$dot$qlobit */
- {
- XC16X_INSN_BMOVN, "bmovn", "bmovn", 32,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
- },
-/* band $reghi8$dot$qhibit,$reg8$dot$qlobit */
- {
- XC16X_INSN_BAND, "band", "band", 32,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
- },
-/* bor $reghi8$dot$qhibit,$reg8$dot$qlobit */
- {
- XC16X_INSN_BOR, "bor", "bor", 32,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
- },
-/* bxor $reghi8$dot$qhibit,$reg8$dot$qlobit */
- {
- XC16X_INSN_BXOR, "bxor", "bxor", 32,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
- },
-/* bcmp $reghi8$dot$qhibit,$reg8$dot$qlobit */
- {
- XC16X_INSN_BCMP, "bcmp", "bcmp", 32,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
- },
-/* bfldl $reg8,$hash$mask8,$hash$datahi8 */
- {
- XC16X_INSN_BFLDL, "bfldl", "bfldl", 32,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
- },
-/* bfldh $reg8,$hash$masklo8,$hash$data8 */
- {
- XC16X_INSN_BFLDH, "bfldh", "bfldh", 32,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
- },
-/* cmp $src1,$src2 */
- {
- XC16X_INSN_CMPR, "cmpr", "cmp", 16,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
- },
-/* cmpb $drb,$srb */
- {
- XC16X_INSN_CMPBR, "cmpbr", "cmpb", 16,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
- },
-/* cmp $src1,$hash$uimm3 */
- {
- XC16X_INSN_CMPRI, "cmpri", "cmp", 16,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
- },
-/* cmpb $drb,$hash$uimm3 */
- {
- XC16X_INSN_CMPBRI, "cmpbri", "cmpb", 16,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
- },
-/* cmp $reg8,$hash$uimm16 */
- {
- XC16X_INSN_CMPI, "cmpi", "cmp", 32,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
- },
-/* cmpb $regb8,$hash$uimm8 */
- {
- XC16X_INSN_CMPBI, "cmpbi", "cmpb", 32,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
- },
-/* cmp $dr,[$sr2] */
- {
- XC16X_INSN_CMPR2, "cmpr2", "cmp", 16,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
- },
-/* cmpb $drb,[$sr2] */
- {
- XC16X_INSN_CMPBR2, "cmpbr2", "cmpb", 16,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
- },
-/* cmp $dr,[$sr2+] */
- {
- XC16X_INSN_CMP2I, "cmp2i", "cmp", 16,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
- },
-/* cmpb $drb,[$sr2+] */
- {
- XC16X_INSN_CMPB2I, "cmpb2i", "cmpb", 16,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
- },
-/* cmp $reg8,$pof$upof16 */
- {
- XC16X_INSN_CMP04, "cmp04", "cmp", 32,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
- },
-/* cmpb $regb8,$pof$upof16 */
- {
- XC16X_INSN_CMPB4, "cmpb4", "cmpb", 32,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
- },
-/* cmp $regmem8,$memgr8 */
- {
- XC16X_INSN_CMP004, "cmp004", "cmp", 32,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
- },
-/* cmp $reg8,$memory */
- {
- XC16X_INSN_CMP0004, "cmp0004", "cmp", 32,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
- },
-/* cmpb $regbmem8,$memgr8 */
- {
- XC16X_INSN_CMPB04, "cmpb04", "cmpb", 32,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
- },
-/* cmpb $regb8,$memory */
- {
- XC16X_INSN_CMPB004, "cmpb004", "cmpb", 32,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
- },
-/* cmpd1 $sr,$hash$uimm4 */
- {
- XC16X_INSN_CMPD1RI, "cmpd1ri", "cmpd1", 16,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
- },
-/* cmpd2 $sr,$hash$uimm4 */
- {
- XC16X_INSN_CMPD2RI, "cmpd2ri", "cmpd2", 16,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
- },
-/* cmpi1 $sr,$hash$uimm4 */
- {
- XC16X_INSN_CMPI1RI, "cmpi1ri", "cmpi1", 16,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
- },
-/* cmpi2 $sr,$hash$uimm4 */
- {
- XC16X_INSN_CMPI2RI, "cmpi2ri", "cmpi2", 16,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
- },
-/* cmpd1 $reg8,$hash$uimm16 */
- {
- XC16X_INSN_CMPD1RIM, "cmpd1rim", "cmpd1", 32,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
- },
-/* cmpd2 $reg8,$hash$uimm16 */
- {
- XC16X_INSN_CMPD2RIM, "cmpd2rim", "cmpd2", 32,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
- },
-/* cmpi1 $reg8,$hash$uimm16 */
- {
- XC16X_INSN_CMPI1RIM, "cmpi1rim", "cmpi1", 32,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
- },
-/* cmpi2 $reg8,$hash$uimm16 */
- {
- XC16X_INSN_CMPI2RIM, "cmpi2rim", "cmpi2", 32,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
- },
-/* cmpd1 $reg8,$pof$upof16 */
- {
- XC16X_INSN_CMPD1RP, "cmpd1rp", "cmpd1", 32,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
- },
-/* cmpd2 $reg8,$pof$upof16 */
- {
- XC16X_INSN_CMPD2RP, "cmpd2rp", "cmpd2", 32,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
- },
-/* cmpi1 $reg8,$pof$upof16 */
- {
- XC16X_INSN_CMPI1RP, "cmpi1rp", "cmpi1", 32,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
- },
-/* cmpi2 $reg8,$pof$upof16 */
- {
- XC16X_INSN_CMPI2RP, "cmpi2rp", "cmpi2", 32,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
- },
-/* cmpd1 $regmem8,$memgr8 */
- {
- XC16X_INSN_CMPD1RM, "cmpd1rm", "cmpd1", 32,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
- },
-/* cmpd2 $regmem8,$memgr8 */
- {
- XC16X_INSN_CMPD2RM, "cmpd2rm", "cmpd2", 32,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
- },
-/* cmpi1 $regmem8,$memgr8 */
- {
- XC16X_INSN_CMPI1RM, "cmpi1rm", "cmpi1", 32,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
- },
-/* cmpi2 $regmem8,$memgr8 */
- {
- XC16X_INSN_CMPI2RM, "cmpi2rm", "cmpi2", 32,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
- },
-/* cmpd1 $reg8,$memory */
- {
- XC16X_INSN_CMPD1RMI, "cmpd1rmi", "cmpd1", 32,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
- },
-/* cmpd2 $reg8,$memory */
- {
- XC16X_INSN_CMPD2RMI, "cmpd2rmi", "cmpd2", 32,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
- },
-/* cmpi1 $reg8,$memory */
- {
- XC16X_INSN_CMPI1RMI, "cmpi1rmi", "cmpi1", 32,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
- },
-/* cmpi2 $reg8,$memory */
- {
- XC16X_INSN_CMPI2RMI, "cmpi2rmi", "cmpi2", 32,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
- },
-/* shl $dr,$sr */
- {
- XC16X_INSN_SHLR, "shlr", "shl", 16,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
- },
-/* shr $dr,$sr */
- {
- XC16X_INSN_SHRR, "shrr", "shr", 16,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
- },
-/* rol $dr,$sr */
- {
- XC16X_INSN_ROLR, "rolr", "rol", 16,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
- },
-/* ror $dr,$sr */
- {
- XC16X_INSN_RORR, "rorr", "ror", 16,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
- },
-/* ashr $dr,$sr */
- {
- XC16X_INSN_ASHRR, "ashrr", "ashr", 16,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
- },
-/* shl $sr,$hash$uimm4 */
- {
- XC16X_INSN_SHLRI, "shlri", "shl", 16,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
- },
-/* shr $sr,$hash$uimm4 */
- {
- XC16X_INSN_SHRRI, "shrri", "shr", 16,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
- },
-/* rol $sr,$hash$uimm4 */
- {
- XC16X_INSN_ROLRI, "rolri", "rol", 16,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
- },
-/* ror $sr,$hash$uimm4 */
- {
- XC16X_INSN_RORRI, "rorri", "ror", 16,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
- },
-/* ashr $sr,$hash$uimm4 */
- {
- XC16X_INSN_ASHRRI, "ashrri", "ashr", 16,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
- },
-};
-
-#undef OP
-#undef A
-
-/* Initialize anything needed to be done once, before any cpu_open call. */
-
-static void
-init_tables (void)
-{
-}
-
-#ifndef opcodes_error_handler
-#define opcodes_error_handler(...) \
- fprintf (stderr, __VA_ARGS__); fputc ('\n', stderr)
-#endif
-
-static const CGEN_MACH * lookup_mach_via_bfd_name (const CGEN_MACH *, const char *);
-static void build_hw_table (CGEN_CPU_TABLE *);
-static void build_ifield_table (CGEN_CPU_TABLE *);
-static void build_operand_table (CGEN_CPU_TABLE *);
-static void build_insn_table (CGEN_CPU_TABLE *);
-static void xc16x_cgen_rebuild_tables (CGEN_CPU_TABLE *);
-
-/* Subroutine of xc16x_cgen_cpu_open to look up a mach via its bfd name. */
-
-static const CGEN_MACH *
-lookup_mach_via_bfd_name (const CGEN_MACH *table, const char *name)
-{
- while (table->name)
- {
- if (strcmp (name, table->bfd_name) == 0)
- return table;
- ++table;
- }
- return NULL;
-}
-
-/* Subroutine of xc16x_cgen_cpu_open to build the hardware table. */
-
-static void
-build_hw_table (CGEN_CPU_TABLE *cd)
-{
- int i;
- int machs = cd->machs;
- const CGEN_HW_ENTRY *init = & xc16x_cgen_hw_table[0];
- /* MAX_HW is only an upper bound on the number of selected entries.
- However each entry is indexed by it's enum so there can be holes in
- the table. */
- const CGEN_HW_ENTRY **selected =
- (const CGEN_HW_ENTRY **) xmalloc (MAX_HW * sizeof (CGEN_HW_ENTRY *));
-
- cd->hw_table.init_entries = init;
- cd->hw_table.entry_size = sizeof (CGEN_HW_ENTRY);
- memset (selected, 0, MAX_HW * sizeof (CGEN_HW_ENTRY *));
- /* ??? For now we just use machs to determine which ones we want. */
- for (i = 0; init[i].name != NULL; ++i)
- if (CGEN_HW_ATTR_VALUE (&init[i], CGEN_HW_MACH)
- & machs)
- selected[init[i].type] = &init[i];
- cd->hw_table.entries = selected;
- cd->hw_table.num_entries = MAX_HW;
-}
-
-/* Subroutine of xc16x_cgen_cpu_open to build the hardware table. */
-
-static void
-build_ifield_table (CGEN_CPU_TABLE *cd)
-{
- cd->ifld_table = & xc16x_cgen_ifld_table[0];
-}
-
-/* Subroutine of xc16x_cgen_cpu_open to build the hardware table. */
-
-static void
-build_operand_table (CGEN_CPU_TABLE *cd)
-{
- int i;
- int machs = cd->machs;
- const CGEN_OPERAND *init = & xc16x_cgen_operand_table[0];
- /* MAX_OPERANDS is only an upper bound on the number of selected entries.
- However each entry is indexed by it's enum so there can be holes in
- the table. */
- const CGEN_OPERAND **selected = xmalloc (MAX_OPERANDS * sizeof (* selected));
-
- cd->operand_table.init_entries = init;
- cd->operand_table.entry_size = sizeof (CGEN_OPERAND);
- memset (selected, 0, MAX_OPERANDS * sizeof (CGEN_OPERAND *));
- /* ??? For now we just use mach to determine which ones we want. */
- for (i = 0; init[i].name != NULL; ++i)
- if (CGEN_OPERAND_ATTR_VALUE (&init[i], CGEN_OPERAND_MACH)
- & machs)
- selected[init[i].type] = &init[i];
- cd->operand_table.entries = selected;
- cd->operand_table.num_entries = MAX_OPERANDS;
-}
-
-/* Subroutine of xc16x_cgen_cpu_open to build the hardware table.
- ??? This could leave out insns not supported by the specified mach/isa,
- but that would cause errors like "foo only supported by bar" to become
- "unknown insn", so for now we include all insns and require the app to
- do the checking later.
- ??? On the other hand, parsing of such insns may require their hardware or
- operand elements to be in the table [which they mightn't be]. */
-
-static void
-build_insn_table (CGEN_CPU_TABLE *cd)
-{
- int i;
- const CGEN_IBASE *ib = & xc16x_cgen_insn_table[0];
- CGEN_INSN *insns = xmalloc (MAX_INSNS * sizeof (CGEN_INSN));
-
- memset (insns, 0, MAX_INSNS * sizeof (CGEN_INSN));
- for (i = 0; i < MAX_INSNS; ++i)
- insns[i].base = &ib[i];
- cd->insn_table.init_entries = insns;
- cd->insn_table.entry_size = sizeof (CGEN_IBASE);
- cd->insn_table.num_init_entries = MAX_INSNS;
-}
-
-/* Subroutine of xc16x_cgen_cpu_open to rebuild the tables. */
-
-static void
-xc16x_cgen_rebuild_tables (CGEN_CPU_TABLE *cd)
-{
- int i;
- CGEN_BITSET *isas = cd->isas;
- unsigned int machs = cd->machs;
-
- cd->int_insn_p = CGEN_INT_INSN_P;
-
- /* Data derived from the isa spec. */
-#define UNSET (CGEN_SIZE_UNKNOWN + 1)
- cd->default_insn_bitsize = UNSET;
- cd->base_insn_bitsize = UNSET;
- cd->min_insn_bitsize = 65535; /* Some ridiculously big number. */
- cd->max_insn_bitsize = 0;
- for (i = 0; i < MAX_ISAS; ++i)
- if (cgen_bitset_contains (isas, i))
- {
- const CGEN_ISA *isa = & xc16x_cgen_isa_table[i];
-
- /* Default insn sizes of all selected isas must be
- equal or we set the result to 0, meaning "unknown". */
- if (cd->default_insn_bitsize == UNSET)
- cd->default_insn_bitsize = isa->default_insn_bitsize;
- else if (isa->default_insn_bitsize == cd->default_insn_bitsize)
- ; /* This is ok. */
- else
- cd->default_insn_bitsize = CGEN_SIZE_UNKNOWN;
-
- /* Base insn sizes of all selected isas must be equal
- or we set the result to 0, meaning "unknown". */
- if (cd->base_insn_bitsize == UNSET)
- cd->base_insn_bitsize = isa->base_insn_bitsize;
- else if (isa->base_insn_bitsize == cd->base_insn_bitsize)
- ; /* This is ok. */
- else
- cd->base_insn_bitsize = CGEN_SIZE_UNKNOWN;
-
- /* Set min,max insn sizes. */
- if (isa->min_insn_bitsize < cd->min_insn_bitsize)
- cd->min_insn_bitsize = isa->min_insn_bitsize;
- if (isa->max_insn_bitsize > cd->max_insn_bitsize)
- cd->max_insn_bitsize = isa->max_insn_bitsize;
- }
-
- /* Data derived from the mach spec. */
- for (i = 0; i < MAX_MACHS; ++i)
- if (((1 << i) & machs) != 0)
- {
- const CGEN_MACH *mach = & xc16x_cgen_mach_table[i];
-
- if (mach->insn_chunk_bitsize != 0)
- {
- if (cd->insn_chunk_bitsize != 0 && cd->insn_chunk_bitsize != mach->insn_chunk_bitsize)
- {
- opcodes_error_handler
- (/* xgettext:c-format */
- _("internal error: xc16x_cgen_rebuild_tables: "
- "conflicting insn-chunk-bitsize values: `%d' vs. `%d'"),
- cd->insn_chunk_bitsize, mach->insn_chunk_bitsize);
- abort ();
- }
-
- cd->insn_chunk_bitsize = mach->insn_chunk_bitsize;
- }
- }
-
- /* Determine which hw elements are used by MACH. */
- build_hw_table (cd);
-
- /* Build the ifield table. */
- build_ifield_table (cd);
-
- /* Determine which operands are used by MACH/ISA. */
- build_operand_table (cd);
-
- /* Build the instruction table. */
- build_insn_table (cd);
-}
-
-/* Initialize a cpu table and return a descriptor.
- It's much like opening a file, and must be the first function called.
- The arguments are a set of (type/value) pairs, terminated with
- CGEN_CPU_OPEN_END.
-
- Currently supported values:
- CGEN_CPU_OPEN_ISAS: bitmap of values in enum isa_attr
- CGEN_CPU_OPEN_MACHS: bitmap of values in enum mach_attr
- CGEN_CPU_OPEN_BFDMACH: specify 1 mach using bfd name
- CGEN_CPU_OPEN_ENDIAN: specify endian choice
- CGEN_CPU_OPEN_INSN_ENDIAN: specify instruction endian choice
- CGEN_CPU_OPEN_END: terminates arguments
-
- ??? Simultaneous multiple isas might not make sense, but it's not (yet)
- precluded. */
-
-CGEN_CPU_DESC
-xc16x_cgen_cpu_open (enum cgen_cpu_open_arg arg_type, ...)
-{
- CGEN_CPU_TABLE *cd = (CGEN_CPU_TABLE *) xmalloc (sizeof (CGEN_CPU_TABLE));
- static int init_p;
- CGEN_BITSET *isas = 0; /* 0 = "unspecified" */
- unsigned int machs = 0; /* 0 = "unspecified" */
- enum cgen_endian endian = CGEN_ENDIAN_UNKNOWN;
- enum cgen_endian insn_endian = CGEN_ENDIAN_UNKNOWN;
- va_list ap;
-
- if (! init_p)
- {
- init_tables ();
- init_p = 1;
- }
-
- memset (cd, 0, sizeof (*cd));
-
- va_start (ap, arg_type);
- while (arg_type != CGEN_CPU_OPEN_END)
- {
- switch (arg_type)
- {
- case CGEN_CPU_OPEN_ISAS :
- isas = va_arg (ap, CGEN_BITSET *);
- break;
- case CGEN_CPU_OPEN_MACHS :
- machs = va_arg (ap, unsigned int);
- break;
- case CGEN_CPU_OPEN_BFDMACH :
- {
- const char *name = va_arg (ap, const char *);
- const CGEN_MACH *mach =
- lookup_mach_via_bfd_name (xc16x_cgen_mach_table, name);
-
- if (mach != NULL)
- machs |= 1 << mach->num;
- break;
- }
- case CGEN_CPU_OPEN_ENDIAN :
- endian = va_arg (ap, enum cgen_endian);
- break;
- case CGEN_CPU_OPEN_INSN_ENDIAN :
- insn_endian = va_arg (ap, enum cgen_endian);
- break;
- default :
- opcodes_error_handler
- (/* xgettext:c-format */
- _("internal error: xc16x_cgen_cpu_open: "
- "unsupported argument `%d'"),
- arg_type);
- abort (); /* ??? return NULL? */
- }
- arg_type = va_arg (ap, enum cgen_cpu_open_arg);
- }
- va_end (ap);
-
- /* Mach unspecified means "all". */
- if (machs == 0)
- machs = (1 << MAX_MACHS) - 1;
- /* Base mach is always selected. */
- machs |= 1;
- if (endian == CGEN_ENDIAN_UNKNOWN)
- {
- /* ??? If target has only one, could have a default. */
- opcodes_error_handler
- (/* xgettext:c-format */
- _("internal error: xc16x_cgen_cpu_open: no endianness specified"));
- abort ();
- }
-
- cd->isas = cgen_bitset_copy (isas);
- cd->machs = machs;
- cd->endian = endian;
- cd->insn_endian
- = (insn_endian == CGEN_ENDIAN_UNKNOWN ? endian : insn_endian);
-
- /* Table (re)builder. */
- cd->rebuild_tables = xc16x_cgen_rebuild_tables;
- xc16x_cgen_rebuild_tables (cd);
-
- /* Default to not allowing signed overflow. */
- cd->signed_overflow_ok_p = 0;
-
- return (CGEN_CPU_DESC) cd;
-}
-
-/* Cover fn to xc16x_cgen_cpu_open to handle the simple case of 1 isa, 1 mach.
- MACH_NAME is the bfd name of the mach. */
-
-CGEN_CPU_DESC
-xc16x_cgen_cpu_open_1 (const char *mach_name, enum cgen_endian endian)
-{
- return xc16x_cgen_cpu_open (CGEN_CPU_OPEN_BFDMACH, mach_name,
- CGEN_CPU_OPEN_ENDIAN, endian,
- CGEN_CPU_OPEN_END);
-}
-
-/* Close a cpu table.
- ??? This can live in a machine independent file, but there's currently
- no place to put this file (there's no libcgen). libopcodes is the wrong
- place as some simulator ports use this but they don't use libopcodes. */
-
-void
-xc16x_cgen_cpu_close (CGEN_CPU_DESC cd)
-{
- unsigned int i;
- const CGEN_INSN *insns;
-
- if (cd->macro_insn_table.init_entries)
- {
- insns = cd->macro_insn_table.init_entries;
- for (i = 0; i < cd->macro_insn_table.num_init_entries; ++i, ++insns)
- if (CGEN_INSN_RX ((insns)))
- regfree (CGEN_INSN_RX (insns));
- }
-
- if (cd->insn_table.init_entries)
- {
- insns = cd->insn_table.init_entries;
- for (i = 0; i < cd->insn_table.num_init_entries; ++i, ++insns)
- if (CGEN_INSN_RX (insns))
- regfree (CGEN_INSN_RX (insns));
- }
-
- free ((CGEN_INSN *) cd->macro_insn_table.init_entries);
- free ((CGEN_INSN *) cd->insn_table.init_entries);
- free ((CGEN_HW_ENTRY *) cd->hw_table.entries);
- free ((CGEN_HW_ENTRY *) cd->operand_table.entries);
- free (cd);
-}
-
+++ /dev/null
-/* DO NOT EDIT! -*- buffer-read-only: t -*- vi:set ro: */
-/* CPU data header for xc16x.
-
-THIS FILE IS MACHINE GENERATED WITH CGEN.
-
-Copyright (C) 1996-2022 Free Software Foundation, Inc.
-
-This file is part of the GNU Binutils and/or GDB, the GNU debugger.
-
- This file is free software; you can redistribute it and/or modify
- it under the terms of the GNU General Public License as published by
- the Free Software Foundation; either version 3, or (at your option)
- any later version.
-
- It is distributed in the hope that it will be useful, but WITHOUT
- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
- License for more details.
-
- You should have received a copy of the GNU General Public License along
- with this program; if not, write to the Free Software Foundation, Inc.,
- 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.
-
-*/
-
-#ifndef XC16X_CPU_H
-#define XC16X_CPU_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#define CGEN_ARCH xc16x
-
-/* Given symbol S, return xc16x_cgen_<S>. */
-#define CGEN_SYM(s) xc16x##_cgen_##s
-
-
-/* Selected cpu families. */
-#define HAVE_CPU_XC16XBF
-
-#define CGEN_INSN_LSB0_P 1
-
-/* Minimum size of any insn (in bytes). */
-#define CGEN_MIN_INSN_SIZE 2
-
-/* Maximum size of any insn (in bytes). */
-#define CGEN_MAX_INSN_SIZE 4
-
-#define CGEN_INT_INSN_P 1
-
-/* Maximum number of syntax elements in an instruction. */
-#define CGEN_ACTUAL_MAX_SYNTAX_ELEMENTS 15
-
-/* CGEN_MNEMONIC_OPERANDS is defined if mnemonics have operands.
- e.g. In "b,a foo" the ",a" is an operand. If mnemonics have operands
- we can't hash on everything up to the space. */
-#define CGEN_MNEMONIC_OPERANDS
-
-/* Maximum number of fields in an instruction. */
-#define CGEN_ACTUAL_MAX_IFMT_OPERANDS 8
-
-/* Enums. */
-
-/* Enum declaration for insn format enums. */
-typedef enum insn_op1 {
- OP1_0, OP1_1, OP1_2, OP1_3
- , OP1_4, OP1_5, OP1_6, OP1_7
- , OP1_8, OP1_9, OP1_10, OP1_11
- , OP1_12, OP1_13, OP1_14, OP1_15
-} INSN_OP1;
-
-/* Enum declaration for op2 enums. */
-typedef enum insn_op2 {
- OP2_0, OP2_1, OP2_2, OP2_3
- , OP2_4, OP2_5, OP2_6, OP2_7
- , OP2_8, OP2_9, OP2_10, OP2_11
- , OP2_12, OP2_13, OP2_14, OP2_15
-} INSN_OP2;
-
-/* Enum declaration for bit set/clear enums. */
-typedef enum insn_qcond {
- QBIT_0, QBIT_1, QBIT_2, QBIT_3
- , QBIT_4, QBIT_5, QBIT_6, QBIT_7
- , QBIT_8, QBIT_9, QBIT_10, QBIT_11
- , QBIT_12, QBIT_13, QBIT_14, QBIT_15
-} INSN_QCOND;
-
-/* Enum declaration for relative jump condition code op2 enums. */
-typedef enum insn_rcond {
- COND_UC = 0, COND_NET = 1, COND_Z = 2, COND_NE_NZ = 3
- , COND_V = 4, COND_NV = 5, COND_N = 6, COND_NN = 7
- , COND_C = 8, COND_NC = 9, COND_SGT = 10, COND_SLE = 11
- , COND_SLT = 12, COND_SGE = 13, COND_UGT = 14, COND_ULE = 15
- , COND_EQ = 2, COND_NE = 3, COND_ULT = 8, COND_UGE = 9
-} INSN_RCOND;
-
-/* Enum declaration for . */
-typedef enum gr_names {
- H_GR_R0, H_GR_R1, H_GR_R2, H_GR_R3
- , H_GR_R4, H_GR_R5, H_GR_R6, H_GR_R7
- , H_GR_R8, H_GR_R9, H_GR_R10, H_GR_R11
- , H_GR_R12, H_GR_R13, H_GR_R14, H_GR_R15
-} GR_NAMES;
-
-/* Enum declaration for . */
-typedef enum ext_names {
- H_EXT_0X1 = 0, H_EXT_0X2 = 1, H_EXT_0X3 = 2, H_EXT_0X4 = 3
- , H_EXT_1 = 0, H_EXT_2 = 1, H_EXT_3 = 2, H_EXT_4 = 3
-} EXT_NAMES;
-
-/* Enum declaration for . */
-typedef enum psw_names {
- H_PSW_IEN = 136, H_PSW_R0_11 = 240, H_PSW_R1_11 = 241, H_PSW_R2_11 = 242
- , H_PSW_R3_11 = 243, H_PSW_R4_11 = 244, H_PSW_R5_11 = 245, H_PSW_R6_11 = 246
- , H_PSW_R7_11 = 247, H_PSW_R8_11 = 248, H_PSW_R9_11 = 249, H_PSW_R10_11 = 250
- , H_PSW_R11_11 = 251, H_PSW_R12_11 = 252, H_PSW_R13_11 = 253, H_PSW_R14_11 = 254
- , H_PSW_R15_11 = 255
-} PSW_NAMES;
-
-/* Enum declaration for . */
-typedef enum grb_names {
- H_GRB_RL0, H_GRB_RH0, H_GRB_RL1, H_GRB_RH1
- , H_GRB_RL2, H_GRB_RH2, H_GRB_RL3, H_GRB_RH3
- , H_GRB_RL4, H_GRB_RH4, H_GRB_RL5, H_GRB_RH5
- , H_GRB_RL6, H_GRB_RH6, H_GRB_RL7, H_GRB_RH7
-} GRB_NAMES;
-
-/* Enum declaration for . */
-typedef enum conditioncode_names {
- H_CC_CC_UC = 0, H_CC_CC_NET = 1, H_CC_CC_Z = 2, H_CC_CC_EQ = 2
- , H_CC_CC_NZ = 3, H_CC_CC_NE = 3, H_CC_CC_V = 4, H_CC_CC_NV = 5
- , H_CC_CC_N = 6, H_CC_CC_NN = 7, H_CC_CC_ULT = 8, H_CC_CC_UGE = 9
- , H_CC_CC_C = 8, H_CC_CC_NC = 9, H_CC_CC_SGT = 10, H_CC_CC_SLE = 11
- , H_CC_CC_SLT = 12, H_CC_CC_SGE = 13, H_CC_CC_UGT = 14, H_CC_CC_ULE = 15
-} CONDITIONCODE_NAMES;
-
-/* Enum declaration for . */
-typedef enum extconditioncode_names {
- H_ECC_CC_UC = 0, H_ECC_CC_NET = 2, H_ECC_CC_Z = 4, H_ECC_CC_EQ = 4
- , H_ECC_CC_NZ = 6, H_ECC_CC_NE = 6, H_ECC_CC_V = 8, H_ECC_CC_NV = 10
- , H_ECC_CC_N = 12, H_ECC_CC_NN = 14, H_ECC_CC_ULT = 16, H_ECC_CC_UGE = 18
- , H_ECC_CC_C = 16, H_ECC_CC_NC = 18, H_ECC_CC_SGT = 20, H_ECC_CC_SLE = 22
- , H_ECC_CC_SLT = 24, H_ECC_CC_SGE = 26, H_ECC_CC_UGT = 28, H_ECC_CC_ULE = 30
- , H_ECC_CC_NUSR0 = 1, H_ECC_CC_NUSR1 = 3, H_ECC_CC_USR0 = 5, H_ECC_CC_USR1 = 7
-} EXTCONDITIONCODE_NAMES;
-
-/* Enum declaration for . */
-typedef enum grb8_names {
- H_GRB8_DPP0 = 0, H_GRB8_DPP1 = 1, H_GRB8_DPP2 = 2, H_GRB8_DPP3 = 3
- , H_GRB8_PSW = 136, H_GRB8_CP = 8, H_GRB8_MDL = 7, H_GRB8_MDH = 6
- , H_GRB8_MDC = 135, H_GRB8_SP = 9, H_GRB8_CSP = 4, H_GRB8_VECSEG = 137
- , H_GRB8_STKOV = 10, H_GRB8_STKUN = 11, H_GRB8_CPUCON1 = 12, H_GRB8_CPUCON2 = 13
- , H_GRB8_ZEROS = 142, H_GRB8_ONES = 143, H_GRB8_SPSEG = 134, H_GRB8_TFR = 214
- , H_GRB8_RL0 = 240, H_GRB8_RH0 = 241, H_GRB8_RL1 = 242, H_GRB8_RH1 = 243
- , H_GRB8_RL2 = 244, H_GRB8_RH2 = 245, H_GRB8_RL3 = 246, H_GRB8_RH3 = 247
- , H_GRB8_RL4 = 248, H_GRB8_RH4 = 249, H_GRB8_RL5 = 250, H_GRB8_RH5 = 251
- , H_GRB8_RL6 = 252, H_GRB8_RH6 = 253, H_GRB8_RL7 = 254, H_GRB8_RH7 = 255
-} GRB8_NAMES;
-
-/* Enum declaration for . */
-typedef enum r8_names {
- H_R8_DPP0 = 0, H_R8_DPP1 = 1, H_R8_DPP2 = 2, H_R8_DPP3 = 3
- , H_R8_PSW = 136, H_R8_CP = 8, H_R8_MDL = 7, H_R8_MDH = 6
- , H_R8_MDC = 135, H_R8_SP = 9, H_R8_CSP = 4, H_R8_VECSEG = 137
- , H_R8_STKOV = 10, H_R8_STKUN = 11, H_R8_CPUCON1 = 12, H_R8_CPUCON2 = 13
- , H_R8_ZEROS = 142, H_R8_ONES = 143, H_R8_SPSEG = 134, H_R8_TFR = 214
- , H_R8_R0 = 240, H_R8_R1 = 241, H_R8_R2 = 242, H_R8_R3 = 243
- , H_R8_R4 = 244, H_R8_R5 = 245, H_R8_R6 = 246, H_R8_R7 = 247
- , H_R8_R8 = 248, H_R8_R9 = 249, H_R8_R10 = 250, H_R8_R11 = 251
- , H_R8_R12 = 252, H_R8_R13 = 253, H_R8_R14 = 254, H_R8_R15 = 255
-} R8_NAMES;
-
-/* Enum declaration for . */
-typedef enum regmem8_names {
- H_REGMEM8_DPP0 = 0, H_REGMEM8_DPP1 = 1, H_REGMEM8_DPP2 = 2, H_REGMEM8_DPP3 = 3
- , H_REGMEM8_PSW = 136, H_REGMEM8_CP = 8, H_REGMEM8_MDL = 7, H_REGMEM8_MDH = 6
- , H_REGMEM8_MDC = 135, H_REGMEM8_SP = 9, H_REGMEM8_CSP = 4, H_REGMEM8_VECSEG = 137
- , H_REGMEM8_STKOV = 10, H_REGMEM8_STKUN = 11, H_REGMEM8_CPUCON1 = 12, H_REGMEM8_CPUCON2 = 13
- , H_REGMEM8_ZEROS = 142, H_REGMEM8_ONES = 143, H_REGMEM8_SPSEG = 134, H_REGMEM8_TFR = 214
- , H_REGMEM8_R0 = 240, H_REGMEM8_R1 = 241, H_REGMEM8_R2 = 242, H_REGMEM8_R3 = 243
- , H_REGMEM8_R4 = 244, H_REGMEM8_R5 = 245, H_REGMEM8_R6 = 246, H_REGMEM8_R7 = 247
- , H_REGMEM8_R8 = 248, H_REGMEM8_R9 = 249, H_REGMEM8_R10 = 250, H_REGMEM8_R11 = 251
- , H_REGMEM8_R12 = 252, H_REGMEM8_R13 = 253, H_REGMEM8_R14 = 254, H_REGMEM8_R15 = 255
-} REGMEM8_NAMES;
-
-/* Enum declaration for . */
-typedef enum regdiv8_names {
- H_REGDIV8_R0 = 0, H_REGDIV8_R1 = 17, H_REGDIV8_R2 = 34, H_REGDIV8_R3 = 51
- , H_REGDIV8_R4 = 68, H_REGDIV8_R5 = 85, H_REGDIV8_R6 = 102, H_REGDIV8_R7 = 119
- , H_REGDIV8_R8 = 136, H_REGDIV8_R9 = 153, H_REGDIV8_R10 = 170, H_REGDIV8_R11 = 187
- , H_REGDIV8_R12 = 204, H_REGDIV8_R13 = 221, H_REGDIV8_R14 = 238, H_REGDIV8_R15 = 255
-} REGDIV8_NAMES;
-
-/* Enum declaration for . */
-typedef enum reg0_name {
- H_REG0_0X1 = 1, H_REG0_0X2 = 2, H_REG0_0X3 = 3, H_REG0_0X4 = 4
- , H_REG0_0X5 = 5, H_REG0_0X6 = 6, H_REG0_0X7 = 7, H_REG0_0X8 = 8
- , H_REG0_0X9 = 9, H_REG0_0XA = 10, H_REG0_0XB = 11, H_REG0_0XC = 12
- , H_REG0_0XD = 13, H_REG0_0XE = 14, H_REG0_0XF = 15, H_REG0_1 = 1
- , H_REG0_2 = 2, H_REG0_3 = 3, H_REG0_4 = 4, H_REG0_5 = 5
- , H_REG0_6 = 6, H_REG0_7 = 7, H_REG0_8 = 8, H_REG0_9 = 9
- , H_REG0_10 = 10, H_REG0_11 = 11, H_REG0_12 = 12, H_REG0_13 = 13
- , H_REG0_14 = 14, H_REG0_15 = 15
-} REG0_NAME;
-
-/* Enum declaration for . */
-typedef enum reg0_name1 {
- H_REG01_0X1 = 1, H_REG01_0X2 = 2, H_REG01_0X3 = 3, H_REG01_0X4 = 4
- , H_REG01_0X5 = 5, H_REG01_0X6 = 6, H_REG01_0X7 = 7, H_REG01_1 = 1
- , H_REG01_2 = 2, H_REG01_3 = 3, H_REG01_4 = 4, H_REG01_5 = 5
- , H_REG01_6 = 6, H_REG01_7 = 7
-} REG0_NAME1;
-
-/* Enum declaration for . */
-typedef enum regbmem8_names {
- H_REGBMEM8_DPP0 = 0, H_REGBMEM8_DPP1 = 1, H_REGBMEM8_DPP2 = 2, H_REGBMEM8_DPP3 = 3
- , H_REGBMEM8_PSW = 136, H_REGBMEM8_CP = 8, H_REGBMEM8_MDL = 7, H_REGBMEM8_MDH = 6
- , H_REGBMEM8_MDC = 135, H_REGBMEM8_SP = 9, H_REGBMEM8_CSP = 4, H_REGBMEM8_VECSEG = 137
- , H_REGBMEM8_STKOV = 10, H_REGBMEM8_STKUN = 11, H_REGBMEM8_CPUCON1 = 12, H_REGBMEM8_CPUCON2 = 13
- , H_REGBMEM8_ZEROS = 142, H_REGBMEM8_ONES = 143, H_REGBMEM8_SPSEG = 134, H_REGBMEM8_TFR = 214
- , H_REGBMEM8_RL0 = 240, H_REGBMEM8_RH0 = 241, H_REGBMEM8_RL1 = 242, H_REGBMEM8_RH1 = 243
- , H_REGBMEM8_RL2 = 244, H_REGBMEM8_RH2 = 245, H_REGBMEM8_RL3 = 246, H_REGBMEM8_RH3 = 247
- , H_REGBMEM8_RL4 = 248, H_REGBMEM8_RH4 = 249, H_REGBMEM8_RL5 = 250, H_REGBMEM8_RH5 = 251
- , H_REGBMEM8_RL6 = 252, H_REGBMEM8_RH6 = 253, H_REGBMEM8_RL7 = 254, H_REGBMEM8_RH7 = 255
-} REGBMEM8_NAMES;
-
-/* Enum declaration for . */
-typedef enum memgr8_names {
- H_MEMGR8_DPP0 = 65024, H_MEMGR8_DPP1 = 65026, H_MEMGR8_DPP2 = 65028, H_MEMGR8_DPP3 = 65030
- , H_MEMGR8_PSW = 65296, H_MEMGR8_CP = 65040, H_MEMGR8_MDL = 65038, H_MEMGR8_MDH = 65036
- , H_MEMGR8_MDC = 65294, H_MEMGR8_SP = 65042, H_MEMGR8_CSP = 65032, H_MEMGR8_VECSEG = 65298
- , H_MEMGR8_STKOV = 65044, H_MEMGR8_STKUN = 65046, H_MEMGR8_CPUCON1 = 65048, H_MEMGR8_CPUCON2 = 65050
- , H_MEMGR8_ZEROS = 65308, H_MEMGR8_ONES = 65310, H_MEMGR8_SPSEG = 65292, H_MEMGR8_TFR = 65452
-} MEMGR8_NAMES;
-
-/* Attributes. */
-
-/* Enum declaration for machine type selection. */
-typedef enum mach_attr {
- MACH_BASE, MACH_XC16X, MACH_MAX
-} MACH_ATTR;
-
-/* Enum declaration for instruction set selection. */
-typedef enum isa_attr {
- ISA_XC16X, ISA_MAX
-} ISA_ATTR;
-
-/* Enum declaration for parallel execution pipeline selection. */
-typedef enum pipe_attr {
- PIPE_NONE, PIPE_OS
-} PIPE_ATTR;
-
-/* Number of architecture variants. */
-#define MAX_ISAS 1
-#define MAX_MACHS ((int) MACH_MAX)
-
-/* Ifield support. */
-
-/* Ifield attribute indices. */
-
-/* Enum declaration for cgen_ifld attrs. */
-typedef enum cgen_ifld_attr {
- CGEN_IFLD_VIRTUAL, CGEN_IFLD_PCREL_ADDR, CGEN_IFLD_ABS_ADDR, CGEN_IFLD_RESERVED
- , CGEN_IFLD_SIGN_OPT, CGEN_IFLD_SIGNED, CGEN_IFLD_RELOC, CGEN_IFLD_END_BOOLS
- , CGEN_IFLD_START_NBOOLS = 31, CGEN_IFLD_MACH, CGEN_IFLD_END_NBOOLS
-} CGEN_IFLD_ATTR;
-
-/* Number of non-boolean elements in cgen_ifld_attr. */
-#define CGEN_IFLD_NBOOL_ATTRS (CGEN_IFLD_END_NBOOLS - CGEN_IFLD_START_NBOOLS - 1)
-
-/* cgen_ifld attribute accessor macros. */
-#define CGEN_ATTR_CGEN_IFLD_MACH_VALUE(attrs) ((attrs)->nonbool[CGEN_IFLD_MACH-CGEN_IFLD_START_NBOOLS-1].nonbitset)
-#define CGEN_ATTR_CGEN_IFLD_VIRTUAL_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_IFLD_VIRTUAL)) != 0)
-#define CGEN_ATTR_CGEN_IFLD_PCREL_ADDR_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_IFLD_PCREL_ADDR)) != 0)
-#define CGEN_ATTR_CGEN_IFLD_ABS_ADDR_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_IFLD_ABS_ADDR)) != 0)
-#define CGEN_ATTR_CGEN_IFLD_RESERVED_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_IFLD_RESERVED)) != 0)
-#define CGEN_ATTR_CGEN_IFLD_SIGN_OPT_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_IFLD_SIGN_OPT)) != 0)
-#define CGEN_ATTR_CGEN_IFLD_SIGNED_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_IFLD_SIGNED)) != 0)
-#define CGEN_ATTR_CGEN_IFLD_RELOC_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_IFLD_RELOC)) != 0)
-
-/* Enum declaration for xc16x ifield types. */
-typedef enum ifield_type {
- XC16X_F_NIL, XC16X_F_ANYOF, XC16X_F_OP1, XC16X_F_OP2
- , XC16X_F_CONDCODE, XC16X_F_ICONDCODE, XC16X_F_RCOND, XC16X_F_QCOND
- , XC16X_F_EXTCCODE, XC16X_F_R0, XC16X_F_R1, XC16X_F_R2
- , XC16X_F_R3, XC16X_F_R4, XC16X_F_UIMM2, XC16X_F_UIMM3
- , XC16X_F_UIMM4, XC16X_F_UIMM7, XC16X_F_UIMM8, XC16X_F_UIMM16
- , XC16X_F_MEMORY, XC16X_F_MEMGR8, XC16X_F_REL8, XC16X_F_RELHI8
- , XC16X_F_REG8, XC16X_F_REGMEM8, XC16X_F_REGOFF8, XC16X_F_REGHI8
- , XC16X_F_REGB8, XC16X_F_SEG8, XC16X_F_SEGNUM8, XC16X_F_MASK8
- , XC16X_F_PAGENUM, XC16X_F_DATAHI8, XC16X_F_DATA8, XC16X_F_OFFSET16
- , XC16X_F_OP_BIT1, XC16X_F_OP_BIT2, XC16X_F_OP_BIT4, XC16X_F_OP_BIT3
- , XC16X_F_OP_2BIT, XC16X_F_OP_BITONE, XC16X_F_OP_ONEBIT, XC16X_F_OP_1BIT
- , XC16X_F_OP_LBIT4, XC16X_F_OP_LBIT2, XC16X_F_OP_BIT8, XC16X_F_OP_BIT16
- , XC16X_F_QBIT, XC16X_F_QLOBIT, XC16X_F_QHIBIT, XC16X_F_QLOBIT2
- , XC16X_F_POF, XC16X_F_MAX
-} IFIELD_TYPE;
-
-#define MAX_IFLD ((int) XC16X_F_MAX)
-
-/* Hardware attribute indices. */
-
-/* Enum declaration for cgen_hw attrs. */
-typedef enum cgen_hw_attr {
- CGEN_HW_VIRTUAL, CGEN_HW_CACHE_ADDR, CGEN_HW_PC, CGEN_HW_PROFILE
- , CGEN_HW_END_BOOLS, CGEN_HW_START_NBOOLS = 31, CGEN_HW_MACH, CGEN_HW_END_NBOOLS
-} CGEN_HW_ATTR;
-
-/* Number of non-boolean elements in cgen_hw_attr. */
-#define CGEN_HW_NBOOL_ATTRS (CGEN_HW_END_NBOOLS - CGEN_HW_START_NBOOLS - 1)
-
-/* cgen_hw attribute accessor macros. */
-#define CGEN_ATTR_CGEN_HW_MACH_VALUE(attrs) ((attrs)->nonbool[CGEN_HW_MACH-CGEN_HW_START_NBOOLS-1].nonbitset)
-#define CGEN_ATTR_CGEN_HW_VIRTUAL_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_HW_VIRTUAL)) != 0)
-#define CGEN_ATTR_CGEN_HW_CACHE_ADDR_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_HW_CACHE_ADDR)) != 0)
-#define CGEN_ATTR_CGEN_HW_PC_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_HW_PC)) != 0)
-#define CGEN_ATTR_CGEN_HW_PROFILE_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_HW_PROFILE)) != 0)
-
-/* Enum declaration for xc16x hardware types. */
-typedef enum cgen_hw_type {
- HW_H_MEMORY, HW_H_SINT, HW_H_UINT, HW_H_ADDR
- , HW_H_IADDR, HW_H_PC, HW_H_GR, HW_H_CR
- , HW_H_EXT, HW_H_PSW, HW_H_GRB, HW_H_CC
- , HW_H_ECC, HW_H_GRB8, HW_H_R8, HW_H_REGMEM8
- , HW_H_REGDIV8, HW_H_R0, HW_H_R01, HW_H_REGBMEM8
- , HW_H_MEMGR8, HW_H_COND, HW_H_CBIT, HW_H_SGTDIS
- , HW_MAX
-} CGEN_HW_TYPE;
-
-#define MAX_HW ((int) HW_MAX)
-
-/* Operand attribute indices. */
-
-/* Enum declaration for cgen_operand attrs. */
-typedef enum cgen_operand_attr {
- CGEN_OPERAND_VIRTUAL, CGEN_OPERAND_PCREL_ADDR, CGEN_OPERAND_ABS_ADDR, CGEN_OPERAND_SIGN_OPT
- , CGEN_OPERAND_SIGNED, CGEN_OPERAND_NEGATIVE, CGEN_OPERAND_RELAX, CGEN_OPERAND_SEM_ONLY
- , CGEN_OPERAND_RELOC, CGEN_OPERAND_HASH_PREFIX, CGEN_OPERAND_DOT_PREFIX, CGEN_OPERAND_POF_PREFIX
- , CGEN_OPERAND_PAG_PREFIX, CGEN_OPERAND_SOF_PREFIX, CGEN_OPERAND_SEG_PREFIX, CGEN_OPERAND_END_BOOLS
- , CGEN_OPERAND_START_NBOOLS = 31, CGEN_OPERAND_MACH, CGEN_OPERAND_END_NBOOLS
-} CGEN_OPERAND_ATTR;
-
-/* Number of non-boolean elements in cgen_operand_attr. */
-#define CGEN_OPERAND_NBOOL_ATTRS (CGEN_OPERAND_END_NBOOLS - CGEN_OPERAND_START_NBOOLS - 1)
-
-/* cgen_operand attribute accessor macros. */
-#define CGEN_ATTR_CGEN_OPERAND_MACH_VALUE(attrs) ((attrs)->nonbool[CGEN_OPERAND_MACH-CGEN_OPERAND_START_NBOOLS-1].nonbitset)
-#define CGEN_ATTR_CGEN_OPERAND_VIRTUAL_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_OPERAND_VIRTUAL)) != 0)
-#define CGEN_ATTR_CGEN_OPERAND_PCREL_ADDR_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_OPERAND_PCREL_ADDR)) != 0)
-#define CGEN_ATTR_CGEN_OPERAND_ABS_ADDR_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_OPERAND_ABS_ADDR)) != 0)
-#define CGEN_ATTR_CGEN_OPERAND_SIGN_OPT_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_OPERAND_SIGN_OPT)) != 0)
-#define CGEN_ATTR_CGEN_OPERAND_SIGNED_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_OPERAND_SIGNED)) != 0)
-#define CGEN_ATTR_CGEN_OPERAND_NEGATIVE_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_OPERAND_NEGATIVE)) != 0)
-#define CGEN_ATTR_CGEN_OPERAND_RELAX_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_OPERAND_RELAX)) != 0)
-#define CGEN_ATTR_CGEN_OPERAND_SEM_ONLY_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_OPERAND_SEM_ONLY)) != 0)
-#define CGEN_ATTR_CGEN_OPERAND_RELOC_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_OPERAND_RELOC)) != 0)
-#define CGEN_ATTR_CGEN_OPERAND_HASH_PREFIX_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_OPERAND_HASH_PREFIX)) != 0)
-#define CGEN_ATTR_CGEN_OPERAND_DOT_PREFIX_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_OPERAND_DOT_PREFIX)) != 0)
-#define CGEN_ATTR_CGEN_OPERAND_POF_PREFIX_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_OPERAND_POF_PREFIX)) != 0)
-#define CGEN_ATTR_CGEN_OPERAND_PAG_PREFIX_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_OPERAND_PAG_PREFIX)) != 0)
-#define CGEN_ATTR_CGEN_OPERAND_SOF_PREFIX_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_OPERAND_SOF_PREFIX)) != 0)
-#define CGEN_ATTR_CGEN_OPERAND_SEG_PREFIX_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_OPERAND_SEG_PREFIX)) != 0)
-
-/* Enum declaration for xc16x operand types. */
-typedef enum cgen_operand_type {
- XC16X_OPERAND_PC, XC16X_OPERAND_SR, XC16X_OPERAND_DR, XC16X_OPERAND_DRI
- , XC16X_OPERAND_SRB, XC16X_OPERAND_DRB, XC16X_OPERAND_SR2, XC16X_OPERAND_SRC1
- , XC16X_OPERAND_SRC2, XC16X_OPERAND_SRDIV, XC16X_OPERAND_REGNAM, XC16X_OPERAND_UIMM2
- , XC16X_OPERAND_UIMM3, XC16X_OPERAND_UIMM4, XC16X_OPERAND_UIMM7, XC16X_OPERAND_UIMM8
- , XC16X_OPERAND_UIMM16, XC16X_OPERAND_UPOF16, XC16X_OPERAND_REG8, XC16X_OPERAND_REGMEM8
- , XC16X_OPERAND_REGBMEM8, XC16X_OPERAND_REGOFF8, XC16X_OPERAND_REGHI8, XC16X_OPERAND_REGB8
- , XC16X_OPERAND_GENREG, XC16X_OPERAND_SEG, XC16X_OPERAND_SEGHI8, XC16X_OPERAND_CADDR
- , XC16X_OPERAND_REL, XC16X_OPERAND_RELHI, XC16X_OPERAND_CONDBIT, XC16X_OPERAND_BIT1
- , XC16X_OPERAND_BIT2, XC16X_OPERAND_BIT4, XC16X_OPERAND_LBIT4, XC16X_OPERAND_LBIT2
- , XC16X_OPERAND_BIT8, XC16X_OPERAND_U4, XC16X_OPERAND_BITONE, XC16X_OPERAND_BIT01
- , XC16X_OPERAND_COND, XC16X_OPERAND_ICOND, XC16X_OPERAND_EXTCOND, XC16X_OPERAND_MEMORY
- , XC16X_OPERAND_MEMGR8, XC16X_OPERAND_CBIT, XC16X_OPERAND_QBIT, XC16X_OPERAND_QLOBIT
- , XC16X_OPERAND_QHIBIT, XC16X_OPERAND_MASK8, XC16X_OPERAND_MASKLO8, XC16X_OPERAND_PAGENUM
- , XC16X_OPERAND_DATA8, XC16X_OPERAND_DATAHI8, XC16X_OPERAND_SGTDISBIT, XC16X_OPERAND_UPAG16
- , XC16X_OPERAND_USEG8, XC16X_OPERAND_USEG16, XC16X_OPERAND_USOF16, XC16X_OPERAND_HASH
- , XC16X_OPERAND_DOT, XC16X_OPERAND_POF, XC16X_OPERAND_PAG, XC16X_OPERAND_SOF
- , XC16X_OPERAND_SEGM, XC16X_OPERAND_MAX
-} CGEN_OPERAND_TYPE;
-
-/* Number of operands types. */
-#define MAX_OPERANDS 65
-
-/* Maximum number of operands referenced by any insn. */
-#define MAX_OPERAND_INSTANCES 8
-
-/* Insn attribute indices. */
-
-/* Enum declaration for cgen_insn attrs. */
-typedef enum cgen_insn_attr {
- CGEN_INSN_ALIAS, CGEN_INSN_VIRTUAL, CGEN_INSN_UNCOND_CTI, CGEN_INSN_COND_CTI
- , CGEN_INSN_SKIP_CTI, CGEN_INSN_DELAY_SLOT, CGEN_INSN_RELAXABLE, CGEN_INSN_RELAXED
- , CGEN_INSN_NO_DIS, CGEN_INSN_PBB, CGEN_INSN_END_BOOLS, CGEN_INSN_START_NBOOLS = 31
- , CGEN_INSN_MACH, CGEN_INSN_PIPE, CGEN_INSN_END_NBOOLS
-} CGEN_INSN_ATTR;
-
-/* Number of non-boolean elements in cgen_insn_attr. */
-#define CGEN_INSN_NBOOL_ATTRS (CGEN_INSN_END_NBOOLS - CGEN_INSN_START_NBOOLS - 1)
-
-/* cgen_insn attribute accessor macros. */
-#define CGEN_ATTR_CGEN_INSN_MACH_VALUE(attrs) ((attrs)->nonbool[CGEN_INSN_MACH-CGEN_INSN_START_NBOOLS-1].nonbitset)
-#define CGEN_ATTR_CGEN_INSN_PIPE_VALUE(attrs) ((attrs)->nonbool[CGEN_INSN_PIPE-CGEN_INSN_START_NBOOLS-1].nonbitset)
-#define CGEN_ATTR_CGEN_INSN_ALIAS_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_ALIAS)) != 0)
-#define CGEN_ATTR_CGEN_INSN_VIRTUAL_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_VIRTUAL)) != 0)
-#define CGEN_ATTR_CGEN_INSN_UNCOND_CTI_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_UNCOND_CTI)) != 0)
-#define CGEN_ATTR_CGEN_INSN_COND_CTI_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_COND_CTI)) != 0)
-#define CGEN_ATTR_CGEN_INSN_SKIP_CTI_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_SKIP_CTI)) != 0)
-#define CGEN_ATTR_CGEN_INSN_DELAY_SLOT_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_DELAY_SLOT)) != 0)
-#define CGEN_ATTR_CGEN_INSN_RELAXABLE_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_RELAXABLE)) != 0)
-#define CGEN_ATTR_CGEN_INSN_RELAXED_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_RELAXED)) != 0)
-#define CGEN_ATTR_CGEN_INSN_NO_DIS_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_NO_DIS)) != 0)
-#define CGEN_ATTR_CGEN_INSN_PBB_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_PBB)) != 0)
-
-/* cgen.h uses things we just defined. */
-#include "opcode/cgen.h"
-
-extern const struct cgen_ifld xc16x_cgen_ifld_table[];
-
-/* Attributes. */
-extern const CGEN_ATTR_TABLE xc16x_cgen_hardware_attr_table[];
-extern const CGEN_ATTR_TABLE xc16x_cgen_ifield_attr_table[];
-extern const CGEN_ATTR_TABLE xc16x_cgen_operand_attr_table[];
-extern const CGEN_ATTR_TABLE xc16x_cgen_insn_attr_table[];
-
-/* Hardware decls. */
-
-extern CGEN_KEYWORD xc16x_cgen_opval_gr_names;
-extern CGEN_KEYWORD xc16x_cgen_opval_gr_names;
-extern CGEN_KEYWORD xc16x_cgen_opval_ext_names;
-extern CGEN_KEYWORD xc16x_cgen_opval_psw_names;
-extern CGEN_KEYWORD xc16x_cgen_opval_grb_names;
-extern CGEN_KEYWORD xc16x_cgen_opval_conditioncode_names;
-extern CGEN_KEYWORD xc16x_cgen_opval_extconditioncode_names;
-extern CGEN_KEYWORD xc16x_cgen_opval_grb8_names;
-extern CGEN_KEYWORD xc16x_cgen_opval_r8_names;
-extern CGEN_KEYWORD xc16x_cgen_opval_regmem8_names;
-extern CGEN_KEYWORD xc16x_cgen_opval_regdiv8_names;
-extern CGEN_KEYWORD xc16x_cgen_opval_reg0_name;
-extern CGEN_KEYWORD xc16x_cgen_opval_reg0_name1;
-extern CGEN_KEYWORD xc16x_cgen_opval_regbmem8_names;
-extern CGEN_KEYWORD xc16x_cgen_opval_memgr8_names;
-
-extern const CGEN_HW_ENTRY xc16x_cgen_hw_table[];
-
-
-
- #ifdef __cplusplus
- }
- #endif
-
-#endif /* XC16X_CPU_H */
+++ /dev/null
-/* DO NOT EDIT! -*- buffer-read-only: t -*- vi:set ro: */
-/* Disassembler interface for targets using CGEN. -*- C -*-
- CGEN: Cpu tools GENerator
-
- THIS FILE IS MACHINE GENERATED WITH CGEN.
- - the resultant file is machine generated, cgen-dis.in isn't
-
- Copyright (C) 1996-2022 Free Software Foundation, Inc.
-
- This file is part of libopcodes.
-
- This library is free software; you can redistribute it and/or modify
- it under the terms of the GNU General Public License as published by
- the Free Software Foundation; either version 3, or (at your option)
- any later version.
-
- It is distributed in the hope that it will be useful, but WITHOUT
- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
- License for more details.
-
- You should have received a copy of the GNU General Public License
- along with this program; if not, write to the Free Software Foundation, Inc.,
- 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */
-
-/* ??? Eventually more and more of this stuff can go to cpu-independent files.
- Keep that in mind. */
-
-#include "sysdep.h"
-#include <stdio.h>
-#include "ansidecl.h"
-#include "disassemble.h"
-#include "bfd.h"
-#include "symcat.h"
-#include "libiberty.h"
-#include "xc16x-desc.h"
-#include "xc16x-opc.h"
-#include "opintl.h"
-
-/* Default text to print if an instruction isn't recognized. */
-#define UNKNOWN_INSN_MSG _("*unknown*")
-
-static void print_normal
- (CGEN_CPU_DESC, void *, long, unsigned int, bfd_vma, int);
-static void print_address
- (CGEN_CPU_DESC, void *, bfd_vma, unsigned int, bfd_vma, int) ATTRIBUTE_UNUSED;
-static void print_keyword
- (CGEN_CPU_DESC, void *, CGEN_KEYWORD *, long, unsigned int) ATTRIBUTE_UNUSED;
-static void print_insn_normal
- (CGEN_CPU_DESC, void *, const CGEN_INSN *, CGEN_FIELDS *, bfd_vma, int);
-static int print_insn
- (CGEN_CPU_DESC, bfd_vma, disassemble_info *, bfd_byte *, unsigned);
-static int default_print_insn
- (CGEN_CPU_DESC, bfd_vma, disassemble_info *) ATTRIBUTE_UNUSED;
-static int read_insn
- (CGEN_CPU_DESC, bfd_vma, disassemble_info *, bfd_byte *, int, CGEN_EXTRACT_INFO *,
- unsigned long *);
-\f
-/* -- disassembler routines inserted here. */
-
-/* -- dis.c */
-
-/* Print an operand with a "." prefix.
- NOTE: This prints the operand in hex.
- ??? This exists to maintain disassembler compatibility with previous
- versions. Ideally we'd print the "." in print_dot. */
-
-static void
-print_with_dot_prefix (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
- void * dis_info,
- long value,
- unsigned attrs ATTRIBUTE_UNUSED,
- bfd_vma pc ATTRIBUTE_UNUSED,
- int length ATTRIBUTE_UNUSED)
-{
- disassemble_info *info = (disassemble_info *) dis_info;
-
- info->fprintf_func (info->stream, ".");
- info->fprintf_func (info->stream, "0x%lx", value);
-}
-
-/* Print an operand with a "#pof:" prefix.
- NOTE: This prints the operand as an address.
- ??? This exists to maintain disassembler compatibility with previous
- versions. Ideally we'd print "#pof:" in print_pof. */
-
-static void
-print_with_pof_prefix (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
- void * dis_info,
- bfd_vma value,
- unsigned attrs ATTRIBUTE_UNUSED,
- bfd_vma pc ATTRIBUTE_UNUSED,
- int length ATTRIBUTE_UNUSED)
-{
- disassemble_info *info = (disassemble_info *) dis_info;
-
- info->fprintf_func (info->stream, "#pof:");
- info->fprintf_func (info->stream, "0x%lx", (long) value);
-}
-
-/* Print an operand with a "#pag:" prefix.
- NOTE: This prints the operand in hex.
- ??? This exists to maintain disassembler compatibility with previous
- versions. Ideally we'd print "#pag:" in print_pag. */
-
-static void
-print_with_pag_prefix (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
- void * dis_info,
- long value,
- unsigned attrs ATTRIBUTE_UNUSED,
- bfd_vma pc ATTRIBUTE_UNUSED,
- int length ATTRIBUTE_UNUSED)
-{
- disassemble_info *info = (disassemble_info *) dis_info;
-
- info->fprintf_func (info->stream, "#pag:");
- info->fprintf_func (info->stream, "0x%lx", value);
-}
-
-/* Print a 'pof:' prefix to an operand. */
-
-static void
-print_pof (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
- void * dis_info ATTRIBUTE_UNUSED,
- long value ATTRIBUTE_UNUSED,
- unsigned int attrs ATTRIBUTE_UNUSED,
- bfd_vma pc ATTRIBUTE_UNUSED,
- int length ATTRIBUTE_UNUSED)
-{
-}
-
-/* Print a 'pag:' prefix to an operand. */
-
-static void
-print_pag (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
- void * dis_info ATTRIBUTE_UNUSED,
- long value ATTRIBUTE_UNUSED,
- unsigned int attrs ATTRIBUTE_UNUSED,
- bfd_vma pc ATTRIBUTE_UNUSED,
- int length ATTRIBUTE_UNUSED)
-{
-}
-
-/* Print a 'sof:' prefix to an operand. */
-
-static void
-print_sof (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
- void * dis_info,
- long value ATTRIBUTE_UNUSED,
- unsigned int attrs ATTRIBUTE_UNUSED,
- bfd_vma pc ATTRIBUTE_UNUSED,
- int length ATTRIBUTE_UNUSED)
-{
- disassemble_info *info = (disassemble_info *) dis_info;
-
- info->fprintf_func (info->stream, "sof:");
-}
-
-/* Print a 'seg:' prefix to an operand. */
-
-static void
-print_seg (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
- void * dis_info,
- long value ATTRIBUTE_UNUSED,
- unsigned int attrs ATTRIBUTE_UNUSED,
- bfd_vma pc ATTRIBUTE_UNUSED,
- int length ATTRIBUTE_UNUSED)
-{
- disassemble_info *info = (disassemble_info *) dis_info;
-
- info->fprintf_func (info->stream, "seg:");
-}
-
-/* Print a '#' prefix to an operand. */
-
-static void
-print_hash (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
- void * dis_info,
- long value ATTRIBUTE_UNUSED,
- unsigned int attrs ATTRIBUTE_UNUSED,
- bfd_vma pc ATTRIBUTE_UNUSED,
- int length ATTRIBUTE_UNUSED)
-{
- disassemble_info *info = (disassemble_info *) dis_info;
-
- info->fprintf_func (info->stream, "#");
-}
-
-/* Print a '.' prefix to an operand. */
-
-static void
-print_dot (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
- void * dis_info ATTRIBUTE_UNUSED,
- long value ATTRIBUTE_UNUSED,
- unsigned int attrs ATTRIBUTE_UNUSED,
- bfd_vma pc ATTRIBUTE_UNUSED,
- int length ATTRIBUTE_UNUSED)
-{
-}
-
-/* -- */
-
-void xc16x_cgen_print_operand
- (CGEN_CPU_DESC, int, void *, CGEN_FIELDS *, void const *, bfd_vma, int);
-
-/* Main entry point for printing operands.
- XINFO is a `void *' and not a `disassemble_info *' to not put a requirement
- of dis-asm.h on cgen.h.
-
- This function is basically just a big switch statement. Earlier versions
- used tables to look up the function to use, but
- - if the table contains both assembler and disassembler functions then
- the disassembler contains much of the assembler and vice-versa,
- - there's a lot of inlining possibilities as things grow,
- - using a switch statement avoids the function call overhead.
-
- This function could be moved into `print_insn_normal', but keeping it
- separate makes clear the interface between `print_insn_normal' and each of
- the handlers. */
-
-void
-xc16x_cgen_print_operand (CGEN_CPU_DESC cd,
- int opindex,
- void * xinfo,
- CGEN_FIELDS *fields,
- void const *attrs ATTRIBUTE_UNUSED,
- bfd_vma pc,
- int length)
-{
- disassemble_info *info = (disassemble_info *) xinfo;
-
- switch (opindex)
- {
- case XC16X_OPERAND_REGNAM :
- print_keyword (cd, info, & xc16x_cgen_opval_psw_names, fields->f_reg8, 0);
- break;
- case XC16X_OPERAND_BIT01 :
- print_normal (cd, info, fields->f_op_1bit, 0, pc, length);
- break;
- case XC16X_OPERAND_BIT1 :
- print_normal (cd, info, fields->f_op_bit1, 0, pc, length);
- break;
- case XC16X_OPERAND_BIT2 :
- print_normal (cd, info, fields->f_op_bit2, 0, pc, length);
- break;
- case XC16X_OPERAND_BIT4 :
- print_normal (cd, info, fields->f_op_bit4, 0, pc, length);
- break;
- case XC16X_OPERAND_BIT8 :
- print_normal (cd, info, fields->f_op_bit8, 0, pc, length);
- break;
- case XC16X_OPERAND_BITONE :
- print_normal (cd, info, fields->f_op_onebit, 0, pc, length);
- break;
- case XC16X_OPERAND_CADDR :
- print_address (cd, info, fields->f_offset16, 0|(1<<CGEN_OPERAND_RELOC)|(1<<CGEN_OPERAND_ABS_ADDR), pc, length);
- break;
- case XC16X_OPERAND_COND :
- print_keyword (cd, info, & xc16x_cgen_opval_conditioncode_names, fields->f_condcode, 0);
- break;
- case XC16X_OPERAND_DATA8 :
- print_normal (cd, info, fields->f_data8, 0|(1<<CGEN_OPERAND_HASH_PREFIX), pc, length);
- break;
- case XC16X_OPERAND_DATAHI8 :
- print_normal (cd, info, fields->f_datahi8, 0|(1<<CGEN_OPERAND_HASH_PREFIX), pc, length);
- break;
- case XC16X_OPERAND_DOT :
- print_dot (cd, info, 0, 0|(1<<CGEN_OPERAND_SIGNED), pc, length);
- break;
- case XC16X_OPERAND_DR :
- print_keyword (cd, info, & xc16x_cgen_opval_gr_names, fields->f_r1, 0);
- break;
- case XC16X_OPERAND_DRB :
- print_keyword (cd, info, & xc16x_cgen_opval_grb_names, fields->f_r1, 0);
- break;
- case XC16X_OPERAND_DRI :
- print_keyword (cd, info, & xc16x_cgen_opval_gr_names, fields->f_r4, 0);
- break;
- case XC16X_OPERAND_EXTCOND :
- print_keyword (cd, info, & xc16x_cgen_opval_extconditioncode_names, fields->f_extccode, 0);
- break;
- case XC16X_OPERAND_GENREG :
- print_keyword (cd, info, & xc16x_cgen_opval_r8_names, fields->f_regb8, 0);
- break;
- case XC16X_OPERAND_HASH :
- print_hash (cd, info, 0, 0|(1<<CGEN_OPERAND_SIGNED), pc, length);
- break;
- case XC16X_OPERAND_ICOND :
- print_keyword (cd, info, & xc16x_cgen_opval_conditioncode_names, fields->f_icondcode, 0);
- break;
- case XC16X_OPERAND_LBIT2 :
- print_normal (cd, info, fields->f_op_lbit2, 0, pc, length);
- break;
- case XC16X_OPERAND_LBIT4 :
- print_normal (cd, info, fields->f_op_lbit4, 0, pc, length);
- break;
- case XC16X_OPERAND_MASK8 :
- print_normal (cd, info, fields->f_mask8, 0|(1<<CGEN_OPERAND_HASH_PREFIX), pc, length);
- break;
- case XC16X_OPERAND_MASKLO8 :
- print_normal (cd, info, fields->f_datahi8, 0|(1<<CGEN_OPERAND_HASH_PREFIX), pc, length);
- break;
- case XC16X_OPERAND_MEMGR8 :
- print_keyword (cd, info, & xc16x_cgen_opval_memgr8_names, fields->f_memgr8, 0);
- break;
- case XC16X_OPERAND_MEMORY :
- print_address (cd, info, fields->f_memory, 0, pc, length);
- break;
- case XC16X_OPERAND_PAG :
- print_pag (cd, info, 0, 0|(1<<CGEN_OPERAND_SIGNED), pc, length);
- break;
- case XC16X_OPERAND_PAGENUM :
- print_normal (cd, info, fields->f_pagenum, 0|(1<<CGEN_OPERAND_HASH_PREFIX), pc, length);
- break;
- case XC16X_OPERAND_POF :
- print_pof (cd, info, 0, 0|(1<<CGEN_OPERAND_SIGNED), pc, length);
- break;
- case XC16X_OPERAND_QBIT :
- print_with_dot_prefix (cd, info, fields->f_qbit, 0|(1<<CGEN_OPERAND_DOT_PREFIX), pc, length);
- break;
- case XC16X_OPERAND_QHIBIT :
- print_with_dot_prefix (cd, info, fields->f_qhibit, 0|(1<<CGEN_OPERAND_DOT_PREFIX), pc, length);
- break;
- case XC16X_OPERAND_QLOBIT :
- print_with_dot_prefix (cd, info, fields->f_qlobit, 0|(1<<CGEN_OPERAND_DOT_PREFIX), pc, length);
- break;
- case XC16X_OPERAND_REG8 :
- print_keyword (cd, info, & xc16x_cgen_opval_r8_names, fields->f_reg8, 0);
- break;
- case XC16X_OPERAND_REGB8 :
- print_keyword (cd, info, & xc16x_cgen_opval_grb8_names, fields->f_regb8, 0);
- break;
- case XC16X_OPERAND_REGBMEM8 :
- print_keyword (cd, info, & xc16x_cgen_opval_regbmem8_names, fields->f_regmem8, 0);
- break;
- case XC16X_OPERAND_REGHI8 :
- print_keyword (cd, info, & xc16x_cgen_opval_r8_names, fields->f_reghi8, 0);
- break;
- case XC16X_OPERAND_REGMEM8 :
- print_keyword (cd, info, & xc16x_cgen_opval_regmem8_names, fields->f_regmem8, 0);
- break;
- case XC16X_OPERAND_REGOFF8 :
- print_keyword (cd, info, & xc16x_cgen_opval_r8_names, fields->f_regoff8, 0);
- break;
- case XC16X_OPERAND_REL :
- print_normal (cd, info, fields->f_rel8, 0|(1<<CGEN_OPERAND_SIGNED)|(1<<CGEN_OPERAND_RELOC)|(1<<CGEN_OPERAND_PCREL_ADDR), pc, length);
- break;
- case XC16X_OPERAND_RELHI :
- print_normal (cd, info, fields->f_relhi8, 0|(1<<CGEN_OPERAND_SIGNED)|(1<<CGEN_OPERAND_RELOC)|(1<<CGEN_OPERAND_PCREL_ADDR), pc, length);
- break;
- case XC16X_OPERAND_SEG :
- print_normal (cd, info, fields->f_seg8, 0, pc, length);
- break;
- case XC16X_OPERAND_SEGHI8 :
- print_normal (cd, info, fields->f_segnum8, 0, pc, length);
- break;
- case XC16X_OPERAND_SEGM :
- print_seg (cd, info, 0, 0|(1<<CGEN_OPERAND_SIGNED), pc, length);
- break;
- case XC16X_OPERAND_SOF :
- print_sof (cd, info, 0, 0|(1<<CGEN_OPERAND_SIGNED), pc, length);
- break;
- case XC16X_OPERAND_SR :
- print_keyword (cd, info, & xc16x_cgen_opval_gr_names, fields->f_r2, 0);
- break;
- case XC16X_OPERAND_SR2 :
- print_keyword (cd, info, & xc16x_cgen_opval_gr_names, fields->f_r0, 0);
- break;
- case XC16X_OPERAND_SRB :
- print_keyword (cd, info, & xc16x_cgen_opval_grb_names, fields->f_r2, 0);
- break;
- case XC16X_OPERAND_SRC1 :
- print_keyword (cd, info, & xc16x_cgen_opval_gr_names, fields->f_r1, 0);
- break;
- case XC16X_OPERAND_SRC2 :
- print_keyword (cd, info, & xc16x_cgen_opval_gr_names, fields->f_r2, 0);
- break;
- case XC16X_OPERAND_SRDIV :
- print_keyword (cd, info, & xc16x_cgen_opval_regdiv8_names, fields->f_reg8, 0);
- break;
- case XC16X_OPERAND_U4 :
- print_keyword (cd, info, & xc16x_cgen_opval_reg0_name, fields->f_uimm4, 0);
- break;
- case XC16X_OPERAND_UIMM16 :
- print_normal (cd, info, fields->f_uimm16, 0|(1<<CGEN_OPERAND_HASH_PREFIX), pc, length);
- break;
- case XC16X_OPERAND_UIMM2 :
- print_keyword (cd, info, & xc16x_cgen_opval_ext_names, fields->f_uimm2, 0|(1<<CGEN_OPERAND_HASH_PREFIX));
- break;
- case XC16X_OPERAND_UIMM3 :
- print_keyword (cd, info, & xc16x_cgen_opval_reg0_name1, fields->f_uimm3, 0|(1<<CGEN_OPERAND_HASH_PREFIX));
- break;
- case XC16X_OPERAND_UIMM4 :
- print_normal (cd, info, fields->f_uimm4, 0|(1<<CGEN_OPERAND_HASH_PREFIX), pc, length);
- break;
- case XC16X_OPERAND_UIMM7 :
- print_normal (cd, info, fields->f_uimm7, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_RELOC)|(1<<CGEN_OPERAND_PCREL_ADDR), pc, length);
- break;
- case XC16X_OPERAND_UIMM8 :
- print_normal (cd, info, fields->f_uimm8, 0|(1<<CGEN_OPERAND_HASH_PREFIX), pc, length);
- break;
- case XC16X_OPERAND_UPAG16 :
- print_with_pag_prefix (cd, info, fields->f_uimm16, 0|(1<<CGEN_OPERAND_PAG_PREFIX), pc, length);
- break;
- case XC16X_OPERAND_UPOF16 :
- print_with_pof_prefix (cd, info, fields->f_memory, 0|(1<<CGEN_OPERAND_POF_PREFIX), pc, length);
- break;
- case XC16X_OPERAND_USEG16 :
- print_normal (cd, info, fields->f_offset16, 0|(1<<CGEN_OPERAND_SEG_PREFIX)|(1<<CGEN_OPERAND_RELOC)|(1<<CGEN_OPERAND_ABS_ADDR), pc, length);
- break;
- case XC16X_OPERAND_USEG8 :
- print_normal (cd, info, fields->f_seg8, 0|(1<<CGEN_OPERAND_SEG_PREFIX), pc, length);
- break;
- case XC16X_OPERAND_USOF16 :
- print_normal (cd, info, fields->f_offset16, 0|(1<<CGEN_OPERAND_SOF_PREFIX)|(1<<CGEN_OPERAND_RELOC)|(1<<CGEN_OPERAND_ABS_ADDR), pc, length);
- break;
-
- default :
- /* xgettext:c-format */
- opcodes_error_handler
- (_("internal error: unrecognized field %d while printing insn"),
- opindex);
- abort ();
- }
-}
-
-cgen_print_fn * const xc16x_cgen_print_handlers[] =
-{
- print_insn_normal,
-};
-
-
-void
-xc16x_cgen_init_dis (CGEN_CPU_DESC cd)
-{
- xc16x_cgen_init_opcode_table (cd);
- xc16x_cgen_init_ibld_table (cd);
- cd->print_handlers = & xc16x_cgen_print_handlers[0];
- cd->print_operand = xc16x_cgen_print_operand;
-}
-
-\f
-/* Default print handler. */
-
-static void
-print_normal (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
- void *dis_info,
- long value,
- unsigned int attrs,
- bfd_vma pc ATTRIBUTE_UNUSED,
- int length ATTRIBUTE_UNUSED)
-{
- disassemble_info *info = (disassemble_info *) dis_info;
-
- /* Print the operand as directed by the attributes. */
- if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_SEM_ONLY))
- ; /* nothing to do */
- else if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_SIGNED))
- (*info->fprintf_func) (info->stream, "%ld", value);
- else
- (*info->fprintf_func) (info->stream, "0x%lx", value);
-}
-
-/* Default address handler. */
-
-static void
-print_address (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
- void *dis_info,
- bfd_vma value,
- unsigned int attrs,
- bfd_vma pc ATTRIBUTE_UNUSED,
- int length ATTRIBUTE_UNUSED)
-{
- disassemble_info *info = (disassemble_info *) dis_info;
-
- /* Print the operand as directed by the attributes. */
- if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_SEM_ONLY))
- ; /* Nothing to do. */
- else if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_PCREL_ADDR))
- (*info->print_address_func) (value, info);
- else if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_ABS_ADDR))
- (*info->print_address_func) (value, info);
- else if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_SIGNED))
- (*info->fprintf_func) (info->stream, "%ld", (long) value);
- else
- (*info->fprintf_func) (info->stream, "0x%lx", (long) value);
-}
-
-/* Keyword print handler. */
-
-static void
-print_keyword (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
- void *dis_info,
- CGEN_KEYWORD *keyword_table,
- long value,
- unsigned int attrs ATTRIBUTE_UNUSED)
-{
- disassemble_info *info = (disassemble_info *) dis_info;
- const CGEN_KEYWORD_ENTRY *ke;
-
- ke = cgen_keyword_lookup_value (keyword_table, value);
- if (ke != NULL)
- (*info->fprintf_func) (info->stream, "%s", ke->name);
- else
- (*info->fprintf_func) (info->stream, "???");
-}
-\f
-/* Default insn printer.
-
- DIS_INFO is defined as `void *' so the disassembler needn't know anything
- about disassemble_info. */
-
-static void
-print_insn_normal (CGEN_CPU_DESC cd,
- void *dis_info,
- const CGEN_INSN *insn,
- CGEN_FIELDS *fields,
- bfd_vma pc,
- int length)
-{
- const CGEN_SYNTAX *syntax = CGEN_INSN_SYNTAX (insn);
- disassemble_info *info = (disassemble_info *) dis_info;
- const CGEN_SYNTAX_CHAR_TYPE *syn;
-
- CGEN_INIT_PRINT (cd);
-
- for (syn = CGEN_SYNTAX_STRING (syntax); *syn; ++syn)
- {
- if (CGEN_SYNTAX_MNEMONIC_P (*syn))
- {
- (*info->fprintf_func) (info->stream, "%s", CGEN_INSN_MNEMONIC (insn));
- continue;
- }
- if (CGEN_SYNTAX_CHAR_P (*syn))
- {
- (*info->fprintf_func) (info->stream, "%c", CGEN_SYNTAX_CHAR (*syn));
- continue;
- }
-
- /* We have an operand. */
- xc16x_cgen_print_operand (cd, CGEN_SYNTAX_FIELD (*syn), info,
- fields, CGEN_INSN_ATTRS (insn), pc, length);
- }
-}
-\f
-/* Subroutine of print_insn. Reads an insn into the given buffers and updates
- the extract info.
- Returns 0 if all is well, non-zero otherwise. */
-
-static int
-read_insn (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
- bfd_vma pc,
- disassemble_info *info,
- bfd_byte *buf,
- int buflen,
- CGEN_EXTRACT_INFO *ex_info,
- unsigned long *insn_value)
-{
- int status = (*info->read_memory_func) (pc, buf, buflen, info);
-
- if (status != 0)
- {
- (*info->memory_error_func) (status, pc, info);
- return -1;
- }
-
- ex_info->dis_info = info;
- ex_info->valid = (1 << buflen) - 1;
- ex_info->insn_bytes = buf;
-
- *insn_value = bfd_get_bits (buf, buflen * 8, info->endian == BFD_ENDIAN_BIG);
- return 0;
-}
-
-/* Utility to print an insn.
- BUF is the base part of the insn, target byte order, BUFLEN bytes long.
- The result is the size of the insn in bytes or zero for an unknown insn
- or -1 if an error occurs fetching data (memory_error_func will have
- been called). */
-
-static int
-print_insn (CGEN_CPU_DESC cd,
- bfd_vma pc,
- disassemble_info *info,
- bfd_byte *buf,
- unsigned int buflen)
-{
- CGEN_INSN_INT insn_value;
- const CGEN_INSN_LIST *insn_list;
- CGEN_EXTRACT_INFO ex_info;
- int basesize;
-
- /* Extract base part of instruction, just in case CGEN_DIS_* uses it. */
- basesize = cd->base_insn_bitsize < buflen * 8 ?
- cd->base_insn_bitsize : buflen * 8;
- insn_value = cgen_get_insn_value (cd, buf, basesize, cd->insn_endian);
-
-
- /* Fill in ex_info fields like read_insn would. Don't actually call
- read_insn, since the incoming buffer is already read (and possibly
- modified a la m32r). */
- ex_info.valid = (1 << buflen) - 1;
- ex_info.dis_info = info;
- ex_info.insn_bytes = buf;
-
- /* The instructions are stored in hash lists.
- Pick the first one and keep trying until we find the right one. */
-
- insn_list = CGEN_DIS_LOOKUP_INSN (cd, (char *) buf, insn_value);
- while (insn_list != NULL)
- {
- const CGEN_INSN *insn = insn_list->insn;
- CGEN_FIELDS fields;
- int length;
- unsigned long insn_value_cropped;
-
-#ifdef CGEN_VALIDATE_INSN_SUPPORTED
- /* Not needed as insn shouldn't be in hash lists if not supported. */
- /* Supported by this cpu? */
- if (! xc16x_cgen_insn_supported (cd, insn))
- {
- insn_list = CGEN_DIS_NEXT_INSN (insn_list);
- continue;
- }
-#endif
-
- /* Basic bit mask must be correct. */
- /* ??? May wish to allow target to defer this check until the extract
- handler. */
-
- /* Base size may exceed this instruction's size. Extract the
- relevant part from the buffer. */
- if ((unsigned) (CGEN_INSN_BITSIZE (insn) / 8) < buflen &&
- (unsigned) (CGEN_INSN_BITSIZE (insn) / 8) <= sizeof (unsigned long))
- insn_value_cropped = bfd_get_bits (buf, CGEN_INSN_BITSIZE (insn),
- info->endian == BFD_ENDIAN_BIG);
- else
- insn_value_cropped = insn_value;
-
- if ((insn_value_cropped & CGEN_INSN_BASE_MASK (insn))
- == CGEN_INSN_BASE_VALUE (insn))
- {
- /* Printing is handled in two passes. The first pass parses the
- machine insn and extracts the fields. The second pass prints
- them. */
-
- /* Make sure the entire insn is loaded into insn_value, if it
- can fit. */
- if (((unsigned) CGEN_INSN_BITSIZE (insn) > cd->base_insn_bitsize) &&
- (unsigned) (CGEN_INSN_BITSIZE (insn) / 8) <= sizeof (unsigned long))
- {
- unsigned long full_insn_value;
- int rc = read_insn (cd, pc, info, buf,
- CGEN_INSN_BITSIZE (insn) / 8,
- & ex_info, & full_insn_value);
- if (rc != 0)
- return rc;
- length = CGEN_EXTRACT_FN (cd, insn)
- (cd, insn, &ex_info, full_insn_value, &fields, pc);
- }
- else
- length = CGEN_EXTRACT_FN (cd, insn)
- (cd, insn, &ex_info, insn_value_cropped, &fields, pc);
-
- /* Length < 0 -> error. */
- if (length < 0)
- return length;
- if (length > 0)
- {
- CGEN_PRINT_FN (cd, insn) (cd, info, insn, &fields, pc, length);
- /* Length is in bits, result is in bytes. */
- return length / 8;
- }
- }
-
- insn_list = CGEN_DIS_NEXT_INSN (insn_list);
- }
-
- return 0;
-}
-
-/* Default value for CGEN_PRINT_INSN.
- The result is the size of the insn in bytes or zero for an unknown insn
- or -1 if an error occured fetching bytes. */
-
-#ifndef CGEN_PRINT_INSN
-#define CGEN_PRINT_INSN default_print_insn
-#endif
-
-static int
-default_print_insn (CGEN_CPU_DESC cd, bfd_vma pc, disassemble_info *info)
-{
- bfd_byte buf[CGEN_MAX_INSN_SIZE];
- int buflen;
- int status;
-
- /* Attempt to read the base part of the insn. */
- buflen = cd->base_insn_bitsize / 8;
- status = (*info->read_memory_func) (pc, buf, buflen, info);
-
- /* Try again with the minimum part, if min < base. */
- if (status != 0 && (cd->min_insn_bitsize < cd->base_insn_bitsize))
- {
- buflen = cd->min_insn_bitsize / 8;
- status = (*info->read_memory_func) (pc, buf, buflen, info);
- }
-
- if (status != 0)
- {
- (*info->memory_error_func) (status, pc, info);
- return -1;
- }
-
- return print_insn (cd, pc, info, buf, buflen);
-}
-
-/* Main entry point.
- Print one instruction from PC on INFO->STREAM.
- Return the size of the instruction (in bytes). */
-
-typedef struct cpu_desc_list
-{
- struct cpu_desc_list *next;
- CGEN_BITSET *isa;
- int mach;
- int endian;
- int insn_endian;
- CGEN_CPU_DESC cd;
-} cpu_desc_list;
-
-int
-print_insn_xc16x (bfd_vma pc, disassemble_info *info)
-{
- static cpu_desc_list *cd_list = 0;
- cpu_desc_list *cl = 0;
- static CGEN_CPU_DESC cd = 0;
- static CGEN_BITSET *prev_isa;
- static int prev_mach;
- static int prev_endian;
- static int prev_insn_endian;
- int length;
- CGEN_BITSET *isa;
- int mach;
- int endian = (info->endian == BFD_ENDIAN_BIG
- ? CGEN_ENDIAN_BIG
- : CGEN_ENDIAN_LITTLE);
- int insn_endian = (info->endian_code == BFD_ENDIAN_BIG
- ? CGEN_ENDIAN_BIG
- : CGEN_ENDIAN_LITTLE);
- enum bfd_architecture arch;
-
- /* ??? gdb will set mach but leave the architecture as "unknown" */
-#ifndef CGEN_BFD_ARCH
-#define CGEN_BFD_ARCH bfd_arch_xc16x
-#endif
- arch = info->arch;
- if (arch == bfd_arch_unknown)
- arch = CGEN_BFD_ARCH;
-
- /* There's no standard way to compute the machine or isa number
- so we leave it to the target. */
-#ifdef CGEN_COMPUTE_MACH
- mach = CGEN_COMPUTE_MACH (info);
-#else
- mach = info->mach;
-#endif
-
-#ifdef CGEN_COMPUTE_ISA
- {
- static CGEN_BITSET *permanent_isa;
-
- if (!permanent_isa)
- permanent_isa = cgen_bitset_create (MAX_ISAS);
- isa = permanent_isa;
- cgen_bitset_clear (isa);
- cgen_bitset_add (isa, CGEN_COMPUTE_ISA (info));
- }
-#else
- isa = info->private_data;
-#endif
-
- /* If we've switched cpu's, try to find a handle we've used before */
- if (cd
- && (cgen_bitset_compare (isa, prev_isa) != 0
- || mach != prev_mach
- || endian != prev_endian))
- {
- cd = 0;
- for (cl = cd_list; cl; cl = cl->next)
- {
- if (cgen_bitset_compare (cl->isa, isa) == 0 &&
- cl->mach == mach &&
- cl->endian == endian)
- {
- cd = cl->cd;
- prev_isa = cd->isas;
- break;
- }
- }
- }
-
- /* If we haven't initialized yet, initialize the opcode table. */
- if (! cd)
- {
- const bfd_arch_info_type *arch_type = bfd_lookup_arch (arch, mach);
- const char *mach_name;
-
- if (!arch_type)
- abort ();
- mach_name = arch_type->printable_name;
-
- prev_isa = cgen_bitset_copy (isa);
- prev_mach = mach;
- prev_endian = endian;
- prev_insn_endian = insn_endian;
- cd = xc16x_cgen_cpu_open (CGEN_CPU_OPEN_ISAS, prev_isa,
- CGEN_CPU_OPEN_BFDMACH, mach_name,
- CGEN_CPU_OPEN_ENDIAN, prev_endian,
- CGEN_CPU_OPEN_INSN_ENDIAN, prev_insn_endian,
- CGEN_CPU_OPEN_END);
- if (!cd)
- abort ();
-
- /* Save this away for future reference. */
- cl = xmalloc (sizeof (struct cpu_desc_list));
- cl->cd = cd;
- cl->isa = prev_isa;
- cl->mach = mach;
- cl->endian = endian;
- cl->next = cd_list;
- cd_list = cl;
-
- xc16x_cgen_init_dis (cd);
- }
-
- /* We try to have as much common code as possible.
- But at this point some targets need to take over. */
- /* ??? Some targets may need a hook elsewhere. Try to avoid this,
- but if not possible try to move this hook elsewhere rather than
- have two hooks. */
- length = CGEN_PRINT_INSN (cd, pc, info);
- if (length > 0)
- return length;
- if (length < 0)
- return -1;
-
- (*info->fprintf_func) (info->stream, UNKNOWN_INSN_MSG);
- return cd->default_insn_bitsize / 8;
-}
+++ /dev/null
-/* DO NOT EDIT! -*- buffer-read-only: t -*- vi:set ro: */
-/* Instruction building/extraction support for xc16x. -*- C -*-
-
- THIS FILE IS MACHINE GENERATED WITH CGEN: Cpu tools GENerator.
- - the resultant file is machine generated, cgen-ibld.in isn't
-
- Copyright (C) 1996-2022 Free Software Foundation, Inc.
-
- This file is part of libopcodes.
-
- This library is free software; you can redistribute it and/or modify
- it under the terms of the GNU General Public License as published by
- the Free Software Foundation; either version 3, or (at your option)
- any later version.
-
- It is distributed in the hope that it will be useful, but WITHOUT
- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
- License for more details.
-
- You should have received a copy of the GNU General Public License
- along with this program; if not, write to the Free Software Foundation, Inc.,
- 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */
-
-/* ??? Eventually more and more of this stuff can go to cpu-independent files.
- Keep that in mind. */
-
-#include "sysdep.h"
-#include <stdio.h>
-#include "ansidecl.h"
-#include "dis-asm.h"
-#include "bfd.h"
-#include "symcat.h"
-#include "xc16x-desc.h"
-#include "xc16x-opc.h"
-#include "cgen/basic-modes.h"
-#include "opintl.h"
-#include "safe-ctype.h"
-
-#undef min
-#define min(a,b) ((a) < (b) ? (a) : (b))
-#undef max
-#define max(a,b) ((a) > (b) ? (a) : (b))
-
-/* Used by the ifield rtx function. */
-#define FLD(f) (fields->f)
-
-static const char * insert_normal
- (CGEN_CPU_DESC, long, unsigned int, unsigned int, unsigned int,
- unsigned int, unsigned int, unsigned int, CGEN_INSN_BYTES_PTR);
-static const char * insert_insn_normal
- (CGEN_CPU_DESC, const CGEN_INSN *,
- CGEN_FIELDS *, CGEN_INSN_BYTES_PTR, bfd_vma);
-static int extract_normal
- (CGEN_CPU_DESC, CGEN_EXTRACT_INFO *, CGEN_INSN_INT,
- unsigned int, unsigned int, unsigned int, unsigned int,
- unsigned int, unsigned int, bfd_vma, long *);
-static int extract_insn_normal
- (CGEN_CPU_DESC, const CGEN_INSN *, CGEN_EXTRACT_INFO *,
- CGEN_INSN_INT, CGEN_FIELDS *, bfd_vma);
-#if CGEN_INT_INSN_P
-static void put_insn_int_value
- (CGEN_CPU_DESC, CGEN_INSN_BYTES_PTR, int, int, CGEN_INSN_INT);
-#endif
-#if ! CGEN_INT_INSN_P
-static CGEN_INLINE void insert_1
- (CGEN_CPU_DESC, unsigned long, int, int, int, unsigned char *);
-static CGEN_INLINE int fill_cache
- (CGEN_CPU_DESC, CGEN_EXTRACT_INFO *, int, int, bfd_vma);
-static CGEN_INLINE long extract_1
- (CGEN_CPU_DESC, CGEN_EXTRACT_INFO *, int, int, int, unsigned char *, bfd_vma);
-#endif
-\f
-/* Operand insertion. */
-
-#if ! CGEN_INT_INSN_P
-
-/* Subroutine of insert_normal. */
-
-static CGEN_INLINE void
-insert_1 (CGEN_CPU_DESC cd,
- unsigned long value,
- int start,
- int length,
- int word_length,
- unsigned char *bufp)
-{
- unsigned long x, mask;
- int shift;
-
- x = cgen_get_insn_value (cd, bufp, word_length, cd->endian);
-
- /* Written this way to avoid undefined behaviour. */
- mask = (1UL << (length - 1) << 1) - 1;
- if (CGEN_INSN_LSB0_P)
- shift = (start + 1) - length;
- else
- shift = (word_length - (start + length));
- x = (x & ~(mask << shift)) | ((value & mask) << shift);
-
- cgen_put_insn_value (cd, bufp, word_length, (bfd_vma) x, cd->endian);
-}
-
-#endif /* ! CGEN_INT_INSN_P */
-
-/* Default insertion routine.
-
- ATTRS is a mask of the boolean attributes.
- WORD_OFFSET is the offset in bits from the start of the insn of the value.
- WORD_LENGTH is the length of the word in bits in which the value resides.
- START is the starting bit number in the word, architecture origin.
- LENGTH is the length of VALUE in bits.
- TOTAL_LENGTH is the total length of the insn in bits.
-
- The result is an error message or NULL if success. */
-
-/* ??? This duplicates functionality with bfd's howto table and
- bfd_install_relocation. */
-/* ??? This doesn't handle bfd_vma's. Create another function when
- necessary. */
-
-static const char *
-insert_normal (CGEN_CPU_DESC cd,
- long value,
- unsigned int attrs,
- unsigned int word_offset,
- unsigned int start,
- unsigned int length,
- unsigned int word_length,
- unsigned int total_length,
- CGEN_INSN_BYTES_PTR buffer)
-{
- static char errbuf[100];
- unsigned long mask;
-
- /* If LENGTH is zero, this operand doesn't contribute to the value. */
- if (length == 0)
- return NULL;
-
- /* Written this way to avoid undefined behaviour. */
- mask = (1UL << (length - 1) << 1) - 1;
-
- if (word_length > 8 * sizeof (CGEN_INSN_INT))
- abort ();
-
- /* For architectures with insns smaller than the base-insn-bitsize,
- word_length may be too big. */
- if (cd->min_insn_bitsize < cd->base_insn_bitsize)
- {
- if (word_offset == 0
- && word_length > total_length)
- word_length = total_length;
- }
-
- /* Ensure VALUE will fit. */
- if (CGEN_BOOL_ATTR (attrs, CGEN_IFLD_SIGN_OPT))
- {
- long minval = - (1UL << (length - 1));
- unsigned long maxval = mask;
-
- if ((value > 0 && (unsigned long) value > maxval)
- || value < minval)
- {
- /* xgettext:c-format */
- sprintf (errbuf,
- _("operand out of range (%ld not between %ld and %lu)"),
- value, minval, maxval);
- return errbuf;
- }
- }
- else if (! CGEN_BOOL_ATTR (attrs, CGEN_IFLD_SIGNED))
- {
- unsigned long maxval = mask;
- unsigned long val = (unsigned long) value;
-
- /* For hosts with a word size > 32 check to see if value has been sign
- extended beyond 32 bits. If so then ignore these higher sign bits
- as the user is attempting to store a 32-bit signed value into an
- unsigned 32-bit field which is allowed. */
- if (sizeof (unsigned long) > 4 && ((value >> 32) == -1))
- val &= 0xFFFFFFFF;
-
- if (val > maxval)
- {
- /* xgettext:c-format */
- sprintf (errbuf,
- _("operand out of range (0x%lx not between 0 and 0x%lx)"),
- val, maxval);
- return errbuf;
- }
- }
- else
- {
- if (! cgen_signed_overflow_ok_p (cd))
- {
- long minval = - (1UL << (length - 1));
- long maxval = (1UL << (length - 1)) - 1;
-
- if (value < minval || value > maxval)
- {
- sprintf
- /* xgettext:c-format */
- (errbuf, _("operand out of range (%ld not between %ld and %ld)"),
- value, minval, maxval);
- return errbuf;
- }
- }
- }
-
-#if CGEN_INT_INSN_P
-
- {
- int shift_within_word, shift_to_word, shift;
-
- /* How to shift the value to BIT0 of the word. */
- shift_to_word = total_length - (word_offset + word_length);
-
- /* How to shift the value to the field within the word. */
- if (CGEN_INSN_LSB0_P)
- shift_within_word = start + 1 - length;
- else
- shift_within_word = word_length - start - length;
-
- /* The total SHIFT, then mask in the value. */
- shift = shift_to_word + shift_within_word;
- *buffer = (*buffer & ~(mask << shift)) | ((value & mask) << shift);
- }
-
-#else /* ! CGEN_INT_INSN_P */
-
- {
- unsigned char *bufp = (unsigned char *) buffer + word_offset / 8;
-
- insert_1 (cd, value, start, length, word_length, bufp);
- }
-
-#endif /* ! CGEN_INT_INSN_P */
-
- return NULL;
-}
-
-/* Default insn builder (insert handler).
- The instruction is recorded in CGEN_INT_INSN_P byte order (meaning
- that if CGEN_INSN_BYTES_PTR is an int * and thus, the value is
- recorded in host byte order, otherwise BUFFER is an array of bytes
- and the value is recorded in target byte order).
- The result is an error message or NULL if success. */
-
-static const char *
-insert_insn_normal (CGEN_CPU_DESC cd,
- const CGEN_INSN * insn,
- CGEN_FIELDS * fields,
- CGEN_INSN_BYTES_PTR buffer,
- bfd_vma pc)
-{
- const CGEN_SYNTAX *syntax = CGEN_INSN_SYNTAX (insn);
- unsigned long value;
- const CGEN_SYNTAX_CHAR_TYPE * syn;
-
- CGEN_INIT_INSERT (cd);
- value = CGEN_INSN_BASE_VALUE (insn);
-
- /* If we're recording insns as numbers (rather than a string of bytes),
- target byte order handling is deferred until later. */
-
-#if CGEN_INT_INSN_P
-
- put_insn_int_value (cd, buffer, cd->base_insn_bitsize,
- CGEN_FIELDS_BITSIZE (fields), value);
-
-#else
-
- cgen_put_insn_value (cd, buffer, min ((unsigned) cd->base_insn_bitsize,
- (unsigned) CGEN_FIELDS_BITSIZE (fields)),
- value, cd->insn_endian);
-
-#endif /* ! CGEN_INT_INSN_P */
-
- /* ??? It would be better to scan the format's fields.
- Still need to be able to insert a value based on the operand though;
- e.g. storing a branch displacement that got resolved later.
- Needs more thought first. */
-
- for (syn = CGEN_SYNTAX_STRING (syntax); * syn; ++ syn)
- {
- const char *errmsg;
-
- if (CGEN_SYNTAX_CHAR_P (* syn))
- continue;
-
- errmsg = (* cd->insert_operand) (cd, CGEN_SYNTAX_FIELD (*syn),
- fields, buffer, pc);
- if (errmsg)
- return errmsg;
- }
-
- return NULL;
-}
-
-#if CGEN_INT_INSN_P
-/* Cover function to store an insn value into an integral insn. Must go here
- because it needs <prefix>-desc.h for CGEN_INT_INSN_P. */
-
-static void
-put_insn_int_value (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
- CGEN_INSN_BYTES_PTR buf,
- int length,
- int insn_length,
- CGEN_INSN_INT value)
-{
- /* For architectures with insns smaller than the base-insn-bitsize,
- length may be too big. */
- if (length > insn_length)
- *buf = value;
- else
- {
- int shift = insn_length - length;
- /* Written this way to avoid undefined behaviour. */
- CGEN_INSN_INT mask = length == 0 ? 0 : (1UL << (length - 1) << 1) - 1;
-
- *buf = (*buf & ~(mask << shift)) | ((value & mask) << shift);
- }
-}
-#endif
-\f
-/* Operand extraction. */
-
-#if ! CGEN_INT_INSN_P
-
-/* Subroutine of extract_normal.
- Ensure sufficient bytes are cached in EX_INFO.
- OFFSET is the offset in bytes from the start of the insn of the value.
- BYTES is the length of the needed value.
- Returns 1 for success, 0 for failure. */
-
-static CGEN_INLINE int
-fill_cache (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
- CGEN_EXTRACT_INFO *ex_info,
- int offset,
- int bytes,
- bfd_vma pc)
-{
- /* It's doubtful that the middle part has already been fetched so
- we don't optimize that case. kiss. */
- unsigned int mask;
- disassemble_info *info = (disassemble_info *) ex_info->dis_info;
-
- /* First do a quick check. */
- mask = (1 << bytes) - 1;
- if (((ex_info->valid >> offset) & mask) == mask)
- return 1;
-
- /* Search for the first byte we need to read. */
- for (mask = 1 << offset; bytes > 0; --bytes, ++offset, mask <<= 1)
- if (! (mask & ex_info->valid))
- break;
-
- if (bytes)
- {
- int status;
-
- pc += offset;
- status = (*info->read_memory_func)
- (pc, ex_info->insn_bytes + offset, bytes, info);
-
- if (status != 0)
- {
- (*info->memory_error_func) (status, pc, info);
- return 0;
- }
-
- ex_info->valid |= ((1 << bytes) - 1) << offset;
- }
-
- return 1;
-}
-
-/* Subroutine of extract_normal. */
-
-static CGEN_INLINE long
-extract_1 (CGEN_CPU_DESC cd,
- CGEN_EXTRACT_INFO *ex_info ATTRIBUTE_UNUSED,
- int start,
- int length,
- int word_length,
- unsigned char *bufp,
- bfd_vma pc ATTRIBUTE_UNUSED)
-{
- unsigned long x;
- int shift;
-
- x = cgen_get_insn_value (cd, bufp, word_length, cd->endian);
-
- if (CGEN_INSN_LSB0_P)
- shift = (start + 1) - length;
- else
- shift = (word_length - (start + length));
- return x >> shift;
-}
-
-#endif /* ! CGEN_INT_INSN_P */
-
-/* Default extraction routine.
-
- INSN_VALUE is the first base_insn_bitsize bits of the insn in host order,
- or sometimes less for cases like the m32r where the base insn size is 32
- but some insns are 16 bits.
- ATTRS is a mask of the boolean attributes. We only need `SIGNED',
- but for generality we take a bitmask of all of them.
- WORD_OFFSET is the offset in bits from the start of the insn of the value.
- WORD_LENGTH is the length of the word in bits in which the value resides.
- START is the starting bit number in the word, architecture origin.
- LENGTH is the length of VALUE in bits.
- TOTAL_LENGTH is the total length of the insn in bits.
-
- Returns 1 for success, 0 for failure. */
-
-/* ??? The return code isn't properly used. wip. */
-
-/* ??? This doesn't handle bfd_vma's. Create another function when
- necessary. */
-
-static int
-extract_normal (CGEN_CPU_DESC cd,
-#if ! CGEN_INT_INSN_P
- CGEN_EXTRACT_INFO *ex_info,
-#else
- CGEN_EXTRACT_INFO *ex_info ATTRIBUTE_UNUSED,
-#endif
- CGEN_INSN_INT insn_value,
- unsigned int attrs,
- unsigned int word_offset,
- unsigned int start,
- unsigned int length,
- unsigned int word_length,
- unsigned int total_length,
-#if ! CGEN_INT_INSN_P
- bfd_vma pc,
-#else
- bfd_vma pc ATTRIBUTE_UNUSED,
-#endif
- long *valuep)
-{
- long value, mask;
-
- /* If LENGTH is zero, this operand doesn't contribute to the value
- so give it a standard value of zero. */
- if (length == 0)
- {
- *valuep = 0;
- return 1;
- }
-
- if (word_length > 8 * sizeof (CGEN_INSN_INT))
- abort ();
-
- /* For architectures with insns smaller than the insn-base-bitsize,
- word_length may be too big. */
- if (cd->min_insn_bitsize < cd->base_insn_bitsize)
- {
- if (word_offset + word_length > total_length)
- word_length = total_length - word_offset;
- }
-
- /* Does the value reside in INSN_VALUE, and at the right alignment? */
-
- if (CGEN_INT_INSN_P || (word_offset == 0 && word_length == total_length))
- {
- if (CGEN_INSN_LSB0_P)
- value = insn_value >> ((word_offset + start + 1) - length);
- else
- value = insn_value >> (total_length - ( word_offset + start + length));
- }
-
-#if ! CGEN_INT_INSN_P
-
- else
- {
- unsigned char *bufp = ex_info->insn_bytes + word_offset / 8;
-
- if (word_length > 8 * sizeof (CGEN_INSN_INT))
- abort ();
-
- if (fill_cache (cd, ex_info, word_offset / 8, word_length / 8, pc) == 0)
- {
- *valuep = 0;
- return 0;
- }
-
- value = extract_1 (cd, ex_info, start, length, word_length, bufp, pc);
- }
-
-#endif /* ! CGEN_INT_INSN_P */
-
- /* Written this way to avoid undefined behaviour. */
- mask = (1UL << (length - 1) << 1) - 1;
-
- value &= mask;
- /* sign extend? */
- if (CGEN_BOOL_ATTR (attrs, CGEN_IFLD_SIGNED)
- && (value & (1UL << (length - 1))))
- value |= ~mask;
-
- *valuep = value;
-
- return 1;
-}
-
-/* Default insn extractor.
-
- INSN_VALUE is the first base_insn_bitsize bits, translated to host order.
- The extracted fields are stored in FIELDS.
- EX_INFO is used to handle reading variable length insns.
- Return the length of the insn in bits, or 0 if no match,
- or -1 if an error occurs fetching data (memory_error_func will have
- been called). */
-
-static int
-extract_insn_normal (CGEN_CPU_DESC cd,
- const CGEN_INSN *insn,
- CGEN_EXTRACT_INFO *ex_info,
- CGEN_INSN_INT insn_value,
- CGEN_FIELDS *fields,
- bfd_vma pc)
-{
- const CGEN_SYNTAX *syntax = CGEN_INSN_SYNTAX (insn);
- const CGEN_SYNTAX_CHAR_TYPE *syn;
-
- CGEN_FIELDS_BITSIZE (fields) = CGEN_INSN_BITSIZE (insn);
-
- CGEN_INIT_EXTRACT (cd);
-
- for (syn = CGEN_SYNTAX_STRING (syntax); *syn; ++syn)
- {
- int length;
-
- if (CGEN_SYNTAX_CHAR_P (*syn))
- continue;
-
- length = (* cd->extract_operand) (cd, CGEN_SYNTAX_FIELD (*syn),
- ex_info, insn_value, fields, pc);
- if (length <= 0)
- return length;
- }
-
- /* We recognized and successfully extracted this insn. */
- return CGEN_INSN_BITSIZE (insn);
-}
-\f
-/* Machine generated code added here. */
-
-const char * xc16x_cgen_insert_operand
- (CGEN_CPU_DESC, int, CGEN_FIELDS *, CGEN_INSN_BYTES_PTR, bfd_vma);
-
-/* Main entry point for operand insertion.
-
- This function is basically just a big switch statement. Earlier versions
- used tables to look up the function to use, but
- - if the table contains both assembler and disassembler functions then
- the disassembler contains much of the assembler and vice-versa,
- - there's a lot of inlining possibilities as things grow,
- - using a switch statement avoids the function call overhead.
-
- This function could be moved into `parse_insn_normal', but keeping it
- separate makes clear the interface between `parse_insn_normal' and each of
- the handlers. It's also needed by GAS to insert operands that couldn't be
- resolved during parsing. */
-
-const char *
-xc16x_cgen_insert_operand (CGEN_CPU_DESC cd,
- int opindex,
- CGEN_FIELDS * fields,
- CGEN_INSN_BYTES_PTR buffer,
- bfd_vma pc ATTRIBUTE_UNUSED)
-{
- const char * errmsg = NULL;
- unsigned int total_length = CGEN_FIELDS_BITSIZE (fields);
-
- switch (opindex)
- {
- case XC16X_OPERAND_REGNAM :
- errmsg = insert_normal (cd, fields->f_reg8, 0, 0, 15, 8, 32, total_length, buffer);
- break;
- case XC16X_OPERAND_BIT01 :
- errmsg = insert_normal (cd, fields->f_op_1bit, 0, 0, 8, 1, 32, total_length, buffer);
- break;
- case XC16X_OPERAND_BIT1 :
- errmsg = insert_normal (cd, fields->f_op_bit1, 0, 0, 11, 1, 32, total_length, buffer);
- break;
- case XC16X_OPERAND_BIT2 :
- errmsg = insert_normal (cd, fields->f_op_bit2, 0, 0, 11, 2, 32, total_length, buffer);
- break;
- case XC16X_OPERAND_BIT4 :
- errmsg = insert_normal (cd, fields->f_op_bit4, 0, 0, 11, 4, 32, total_length, buffer);
- break;
- case XC16X_OPERAND_BIT8 :
- errmsg = insert_normal (cd, fields->f_op_bit8, 0, 0, 31, 8, 32, total_length, buffer);
- break;
- case XC16X_OPERAND_BITONE :
- errmsg = insert_normal (cd, fields->f_op_onebit, 0, 0, 9, 1, 32, total_length, buffer);
- break;
- case XC16X_OPERAND_CADDR :
- errmsg = insert_normal (cd, fields->f_offset16, 0|(1<<CGEN_IFLD_RELOC)|(1<<CGEN_IFLD_ABS_ADDR), 0, 31, 16, 32, total_length, buffer);
- break;
- case XC16X_OPERAND_COND :
- errmsg = insert_normal (cd, fields->f_condcode, 0, 0, 7, 4, 32, total_length, buffer);
- break;
- case XC16X_OPERAND_DATA8 :
- errmsg = insert_normal (cd, fields->f_data8, 0, 0, 23, 8, 32, total_length, buffer);
- break;
- case XC16X_OPERAND_DATAHI8 :
- errmsg = insert_normal (cd, fields->f_datahi8, 0, 0, 31, 8, 32, total_length, buffer);
- break;
- case XC16X_OPERAND_DOT :
- break;
- case XC16X_OPERAND_DR :
- errmsg = insert_normal (cd, fields->f_r1, 0, 0, 15, 4, 32, total_length, buffer);
- break;
- case XC16X_OPERAND_DRB :
- errmsg = insert_normal (cd, fields->f_r1, 0, 0, 15, 4, 32, total_length, buffer);
- break;
- case XC16X_OPERAND_DRI :
- errmsg = insert_normal (cd, fields->f_r4, 0, 0, 11, 4, 32, total_length, buffer);
- break;
- case XC16X_OPERAND_EXTCOND :
- errmsg = insert_normal (cd, fields->f_extccode, 0, 0, 15, 5, 32, total_length, buffer);
- break;
- case XC16X_OPERAND_GENREG :
- errmsg = insert_normal (cd, fields->f_regb8, 0, 0, 15, 8, 32, total_length, buffer);
- break;
- case XC16X_OPERAND_HASH :
- break;
- case XC16X_OPERAND_ICOND :
- errmsg = insert_normal (cd, fields->f_icondcode, 0, 0, 15, 4, 32, total_length, buffer);
- break;
- case XC16X_OPERAND_LBIT2 :
- errmsg = insert_normal (cd, fields->f_op_lbit2, 0, 0, 15, 2, 32, total_length, buffer);
- break;
- case XC16X_OPERAND_LBIT4 :
- errmsg = insert_normal (cd, fields->f_op_lbit4, 0, 0, 15, 4, 32, total_length, buffer);
- break;
- case XC16X_OPERAND_MASK8 :
- errmsg = insert_normal (cd, fields->f_mask8, 0, 0, 23, 8, 32, total_length, buffer);
- break;
- case XC16X_OPERAND_MASKLO8 :
- errmsg = insert_normal (cd, fields->f_datahi8, 0, 0, 31, 8, 32, total_length, buffer);
- break;
- case XC16X_OPERAND_MEMGR8 :
- errmsg = insert_normal (cd, fields->f_memgr8, 0, 0, 31, 16, 32, total_length, buffer);
- break;
- case XC16X_OPERAND_MEMORY :
- errmsg = insert_normal (cd, fields->f_memory, 0, 0, 31, 16, 32, total_length, buffer);
- break;
- case XC16X_OPERAND_PAG :
- break;
- case XC16X_OPERAND_PAGENUM :
- errmsg = insert_normal (cd, fields->f_pagenum, 0, 0, 25, 10, 32, total_length, buffer);
- break;
- case XC16X_OPERAND_POF :
- break;
- case XC16X_OPERAND_QBIT :
- errmsg = insert_normal (cd, fields->f_qbit, 0, 0, 7, 4, 32, total_length, buffer);
- break;
- case XC16X_OPERAND_QHIBIT :
- errmsg = insert_normal (cd, fields->f_qhibit, 0, 0, 27, 4, 32, total_length, buffer);
- break;
- case XC16X_OPERAND_QLOBIT :
- errmsg = insert_normal (cd, fields->f_qlobit, 0, 0, 31, 4, 32, total_length, buffer);
- break;
- case XC16X_OPERAND_REG8 :
- errmsg = insert_normal (cd, fields->f_reg8, 0, 0, 15, 8, 32, total_length, buffer);
- break;
- case XC16X_OPERAND_REGB8 :
- errmsg = insert_normal (cd, fields->f_regb8, 0, 0, 15, 8, 32, total_length, buffer);
- break;
- case XC16X_OPERAND_REGBMEM8 :
- errmsg = insert_normal (cd, fields->f_regmem8, 0, 0, 15, 8, 32, total_length, buffer);
- break;
- case XC16X_OPERAND_REGHI8 :
- errmsg = insert_normal (cd, fields->f_reghi8, 0, 0, 23, 8, 32, total_length, buffer);
- break;
- case XC16X_OPERAND_REGMEM8 :
- errmsg = insert_normal (cd, fields->f_regmem8, 0, 0, 15, 8, 32, total_length, buffer);
- break;
- case XC16X_OPERAND_REGOFF8 :
- errmsg = insert_normal (cd, fields->f_regoff8, 0, 0, 15, 8, 32, total_length, buffer);
- break;
- case XC16X_OPERAND_REL :
- errmsg = insert_normal (cd, fields->f_rel8, 0|(1<<CGEN_IFLD_RELOC)|(1<<CGEN_IFLD_PCREL_ADDR), 0, 15, 8, 32, total_length, buffer);
- break;
- case XC16X_OPERAND_RELHI :
- errmsg = insert_normal (cd, fields->f_relhi8, 0|(1<<CGEN_IFLD_RELOC)|(1<<CGEN_IFLD_PCREL_ADDR), 0, 23, 8, 32, total_length, buffer);
- break;
- case XC16X_OPERAND_SEG :
- errmsg = insert_normal (cd, fields->f_seg8, 0, 0, 15, 8, 32, total_length, buffer);
- break;
- case XC16X_OPERAND_SEGHI8 :
- errmsg = insert_normal (cd, fields->f_segnum8, 0, 0, 23, 8, 32, total_length, buffer);
- break;
- case XC16X_OPERAND_SEGM :
- break;
- case XC16X_OPERAND_SOF :
- break;
- case XC16X_OPERAND_SR :
- errmsg = insert_normal (cd, fields->f_r2, 0, 0, 11, 4, 32, total_length, buffer);
- break;
- case XC16X_OPERAND_SR2 :
- errmsg = insert_normal (cd, fields->f_r0, 0, 0, 9, 2, 32, total_length, buffer);
- break;
- case XC16X_OPERAND_SRB :
- errmsg = insert_normal (cd, fields->f_r2, 0, 0, 11, 4, 32, total_length, buffer);
- break;
- case XC16X_OPERAND_SRC1 :
- errmsg = insert_normal (cd, fields->f_r1, 0, 0, 15, 4, 32, total_length, buffer);
- break;
- case XC16X_OPERAND_SRC2 :
- errmsg = insert_normal (cd, fields->f_r2, 0, 0, 11, 4, 32, total_length, buffer);
- break;
- case XC16X_OPERAND_SRDIV :
- errmsg = insert_normal (cd, fields->f_reg8, 0, 0, 15, 8, 32, total_length, buffer);
- break;
- case XC16X_OPERAND_U4 :
- errmsg = insert_normal (cd, fields->f_uimm4, 0, 0, 15, 4, 32, total_length, buffer);
- break;
- case XC16X_OPERAND_UIMM16 :
- errmsg = insert_normal (cd, fields->f_uimm16, 0, 0, 31, 16, 32, total_length, buffer);
- break;
- case XC16X_OPERAND_UIMM2 :
- errmsg = insert_normal (cd, fields->f_uimm2, 0, 0, 13, 2, 32, total_length, buffer);
- break;
- case XC16X_OPERAND_UIMM3 :
- errmsg = insert_normal (cd, fields->f_uimm3, 0, 0, 10, 3, 32, total_length, buffer);
- break;
- case XC16X_OPERAND_UIMM4 :
- errmsg = insert_normal (cd, fields->f_uimm4, 0, 0, 15, 4, 32, total_length, buffer);
- break;
- case XC16X_OPERAND_UIMM7 :
- errmsg = insert_normal (cd, fields->f_uimm7, 0|(1<<CGEN_IFLD_RELOC)|(1<<CGEN_IFLD_PCREL_ADDR), 0, 15, 7, 32, total_length, buffer);
- break;
- case XC16X_OPERAND_UIMM8 :
- errmsg = insert_normal (cd, fields->f_uimm8, 0, 0, 23, 8, 32, total_length, buffer);
- break;
- case XC16X_OPERAND_UPAG16 :
- errmsg = insert_normal (cd, fields->f_uimm16, 0, 0, 31, 16, 32, total_length, buffer);
- break;
- case XC16X_OPERAND_UPOF16 :
- errmsg = insert_normal (cd, fields->f_memory, 0, 0, 31, 16, 32, total_length, buffer);
- break;
- case XC16X_OPERAND_USEG16 :
- errmsg = insert_normal (cd, fields->f_offset16, 0|(1<<CGEN_IFLD_RELOC)|(1<<CGEN_IFLD_ABS_ADDR), 0, 31, 16, 32, total_length, buffer);
- break;
- case XC16X_OPERAND_USEG8 :
- errmsg = insert_normal (cd, fields->f_seg8, 0, 0, 15, 8, 32, total_length, buffer);
- break;
- case XC16X_OPERAND_USOF16 :
- errmsg = insert_normal (cd, fields->f_offset16, 0|(1<<CGEN_IFLD_RELOC)|(1<<CGEN_IFLD_ABS_ADDR), 0, 31, 16, 32, total_length, buffer);
- break;
-
- default :
- /* xgettext:c-format */
- opcodes_error_handler
- (_("internal error: unrecognized field %d while building insn"),
- opindex);
- abort ();
- }
-
- return errmsg;
-}
-
-int xc16x_cgen_extract_operand
- (CGEN_CPU_DESC, int, CGEN_EXTRACT_INFO *, CGEN_INSN_INT, CGEN_FIELDS *, bfd_vma);
-
-/* Main entry point for operand extraction.
- The result is <= 0 for error, >0 for success.
- ??? Actual values aren't well defined right now.
-
- This function is basically just a big switch statement. Earlier versions
- used tables to look up the function to use, but
- - if the table contains both assembler and disassembler functions then
- the disassembler contains much of the assembler and vice-versa,
- - there's a lot of inlining possibilities as things grow,
- - using a switch statement avoids the function call overhead.
-
- This function could be moved into `print_insn_normal', but keeping it
- separate makes clear the interface between `print_insn_normal' and each of
- the handlers. */
-
-int
-xc16x_cgen_extract_operand (CGEN_CPU_DESC cd,
- int opindex,
- CGEN_EXTRACT_INFO *ex_info,
- CGEN_INSN_INT insn_value,
- CGEN_FIELDS * fields,
- bfd_vma pc)
-{
- /* Assume success (for those operands that are nops). */
- int length = 1;
- unsigned int total_length = CGEN_FIELDS_BITSIZE (fields);
-
- switch (opindex)
- {
- case XC16X_OPERAND_REGNAM :
- length = extract_normal (cd, ex_info, insn_value, 0, 0, 15, 8, 32, total_length, pc, & fields->f_reg8);
- break;
- case XC16X_OPERAND_BIT01 :
- length = extract_normal (cd, ex_info, insn_value, 0, 0, 8, 1, 32, total_length, pc, & fields->f_op_1bit);
- break;
- case XC16X_OPERAND_BIT1 :
- length = extract_normal (cd, ex_info, insn_value, 0, 0, 11, 1, 32, total_length, pc, & fields->f_op_bit1);
- break;
- case XC16X_OPERAND_BIT2 :
- length = extract_normal (cd, ex_info, insn_value, 0, 0, 11, 2, 32, total_length, pc, & fields->f_op_bit2);
- break;
- case XC16X_OPERAND_BIT4 :
- length = extract_normal (cd, ex_info, insn_value, 0, 0, 11, 4, 32, total_length, pc, & fields->f_op_bit4);
- break;
- case XC16X_OPERAND_BIT8 :
- length = extract_normal (cd, ex_info, insn_value, 0, 0, 31, 8, 32, total_length, pc, & fields->f_op_bit8);
- break;
- case XC16X_OPERAND_BITONE :
- length = extract_normal (cd, ex_info, insn_value, 0, 0, 9, 1, 32, total_length, pc, & fields->f_op_onebit);
- break;
- case XC16X_OPERAND_CADDR :
- length = extract_normal (cd, ex_info, insn_value, 0|(1<<CGEN_IFLD_RELOC)|(1<<CGEN_IFLD_ABS_ADDR), 0, 31, 16, 32, total_length, pc, & fields->f_offset16);
- break;
- case XC16X_OPERAND_COND :
- length = extract_normal (cd, ex_info, insn_value, 0, 0, 7, 4, 32, total_length, pc, & fields->f_condcode);
- break;
- case XC16X_OPERAND_DATA8 :
- length = extract_normal (cd, ex_info, insn_value, 0, 0, 23, 8, 32, total_length, pc, & fields->f_data8);
- break;
- case XC16X_OPERAND_DATAHI8 :
- length = extract_normal (cd, ex_info, insn_value, 0, 0, 31, 8, 32, total_length, pc, & fields->f_datahi8);
- break;
- case XC16X_OPERAND_DOT :
- break;
- case XC16X_OPERAND_DR :
- length = extract_normal (cd, ex_info, insn_value, 0, 0, 15, 4, 32, total_length, pc, & fields->f_r1);
- break;
- case XC16X_OPERAND_DRB :
- length = extract_normal (cd, ex_info, insn_value, 0, 0, 15, 4, 32, total_length, pc, & fields->f_r1);
- break;
- case XC16X_OPERAND_DRI :
- length = extract_normal (cd, ex_info, insn_value, 0, 0, 11, 4, 32, total_length, pc, & fields->f_r4);
- break;
- case XC16X_OPERAND_EXTCOND :
- length = extract_normal (cd, ex_info, insn_value, 0, 0, 15, 5, 32, total_length, pc, & fields->f_extccode);
- break;
- case XC16X_OPERAND_GENREG :
- length = extract_normal (cd, ex_info, insn_value, 0, 0, 15, 8, 32, total_length, pc, & fields->f_regb8);
- break;
- case XC16X_OPERAND_HASH :
- break;
- case XC16X_OPERAND_ICOND :
- length = extract_normal (cd, ex_info, insn_value, 0, 0, 15, 4, 32, total_length, pc, & fields->f_icondcode);
- break;
- case XC16X_OPERAND_LBIT2 :
- length = extract_normal (cd, ex_info, insn_value, 0, 0, 15, 2, 32, total_length, pc, & fields->f_op_lbit2);
- break;
- case XC16X_OPERAND_LBIT4 :
- length = extract_normal (cd, ex_info, insn_value, 0, 0, 15, 4, 32, total_length, pc, & fields->f_op_lbit4);
- break;
- case XC16X_OPERAND_MASK8 :
- length = extract_normal (cd, ex_info, insn_value, 0, 0, 23, 8, 32, total_length, pc, & fields->f_mask8);
- break;
- case XC16X_OPERAND_MASKLO8 :
- length = extract_normal (cd, ex_info, insn_value, 0, 0, 31, 8, 32, total_length, pc, & fields->f_datahi8);
- break;
- case XC16X_OPERAND_MEMGR8 :
- length = extract_normal (cd, ex_info, insn_value, 0, 0, 31, 16, 32, total_length, pc, & fields->f_memgr8);
- break;
- case XC16X_OPERAND_MEMORY :
- length = extract_normal (cd, ex_info, insn_value, 0, 0, 31, 16, 32, total_length, pc, & fields->f_memory);
- break;
- case XC16X_OPERAND_PAG :
- break;
- case XC16X_OPERAND_PAGENUM :
- length = extract_normal (cd, ex_info, insn_value, 0, 0, 25, 10, 32, total_length, pc, & fields->f_pagenum);
- break;
- case XC16X_OPERAND_POF :
- break;
- case XC16X_OPERAND_QBIT :
- length = extract_normal (cd, ex_info, insn_value, 0, 0, 7, 4, 32, total_length, pc, & fields->f_qbit);
- break;
- case XC16X_OPERAND_QHIBIT :
- length = extract_normal (cd, ex_info, insn_value, 0, 0, 27, 4, 32, total_length, pc, & fields->f_qhibit);
- break;
- case XC16X_OPERAND_QLOBIT :
- length = extract_normal (cd, ex_info, insn_value, 0, 0, 31, 4, 32, total_length, pc, & fields->f_qlobit);
- break;
- case XC16X_OPERAND_REG8 :
- length = extract_normal (cd, ex_info, insn_value, 0, 0, 15, 8, 32, total_length, pc, & fields->f_reg8);
- break;
- case XC16X_OPERAND_REGB8 :
- length = extract_normal (cd, ex_info, insn_value, 0, 0, 15, 8, 32, total_length, pc, & fields->f_regb8);
- break;
- case XC16X_OPERAND_REGBMEM8 :
- length = extract_normal (cd, ex_info, insn_value, 0, 0, 15, 8, 32, total_length, pc, & fields->f_regmem8);
- break;
- case XC16X_OPERAND_REGHI8 :
- length = extract_normal (cd, ex_info, insn_value, 0, 0, 23, 8, 32, total_length, pc, & fields->f_reghi8);
- break;
- case XC16X_OPERAND_REGMEM8 :
- length = extract_normal (cd, ex_info, insn_value, 0, 0, 15, 8, 32, total_length, pc, & fields->f_regmem8);
- break;
- case XC16X_OPERAND_REGOFF8 :
- length = extract_normal (cd, ex_info, insn_value, 0, 0, 15, 8, 32, total_length, pc, & fields->f_regoff8);
- break;
- case XC16X_OPERAND_REL :
- length = extract_normal (cd, ex_info, insn_value, 0|(1<<CGEN_IFLD_RELOC)|(1<<CGEN_IFLD_PCREL_ADDR), 0, 15, 8, 32, total_length, pc, & fields->f_rel8);
- break;
- case XC16X_OPERAND_RELHI :
- length = extract_normal (cd, ex_info, insn_value, 0|(1<<CGEN_IFLD_RELOC)|(1<<CGEN_IFLD_PCREL_ADDR), 0, 23, 8, 32, total_length, pc, & fields->f_relhi8);
- break;
- case XC16X_OPERAND_SEG :
- length = extract_normal (cd, ex_info, insn_value, 0, 0, 15, 8, 32, total_length, pc, & fields->f_seg8);
- break;
- case XC16X_OPERAND_SEGHI8 :
- length = extract_normal (cd, ex_info, insn_value, 0, 0, 23, 8, 32, total_length, pc, & fields->f_segnum8);
- break;
- case XC16X_OPERAND_SEGM :
- break;
- case XC16X_OPERAND_SOF :
- break;
- case XC16X_OPERAND_SR :
- length = extract_normal (cd, ex_info, insn_value, 0, 0, 11, 4, 32, total_length, pc, & fields->f_r2);
- break;
- case XC16X_OPERAND_SR2 :
- length = extract_normal (cd, ex_info, insn_value, 0, 0, 9, 2, 32, total_length, pc, & fields->f_r0);
- break;
- case XC16X_OPERAND_SRB :
- length = extract_normal (cd, ex_info, insn_value, 0, 0, 11, 4, 32, total_length, pc, & fields->f_r2);
- break;
- case XC16X_OPERAND_SRC1 :
- length = extract_normal (cd, ex_info, insn_value, 0, 0, 15, 4, 32, total_length, pc, & fields->f_r1);
- break;
- case XC16X_OPERAND_SRC2 :
- length = extract_normal (cd, ex_info, insn_value, 0, 0, 11, 4, 32, total_length, pc, & fields->f_r2);
- break;
- case XC16X_OPERAND_SRDIV :
- length = extract_normal (cd, ex_info, insn_value, 0, 0, 15, 8, 32, total_length, pc, & fields->f_reg8);
- break;
- case XC16X_OPERAND_U4 :
- length = extract_normal (cd, ex_info, insn_value, 0, 0, 15, 4, 32, total_length, pc, & fields->f_uimm4);
- break;
- case XC16X_OPERAND_UIMM16 :
- length = extract_normal (cd, ex_info, insn_value, 0, 0, 31, 16, 32, total_length, pc, & fields->f_uimm16);
- break;
- case XC16X_OPERAND_UIMM2 :
- length = extract_normal (cd, ex_info, insn_value, 0, 0, 13, 2, 32, total_length, pc, & fields->f_uimm2);
- break;
- case XC16X_OPERAND_UIMM3 :
- length = extract_normal (cd, ex_info, insn_value, 0, 0, 10, 3, 32, total_length, pc, & fields->f_uimm3);
- break;
- case XC16X_OPERAND_UIMM4 :
- length = extract_normal (cd, ex_info, insn_value, 0, 0, 15, 4, 32, total_length, pc, & fields->f_uimm4);
- break;
- case XC16X_OPERAND_UIMM7 :
- length = extract_normal (cd, ex_info, insn_value, 0|(1<<CGEN_IFLD_RELOC)|(1<<CGEN_IFLD_PCREL_ADDR), 0, 15, 7, 32, total_length, pc, & fields->f_uimm7);
- break;
- case XC16X_OPERAND_UIMM8 :
- length = extract_normal (cd, ex_info, insn_value, 0, 0, 23, 8, 32, total_length, pc, & fields->f_uimm8);
- break;
- case XC16X_OPERAND_UPAG16 :
- length = extract_normal (cd, ex_info, insn_value, 0, 0, 31, 16, 32, total_length, pc, & fields->f_uimm16);
- break;
- case XC16X_OPERAND_UPOF16 :
- length = extract_normal (cd, ex_info, insn_value, 0, 0, 31, 16, 32, total_length, pc, & fields->f_memory);
- break;
- case XC16X_OPERAND_USEG16 :
- length = extract_normal (cd, ex_info, insn_value, 0|(1<<CGEN_IFLD_RELOC)|(1<<CGEN_IFLD_ABS_ADDR), 0, 31, 16, 32, total_length, pc, & fields->f_offset16);
- break;
- case XC16X_OPERAND_USEG8 :
- length = extract_normal (cd, ex_info, insn_value, 0, 0, 15, 8, 32, total_length, pc, & fields->f_seg8);
- break;
- case XC16X_OPERAND_USOF16 :
- length = extract_normal (cd, ex_info, insn_value, 0|(1<<CGEN_IFLD_RELOC)|(1<<CGEN_IFLD_ABS_ADDR), 0, 31, 16, 32, total_length, pc, & fields->f_offset16);
- break;
-
- default :
- /* xgettext:c-format */
- opcodes_error_handler
- (_("internal error: unrecognized field %d while decoding insn"),
- opindex);
- abort ();
- }
-
- return length;
-}
-
-cgen_insert_fn * const xc16x_cgen_insert_handlers[] =
-{
- insert_insn_normal,
-};
-
-cgen_extract_fn * const xc16x_cgen_extract_handlers[] =
-{
- extract_insn_normal,
-};
-
-int xc16x_cgen_get_int_operand (CGEN_CPU_DESC, int, const CGEN_FIELDS *);
-bfd_vma xc16x_cgen_get_vma_operand (CGEN_CPU_DESC, int, const CGEN_FIELDS *);
-
-/* Getting values from cgen_fields is handled by a collection of functions.
- They are distinguished by the type of the VALUE argument they return.
- TODO: floating point, inlining support, remove cases where result type
- not appropriate. */
-
-int
-xc16x_cgen_get_int_operand (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
- int opindex,
- const CGEN_FIELDS * fields)
-{
- int value;
-
- switch (opindex)
- {
- case XC16X_OPERAND_REGNAM :
- value = fields->f_reg8;
- break;
- case XC16X_OPERAND_BIT01 :
- value = fields->f_op_1bit;
- break;
- case XC16X_OPERAND_BIT1 :
- value = fields->f_op_bit1;
- break;
- case XC16X_OPERAND_BIT2 :
- value = fields->f_op_bit2;
- break;
- case XC16X_OPERAND_BIT4 :
- value = fields->f_op_bit4;
- break;
- case XC16X_OPERAND_BIT8 :
- value = fields->f_op_bit8;
- break;
- case XC16X_OPERAND_BITONE :
- value = fields->f_op_onebit;
- break;
- case XC16X_OPERAND_CADDR :
- value = fields->f_offset16;
- break;
- case XC16X_OPERAND_COND :
- value = fields->f_condcode;
- break;
- case XC16X_OPERAND_DATA8 :
- value = fields->f_data8;
- break;
- case XC16X_OPERAND_DATAHI8 :
- value = fields->f_datahi8;
- break;
- case XC16X_OPERAND_DOT :
- value = 0;
- break;
- case XC16X_OPERAND_DR :
- value = fields->f_r1;
- break;
- case XC16X_OPERAND_DRB :
- value = fields->f_r1;
- break;
- case XC16X_OPERAND_DRI :
- value = fields->f_r4;
- break;
- case XC16X_OPERAND_EXTCOND :
- value = fields->f_extccode;
- break;
- case XC16X_OPERAND_GENREG :
- value = fields->f_regb8;
- break;
- case XC16X_OPERAND_HASH :
- value = 0;
- break;
- case XC16X_OPERAND_ICOND :
- value = fields->f_icondcode;
- break;
- case XC16X_OPERAND_LBIT2 :
- value = fields->f_op_lbit2;
- break;
- case XC16X_OPERAND_LBIT4 :
- value = fields->f_op_lbit4;
- break;
- case XC16X_OPERAND_MASK8 :
- value = fields->f_mask8;
- break;
- case XC16X_OPERAND_MASKLO8 :
- value = fields->f_datahi8;
- break;
- case XC16X_OPERAND_MEMGR8 :
- value = fields->f_memgr8;
- break;
- case XC16X_OPERAND_MEMORY :
- value = fields->f_memory;
- break;
- case XC16X_OPERAND_PAG :
- value = 0;
- break;
- case XC16X_OPERAND_PAGENUM :
- value = fields->f_pagenum;
- break;
- case XC16X_OPERAND_POF :
- value = 0;
- break;
- case XC16X_OPERAND_QBIT :
- value = fields->f_qbit;
- break;
- case XC16X_OPERAND_QHIBIT :
- value = fields->f_qhibit;
- break;
- case XC16X_OPERAND_QLOBIT :
- value = fields->f_qlobit;
- break;
- case XC16X_OPERAND_REG8 :
- value = fields->f_reg8;
- break;
- case XC16X_OPERAND_REGB8 :
- value = fields->f_regb8;
- break;
- case XC16X_OPERAND_REGBMEM8 :
- value = fields->f_regmem8;
- break;
- case XC16X_OPERAND_REGHI8 :
- value = fields->f_reghi8;
- break;
- case XC16X_OPERAND_REGMEM8 :
- value = fields->f_regmem8;
- break;
- case XC16X_OPERAND_REGOFF8 :
- value = fields->f_regoff8;
- break;
- case XC16X_OPERAND_REL :
- value = fields->f_rel8;
- break;
- case XC16X_OPERAND_RELHI :
- value = fields->f_relhi8;
- break;
- case XC16X_OPERAND_SEG :
- value = fields->f_seg8;
- break;
- case XC16X_OPERAND_SEGHI8 :
- value = fields->f_segnum8;
- break;
- case XC16X_OPERAND_SEGM :
- value = 0;
- break;
- case XC16X_OPERAND_SOF :
- value = 0;
- break;
- case XC16X_OPERAND_SR :
- value = fields->f_r2;
- break;
- case XC16X_OPERAND_SR2 :
- value = fields->f_r0;
- break;
- case XC16X_OPERAND_SRB :
- value = fields->f_r2;
- break;
- case XC16X_OPERAND_SRC1 :
- value = fields->f_r1;
- break;
- case XC16X_OPERAND_SRC2 :
- value = fields->f_r2;
- break;
- case XC16X_OPERAND_SRDIV :
- value = fields->f_reg8;
- break;
- case XC16X_OPERAND_U4 :
- value = fields->f_uimm4;
- break;
- case XC16X_OPERAND_UIMM16 :
- value = fields->f_uimm16;
- break;
- case XC16X_OPERAND_UIMM2 :
- value = fields->f_uimm2;
- break;
- case XC16X_OPERAND_UIMM3 :
- value = fields->f_uimm3;
- break;
- case XC16X_OPERAND_UIMM4 :
- value = fields->f_uimm4;
- break;
- case XC16X_OPERAND_UIMM7 :
- value = fields->f_uimm7;
- break;
- case XC16X_OPERAND_UIMM8 :
- value = fields->f_uimm8;
- break;
- case XC16X_OPERAND_UPAG16 :
- value = fields->f_uimm16;
- break;
- case XC16X_OPERAND_UPOF16 :
- value = fields->f_memory;
- break;
- case XC16X_OPERAND_USEG16 :
- value = fields->f_offset16;
- break;
- case XC16X_OPERAND_USEG8 :
- value = fields->f_seg8;
- break;
- case XC16X_OPERAND_USOF16 :
- value = fields->f_offset16;
- break;
-
- default :
- /* xgettext:c-format */
- opcodes_error_handler
- (_("internal error: unrecognized field %d while getting int operand"),
- opindex);
- abort ();
- }
-
- return value;
-}
-
-bfd_vma
-xc16x_cgen_get_vma_operand (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
- int opindex,
- const CGEN_FIELDS * fields)
-{
- bfd_vma value;
-
- switch (opindex)
- {
- case XC16X_OPERAND_REGNAM :
- value = fields->f_reg8;
- break;
- case XC16X_OPERAND_BIT01 :
- value = fields->f_op_1bit;
- break;
- case XC16X_OPERAND_BIT1 :
- value = fields->f_op_bit1;
- break;
- case XC16X_OPERAND_BIT2 :
- value = fields->f_op_bit2;
- break;
- case XC16X_OPERAND_BIT4 :
- value = fields->f_op_bit4;
- break;
- case XC16X_OPERAND_BIT8 :
- value = fields->f_op_bit8;
- break;
- case XC16X_OPERAND_BITONE :
- value = fields->f_op_onebit;
- break;
- case XC16X_OPERAND_CADDR :
- value = fields->f_offset16;
- break;
- case XC16X_OPERAND_COND :
- value = fields->f_condcode;
- break;
- case XC16X_OPERAND_DATA8 :
- value = fields->f_data8;
- break;
- case XC16X_OPERAND_DATAHI8 :
- value = fields->f_datahi8;
- break;
- case XC16X_OPERAND_DOT :
- value = 0;
- break;
- case XC16X_OPERAND_DR :
- value = fields->f_r1;
- break;
- case XC16X_OPERAND_DRB :
- value = fields->f_r1;
- break;
- case XC16X_OPERAND_DRI :
- value = fields->f_r4;
- break;
- case XC16X_OPERAND_EXTCOND :
- value = fields->f_extccode;
- break;
- case XC16X_OPERAND_GENREG :
- value = fields->f_regb8;
- break;
- case XC16X_OPERAND_HASH :
- value = 0;
- break;
- case XC16X_OPERAND_ICOND :
- value = fields->f_icondcode;
- break;
- case XC16X_OPERAND_LBIT2 :
- value = fields->f_op_lbit2;
- break;
- case XC16X_OPERAND_LBIT4 :
- value = fields->f_op_lbit4;
- break;
- case XC16X_OPERAND_MASK8 :
- value = fields->f_mask8;
- break;
- case XC16X_OPERAND_MASKLO8 :
- value = fields->f_datahi8;
- break;
- case XC16X_OPERAND_MEMGR8 :
- value = fields->f_memgr8;
- break;
- case XC16X_OPERAND_MEMORY :
- value = fields->f_memory;
- break;
- case XC16X_OPERAND_PAG :
- value = 0;
- break;
- case XC16X_OPERAND_PAGENUM :
- value = fields->f_pagenum;
- break;
- case XC16X_OPERAND_POF :
- value = 0;
- break;
- case XC16X_OPERAND_QBIT :
- value = fields->f_qbit;
- break;
- case XC16X_OPERAND_QHIBIT :
- value = fields->f_qhibit;
- break;
- case XC16X_OPERAND_QLOBIT :
- value = fields->f_qlobit;
- break;
- case XC16X_OPERAND_REG8 :
- value = fields->f_reg8;
- break;
- case XC16X_OPERAND_REGB8 :
- value = fields->f_regb8;
- break;
- case XC16X_OPERAND_REGBMEM8 :
- value = fields->f_regmem8;
- break;
- case XC16X_OPERAND_REGHI8 :
- value = fields->f_reghi8;
- break;
- case XC16X_OPERAND_REGMEM8 :
- value = fields->f_regmem8;
- break;
- case XC16X_OPERAND_REGOFF8 :
- value = fields->f_regoff8;
- break;
- case XC16X_OPERAND_REL :
- value = fields->f_rel8;
- break;
- case XC16X_OPERAND_RELHI :
- value = fields->f_relhi8;
- break;
- case XC16X_OPERAND_SEG :
- value = fields->f_seg8;
- break;
- case XC16X_OPERAND_SEGHI8 :
- value = fields->f_segnum8;
- break;
- case XC16X_OPERAND_SEGM :
- value = 0;
- break;
- case XC16X_OPERAND_SOF :
- value = 0;
- break;
- case XC16X_OPERAND_SR :
- value = fields->f_r2;
- break;
- case XC16X_OPERAND_SR2 :
- value = fields->f_r0;
- break;
- case XC16X_OPERAND_SRB :
- value = fields->f_r2;
- break;
- case XC16X_OPERAND_SRC1 :
- value = fields->f_r1;
- break;
- case XC16X_OPERAND_SRC2 :
- value = fields->f_r2;
- break;
- case XC16X_OPERAND_SRDIV :
- value = fields->f_reg8;
- break;
- case XC16X_OPERAND_U4 :
- value = fields->f_uimm4;
- break;
- case XC16X_OPERAND_UIMM16 :
- value = fields->f_uimm16;
- break;
- case XC16X_OPERAND_UIMM2 :
- value = fields->f_uimm2;
- break;
- case XC16X_OPERAND_UIMM3 :
- value = fields->f_uimm3;
- break;
- case XC16X_OPERAND_UIMM4 :
- value = fields->f_uimm4;
- break;
- case XC16X_OPERAND_UIMM7 :
- value = fields->f_uimm7;
- break;
- case XC16X_OPERAND_UIMM8 :
- value = fields->f_uimm8;
- break;
- case XC16X_OPERAND_UPAG16 :
- value = fields->f_uimm16;
- break;
- case XC16X_OPERAND_UPOF16 :
- value = fields->f_memory;
- break;
- case XC16X_OPERAND_USEG16 :
- value = fields->f_offset16;
- break;
- case XC16X_OPERAND_USEG8 :
- value = fields->f_seg8;
- break;
- case XC16X_OPERAND_USOF16 :
- value = fields->f_offset16;
- break;
-
- default :
- /* xgettext:c-format */
- opcodes_error_handler
- (_("internal error: unrecognized field %d while getting vma operand"),
- opindex);
- abort ();
- }
-
- return value;
-}
-
-void xc16x_cgen_set_int_operand (CGEN_CPU_DESC, int, CGEN_FIELDS *, int);
-void xc16x_cgen_set_vma_operand (CGEN_CPU_DESC, int, CGEN_FIELDS *, bfd_vma);
-
-/* Stuffing values in cgen_fields is handled by a collection of functions.
- They are distinguished by the type of the VALUE argument they accept.
- TODO: floating point, inlining support, remove cases where argument type
- not appropriate. */
-
-void
-xc16x_cgen_set_int_operand (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
- int opindex,
- CGEN_FIELDS * fields,
- int value)
-{
- switch (opindex)
- {
- case XC16X_OPERAND_REGNAM :
- fields->f_reg8 = value;
- break;
- case XC16X_OPERAND_BIT01 :
- fields->f_op_1bit = value;
- break;
- case XC16X_OPERAND_BIT1 :
- fields->f_op_bit1 = value;
- break;
- case XC16X_OPERAND_BIT2 :
- fields->f_op_bit2 = value;
- break;
- case XC16X_OPERAND_BIT4 :
- fields->f_op_bit4 = value;
- break;
- case XC16X_OPERAND_BIT8 :
- fields->f_op_bit8 = value;
- break;
- case XC16X_OPERAND_BITONE :
- fields->f_op_onebit = value;
- break;
- case XC16X_OPERAND_CADDR :
- fields->f_offset16 = value;
- break;
- case XC16X_OPERAND_COND :
- fields->f_condcode = value;
- break;
- case XC16X_OPERAND_DATA8 :
- fields->f_data8 = value;
- break;
- case XC16X_OPERAND_DATAHI8 :
- fields->f_datahi8 = value;
- break;
- case XC16X_OPERAND_DOT :
- break;
- case XC16X_OPERAND_DR :
- fields->f_r1 = value;
- break;
- case XC16X_OPERAND_DRB :
- fields->f_r1 = value;
- break;
- case XC16X_OPERAND_DRI :
- fields->f_r4 = value;
- break;
- case XC16X_OPERAND_EXTCOND :
- fields->f_extccode = value;
- break;
- case XC16X_OPERAND_GENREG :
- fields->f_regb8 = value;
- break;
- case XC16X_OPERAND_HASH :
- break;
- case XC16X_OPERAND_ICOND :
- fields->f_icondcode = value;
- break;
- case XC16X_OPERAND_LBIT2 :
- fields->f_op_lbit2 = value;
- break;
- case XC16X_OPERAND_LBIT4 :
- fields->f_op_lbit4 = value;
- break;
- case XC16X_OPERAND_MASK8 :
- fields->f_mask8 = value;
- break;
- case XC16X_OPERAND_MASKLO8 :
- fields->f_datahi8 = value;
- break;
- case XC16X_OPERAND_MEMGR8 :
- fields->f_memgr8 = value;
- break;
- case XC16X_OPERAND_MEMORY :
- fields->f_memory = value;
- break;
- case XC16X_OPERAND_PAG :
- break;
- case XC16X_OPERAND_PAGENUM :
- fields->f_pagenum = value;
- break;
- case XC16X_OPERAND_POF :
- break;
- case XC16X_OPERAND_QBIT :
- fields->f_qbit = value;
- break;
- case XC16X_OPERAND_QHIBIT :
- fields->f_qhibit = value;
- break;
- case XC16X_OPERAND_QLOBIT :
- fields->f_qlobit = value;
- break;
- case XC16X_OPERAND_REG8 :
- fields->f_reg8 = value;
- break;
- case XC16X_OPERAND_REGB8 :
- fields->f_regb8 = value;
- break;
- case XC16X_OPERAND_REGBMEM8 :
- fields->f_regmem8 = value;
- break;
- case XC16X_OPERAND_REGHI8 :
- fields->f_reghi8 = value;
- break;
- case XC16X_OPERAND_REGMEM8 :
- fields->f_regmem8 = value;
- break;
- case XC16X_OPERAND_REGOFF8 :
- fields->f_regoff8 = value;
- break;
- case XC16X_OPERAND_REL :
- fields->f_rel8 = value;
- break;
- case XC16X_OPERAND_RELHI :
- fields->f_relhi8 = value;
- break;
- case XC16X_OPERAND_SEG :
- fields->f_seg8 = value;
- break;
- case XC16X_OPERAND_SEGHI8 :
- fields->f_segnum8 = value;
- break;
- case XC16X_OPERAND_SEGM :
- break;
- case XC16X_OPERAND_SOF :
- break;
- case XC16X_OPERAND_SR :
- fields->f_r2 = value;
- break;
- case XC16X_OPERAND_SR2 :
- fields->f_r0 = value;
- break;
- case XC16X_OPERAND_SRB :
- fields->f_r2 = value;
- break;
- case XC16X_OPERAND_SRC1 :
- fields->f_r1 = value;
- break;
- case XC16X_OPERAND_SRC2 :
- fields->f_r2 = value;
- break;
- case XC16X_OPERAND_SRDIV :
- fields->f_reg8 = value;
- break;
- case XC16X_OPERAND_U4 :
- fields->f_uimm4 = value;
- break;
- case XC16X_OPERAND_UIMM16 :
- fields->f_uimm16 = value;
- break;
- case XC16X_OPERAND_UIMM2 :
- fields->f_uimm2 = value;
- break;
- case XC16X_OPERAND_UIMM3 :
- fields->f_uimm3 = value;
- break;
- case XC16X_OPERAND_UIMM4 :
- fields->f_uimm4 = value;
- break;
- case XC16X_OPERAND_UIMM7 :
- fields->f_uimm7 = value;
- break;
- case XC16X_OPERAND_UIMM8 :
- fields->f_uimm8 = value;
- break;
- case XC16X_OPERAND_UPAG16 :
- fields->f_uimm16 = value;
- break;
- case XC16X_OPERAND_UPOF16 :
- fields->f_memory = value;
- break;
- case XC16X_OPERAND_USEG16 :
- fields->f_offset16 = value;
- break;
- case XC16X_OPERAND_USEG8 :
- fields->f_seg8 = value;
- break;
- case XC16X_OPERAND_USOF16 :
- fields->f_offset16 = value;
- break;
-
- default :
- /* xgettext:c-format */
- opcodes_error_handler
- (_("internal error: unrecognized field %d while setting int operand"),
- opindex);
- abort ();
- }
-}
-
-void
-xc16x_cgen_set_vma_operand (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
- int opindex,
- CGEN_FIELDS * fields,
- bfd_vma value)
-{
- switch (opindex)
- {
- case XC16X_OPERAND_REGNAM :
- fields->f_reg8 = value;
- break;
- case XC16X_OPERAND_BIT01 :
- fields->f_op_1bit = value;
- break;
- case XC16X_OPERAND_BIT1 :
- fields->f_op_bit1 = value;
- break;
- case XC16X_OPERAND_BIT2 :
- fields->f_op_bit2 = value;
- break;
- case XC16X_OPERAND_BIT4 :
- fields->f_op_bit4 = value;
- break;
- case XC16X_OPERAND_BIT8 :
- fields->f_op_bit8 = value;
- break;
- case XC16X_OPERAND_BITONE :
- fields->f_op_onebit = value;
- break;
- case XC16X_OPERAND_CADDR :
- fields->f_offset16 = value;
- break;
- case XC16X_OPERAND_COND :
- fields->f_condcode = value;
- break;
- case XC16X_OPERAND_DATA8 :
- fields->f_data8 = value;
- break;
- case XC16X_OPERAND_DATAHI8 :
- fields->f_datahi8 = value;
- break;
- case XC16X_OPERAND_DOT :
- break;
- case XC16X_OPERAND_DR :
- fields->f_r1 = value;
- break;
- case XC16X_OPERAND_DRB :
- fields->f_r1 = value;
- break;
- case XC16X_OPERAND_DRI :
- fields->f_r4 = value;
- break;
- case XC16X_OPERAND_EXTCOND :
- fields->f_extccode = value;
- break;
- case XC16X_OPERAND_GENREG :
- fields->f_regb8 = value;
- break;
- case XC16X_OPERAND_HASH :
- break;
- case XC16X_OPERAND_ICOND :
- fields->f_icondcode = value;
- break;
- case XC16X_OPERAND_LBIT2 :
- fields->f_op_lbit2 = value;
- break;
- case XC16X_OPERAND_LBIT4 :
- fields->f_op_lbit4 = value;
- break;
- case XC16X_OPERAND_MASK8 :
- fields->f_mask8 = value;
- break;
- case XC16X_OPERAND_MASKLO8 :
- fields->f_datahi8 = value;
- break;
- case XC16X_OPERAND_MEMGR8 :
- fields->f_memgr8 = value;
- break;
- case XC16X_OPERAND_MEMORY :
- fields->f_memory = value;
- break;
- case XC16X_OPERAND_PAG :
- break;
- case XC16X_OPERAND_PAGENUM :
- fields->f_pagenum = value;
- break;
- case XC16X_OPERAND_POF :
- break;
- case XC16X_OPERAND_QBIT :
- fields->f_qbit = value;
- break;
- case XC16X_OPERAND_QHIBIT :
- fields->f_qhibit = value;
- break;
- case XC16X_OPERAND_QLOBIT :
- fields->f_qlobit = value;
- break;
- case XC16X_OPERAND_REG8 :
- fields->f_reg8 = value;
- break;
- case XC16X_OPERAND_REGB8 :
- fields->f_regb8 = value;
- break;
- case XC16X_OPERAND_REGBMEM8 :
- fields->f_regmem8 = value;
- break;
- case XC16X_OPERAND_REGHI8 :
- fields->f_reghi8 = value;
- break;
- case XC16X_OPERAND_REGMEM8 :
- fields->f_regmem8 = value;
- break;
- case XC16X_OPERAND_REGOFF8 :
- fields->f_regoff8 = value;
- break;
- case XC16X_OPERAND_REL :
- fields->f_rel8 = value;
- break;
- case XC16X_OPERAND_RELHI :
- fields->f_relhi8 = value;
- break;
- case XC16X_OPERAND_SEG :
- fields->f_seg8 = value;
- break;
- case XC16X_OPERAND_SEGHI8 :
- fields->f_segnum8 = value;
- break;
- case XC16X_OPERAND_SEGM :
- break;
- case XC16X_OPERAND_SOF :
- break;
- case XC16X_OPERAND_SR :
- fields->f_r2 = value;
- break;
- case XC16X_OPERAND_SR2 :
- fields->f_r0 = value;
- break;
- case XC16X_OPERAND_SRB :
- fields->f_r2 = value;
- break;
- case XC16X_OPERAND_SRC1 :
- fields->f_r1 = value;
- break;
- case XC16X_OPERAND_SRC2 :
- fields->f_r2 = value;
- break;
- case XC16X_OPERAND_SRDIV :
- fields->f_reg8 = value;
- break;
- case XC16X_OPERAND_U4 :
- fields->f_uimm4 = value;
- break;
- case XC16X_OPERAND_UIMM16 :
- fields->f_uimm16 = value;
- break;
- case XC16X_OPERAND_UIMM2 :
- fields->f_uimm2 = value;
- break;
- case XC16X_OPERAND_UIMM3 :
- fields->f_uimm3 = value;
- break;
- case XC16X_OPERAND_UIMM4 :
- fields->f_uimm4 = value;
- break;
- case XC16X_OPERAND_UIMM7 :
- fields->f_uimm7 = value;
- break;
- case XC16X_OPERAND_UIMM8 :
- fields->f_uimm8 = value;
- break;
- case XC16X_OPERAND_UPAG16 :
- fields->f_uimm16 = value;
- break;
- case XC16X_OPERAND_UPOF16 :
- fields->f_memory = value;
- break;
- case XC16X_OPERAND_USEG16 :
- fields->f_offset16 = value;
- break;
- case XC16X_OPERAND_USEG8 :
- fields->f_seg8 = value;
- break;
- case XC16X_OPERAND_USOF16 :
- fields->f_offset16 = value;
- break;
-
- default :
- /* xgettext:c-format */
- opcodes_error_handler
- (_("internal error: unrecognized field %d while setting vma operand"),
- opindex);
- abort ();
- }
-}
-
-/* Function to call before using the instruction builder tables. */
-
-void
-xc16x_cgen_init_ibld_table (CGEN_CPU_DESC cd)
-{
- cd->insert_handlers = & xc16x_cgen_insert_handlers[0];
- cd->extract_handlers = & xc16x_cgen_extract_handlers[0];
-
- cd->insert_operand = xc16x_cgen_insert_operand;
- cd->extract_operand = xc16x_cgen_extract_operand;
-
- cd->get_int_operand = xc16x_cgen_get_int_operand;
- cd->set_int_operand = xc16x_cgen_set_int_operand;
- cd->get_vma_operand = xc16x_cgen_get_vma_operand;
- cd->set_vma_operand = xc16x_cgen_set_vma_operand;
-}
+++ /dev/null
-/* DO NOT EDIT! -*- buffer-read-only: t -*- vi:set ro: */
-/* Instruction opcode table for xc16x.
-
-THIS FILE IS MACHINE GENERATED WITH CGEN.
-
-Copyright (C) 1996-2022 Free Software Foundation, Inc.
-
-This file is part of the GNU Binutils and/or GDB, the GNU debugger.
-
- This file is free software; you can redistribute it and/or modify
- it under the terms of the GNU General Public License as published by
- the Free Software Foundation; either version 3, or (at your option)
- any later version.
-
- It is distributed in the hope that it will be useful, but WITHOUT
- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
- License for more details.
-
- You should have received a copy of the GNU General Public License along
- with this program; if not, write to the Free Software Foundation, Inc.,
- 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.
-
-*/
-
-#include "sysdep.h"
-#include "ansidecl.h"
-#include "bfd.h"
-#include "symcat.h"
-#include "xc16x-desc.h"
-#include "xc16x-opc.h"
-#include "libiberty.h"
-
-/* -- opc.c */
-
-/* -- */
-/* The hash functions are recorded here to help keep assembler code out of
- the disassembler and vice versa. */
-
-static int asm_hash_insn_p (const CGEN_INSN *);
-static unsigned int asm_hash_insn (const char *);
-static int dis_hash_insn_p (const CGEN_INSN *);
-static unsigned int dis_hash_insn (const char *, CGEN_INSN_INT);
-
-/* Instruction formats. */
-
-#define F(f) & xc16x_cgen_ifld_table[XC16X_##f]
-static const CGEN_IFMT ifmt_empty ATTRIBUTE_UNUSED = {
- 0, 0, 0x0, { { 0 } }
-};
-
-static const CGEN_IFMT ifmt_addrpof ATTRIBUTE_UNUSED = {
- 32, 32, 0xff, { { F (F_MEMORY) }, { F (F_REG8) }, { F (F_OP1) }, { F (F_OP2) }, { 0 } }
-};
-
-static const CGEN_IFMT ifmt_addbrpof ATTRIBUTE_UNUSED = {
- 32, 32, 0xff, { { F (F_MEMORY) }, { F (F_REGB8) }, { F (F_OP1) }, { F (F_OP2) }, { 0 } }
-};
-
-static const CGEN_IFMT ifmt_addrpag ATTRIBUTE_UNUSED = {
- 32, 32, 0xff, { { F (F_UIMM16) }, { F (F_REG8) }, { F (F_OP1) }, { F (F_OP2) }, { 0 } }
-};
-
-static const CGEN_IFMT ifmt_addbrpag ATTRIBUTE_UNUSED = {
- 32, 32, 0xff, { { F (F_UIMM16) }, { F (F_REGB8) }, { F (F_OP1) }, { F (F_OP2) }, { 0 } }
-};
-
-static const CGEN_IFMT ifmt_addrhpof ATTRIBUTE_UNUSED = {
- 32, 32, 0xff, { { F (F_UIMM16) }, { F (F_REG8) }, { F (F_OP1) }, { F (F_OP2) }, { 0 } }
-};
-
-static const CGEN_IFMT ifmt_addrhpof3 ATTRIBUTE_UNUSED = {
- 16, 16, 0x8ff, { { F (F_R1) }, { F (F_OP_BIT1) }, { F (F_UIMM3) }, { F (F_OP1) }, { F (F_OP2) }, { 0 } }
-};
-
-static const CGEN_IFMT ifmt_addbrhpag3 ATTRIBUTE_UNUSED = {
- 16, 16, 0x8ff, { { F (F_R1) }, { F (F_OP_BIT1) }, { F (F_UIMM3) }, { F (F_OP1) }, { F (F_OP2) }, { 0 } }
-};
-
-static const CGEN_IFMT ifmt_addrbhpof ATTRIBUTE_UNUSED = {
- 32, 32, 0xff0000ff, { { F (F_OP_BIT8) }, { F (F_UIMM8) }, { F (F_REGB8) }, { F (F_OP1) }, { F (F_OP2) }, { 0 } }
-};
-
-static const CGEN_IFMT ifmt_addr ATTRIBUTE_UNUSED = {
- 16, 16, 0xff, { { F (F_R1) }, { F (F_R2) }, { F (F_OP1) }, { F (F_OP2) }, { 0 } }
-};
-
-static const CGEN_IFMT ifmt_addbr ATTRIBUTE_UNUSED = {
- 16, 16, 0xff, { { F (F_R1) }, { F (F_R2) }, { F (F_OP1) }, { F (F_OP2) }, { 0 } }
-};
-
-static const CGEN_IFMT ifmt_add2 ATTRIBUTE_UNUSED = {
- 16, 16, 0xcff, { { F (F_R1) }, { F (F_OP_BIT2) }, { F (F_R0) }, { F (F_OP1) }, { F (F_OP2) }, { 0 } }
-};
-
-static const CGEN_IFMT ifmt_addb2 ATTRIBUTE_UNUSED = {
- 16, 16, 0xcff, { { F (F_R1) }, { F (F_OP_BIT2) }, { F (F_R0) }, { F (F_OP1) }, { F (F_OP2) }, { 0 } }
-};
-
-static const CGEN_IFMT ifmt_addrm2 ATTRIBUTE_UNUSED = {
- 32, 32, 0xff, { { F (F_MEMGR8) }, { F (F_REGMEM8) }, { F (F_OP1) }, { F (F_OP2) }, { 0 } }
-};
-
-static const CGEN_IFMT ifmt_addrm ATTRIBUTE_UNUSED = {
- 32, 32, 0xff, { { F (F_MEMORY) }, { F (F_REG8) }, { F (F_OP1) }, { F (F_OP2) }, { 0 } }
-};
-
-static const CGEN_IFMT ifmt_addbrm2 ATTRIBUTE_UNUSED = {
- 32, 32, 0xff, { { F (F_MEMGR8) }, { F (F_REGMEM8) }, { F (F_OP1) }, { F (F_OP2) }, { 0 } }
-};
-
-static const CGEN_IFMT ifmt_addbrm ATTRIBUTE_UNUSED = {
- 32, 32, 0xff, { { F (F_MEMORY) }, { F (F_REGB8) }, { F (F_OP1) }, { F (F_OP2) }, { 0 } }
-};
-
-static const CGEN_IFMT ifmt_muls ATTRIBUTE_UNUSED = {
- 16, 16, 0xff, { { F (F_R1) }, { F (F_R2) }, { F (F_OP1) }, { F (F_OP2) }, { 0 } }
-};
-
-static const CGEN_IFMT ifmt_div ATTRIBUTE_UNUSED = {
- 16, 16, 0xff, { { F (F_REG8) }, { F (F_OP1) }, { F (F_OP2) }, { 0 } }
-};
-
-static const CGEN_IFMT ifmt_cpl ATTRIBUTE_UNUSED = {
- 16, 16, 0xfff, { { F (F_R1) }, { F (F_OP_BIT4) }, { F (F_OP1) }, { F (F_OP2) }, { 0 } }
-};
-
-static const CGEN_IFMT ifmt_cplb ATTRIBUTE_UNUSED = {
- 16, 16, 0xfff, { { F (F_R1) }, { F (F_OP_BIT4) }, { F (F_OP1) }, { F (F_OP2) }, { 0 } }
-};
-
-static const CGEN_IFMT ifmt_movri ATTRIBUTE_UNUSED = {
- 16, 16, 0xff, { { F (F_UIMM4) }, { F (F_R4) }, { F (F_OP1) }, { F (F_OP2) }, { 0 } }
-};
-
-static const CGEN_IFMT ifmt_movbri ATTRIBUTE_UNUSED = {
- 16, 16, 0xff, { { F (F_UIMM4) }, { F (F_R2) }, { F (F_OP1) }, { F (F_OP2) }, { 0 } }
-};
-
-static const CGEN_IFMT ifmt_movbr2 ATTRIBUTE_UNUSED = {
- 16, 16, 0xff, { { F (F_R1) }, { F (F_R2) }, { F (F_OP1) }, { F (F_OP2) }, { 0 } }
-};
-
-static const CGEN_IFMT ifmt_mov9i ATTRIBUTE_UNUSED = {
- 32, 32, 0xff, { { F (F_UIMM16) }, { F (F_R1) }, { F (F_R2) }, { F (F_OP1) }, { F (F_OP2) }, { 0 } }
-};
-
-static const CGEN_IFMT ifmt_movb9i ATTRIBUTE_UNUSED = {
- 32, 32, 0xff, { { F (F_UIMM16) }, { F (F_R1) }, { F (F_R2) }, { F (F_OP1) }, { F (F_OP2) }, { 0 } }
-};
-
-static const CGEN_IFMT ifmt_movri11 ATTRIBUTE_UNUSED = {
- 32, 32, 0xf0ff, { { F (F_MEMORY) }, { F (F_OP_LBIT4) }, { F (F_R2) }, { F (F_OP1) }, { F (F_OP2) }, { 0 } }
-};
-
-static const CGEN_IFMT ifmt_movehm5 ATTRIBUTE_UNUSED = {
- 32, 32, 0xff, { { F (F_MEMORY) }, { F (F_REGOFF8) }, { F (F_OP1) }, { F (F_OP2) }, { 0 } }
-};
-
-static const CGEN_IFMT ifmt_movehm6 ATTRIBUTE_UNUSED = {
- 32, 32, 0xff, { { F (F_UIMM16) }, { F (F_REGOFF8) }, { F (F_OP1) }, { F (F_OP2) }, { 0 } }
-};
-
-static const CGEN_IFMT ifmt_movehm7 ATTRIBUTE_UNUSED = {
- 32, 32, 0xff, { { F (F_OFFSET16) }, { F (F_REGOFF8) }, { F (F_OP1) }, { F (F_OP2) }, { 0 } }
-};
-
-static const CGEN_IFMT ifmt_movehm8 ATTRIBUTE_UNUSED = {
- 32, 32, 0xff, { { F (F_OFFSET16) }, { F (F_REGOFF8) }, { F (F_OP1) }, { F (F_OP2) }, { 0 } }
-};
-
-static const CGEN_IFMT ifmt_movehm10 ATTRIBUTE_UNUSED = {
- 32, 32, 0xff0000ff, { { F (F_OP_BIT8) }, { F (F_UIMM8) }, { F (F_REGOFF8) }, { F (F_OP1) }, { F (F_OP2) }, { 0 } }
-};
-
-static const CGEN_IFMT ifmt_movbsrpofm ATTRIBUTE_UNUSED = {
- 32, 32, 0xff, { { F (F_MEMORY) }, { F (F_REGMEM8) }, { F (F_OP1) }, { F (F_OP2) }, { 0 } }
-};
-
-static const CGEN_IFMT ifmt_movbspofmr ATTRIBUTE_UNUSED = {
- 32, 32, 0xff, { { F (F_MEMORY) }, { F (F_REGMEM8) }, { F (F_OP1) }, { F (F_OP2) }, { 0 } }
-};
-
-static const CGEN_IFMT ifmt_jmpa0 ATTRIBUTE_UNUSED = {
- 32, 32, 0x4ff, { { F (F_OFFSET16) }, { F (F_EXTCCODE) }, { F (F_OP_BITONE) }, { F (F_OP_ONEBIT) }, { F (F_OP_1BIT) }, { F (F_OP1) }, { F (F_OP2) }, { 0 } }
-};
-
-static const CGEN_IFMT ifmt_jmpa_ ATTRIBUTE_UNUSED = {
- 32, 32, 0x5ff, { { F (F_OFFSET16) }, { F (F_EXTCCODE) }, { F (F_OP_BITONE) }, { F (F_OP_ONEBIT) }, { F (F_OP_1BIT) }, { F (F_OP1) }, { F (F_OP2) }, { 0 } }
-};
-
-static const CGEN_IFMT ifmt_jmpi ATTRIBUTE_UNUSED = {
- 16, 16, 0xff, { { F (F_ICONDCODE) }, { F (F_R2) }, { F (F_OP1) }, { F (F_OP2) }, { 0 } }
-};
-
-static const CGEN_IFMT ifmt_jmpr_nenz ATTRIBUTE_UNUSED = {
- 16, 16, 0xff, { { F (F_REL8) }, { F (F_RCOND) }, { F (F_OP2) }, { 0 } }
-};
-
-static const CGEN_IFMT ifmt_jmpseg ATTRIBUTE_UNUSED = {
- 32, 32, 0xff, { { F (F_OFFSET16) }, { F (F_SEG8) }, { F (F_OP1) }, { F (F_OP2) }, { 0 } }
-};
-
-static const CGEN_IFMT ifmt_jmps ATTRIBUTE_UNUSED = {
- 32, 32, 0xff, { { F (F_OFFSET16) }, { F (F_SEG8) }, { F (F_OP1) }, { F (F_OP2) }, { 0 } }
-};
-
-static const CGEN_IFMT ifmt_jb ATTRIBUTE_UNUSED = {
- 32, 32, 0xf0000ff, { { F (F_QLOBIT) }, { F (F_QHIBIT) }, { F (F_RELHI8) }, { F (F_REGB8) }, { F (F_OP1) }, { F (F_OP2) }, { 0 } }
-};
-
-static const CGEN_IFMT ifmt_calla0 ATTRIBUTE_UNUSED = {
- 32, 32, 0x6ff, { { F (F_OFFSET16) }, { F (F_EXTCCODE) }, { F (F_OP_2BIT) }, { F (F_OP_1BIT) }, { F (F_OP1) }, { F (F_OP2) }, { 0 } }
-};
-
-static const CGEN_IFMT ifmt_calla_ ATTRIBUTE_UNUSED = {
- 32, 32, 0x7ff, { { F (F_OFFSET16) }, { F (F_EXTCCODE) }, { F (F_OP_BIT3) }, { F (F_OP1) }, { F (F_OP2) }, { 0 } }
-};
-
-static const CGEN_IFMT ifmt_callr ATTRIBUTE_UNUSED = {
- 16, 16, 0xff, { { F (F_REL8) }, { F (F_OP1) }, { F (F_OP2) }, { 0 } }
-};
-
-static const CGEN_IFMT ifmt_callseg ATTRIBUTE_UNUSED = {
- 32, 32, 0xff, { { F (F_OFFSET16) }, { F (F_SEG8) }, { F (F_OP1) }, { F (F_OP2) }, { 0 } }
-};
-
-static const CGEN_IFMT ifmt_pcall ATTRIBUTE_UNUSED = {
- 32, 32, 0xff, { { F (F_OFFSET16) }, { F (F_REG8) }, { F (F_OP1) }, { F (F_OP2) }, { 0 } }
-};
-
-static const CGEN_IFMT ifmt_trap ATTRIBUTE_UNUSED = {
- 16, 16, 0x1ff, { { F (F_UIMM7) }, { F (F_OP_1BIT) }, { F (F_OP1) }, { F (F_OP2) }, { 0 } }
-};
-
-static const CGEN_IFMT ifmt_ret ATTRIBUTE_UNUSED = {
- 16, 16, 0xff0000ff, { { F (F_OP_BIT8) }, { F (F_OP1) }, { F (F_OP2) }, { 0 } }
-};
-
-static const CGEN_IFMT ifmt_retp ATTRIBUTE_UNUSED = {
- 16, 16, 0xff, { { F (F_REG8) }, { F (F_OP1) }, { F (F_OP2) }, { 0 } }
-};
-
-static const CGEN_IFMT ifmt_reti ATTRIBUTE_UNUSED = {
- 16, 16, 0xffff, { { F (F_OP_LBIT4) }, { F (F_OP_BIT4) }, { F (F_OP1) }, { F (F_OP2) }, { 0 } }
-};
-
-static const CGEN_IFMT ifmt_srstm ATTRIBUTE_UNUSED = {
- 32, 32, 0xffffffff, { { F (F_OP_BIT8) }, { F (F_DATA8) }, { F (F_OP_LBIT4) }, { F (F_OP_BIT4) }, { F (F_OP1) }, { F (F_OP2) }, { 0 } }
-};
-
-static const CGEN_IFMT ifmt_atomic ATTRIBUTE_UNUSED = {
- 16, 16, 0xcfff, { { F (F_OP_LBIT2) }, { F (F_UIMM2) }, { F (F_OP_BIT4) }, { F (F_OP1) }, { F (F_OP2) }, { 0 } }
-};
-
-static const CGEN_IFMT ifmt_extp ATTRIBUTE_UNUSED = {
- 16, 16, 0xc0ff, { { F (F_OP_LBIT2) }, { F (F_UIMM2) }, { F (F_R2) }, { F (F_OP1) }, { F (F_OP2) }, { 0 } }
-};
-
-static const CGEN_IFMT ifmt_extp1 ATTRIBUTE_UNUSED = {
- 32, 32, 0xfc00cfff, { { F (F_QLOBIT) }, { F (F_QLOBIT2) }, { F (F_PAGENUM) }, { F (F_OP_LBIT2) }, { F (F_UIMM2) }, { F (F_OP_BIT4) }, { F (F_OP1) }, { F (F_OP2) }, { 0 } }
-};
-
-static const CGEN_IFMT ifmt_extpg1 ATTRIBUTE_UNUSED = {
- 32, 32, 0xcfff, { { F (F_UIMM16) }, { F (F_OP_LBIT2) }, { F (F_UIMM2) }, { F (F_OP_BIT4) }, { F (F_OP1) }, { F (F_OP2) }, { 0 } }
-};
-
-static const CGEN_IFMT ifmt_exts1 ATTRIBUTE_UNUSED = {
- 32, 32, 0xff00cfff, { { F (F_OP_BIT8) }, { F (F_SEGNUM8) }, { F (F_OP_LBIT2) }, { F (F_UIMM2) }, { F (F_OP_BIT4) }, { F (F_OP1) }, { F (F_OP2) }, { 0 } }
-};
-
-static const CGEN_IFMT ifmt_bclr18 ATTRIBUTE_UNUSED = {
- 16, 16, 0xff, { { F (F_REG8) }, { F (F_OP1) }, { F (F_OP2) }, { 0 } }
-};
-
-static const CGEN_IFMT ifmt_bclr0 ATTRIBUTE_UNUSED = {
- 16, 16, 0xff, { { F (F_REG8) }, { F (F_QCOND) }, { F (F_OP2) }, { 0 } }
-};
-
-static const CGEN_IFMT ifmt_bmov ATTRIBUTE_UNUSED = {
- 32, 32, 0xff, { { F (F_QLOBIT) }, { F (F_QHIBIT) }, { F (F_REGHI8) }, { F (F_REG8) }, { F (F_OP1) }, { F (F_OP2) }, { 0 } }
-};
-
-static const CGEN_IFMT ifmt_bfldl ATTRIBUTE_UNUSED = {
- 32, 32, 0xff, { { F (F_DATAHI8) }, { F (F_MASK8) }, { F (F_REG8) }, { F (F_OP1) }, { F (F_OP2) }, { 0 } }
-};
-
-static const CGEN_IFMT ifmt_bfldh ATTRIBUTE_UNUSED = {
- 32, 32, 0xff, { { F (F_DATAHI8) }, { F (F_DATA8) }, { F (F_REG8) }, { F (F_OP1) }, { F (F_OP2) }, { 0 } }
-};
-
-static const CGEN_IFMT ifmt_cmpri ATTRIBUTE_UNUSED = {
- 16, 16, 0x8ff, { { F (F_R1) }, { F (F_OP_BIT1) }, { F (F_UIMM3) }, { F (F_OP1) }, { F (F_OP2) }, { 0 } }
-};
-
-static const CGEN_IFMT ifmt_cmpd1ri ATTRIBUTE_UNUSED = {
- 16, 16, 0xff, { { F (F_UIMM4) }, { F (F_R2) }, { F (F_OP1) }, { F (F_OP2) }, { 0 } }
-};
-
-#undef F
-
-#define A(a) (1 << CGEN_INSN_##a)
-#define OPERAND(op) XC16X_OPERAND_##op
-#define MNEM CGEN_SYNTAX_MNEMONIC /* syntax value for mnemonic */
-#define OP(field) CGEN_SYNTAX_MAKE_FIELD (OPERAND (field))
-
-/* The instruction table. */
-
-static const CGEN_OPCODE xc16x_cgen_insn_opcode_table[MAX_INSNS] =
-{
- /* Special null first entry.
- A `num' value of zero is thus invalid.
- Also, the special `invalid' insn resides here. */
- { { 0, 0, 0, 0 }, {{0}}, 0, {0}},
-/* add $reg8,$pof$upof16 */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (REG8), ',', OP (POF), OP (UPOF16), 0 } },
- & ifmt_addrpof, { 0x2 }
- },
-/* sub $reg8,$pof$upof16 */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (REG8), ',', OP (POF), OP (UPOF16), 0 } },
- & ifmt_addrpof, { 0x22 }
- },
-/* addb $regb8,$pof$upof16 */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (REGB8), ',', OP (POF), OP (UPOF16), 0 } },
- & ifmt_addbrpof, { 0x3 }
- },
-/* subb $regb8,$pof$upof16 */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (REGB8), ',', OP (POF), OP (UPOF16), 0 } },
- & ifmt_addbrpof, { 0x23 }
- },
-/* add $reg8,$pag$upag16 */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (REG8), ',', OP (PAG), OP (UPAG16), 0 } },
- & ifmt_addrpag, { 0x2 }
- },
-/* sub $reg8,$pag$upag16 */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (REG8), ',', OP (PAG), OP (UPAG16), 0 } },
- & ifmt_addrpag, { 0x22 }
- },
-/* addb $regb8,$pag$upag16 */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (REGB8), ',', OP (PAG), OP (UPAG16), 0 } },
- & ifmt_addbrpag, { 0x3 }
- },
-/* subb $regb8,$pag$upag16 */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (REGB8), ',', OP (PAG), OP (UPAG16), 0 } },
- & ifmt_addbrpag, { 0x23 }
- },
-/* addc $reg8,$pof$upof16 */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (REG8), ',', OP (POF), OP (UPOF16), 0 } },
- & ifmt_addrpof, { 0x12 }
- },
-/* subc $reg8,$pof$upof16 */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (REG8), ',', OP (POF), OP (UPOF16), 0 } },
- & ifmt_addrpof, { 0x32 }
- },
-/* addcb $regb8,$pof$upof16 */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (REGB8), ',', OP (POF), OP (UPOF16), 0 } },
- & ifmt_addbrpof, { 0x13 }
- },
-/* subcb $regb8,$pof$upof16 */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (REGB8), ',', OP (POF), OP (UPOF16), 0 } },
- & ifmt_addbrpof, { 0x33 }
- },
-/* addc $reg8,$pag$upag16 */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (REG8), ',', OP (PAG), OP (UPAG16), 0 } },
- & ifmt_addrpag, { 0x12 }
- },
-/* subc $reg8,$pag$upag16 */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (REG8), ',', OP (PAG), OP (UPAG16), 0 } },
- & ifmt_addrpag, { 0x32 }
- },
-/* addcb $regb8,$pag$upag16 */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (REGB8), ',', OP (PAG), OP (UPAG16), 0 } },
- & ifmt_addbrpag, { 0x13 }
- },
-/* subcb $regb8,$pag$upag16 */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (REGB8), ',', OP (PAG), OP (UPAG16), 0 } },
- & ifmt_addbrpag, { 0x33 }
- },
-/* add $pof$upof16,$reg8 */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (POF), OP (UPOF16), ',', OP (REG8), 0 } },
- & ifmt_addrpof, { 0x4 }
- },
-/* sub $pof$upof16,$reg8 */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (POF), OP (UPOF16), ',', OP (REG8), 0 } },
- & ifmt_addrpof, { 0x24 }
- },
-/* addb $pof$upof16,$regb8 */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (POF), OP (UPOF16), ',', OP (REGB8), 0 } },
- & ifmt_addbrpof, { 0x5 }
- },
-/* subb $pof$upof16,$regb8 */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (POF), OP (UPOF16), ',', OP (REGB8), 0 } },
- & ifmt_addbrpof, { 0x25 }
- },
-/* addc $pof$upof16,$reg8 */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (POF), OP (UPOF16), ',', OP (REG8), 0 } },
- & ifmt_addrpof, { 0x14 }
- },
-/* subc $pof$upof16,$reg8 */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (POF), OP (UPOF16), ',', OP (REG8), 0 } },
- & ifmt_addrpof, { 0x34 }
- },
-/* addcb $pof$upof16,$regb8 */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (POF), OP (UPOF16), ',', OP (REGB8), 0 } },
- & ifmt_addbrpof, { 0x15 }
- },
-/* subcb $pof$upof16,$regb8 */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (POF), OP (UPOF16), ',', OP (REGB8), 0 } },
- & ifmt_addbrpof, { 0x35 }
- },
-/* add $reg8,$hash$pof$uimm16 */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (REG8), ',', OP (HASH), OP (POF), OP (UIMM16), 0 } },
- & ifmt_addrhpof, { 0x6 }
- },
-/* sub $reg8,$hash$pof$uimm16 */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (REG8), ',', OP (HASH), OP (POF), OP (UIMM16), 0 } },
- & ifmt_addrhpof, { 0x26 }
- },
-/* add $reg8,$hash$pag$uimm16 */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (REG8), ',', OP (HASH), OP (PAG), OP (UIMM16), 0 } },
- & ifmt_addrhpof, { 0x6 }
- },
-/* sub $reg8,$hash$pag$uimm16 */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (REG8), ',', OP (HASH), OP (PAG), OP (UIMM16), 0 } },
- & ifmt_addrhpof, { 0x26 }
- },
-/* add $dr,$hash$pof$uimm3 */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (DR), ',', OP (HASH), OP (POF), OP (UIMM3), 0 } },
- & ifmt_addrhpof3, { 0x8 }
- },
-/* sub $dr,$hash$pof$uimm3 */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (DR), ',', OP (HASH), OP (POF), OP (UIMM3), 0 } },
- & ifmt_addrhpof3, { 0x28 }
- },
-/* addb $drb,$hash$pag$uimm3 */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (DRB), ',', OP (HASH), OP (PAG), OP (UIMM3), 0 } },
- & ifmt_addbrhpag3, { 0x9 }
- },
-/* subb $drb,$hash$pag$uimm3 */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (DRB), ',', OP (HASH), OP (PAG), OP (UIMM3), 0 } },
- & ifmt_addbrhpag3, { 0x29 }
- },
-/* add $dr,$hash$pag$uimm3 */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (DR), ',', OP (HASH), OP (PAG), OP (UIMM3), 0 } },
- & ifmt_addrhpof3, { 0x8 }
- },
-/* sub $dr,$hash$pag$uimm3 */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (DR), ',', OP (HASH), OP (PAG), OP (UIMM3), 0 } },
- & ifmt_addrhpof3, { 0x28 }
- },
-/* addb $drb,$hash$pof$uimm3 */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (DRB), ',', OP (HASH), OP (POF), OP (UIMM3), 0 } },
- & ifmt_addbrhpag3, { 0x9 }
- },
-/* subb $drb,$hash$pof$uimm3 */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (DRB), ',', OP (HASH), OP (POF), OP (UIMM3), 0 } },
- & ifmt_addbrhpag3, { 0x29 }
- },
-/* addb $regb8,$hash$pof$uimm8 */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (REGB8), ',', OP (HASH), OP (POF), OP (UIMM8), 0 } },
- & ifmt_addrbhpof, { 0x7 }
- },
-/* subb $regb8,$hash$pof$uimm8 */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (REGB8), ',', OP (HASH), OP (POF), OP (UIMM8), 0 } },
- & ifmt_addrbhpof, { 0x27 }
- },
-/* addb $regb8,$hash$pag$uimm8 */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (REGB8), ',', OP (HASH), OP (PAG), OP (UIMM8), 0 } },
- & ifmt_addrbhpof, { 0x7 }
- },
-/* subb $regb8,$hash$pag$uimm8 */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (REGB8), ',', OP (HASH), OP (PAG), OP (UIMM8), 0 } },
- & ifmt_addrbhpof, { 0x27 }
- },
-/* addc $reg8,$hash$pof$uimm16 */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (REG8), ',', OP (HASH), OP (POF), OP (UIMM16), 0 } },
- & ifmt_addrhpof, { 0x16 }
- },
-/* subc $reg8,$hash$pof$uimm16 */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (REG8), ',', OP (HASH), OP (POF), OP (UIMM16), 0 } },
- & ifmt_addrhpof, { 0x36 }
- },
-/* addc $reg8,$hash$pag$uimm16 */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (REG8), ',', OP (HASH), OP (PAG), OP (UIMM16), 0 } },
- & ifmt_addrhpof, { 0x16 }
- },
-/* subc $reg8,$hash$pag$uimm16 */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (REG8), ',', OP (HASH), OP (PAG), OP (UIMM16), 0 } },
- & ifmt_addrhpof, { 0x36 }
- },
-/* addc $dr,$hash$pof$uimm3 */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (DR), ',', OP (HASH), OP (POF), OP (UIMM3), 0 } },
- & ifmt_addrhpof3, { 0x18 }
- },
-/* subc $dr,$hash$pof$uimm3 */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (DR), ',', OP (HASH), OP (POF), OP (UIMM3), 0 } },
- & ifmt_addrhpof3, { 0x38 }
- },
-/* addcb $drb,$hash$pag$uimm3 */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (DRB), ',', OP (HASH), OP (PAG), OP (UIMM3), 0 } },
- & ifmt_addbrhpag3, { 0x19 }
- },
-/* subcb $drb,$hash$pag$uimm3 */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (DRB), ',', OP (HASH), OP (PAG), OP (UIMM3), 0 } },
- & ifmt_addbrhpag3, { 0x39 }
- },
-/* addc $dr,$hash$pag$uimm3 */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (DR), ',', OP (HASH), OP (PAG), OP (UIMM3), 0 } },
- & ifmt_addrhpof3, { 0x18 }
- },
-/* subc $dr,$hash$pag$uimm3 */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (DR), ',', OP (HASH), OP (PAG), OP (UIMM3), 0 } },
- & ifmt_addrhpof3, { 0x38 }
- },
-/* addcb $drb,$hash$pof$uimm3 */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (DRB), ',', OP (HASH), OP (POF), OP (UIMM3), 0 } },
- & ifmt_addbrhpag3, { 0x19 }
- },
-/* subcb $drb,$hash$pof$uimm3 */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (DRB), ',', OP (HASH), OP (POF), OP (UIMM3), 0 } },
- & ifmt_addbrhpag3, { 0x39 }
- },
-/* addcb $regb8,$hash$pof$uimm8 */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (REGB8), ',', OP (HASH), OP (POF), OP (UIMM8), 0 } },
- & ifmt_addrbhpof, { 0x17 }
- },
-/* subcb $regb8,$hash$pof$uimm8 */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (REGB8), ',', OP (HASH), OP (POF), OP (UIMM8), 0 } },
- & ifmt_addrbhpof, { 0x37 }
- },
-/* addcb $regb8,$hash$pag$uimm8 */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (REGB8), ',', OP (HASH), OP (PAG), OP (UIMM8), 0 } },
- & ifmt_addrbhpof, { 0x17 }
- },
-/* subcb $regb8,$hash$pag$uimm8 */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (REGB8), ',', OP (HASH), OP (PAG), OP (UIMM8), 0 } },
- & ifmt_addrbhpof, { 0x37 }
- },
-/* add $dr,$hash$uimm3 */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (DR), ',', OP (HASH), OP (UIMM3), 0 } },
- & ifmt_addrhpof3, { 0x8 }
- },
-/* sub $dr,$hash$uimm3 */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (DR), ',', OP (HASH), OP (UIMM3), 0 } },
- & ifmt_addrhpof3, { 0x28 }
- },
-/* addb $drb,$hash$uimm3 */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (DRB), ',', OP (HASH), OP (UIMM3), 0 } },
- & ifmt_addbrhpag3, { 0x9 }
- },
-/* subb $drb,$hash$uimm3 */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (DRB), ',', OP (HASH), OP (UIMM3), 0 } },
- & ifmt_addbrhpag3, { 0x29 }
- },
-/* add $reg8,$hash$uimm16 */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (REG8), ',', OP (HASH), OP (UIMM16), 0 } },
- & ifmt_addrhpof, { 0x6 }
- },
-/* sub $reg8,$hash$uimm16 */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (REG8), ',', OP (HASH), OP (UIMM16), 0 } },
- & ifmt_addrhpof, { 0x26 }
- },
-/* addb $regb8,$hash$uimm8 */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (REGB8), ',', OP (HASH), OP (UIMM8), 0 } },
- & ifmt_addrbhpof, { 0x7 }
- },
-/* subb $regb8,$hash$uimm8 */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (REGB8), ',', OP (HASH), OP (UIMM8), 0 } },
- & ifmt_addrbhpof, { 0x27 }
- },
-/* addc $dr,$hash$uimm3 */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (DR), ',', OP (HASH), OP (UIMM3), 0 } },
- & ifmt_addrhpof3, { 0x18 }
- },
-/* subc $dr,$hash$uimm3 */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (DR), ',', OP (HASH), OP (UIMM3), 0 } },
- & ifmt_addrhpof3, { 0x38 }
- },
-/* addcb $drb,$hash$uimm3 */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (DRB), ',', OP (HASH), OP (UIMM3), 0 } },
- & ifmt_addbrhpag3, { 0x19 }
- },
-/* subcb $drb,$hash$uimm3 */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (DRB), ',', OP (HASH), OP (UIMM3), 0 } },
- & ifmt_addbrhpag3, { 0x39 }
- },
-/* addc $reg8,$hash$uimm16 */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (REG8), ',', OP (HASH), OP (UIMM16), 0 } },
- & ifmt_addrhpof, { 0x16 }
- },
-/* subc $reg8,$hash$uimm16 */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (REG8), ',', OP (HASH), OP (UIMM16), 0 } },
- & ifmt_addrhpof, { 0x36 }
- },
-/* addcb $regb8,$hash$uimm8 */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (REGB8), ',', OP (HASH), OP (UIMM8), 0 } },
- & ifmt_addrbhpof, { 0x17 }
- },
-/* subcb $regb8,$hash$uimm8 */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (REGB8), ',', OP (HASH), OP (UIMM8), 0 } },
- & ifmt_addrbhpof, { 0x37 }
- },
-/* add $dr,$sr */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
- & ifmt_addr, { 0x0 }
- },
-/* sub $dr,$sr */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
- & ifmt_addr, { 0x20 }
- },
-/* addb $drb,$srb */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (DRB), ',', OP (SRB), 0 } },
- & ifmt_addbr, { 0x1 }
- },
-/* subb $drb,$srb */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (DRB), ',', OP (SRB), 0 } },
- & ifmt_addbr, { 0x21 }
- },
-/* add $dr,[$sr2] */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (DR), ',', '[', OP (SR2), ']', 0 } },
- & ifmt_add2, { 0x808 }
- },
-/* sub $dr,[$sr2] */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (DR), ',', '[', OP (SR2), ']', 0 } },
- & ifmt_add2, { 0x828 }
- },
-/* addb $drb,[$sr2] */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (DRB), ',', '[', OP (SR2), ']', 0 } },
- & ifmt_addb2, { 0x809 }
- },
-/* subb $drb,[$sr2] */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (DRB), ',', '[', OP (SR2), ']', 0 } },
- & ifmt_addb2, { 0x829 }
- },
-/* add $dr,[$sr2+] */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (DR), ',', '[', OP (SR2), '+', ']', 0 } },
- & ifmt_add2, { 0xc08 }
- },
-/* sub $dr,[$sr2+] */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (DR), ',', '[', OP (SR2), '+', ']', 0 } },
- & ifmt_add2, { 0xc28 }
- },
-/* addb $drb,[$sr2+] */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (DRB), ',', '[', OP (SR2), '+', ']', 0 } },
- & ifmt_addb2, { 0xc09 }
- },
-/* subb $drb,[$sr2+] */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (DRB), ',', '[', OP (SR2), '+', ']', 0 } },
- & ifmt_addb2, { 0xc29 }
- },
-/* addc $dr,$sr */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
- & ifmt_addr, { 0x10 }
- },
-/* subc $dr,$sr */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
- & ifmt_addr, { 0x30 }
- },
-/* addcb $drb,$srb */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (DRB), ',', OP (SRB), 0 } },
- & ifmt_addbr, { 0x11 }
- },
-/* subcb $drb,$srb */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (DRB), ',', OP (SRB), 0 } },
- & ifmt_addbr, { 0x31 }
- },
-/* addc $dr,[$sr2] */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (DR), ',', '[', OP (SR2), ']', 0 } },
- & ifmt_add2, { 0x818 }
- },
-/* subc $dr,[$sr2] */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (DR), ',', '[', OP (SR2), ']', 0 } },
- & ifmt_add2, { 0x838 }
- },
-/* addcb $drb,[$sr2] */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (DRB), ',', '[', OP (SR2), ']', 0 } },
- & ifmt_addb2, { 0x819 }
- },
-/* subcb $drb,[$sr2] */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (DRB), ',', '[', OP (SR2), ']', 0 } },
- & ifmt_addb2, { 0x839 }
- },
-/* addc $dr,[$sr2+] */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (DR), ',', '[', OP (SR2), '+', ']', 0 } },
- & ifmt_add2, { 0xc18 }
- },
-/* subc $dr,[$sr2+] */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (DR), ',', '[', OP (SR2), '+', ']', 0 } },
- & ifmt_add2, { 0xc38 }
- },
-/* addcb $drb,[$sr2+] */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (DRB), ',', '[', OP (SR2), '+', ']', 0 } },
- & ifmt_addb2, { 0xc19 }
- },
-/* subcb $drb,[$sr2+] */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (DRB), ',', '[', OP (SR2), '+', ']', 0 } },
- & ifmt_addb2, { 0xc39 }
- },
-/* add $regmem8,$memgr8 */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (REGMEM8), ',', OP (MEMGR8), 0 } },
- & ifmt_addrm2, { 0x2 }
- },
-/* add $memgr8,$regmem8 */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (MEMGR8), ',', OP (REGMEM8), 0 } },
- & ifmt_addrm2, { 0x4 }
- },
-/* add $reg8,$memory */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (REG8), ',', OP (MEMORY), 0 } },
- & ifmt_addrm, { 0x2 }
- },
-/* add $memory,$reg8 */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (MEMORY), ',', OP (REG8), 0 } },
- & ifmt_addrm, { 0x4 }
- },
-/* sub $regmem8,$memgr8 */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (REGMEM8), ',', OP (MEMGR8), 0 } },
- & ifmt_addrm2, { 0x22 }
- },
-/* sub $memgr8,$regmem8 */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (MEMGR8), ',', OP (REGMEM8), 0 } },
- & ifmt_addrm2, { 0x24 }
- },
-/* sub $reg8,$memory */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (REG8), ',', OP (MEMORY), 0 } },
- & ifmt_addrm, { 0x22 }
- },
-/* sub $memory,$reg8 */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (MEMORY), ',', OP (REG8), 0 } },
- & ifmt_addrm, { 0x24 }
- },
-/* addb $regbmem8,$memgr8 */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (REGBMEM8), ',', OP (MEMGR8), 0 } },
- & ifmt_addbrm2, { 0x3 }
- },
-/* addb $memgr8,$regbmem8 */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (MEMGR8), ',', OP (REGBMEM8), 0 } },
- & ifmt_addbrm2, { 0x5 }
- },
-/* addb $regb8,$memory */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (REGB8), ',', OP (MEMORY), 0 } },
- & ifmt_addbrm, { 0x3 }
- },
-/* addb $memory,$regb8 */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (MEMORY), ',', OP (REGB8), 0 } },
- & ifmt_addbrm, { 0x5 }
- },
-/* subb $regbmem8,$memgr8 */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (REGBMEM8), ',', OP (MEMGR8), 0 } },
- & ifmt_addbrm2, { 0x23 }
- },
-/* subb $memgr8,$regbmem8 */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (MEMGR8), ',', OP (REGBMEM8), 0 } },
- & ifmt_addbrm2, { 0x25 }
- },
-/* subb $regb8,$memory */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (REGB8), ',', OP (MEMORY), 0 } },
- & ifmt_addbrm, { 0x23 }
- },
-/* subb $memory,$regb8 */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (MEMORY), ',', OP (REGB8), 0 } },
- & ifmt_addbrm, { 0x25 }
- },
-/* addc $regmem8,$memgr8 */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (REGMEM8), ',', OP (MEMGR8), 0 } },
- & ifmt_addrm2, { 0x12 }
- },
-/* addc $memgr8,$regmem8 */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (MEMGR8), ',', OP (REGMEM8), 0 } },
- & ifmt_addrm2, { 0x14 }
- },
-/* addc $reg8,$memory */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (REG8), ',', OP (MEMORY), 0 } },
- & ifmt_addrm, { 0x12 }
- },
-/* addc $memory,$reg8 */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (MEMORY), ',', OP (REG8), 0 } },
- & ifmt_addrm, { 0x14 }
- },
-/* subc $regmem8,$memgr8 */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (REGMEM8), ',', OP (MEMGR8), 0 } },
- & ifmt_addrm2, { 0x32 }
- },
-/* subc $memgr8,$regmem8 */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (MEMGR8), ',', OP (REGMEM8), 0 } },
- & ifmt_addrm2, { 0x34 }
- },
-/* subc $reg8,$memory */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (REG8), ',', OP (MEMORY), 0 } },
- & ifmt_addrm, { 0x32 }
- },
-/* subc $memory,$reg8 */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (MEMORY), ',', OP (REG8), 0 } },
- & ifmt_addrm, { 0x34 }
- },
-/* addcb $regbmem8,$memgr8 */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (REGBMEM8), ',', OP (MEMGR8), 0 } },
- & ifmt_addbrm2, { 0x13 }
- },
-/* addcb $memgr8,$regbmem8 */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (MEMGR8), ',', OP (REGBMEM8), 0 } },
- & ifmt_addbrm2, { 0x15 }
- },
-/* addcb $regb8,$memory */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (REGB8), ',', OP (MEMORY), 0 } },
- & ifmt_addbrm, { 0x13 }
- },
-/* addcb $memory,$regb8 */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (MEMORY), ',', OP (REGB8), 0 } },
- & ifmt_addbrm, { 0x15 }
- },
-/* subcb $regbmem8,$memgr8 */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (REGBMEM8), ',', OP (MEMGR8), 0 } },
- & ifmt_addbrm2, { 0x33 }
- },
-/* subcb $memgr8,$regbmem8 */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (MEMGR8), ',', OP (REGBMEM8), 0 } },
- & ifmt_addbrm2, { 0x35 }
- },
-/* subcb $regb8,$memory */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (REGB8), ',', OP (MEMORY), 0 } },
- & ifmt_addbrm, { 0x33 }
- },
-/* subcb $memory,$regb8 */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (MEMORY), ',', OP (REGB8), 0 } },
- & ifmt_addbrm, { 0x35 }
- },
-/* mul $src1,$src2 */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 } },
- & ifmt_muls, { 0xb }
- },
-/* mulu $src1,$src2 */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 } },
- & ifmt_muls, { 0x1b }
- },
-/* div $srdiv */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (SRDIV), 0 } },
- & ifmt_div, { 0x4b }
- },
-/* divl $srdiv */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (SRDIV), 0 } },
- & ifmt_div, { 0x6b }
- },
-/* divlu $srdiv */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (SRDIV), 0 } },
- & ifmt_div, { 0x7b }
- },
-/* divu $srdiv */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (SRDIV), 0 } },
- & ifmt_div, { 0x5b }
- },
-/* cpl $dr */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (DR), 0 } },
- & ifmt_cpl, { 0x91 }
- },
-/* cplb $drb */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (DRB), 0 } },
- & ifmt_cplb, { 0xb1 }
- },
-/* neg $dr */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (DR), 0 } },
- & ifmt_cpl, { 0x81 }
- },
-/* negb $drb */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (DRB), 0 } },
- & ifmt_cplb, { 0xa1 }
- },
-/* and $dr,$sr */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
- & ifmt_addr, { 0x60 }
- },
-/* or $dr,$sr */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
- & ifmt_addr, { 0x70 }
- },
-/* xor $dr,$sr */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
- & ifmt_addr, { 0x50 }
- },
-/* andb $drb,$srb */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (DRB), ',', OP (SRB), 0 } },
- & ifmt_addbr, { 0x61 }
- },
-/* orb $drb,$srb */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (DRB), ',', OP (SRB), 0 } },
- & ifmt_addbr, { 0x71 }
- },
-/* xorb $drb,$srb */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (DRB), ',', OP (SRB), 0 } },
- & ifmt_addbr, { 0x51 }
- },
-/* and $dr,$hash$uimm3 */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (DR), ',', OP (HASH), OP (UIMM3), 0 } },
- & ifmt_addrhpof3, { 0x68 }
- },
-/* or $dr,$hash$uimm3 */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (DR), ',', OP (HASH), OP (UIMM3), 0 } },
- & ifmt_addrhpof3, { 0x78 }
- },
-/* xor $dr,$hash$uimm3 */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (DR), ',', OP (HASH), OP (UIMM3), 0 } },
- & ifmt_addrhpof3, { 0x58 }
- },
-/* andb $drb,$hash$uimm3 */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (DRB), ',', OP (HASH), OP (UIMM3), 0 } },
- & ifmt_addbrhpag3, { 0x69 }
- },
-/* orb $drb,$hash$uimm3 */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (DRB), ',', OP (HASH), OP (UIMM3), 0 } },
- & ifmt_addbrhpag3, { 0x79 }
- },
-/* xorb $drb,$hash$uimm3 */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (DRB), ',', OP (HASH), OP (UIMM3), 0 } },
- & ifmt_addbrhpag3, { 0x59 }
- },
-/* and $reg8,$hash$uimm16 */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (REG8), ',', OP (HASH), OP (UIMM16), 0 } },
- & ifmt_addrhpof, { 0x66 }
- },
-/* or $reg8,$hash$uimm16 */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (REG8), ',', OP (HASH), OP (UIMM16), 0 } },
- & ifmt_addrhpof, { 0x76 }
- },
-/* xor $reg8,$hash$uimm16 */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (REG8), ',', OP (HASH), OP (UIMM16), 0 } },
- & ifmt_addrhpof, { 0x56 }
- },
-/* andb $regb8,$hash$uimm8 */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (REGB8), ',', OP (HASH), OP (UIMM8), 0 } },
- & ifmt_addrbhpof, { 0x67 }
- },
-/* orb $regb8,$hash$uimm8 */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (REGB8), ',', OP (HASH), OP (UIMM8), 0 } },
- & ifmt_addrbhpof, { 0x77 }
- },
-/* xorb $regb8,$hash$uimm8 */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (REGB8), ',', OP (HASH), OP (UIMM8), 0 } },
- & ifmt_addrbhpof, { 0x57 }
- },
-/* and $dr,[$sr2] */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (DR), ',', '[', OP (SR2), ']', 0 } },
- & ifmt_add2, { 0x868 }
- },
-/* or $dr,[$sr2] */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (DR), ',', '[', OP (SR2), ']', 0 } },
- & ifmt_add2, { 0x878 }
- },
-/* xor $dr,[$sr2] */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (DR), ',', '[', OP (SR2), ']', 0 } },
- & ifmt_add2, { 0x858 }
- },
-/* andb $drb,[$sr2] */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (DRB), ',', '[', OP (SR2), ']', 0 } },
- & ifmt_addb2, { 0x869 }
- },
-/* orb $drb,[$sr2] */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (DRB), ',', '[', OP (SR2), ']', 0 } },
- & ifmt_addb2, { 0x879 }
- },
-/* xorb $drb,[$sr2] */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (DRB), ',', '[', OP (SR2), ']', 0 } },
- & ifmt_addb2, { 0x859 }
- },
-/* and $dr,[$sr2+] */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (DR), ',', '[', OP (SR2), '+', ']', 0 } },
- & ifmt_add2, { 0xc68 }
- },
-/* or $dr,[$sr2+] */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (DR), ',', '[', OP (SR2), '+', ']', 0 } },
- & ifmt_add2, { 0xc78 }
- },
-/* xor $dr,[$sr2+] */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (DR), ',', '[', OP (SR2), '+', ']', 0 } },
- & ifmt_add2, { 0xc58 }
- },
-/* andb $drb,[$sr2+] */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (DRB), ',', '[', OP (SR2), '+', ']', 0 } },
- & ifmt_addb2, { 0xc69 }
- },
-/* orb $drb,[$sr2+] */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (DRB), ',', '[', OP (SR2), '+', ']', 0 } },
- & ifmt_addb2, { 0xc79 }
- },
-/* xorb $drb,[$sr2+] */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (DRB), ',', '[', OP (SR2), '+', ']', 0 } },
- & ifmt_addb2, { 0xc59 }
- },
-/* and $pof$reg8,$upof16 */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (POF), OP (REG8), ',', OP (UPOF16), 0 } },
- & ifmt_addrpof, { 0x62 }
- },
-/* or $pof$reg8,$upof16 */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (POF), OP (REG8), ',', OP (UPOF16), 0 } },
- & ifmt_addrpof, { 0x72 }
- },
-/* xor $pof$reg8,$upof16 */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (POF), OP (REG8), ',', OP (UPOF16), 0 } },
- & ifmt_addrpof, { 0x52 }
- },
-/* andb $pof$regb8,$upof16 */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (POF), OP (REGB8), ',', OP (UPOF16), 0 } },
- & ifmt_addbrpof, { 0x63 }
- },
-/* orb $pof$regb8,$upof16 */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (POF), OP (REGB8), ',', OP (UPOF16), 0 } },
- & ifmt_addbrpof, { 0x73 }
- },
-/* xorb $pof$regb8,$upof16 */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (POF), OP (REGB8), ',', OP (UPOF16), 0 } },
- & ifmt_addbrpof, { 0x53 }
- },
-/* and $pof$upof16,$reg8 */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (POF), OP (UPOF16), ',', OP (REG8), 0 } },
- & ifmt_addrpof, { 0x64 }
- },
-/* or $pof$upof16,$reg8 */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (POF), OP (UPOF16), ',', OP (REG8), 0 } },
- & ifmt_addrpof, { 0x74 }
- },
-/* xor $pof$upof16,$reg8 */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (POF), OP (UPOF16), ',', OP (REG8), 0 } },
- & ifmt_addrpof, { 0x54 }
- },
-/* andb $pof$upof16,$regb8 */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (POF), OP (UPOF16), ',', OP (REGB8), 0 } },
- & ifmt_addbrpof, { 0x65 }
- },
-/* orb $pof$upof16,$regb8 */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (POF), OP (UPOF16), ',', OP (REGB8), 0 } },
- & ifmt_addbrpof, { 0x75 }
- },
-/* xorb $pof$upof16,$regb8 */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (POF), OP (UPOF16), ',', OP (REGB8), 0 } },
- & ifmt_addbrpof, { 0x55 }
- },
-/* and $regmem8,$memgr8 */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (REGMEM8), ',', OP (MEMGR8), 0 } },
- & ifmt_addrm2, { 0x62 }
- },
-/* and $memgr8,$regmem8 */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (MEMGR8), ',', OP (REGMEM8), 0 } },
- & ifmt_addrm2, { 0x64 }
- },
-/* and $reg8,$memory */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (REG8), ',', OP (MEMORY), 0 } },
- & ifmt_addrm, { 0x62 }
- },
-/* and $memory,$reg8 */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (MEMORY), ',', OP (REG8), 0 } },
- & ifmt_addrm, { 0x64 }
- },
-/* or $regmem8,$memgr8 */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (REGMEM8), ',', OP (MEMGR8), 0 } },
- & ifmt_addrm2, { 0x72 }
- },
-/* or $memgr8,$regmem8 */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (MEMGR8), ',', OP (REGMEM8), 0 } },
- & ifmt_addrm2, { 0x74 }
- },
-/* or $reg8,$memory */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (REG8), ',', OP (MEMORY), 0 } },
- & ifmt_addrm, { 0x72 }
- },
-/* or $memory,$reg8 */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (MEMORY), ',', OP (REG8), 0 } },
- & ifmt_addrm, { 0x74 }
- },
-/* xor $regmem8,$memgr8 */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (REGMEM8), ',', OP (MEMGR8), 0 } },
- & ifmt_addrm2, { 0x52 }
- },
-/* xor $memgr8,$regmem8 */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (MEMGR8), ',', OP (REGMEM8), 0 } },
- & ifmt_addrm2, { 0x54 }
- },
-/* xor $reg8,$memory */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (REG8), ',', OP (MEMORY), 0 } },
- & ifmt_addrm, { 0x52 }
- },
-/* xor $memory,$reg8 */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (MEMORY), ',', OP (REG8), 0 } },
- & ifmt_addrm, { 0x54 }
- },
-/* andb $regbmem8,$memgr8 */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (REGBMEM8), ',', OP (MEMGR8), 0 } },
- & ifmt_addbrm2, { 0x63 }
- },
-/* andb $memgr8,$regbmem8 */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (MEMGR8), ',', OP (REGBMEM8), 0 } },
- & ifmt_addbrm2, { 0x65 }
- },
-/* andb $regb8,$memory */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (REGB8), ',', OP (MEMORY), 0 } },
- & ifmt_addbrm, { 0x63 }
- },
-/* andb $memory,$regb8 */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (MEMORY), ',', OP (REGB8), 0 } },
- & ifmt_addbrm, { 0x65 }
- },
-/* orb $regbmem8,$memgr8 */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (REGBMEM8), ',', OP (MEMGR8), 0 } },
- & ifmt_addbrm2, { 0x73 }
- },
-/* orb $memgr8,$regbmem8 */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (MEMGR8), ',', OP (REGBMEM8), 0 } },
- & ifmt_addbrm2, { 0x75 }
- },
-/* orb $regb8,$memory */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (REGB8), ',', OP (MEMORY), 0 } },
- & ifmt_addbrm, { 0x73 }
- },
-/* orb $memory,$regb8 */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (MEMORY), ',', OP (REGB8), 0 } },
- & ifmt_addbrm, { 0x75 }
- },
-/* xorb $regbmem8,$memgr8 */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (REGBMEM8), ',', OP (MEMGR8), 0 } },
- & ifmt_addbrm2, { 0x53 }
- },
-/* xorb $memgr8,$regbmem8 */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (MEMGR8), ',', OP (REGBMEM8), 0 } },
- & ifmt_addbrm2, { 0x55 }
- },
-/* xorb $regb8,$memory */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (REGB8), ',', OP (MEMORY), 0 } },
- & ifmt_addbrm, { 0x53 }
- },
-/* xorb $memory,$regb8 */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (MEMORY), ',', OP (REGB8), 0 } },
- & ifmt_addbrm, { 0x55 }
- },
-/* mov $dr,$sr */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
- & ifmt_addr, { 0xf0 }
- },
-/* movb $drb,$srb */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (DRB), ',', OP (SRB), 0 } },
- & ifmt_addbr, { 0xf1 }
- },
-/* mov $dri,$hash$u4 */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (DRI), ',', OP (HASH), OP (U4), 0 } },
- & ifmt_movri, { 0xe0 }
- },
-/* movb $srb,$hash$u4 */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (SRB), ',', OP (HASH), OP (U4), 0 } },
- & ifmt_movbri, { 0xe1 }
- },
-/* mov $reg8,$hash$uimm16 */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (REG8), ',', OP (HASH), OP (UIMM16), 0 } },
- & ifmt_addrhpof, { 0xe6 }
- },
-/* movb $regb8,$hash$uimm8 */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (REGB8), ',', OP (HASH), OP (UIMM8), 0 } },
- & ifmt_addrbhpof, { 0xe7 }
- },
-/* mov $dr,[$sr] */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (DR), ',', '[', OP (SR), ']', 0 } },
- & ifmt_addr, { 0xa8 }
- },
-/* movb $drb,[$sr] */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (DRB), ',', '[', OP (SR), ']', 0 } },
- & ifmt_movbr2, { 0xa9 }
- },
-/* mov [$sr],$dr */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', '[', OP (SR), ']', ',', OP (DR), 0 } },
- & ifmt_addr, { 0xb8 }
- },
-/* movb [$sr],$drb */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', '[', OP (SR), ']', ',', OP (DRB), 0 } },
- & ifmt_movbr2, { 0xb9 }
- },
-/* mov [-$sr],$dr */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', '[', '-', OP (SR), ']', ',', OP (DR), 0 } },
- & ifmt_addr, { 0x88 }
- },
-/* movb [-$sr],$drb */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', '[', '-', OP (SR), ']', ',', OP (DRB), 0 } },
- & ifmt_movbr2, { 0x89 }
- },
-/* mov $dr,[$sr+] */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (DR), ',', '[', OP (SR), '+', ']', 0 } },
- & ifmt_addr, { 0x98 }
- },
-/* movb $drb,[$sr+] */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (DRB), ',', '[', OP (SR), '+', ']', 0 } },
- & ifmt_movbr2, { 0x99 }
- },
-/* mov [$dr],[$sr] */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', '[', OP (DR), ']', ',', '[', OP (SR), ']', 0 } },
- & ifmt_addr, { 0xc8 }
- },
-/* movb [$dr],[$sr] */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', '[', OP (DR), ']', ',', '[', OP (SR), ']', 0 } },
- & ifmt_addr, { 0xc9 }
- },
-/* mov [$dr+],[$sr] */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', '[', OP (DR), '+', ']', ',', '[', OP (SR), ']', 0 } },
- & ifmt_addr, { 0xd8 }
- },
-/* movb [$dr+],[$sr] */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', '[', OP (DR), '+', ']', ',', '[', OP (SR), ']', 0 } },
- & ifmt_addr, { 0xd9 }
- },
-/* mov [$dr],[$sr+] */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', '[', OP (DR), ']', ',', '[', OP (SR), '+', ']', 0 } },
- & ifmt_addr, { 0xe8 }
- },
-/* movb [$dr],[$sr+] */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', '[', OP (DR), ']', ',', '[', OP (SR), '+', ']', 0 } },
- & ifmt_addr, { 0xe9 }
- },
-/* mov $dr,[$sr+$hash$uimm16] */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (DR), ',', '[', OP (SR), '+', OP (HASH), OP (UIMM16), ']', 0 } },
- & ifmt_mov9i, { 0xd4 }
- },
-/* movb $drb,[$sr+$hash$uimm16] */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (DRB), ',', '[', OP (SR), '+', OP (HASH), OP (UIMM16), ']', 0 } },
- & ifmt_movb9i, { 0xf4 }
- },
-/* mov [$sr+$hash$uimm16],$dr */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', '[', OP (SR), '+', OP (HASH), OP (UIMM16), ']', ',', OP (DR), 0 } },
- & ifmt_mov9i, { 0xc4 }
- },
-/* movb [$sr+$hash$uimm16],$drb */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', '[', OP (SR), '+', OP (HASH), OP (UIMM16), ']', ',', OP (DRB), 0 } },
- & ifmt_movb9i, { 0xe4 }
- },
-/* mov [$src2],$memory */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', '[', OP (SRC2), ']', ',', OP (MEMORY), 0 } },
- & ifmt_movri11, { 0x84 }
- },
-/* movb [$src2],$memory */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', '[', OP (SRC2), ']', ',', OP (MEMORY), 0 } },
- & ifmt_movri11, { 0xa4 }
- },
-/* mov $memory,[$src2] */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (MEMORY), ',', '[', OP (SRC2), ']', 0 } },
- & ifmt_movri11, { 0x94 }
- },
-/* movb $memory,[$src2] */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (MEMORY), ',', '[', OP (SRC2), ']', 0 } },
- & ifmt_movri11, { 0xb4 }
- },
-/* mov $regoff8,$hash$pof$upof16 */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (REGOFF8), ',', OP (HASH), OP (POF), OP (UPOF16), 0 } },
- & ifmt_movehm5, { 0xe6 }
- },
-/* mov $regoff8,$hash$pag$upag16 */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (REGOFF8), ',', OP (HASH), OP (PAG), OP (UPAG16), 0 } },
- & ifmt_movehm6, { 0xe6 }
- },
-/* mov $regoff8,$hash$segm$useg16 */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (REGOFF8), ',', OP (HASH), OP (SEGM), OP (USEG16), 0 } },
- & ifmt_movehm7, { 0xe6 }
- },
-/* mov $regoff8,$hash$sof$usof16 */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (REGOFF8), ',', OP (HASH), OP (SOF), OP (USOF16), 0 } },
- & ifmt_movehm8, { 0xe6 }
- },
-/* movb $regb8,$hash$pof$uimm8 */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (REGB8), ',', OP (HASH), OP (POF), OP (UIMM8), 0 } },
- & ifmt_addrbhpof, { 0xe7 }
- },
-/* movb $regoff8,$hash$pag$uimm8 */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (REGOFF8), ',', OP (HASH), OP (PAG), OP (UIMM8), 0 } },
- & ifmt_movehm10, { 0xe7 }
- },
-/* mov $regoff8,$pof$upof16 */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (REGOFF8), ',', OP (POF), OP (UPOF16), 0 } },
- & ifmt_movehm5, { 0xf2 }
- },
-/* movb $regb8,$pof$upof16 */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (REGB8), ',', OP (POF), OP (UPOF16), 0 } },
- & ifmt_addbrpof, { 0xf3 }
- },
-/* mov $regoff8,$pag$upag16 */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (REGOFF8), ',', OP (PAG), OP (UPAG16), 0 } },
- & ifmt_movehm6, { 0xf2 }
- },
-/* movb $regb8,$pag$upag16 */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (REGB8), ',', OP (PAG), OP (UPAG16), 0 } },
- & ifmt_addbrpag, { 0xf3 }
- },
-/* mov $pof$upof16,$regoff8 */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (POF), OP (UPOF16), ',', OP (REGOFF8), 0 } },
- & ifmt_movehm5, { 0xf6 }
- },
-/* movb $pof$upof16,$regb8 */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (POF), OP (UPOF16), ',', OP (REGB8), 0 } },
- & ifmt_addbrpof, { 0xf7 }
- },
-/* mov $dri,$hash$pof$u4 */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (DRI), ',', OP (HASH), OP (POF), OP (U4), 0 } },
- & ifmt_movri, { 0xe0 }
- },
-/* movb $srb,$hash$pof$u4 */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (SRB), ',', OP (HASH), OP (POF), OP (U4), 0 } },
- & ifmt_movbri, { 0xe1 }
- },
-/* mov $dri,$hash$pag$u4 */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (DRI), ',', OP (HASH), OP (PAG), OP (U4), 0 } },
- & ifmt_movri, { 0xe0 }
- },
-/* movb $srb,$hash$pag$u4 */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (SRB), ',', OP (HASH), OP (PAG), OP (U4), 0 } },
- & ifmt_movbri, { 0xe1 }
- },
-/* mov $regmem8,$memgr8 */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (REGMEM8), ',', OP (MEMGR8), 0 } },
- & ifmt_addrm2, { 0xf2 }
- },
-/* mov $memgr8,$regmem8 */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (MEMGR8), ',', OP (REGMEM8), 0 } },
- & ifmt_addrm2, { 0xf6 }
- },
-/* mov $reg8,$memory */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (REG8), ',', OP (MEMORY), 0 } },
- & ifmt_addrm, { 0xf2 }
- },
-/* mov $memory,$reg8 */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (MEMORY), ',', OP (REG8), 0 } },
- & ifmt_addrm, { 0xf6 }
- },
-/* movb $regbmem8,$memgr8 */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (REGBMEM8), ',', OP (MEMGR8), 0 } },
- & ifmt_addbrm2, { 0xf3 }
- },
-/* movb $memgr8,$regbmem8 */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (MEMGR8), ',', OP (REGBMEM8), 0 } },
- & ifmt_addbrm2, { 0xf7 }
- },
-/* movb $regb8,$memory */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (REGB8), ',', OP (MEMORY), 0 } },
- & ifmt_addbrm, { 0xf3 }
- },
-/* movb $memory,$regb8 */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (MEMORY), ',', OP (REGB8), 0 } },
- & ifmt_addbrm, { 0xf7 }
- },
-/* movbs $sr,$drb */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (SR), ',', OP (DRB), 0 } },
- & ifmt_movbr2, { 0xd0 }
- },
-/* movbz $sr,$drb */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (SR), ',', OP (DRB), 0 } },
- & ifmt_movbr2, { 0xc0 }
- },
-/* movbs $regmem8,$pof$upof16 */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (REGMEM8), ',', OP (POF), OP (UPOF16), 0 } },
- & ifmt_movbsrpofm, { 0xd2 }
- },
-/* movbs $pof$upof16,$regbmem8 */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (POF), OP (UPOF16), ',', OP (REGBMEM8), 0 } },
- & ifmt_movbspofmr, { 0xd5 }
- },
-/* movbz $reg8,$pof$upof16 */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (REG8), ',', OP (POF), OP (UPOF16), 0 } },
- & ifmt_addrpof, { 0xc2 }
- },
-/* movbz $pof$upof16,$regb8 */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (POF), OP (UPOF16), ',', OP (REGB8), 0 } },
- & ifmt_addbrpof, { 0xc5 }
- },
-/* movbs $regmem8,$memgr8 */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (REGMEM8), ',', OP (MEMGR8), 0 } },
- & ifmt_addrm2, { 0xd2 }
- },
-/* movbs $memgr8,$regbmem8 */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (MEMGR8), ',', OP (REGBMEM8), 0 } },
- & ifmt_addbrm2, { 0xd5 }
- },
-/* movbs $reg8,$memory */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (REG8), ',', OP (MEMORY), 0 } },
- & ifmt_addrm, { 0xd2 }
- },
-/* movbs $memory,$regb8 */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (MEMORY), ',', OP (REGB8), 0 } },
- & ifmt_addbrm, { 0xd5 }
- },
-/* movbz $regmem8,$memgr8 */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (REGMEM8), ',', OP (MEMGR8), 0 } },
- & ifmt_addrm2, { 0xc2 }
- },
-/* movbz $memgr8,$regbmem8 */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (MEMGR8), ',', OP (REGBMEM8), 0 } },
- & ifmt_addbrm2, { 0xc5 }
- },
-/* movbz $reg8,$memory */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (REG8), ',', OP (MEMORY), 0 } },
- & ifmt_addrm, { 0xc2 }
- },
-/* movbz $memory,$regb8 */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (MEMORY), ',', OP (REGB8), 0 } },
- & ifmt_addbrm, { 0xc5 }
- },
-/* movbs $sr,$drb */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (SR), ',', OP (DRB), 0 } },
- & ifmt_movbr2, { 0xd0 }
- },
-/* movbz $sr,$drb */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (SR), ',', OP (DRB), 0 } },
- & ifmt_movbr2, { 0xc0 }
- },
-/* jmpa+ $extcond,$caddr */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (EXTCOND), ',', OP (CADDR), 0 } },
- & ifmt_jmpa0, { 0xea }
- },
-/* jmpa $extcond,$caddr */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (EXTCOND), ',', OP (CADDR), 0 } },
- & ifmt_jmpa0, { 0xea }
- },
-/* jmpa- $extcond,$caddr */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (EXTCOND), ',', OP (CADDR), 0 } },
- & ifmt_jmpa_, { 0x1ea }
- },
-/* jmpi $icond,[$sr] */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (ICOND), ',', '[', OP (SR), ']', 0 } },
- & ifmt_jmpi, { 0x9c }
- },
-/* jmpr $cond,$rel */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (COND), ',', OP (REL), 0 } },
- & ifmt_jmpr_nenz, { 0x3d }
- },
-/* jmpr $cond,$rel */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (COND), ',', OP (REL), 0 } },
- & ifmt_jmpr_nenz, { 0xad }
- },
-/* jmpr $cond,$rel */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (COND), ',', OP (REL), 0 } },
- & ifmt_jmpr_nenz, { 0x2d }
- },
-/* jmpr $cond,$rel */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (COND), ',', OP (REL), 0 } },
- & ifmt_jmpr_nenz, { 0x4d }
- },
-/* jmpr $cond,$rel */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (COND), ',', OP (REL), 0 } },
- & ifmt_jmpr_nenz, { 0x5d }
- },
-/* jmpr $cond,$rel */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (COND), ',', OP (REL), 0 } },
- & ifmt_jmpr_nenz, { 0x6d }
- },
-/* jmpr $cond,$rel */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (COND), ',', OP (REL), 0 } },
- & ifmt_jmpr_nenz, { 0x7d }
- },
-/* jmpr $cond,$rel */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (COND), ',', OP (REL), 0 } },
- & ifmt_jmpr_nenz, { 0x8d }
- },
-/* jmpr $cond,$rel */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (COND), ',', OP (REL), 0 } },
- & ifmt_jmpr_nenz, { 0x9d }
- },
-/* jmpr $cond,$rel */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (COND), ',', OP (REL), 0 } },
- & ifmt_jmpr_nenz, { 0x2d }
- },
-/* jmpr $cond,$rel */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (COND), ',', OP (REL), 0 } },
- & ifmt_jmpr_nenz, { 0x3d }
- },
-/* jmpr $cond,$rel */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (COND), ',', OP (REL), 0 } },
- & ifmt_jmpr_nenz, { 0x8d }
- },
-/* jmpr $cond,$rel */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (COND), ',', OP (REL), 0 } },
- & ifmt_jmpr_nenz, { 0xfd }
- },
-/* jmpr $cond,$rel */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (COND), ',', OP (REL), 0 } },
- & ifmt_jmpr_nenz, { 0x9d }
- },
-/* jmpr $cond,$rel */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (COND), ',', OP (REL), 0 } },
- & ifmt_jmpr_nenz, { 0xed }
- },
-/* jmpr $cond,$rel */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (COND), ',', OP (REL), 0 } },
- & ifmt_jmpr_nenz, { 0xbd }
- },
-/* jmpr $cond,$rel */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (COND), ',', OP (REL), 0 } },
- & ifmt_jmpr_nenz, { 0xdd }
- },
-/* jmpr $cond,$rel */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (COND), ',', OP (REL), 0 } },
- & ifmt_jmpr_nenz, { 0x1d }
- },
-/* jmpr $cond,$rel */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (COND), ',', OP (REL), 0 } },
- & ifmt_jmpr_nenz, { 0xd }
- },
-/* jmpr $cond,$rel */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (COND), ',', OP (REL), 0 } },
- & ifmt_jmpr_nenz, { 0xcd }
- },
-/* jmps $hash$segm$useg8,$hash$sof$usof16 */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (HASH), OP (SEGM), OP (USEG8), ',', OP (HASH), OP (SOF), OP (USOF16), 0 } },
- & ifmt_jmpseg, { 0xfa }
- },
-/* jmps $seg,$caddr */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (SEG), ',', OP (CADDR), 0 } },
- & ifmt_jmps, { 0xfa }
- },
-/* jb $genreg$dot$qlobit,$relhi */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (GENREG), OP (DOT), OP (QLOBIT), ',', OP (RELHI), 0 } },
- & ifmt_jb, { 0x8a }
- },
-/* jbc $genreg$dot$qlobit,$relhi */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (GENREG), OP (DOT), OP (QLOBIT), ',', OP (RELHI), 0 } },
- & ifmt_jb, { 0xaa }
- },
-/* jnb $genreg$dot$qlobit,$relhi */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (GENREG), OP (DOT), OP (QLOBIT), ',', OP (RELHI), 0 } },
- & ifmt_jb, { 0x9a }
- },
-/* jnbs $genreg$dot$qlobit,$relhi */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (GENREG), OP (DOT), OP (QLOBIT), ',', OP (RELHI), 0 } },
- & ifmt_jb, { 0xba }
- },
-/* calla+ $extcond,$caddr */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (EXTCOND), ',', OP (CADDR), 0 } },
- & ifmt_calla0, { 0xca }
- },
-/* calla $extcond,$caddr */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (EXTCOND), ',', OP (CADDR), 0 } },
- & ifmt_calla0, { 0xca }
- },
-/* calla- $extcond,$caddr */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (EXTCOND), ',', OP (CADDR), 0 } },
- & ifmt_calla_, { 0x1ca }
- },
-/* calli $icond,[$sr] */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (ICOND), ',', '[', OP (SR), ']', 0 } },
- & ifmt_jmpi, { 0xab }
- },
-/* callr $rel */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (REL), 0 } },
- & ifmt_callr, { 0xbb }
- },
-/* calls $hash$segm$useg8,$hash$sof$usof16 */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (HASH), OP (SEGM), OP (USEG8), ',', OP (HASH), OP (SOF), OP (USOF16), 0 } },
- & ifmt_callseg, { 0xda }
- },
-/* calls $seg,$caddr */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (SEG), ',', OP (CADDR), 0 } },
- & ifmt_jmps, { 0xda }
- },
-/* pcall $reg8,$caddr */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (REG8), ',', OP (CADDR), 0 } },
- & ifmt_pcall, { 0xe2 }
- },
-/* trap $hash$uimm7 */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (HASH), OP (UIMM7), 0 } },
- & ifmt_trap, { 0x9b }
- },
-/* ret */
- {
- { 0, 0, 0, 0 },
- { { MNEM, 0 } },
- & ifmt_ret, { 0xcb }
- },
-/* rets */
- {
- { 0, 0, 0, 0 },
- { { MNEM, 0 } },
- & ifmt_ret, { 0xdb }
- },
-/* retp $reg8 */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (REG8), 0 } },
- & ifmt_retp, { 0xeb }
- },
-/* reti */
- {
- { 0, 0, 0, 0 },
- { { MNEM, 0 } },
- & ifmt_reti, { 0x88fb }
- },
-/* pop $reg8 */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (REG8), 0 } },
- & ifmt_retp, { 0xfc }
- },
-/* push $reg8 */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (REG8), 0 } },
- & ifmt_retp, { 0xec }
- },
-/* scxt $reg8,$hash$uimm16 */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (REG8), ',', OP (HASH), OP (UIMM16), 0 } },
- & ifmt_addrhpof, { 0xc6 }
- },
-/* scxt $reg8,$pof$upof16 */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (REG8), ',', OP (POF), OP (UPOF16), 0 } },
- & ifmt_addrpof, { 0xd6 }
- },
-/* scxt $regmem8,$memgr8 */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (REGMEM8), ',', OP (MEMGR8), 0 } },
- & ifmt_addrm2, { 0xd6 }
- },
-/* scxt $reg8,$memory */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (REG8), ',', OP (MEMORY), 0 } },
- & ifmt_addrm, { 0xd6 }
- },
-/* nop */
- {
- { 0, 0, 0, 0 },
- { { MNEM, 0 } },
- & ifmt_ret, { 0xcc }
- },
-/* srst */
- {
- { 0, 0, 0, 0 },
- { { MNEM, 0 } },
- & ifmt_srstm, { 0xb7b748b7 }
- },
-/* idle */
- {
- { 0, 0, 0, 0 },
- { { MNEM, 0 } },
- & ifmt_srstm, { 0x87877887 }
- },
-/* pwrdn */
- {
- { 0, 0, 0, 0 },
- { { MNEM, 0 } },
- & ifmt_srstm, { 0x97976897 }
- },
-/* diswdt */
- {
- { 0, 0, 0, 0 },
- { { MNEM, 0 } },
- & ifmt_srstm, { 0xa5a55aa5 }
- },
-/* enwdt */
- {
- { 0, 0, 0, 0 },
- { { MNEM, 0 } },
- & ifmt_srstm, { 0x85857a85 }
- },
-/* einit */
- {
- { 0, 0, 0, 0 },
- { { MNEM, 0 } },
- & ifmt_srstm, { 0xb5b54ab5 }
- },
-/* srvwdt */
- {
- { 0, 0, 0, 0 },
- { { MNEM, 0 } },
- & ifmt_srstm, { 0xa7a758a7 }
- },
-/* sbrk */
- {
- { 0, 0, 0, 0 },
- { { MNEM, 0 } },
- & ifmt_ret, { 0x8c }
- },
-/* atomic $hash$uimm2 */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (HASH), OP (UIMM2), 0 } },
- & ifmt_atomic, { 0xd1 }
- },
-/* extr $hash$uimm2 */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (HASH), OP (UIMM2), 0 } },
- & ifmt_atomic, { 0x80d1 }
- },
-/* extp $sr,$hash$uimm2 */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (SR), ',', OP (HASH), OP (UIMM2), 0 } },
- & ifmt_extp, { 0x40dc }
- },
-/* extp $hash$pagenum,$hash$uimm2 */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (HASH), OP (PAGENUM), ',', OP (HASH), OP (UIMM2), 0 } },
- & ifmt_extp1, { 0x40d7 }
- },
-/* extp $hash$pag$upag16,$hash$uimm2 */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (HASH), OP (PAG), OP (UPAG16), ',', OP (HASH), OP (UIMM2), 0 } },
- & ifmt_extpg1, { 0x40d7 }
- },
-/* extpr $sr,$hash$uimm2 */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (SR), ',', OP (HASH), OP (UIMM2), 0 } },
- & ifmt_extp, { 0xc0dc }
- },
-/* extpr $hash$pagenum,$hash$uimm2 */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (HASH), OP (PAGENUM), ',', OP (HASH), OP (UIMM2), 0 } },
- & ifmt_extp1, { 0xc0d7 }
- },
-/* exts $sr,$hash$uimm2 */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (SR), ',', OP (HASH), OP (UIMM2), 0 } },
- & ifmt_extp, { 0xdc }
- },
-/* exts $hash$seghi8,$hash$uimm2 */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (HASH), OP (SEGHI8), ',', OP (HASH), OP (UIMM2), 0 } },
- & ifmt_exts1, { 0xd7 }
- },
-/* extsr $sr,$hash$uimm2 */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (SR), ',', OP (HASH), OP (UIMM2), 0 } },
- & ifmt_extp, { 0x80dc }
- },
-/* extsr $hash$seghi8,$hash$uimm2 */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (HASH), OP (SEGHI8), ',', OP (HASH), OP (UIMM2), 0 } },
- & ifmt_exts1, { 0x80d7 }
- },
-/* prior $dr,$sr */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
- & ifmt_addr, { 0x2b }
- },
-/* bclr $RegNam */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (REGNAM), 0 } },
- & ifmt_bclr18, { 0xbe }
- },
-/* bclr $reg8$dot$qbit */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (REG8), OP (DOT), OP (QBIT), 0 } },
- & ifmt_bclr0, { 0xe }
- },
-/* bclr $reg8$dot$qbit */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (REG8), OP (DOT), OP (QBIT), 0 } },
- & ifmt_bclr0, { 0x1e }
- },
-/* bclr $reg8$dot$qbit */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (REG8), OP (DOT), OP (QBIT), 0 } },
- & ifmt_bclr0, { 0x2e }
- },
-/* bclr $reg8$dot$qbit */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (REG8), OP (DOT), OP (QBIT), 0 } },
- & ifmt_bclr0, { 0x3e }
- },
-/* bclr $reg8$dot$qbit */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (REG8), OP (DOT), OP (QBIT), 0 } },
- & ifmt_bclr0, { 0x4e }
- },
-/* bclr $reg8$dot$qbit */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (REG8), OP (DOT), OP (QBIT), 0 } },
- & ifmt_bclr0, { 0x5e }
- },
-/* bclr $reg8$dot$qbit */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (REG8), OP (DOT), OP (QBIT), 0 } },
- & ifmt_bclr0, { 0x6e }
- },
-/* bclr $reg8$dot$qbit */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (REG8), OP (DOT), OP (QBIT), 0 } },
- & ifmt_bclr0, { 0x7e }
- },
-/* bclr $reg8$dot$qbit */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (REG8), OP (DOT), OP (QBIT), 0 } },
- & ifmt_bclr0, { 0x8e }
- },
-/* bclr $reg8$dot$qbit */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (REG8), OP (DOT), OP (QBIT), 0 } },
- & ifmt_bclr0, { 0x9e }
- },
-/* bclr $reg8$dot$qbit */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (REG8), OP (DOT), OP (QBIT), 0 } },
- & ifmt_bclr0, { 0xae }
- },
-/* bclr $reg8$dot$qbit */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (REG8), OP (DOT), OP (QBIT), 0 } },
- & ifmt_bclr0, { 0xbe }
- },
-/* bclr $reg8$dot$qbit */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (REG8), OP (DOT), OP (QBIT), 0 } },
- & ifmt_bclr0, { 0xce }
- },
-/* bclr $reg8$dot$qbit */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (REG8), OP (DOT), OP (QBIT), 0 } },
- & ifmt_bclr0, { 0xde }
- },
-/* bclr $reg8$dot$qbit */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (REG8), OP (DOT), OP (QBIT), 0 } },
- & ifmt_bclr0, { 0xee }
- },
-/* bclr $reg8$dot$qbit */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (REG8), OP (DOT), OP (QBIT), 0 } },
- & ifmt_bclr0, { 0xfe }
- },
-/* bset $RegNam */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (REGNAM), 0 } },
- & ifmt_bclr18, { 0xbf }
- },
-/* bset $reg8$dot$qbit */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (REG8), OP (DOT), OP (QBIT), 0 } },
- & ifmt_bclr0, { 0xf }
- },
-/* bset $reg8$dot$qbit */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (REG8), OP (DOT), OP (QBIT), 0 } },
- & ifmt_bclr0, { 0x1f }
- },
-/* bset $reg8$dot$qbit */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (REG8), OP (DOT), OP (QBIT), 0 } },
- & ifmt_bclr0, { 0x2f }
- },
-/* bset $reg8$dot$qbit */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (REG8), OP (DOT), OP (QBIT), 0 } },
- & ifmt_bclr0, { 0x3f }
- },
-/* bset $reg8$dot$qbit */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (REG8), OP (DOT), OP (QBIT), 0 } },
- & ifmt_bclr0, { 0x4f }
- },
-/* bset $reg8$dot$qbit */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (REG8), OP (DOT), OP (QBIT), 0 } },
- & ifmt_bclr0, { 0x5f }
- },
-/* bset $reg8$dot$qbit */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (REG8), OP (DOT), OP (QBIT), 0 } },
- & ifmt_bclr0, { 0x6f }
- },
-/* bset $reg8$dot$qbit */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (REG8), OP (DOT), OP (QBIT), 0 } },
- & ifmt_bclr0, { 0x7f }
- },
-/* bset $reg8$dot$qbit */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (REG8), OP (DOT), OP (QBIT), 0 } },
- & ifmt_bclr0, { 0x8f }
- },
-/* bset $reg8$dot$qbit */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (REG8), OP (DOT), OP (QBIT), 0 } },
- & ifmt_bclr0, { 0x9f }
- },
-/* bset $reg8$dot$qbit */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (REG8), OP (DOT), OP (QBIT), 0 } },
- & ifmt_bclr0, { 0xaf }
- },
-/* bset $reg8$dot$qbit */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (REG8), OP (DOT), OP (QBIT), 0 } },
- & ifmt_bclr0, { 0xbf }
- },
-/* bset $reg8$dot$qbit */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (REG8), OP (DOT), OP (QBIT), 0 } },
- & ifmt_bclr0, { 0xcf }
- },
-/* bset $reg8$dot$qbit */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (REG8), OP (DOT), OP (QBIT), 0 } },
- & ifmt_bclr0, { 0xdf }
- },
-/* bset $reg8$dot$qbit */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (REG8), OP (DOT), OP (QBIT), 0 } },
- & ifmt_bclr0, { 0xef }
- },
-/* bset $reg8$dot$qbit */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (REG8), OP (DOT), OP (QBIT), 0 } },
- & ifmt_bclr0, { 0xff }
- },
-/* bmov $reghi8$dot$qhibit,$reg8$dot$qlobit */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (REGHI8), OP (DOT), OP (QHIBIT), ',', OP (REG8), OP (DOT), OP (QLOBIT), 0 } },
- & ifmt_bmov, { 0x4a }
- },
-/* bmovn $reghi8$dot$qhibit,$reg8$dot$qlobit */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (REGHI8), OP (DOT), OP (QHIBIT), ',', OP (REG8), OP (DOT), OP (QLOBIT), 0 } },
- & ifmt_bmov, { 0x3a }
- },
-/* band $reghi8$dot$qhibit,$reg8$dot$qlobit */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (REGHI8), OP (DOT), OP (QHIBIT), ',', OP (REG8), OP (DOT), OP (QLOBIT), 0 } },
- & ifmt_bmov, { 0x6a }
- },
-/* bor $reghi8$dot$qhibit,$reg8$dot$qlobit */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (REGHI8), OP (DOT), OP (QHIBIT), ',', OP (REG8), OP (DOT), OP (QLOBIT), 0 } },
- & ifmt_bmov, { 0x5a }
- },
-/* bxor $reghi8$dot$qhibit,$reg8$dot$qlobit */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (REGHI8), OP (DOT), OP (QHIBIT), ',', OP (REG8), OP (DOT), OP (QLOBIT), 0 } },
- & ifmt_bmov, { 0x7a }
- },
-/* bcmp $reghi8$dot$qhibit,$reg8$dot$qlobit */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (REGHI8), OP (DOT), OP (QHIBIT), ',', OP (REG8), OP (DOT), OP (QLOBIT), 0 } },
- & ifmt_bmov, { 0x2a }
- },
-/* bfldl $reg8,$hash$mask8,$hash$datahi8 */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (REG8), ',', OP (HASH), OP (MASK8), ',', OP (HASH), OP (DATAHI8), 0 } },
- & ifmt_bfldl, { 0xa }
- },
-/* bfldh $reg8,$hash$masklo8,$hash$data8 */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (REG8), ',', OP (HASH), OP (MASKLO8), ',', OP (HASH), OP (DATA8), 0 } },
- & ifmt_bfldh, { 0x1a }
- },
-/* cmp $src1,$src2 */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 } },
- & ifmt_muls, { 0x40 }
- },
-/* cmpb $drb,$srb */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (DRB), ',', OP (SRB), 0 } },
- & ifmt_addbr, { 0x41 }
- },
-/* cmp $src1,$hash$uimm3 */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (SRC1), ',', OP (HASH), OP (UIMM3), 0 } },
- & ifmt_cmpri, { 0x48 }
- },
-/* cmpb $drb,$hash$uimm3 */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (DRB), ',', OP (HASH), OP (UIMM3), 0 } },
- & ifmt_addbrhpag3, { 0x49 }
- },
-/* cmp $reg8,$hash$uimm16 */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (REG8), ',', OP (HASH), OP (UIMM16), 0 } },
- & ifmt_addrhpof, { 0x46 }
- },
-/* cmpb $regb8,$hash$uimm8 */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (REGB8), ',', OP (HASH), OP (UIMM8), 0 } },
- & ifmt_addrbhpof, { 0x47 }
- },
-/* cmp $dr,[$sr2] */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (DR), ',', '[', OP (SR2), ']', 0 } },
- & ifmt_add2, { 0x848 }
- },
-/* cmpb $drb,[$sr2] */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (DRB), ',', '[', OP (SR2), ']', 0 } },
- & ifmt_addb2, { 0x849 }
- },
-/* cmp $dr,[$sr2+] */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (DR), ',', '[', OP (SR2), '+', ']', 0 } },
- & ifmt_add2, { 0xc48 }
- },
-/* cmpb $drb,[$sr2+] */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (DRB), ',', '[', OP (SR2), '+', ']', 0 } },
- & ifmt_addb2, { 0xc49 }
- },
-/* cmp $reg8,$pof$upof16 */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (REG8), ',', OP (POF), OP (UPOF16), 0 } },
- & ifmt_addrpof, { 0x42 }
- },
-/* cmpb $regb8,$pof$upof16 */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (REGB8), ',', OP (POF), OP (UPOF16), 0 } },
- & ifmt_addbrpof, { 0x43 }
- },
-/* cmp $regmem8,$memgr8 */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (REGMEM8), ',', OP (MEMGR8), 0 } },
- & ifmt_addrm2, { 0x42 }
- },
-/* cmp $reg8,$memory */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (REG8), ',', OP (MEMORY), 0 } },
- & ifmt_addrm, { 0x42 }
- },
-/* cmpb $regbmem8,$memgr8 */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (REGBMEM8), ',', OP (MEMGR8), 0 } },
- & ifmt_addbrm2, { 0x43 }
- },
-/* cmpb $regb8,$memory */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (REGB8), ',', OP (MEMORY), 0 } },
- & ifmt_addbrm, { 0x43 }
- },
-/* cmpd1 $sr,$hash$uimm4 */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (SR), ',', OP (HASH), OP (UIMM4), 0 } },
- & ifmt_cmpd1ri, { 0xa0 }
- },
-/* cmpd2 $sr,$hash$uimm4 */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (SR), ',', OP (HASH), OP (UIMM4), 0 } },
- & ifmt_cmpd1ri, { 0xb0 }
- },
-/* cmpi1 $sr,$hash$uimm4 */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (SR), ',', OP (HASH), OP (UIMM4), 0 } },
- & ifmt_cmpd1ri, { 0x80 }
- },
-/* cmpi2 $sr,$hash$uimm4 */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (SR), ',', OP (HASH), OP (UIMM4), 0 } },
- & ifmt_cmpd1ri, { 0x90 }
- },
-/* cmpd1 $reg8,$hash$uimm16 */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (REG8), ',', OP (HASH), OP (UIMM16), 0 } },
- & ifmt_addrhpof, { 0xa6 }
- },
-/* cmpd2 $reg8,$hash$uimm16 */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (REG8), ',', OP (HASH), OP (UIMM16), 0 } },
- & ifmt_addrhpof, { 0xb6 }
- },
-/* cmpi1 $reg8,$hash$uimm16 */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (REG8), ',', OP (HASH), OP (UIMM16), 0 } },
- & ifmt_addrhpof, { 0x86 }
- },
-/* cmpi2 $reg8,$hash$uimm16 */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (REG8), ',', OP (HASH), OP (UIMM16), 0 } },
- & ifmt_addrhpof, { 0x96 }
- },
-/* cmpd1 $reg8,$pof$upof16 */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (REG8), ',', OP (POF), OP (UPOF16), 0 } },
- & ifmt_addrpof, { 0xa2 }
- },
-/* cmpd2 $reg8,$pof$upof16 */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (REG8), ',', OP (POF), OP (UPOF16), 0 } },
- & ifmt_addrpof, { 0xb2 }
- },
-/* cmpi1 $reg8,$pof$upof16 */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (REG8), ',', OP (POF), OP (UPOF16), 0 } },
- & ifmt_addrpof, { 0x82 }
- },
-/* cmpi2 $reg8,$pof$upof16 */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (REG8), ',', OP (POF), OP (UPOF16), 0 } },
- & ifmt_addrpof, { 0x92 }
- },
-/* cmpd1 $regmem8,$memgr8 */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (REGMEM8), ',', OP (MEMGR8), 0 } },
- & ifmt_addrm2, { 0xa2 }
- },
-/* cmpd2 $regmem8,$memgr8 */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (REGMEM8), ',', OP (MEMGR8), 0 } },
- & ifmt_addrm2, { 0xb2 }
- },
-/* cmpi1 $regmem8,$memgr8 */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (REGMEM8), ',', OP (MEMGR8), 0 } },
- & ifmt_addrm2, { 0x82 }
- },
-/* cmpi2 $regmem8,$memgr8 */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (REGMEM8), ',', OP (MEMGR8), 0 } },
- & ifmt_addrm2, { 0x92 }
- },
-/* cmpd1 $reg8,$memory */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (REG8), ',', OP (MEMORY), 0 } },
- & ifmt_addrm, { 0xa2 }
- },
-/* cmpd2 $reg8,$memory */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (REG8), ',', OP (MEMORY), 0 } },
- & ifmt_addrm, { 0xb2 }
- },
-/* cmpi1 $reg8,$memory */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (REG8), ',', OP (MEMORY), 0 } },
- & ifmt_addrm, { 0x82 }
- },
-/* cmpi2 $reg8,$memory */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (REG8), ',', OP (MEMORY), 0 } },
- & ifmt_addrm, { 0x92 }
- },
-/* shl $dr,$sr */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
- & ifmt_addr, { 0x4c }
- },
-/* shr $dr,$sr */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
- & ifmt_addr, { 0x6c }
- },
-/* rol $dr,$sr */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
- & ifmt_addr, { 0xc }
- },
-/* ror $dr,$sr */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
- & ifmt_addr, { 0x2c }
- },
-/* ashr $dr,$sr */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
- & ifmt_addr, { 0xac }
- },
-/* shl $sr,$hash$uimm4 */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (SR), ',', OP (HASH), OP (UIMM4), 0 } },
- & ifmt_cmpd1ri, { 0x5c }
- },
-/* shr $sr,$hash$uimm4 */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (SR), ',', OP (HASH), OP (UIMM4), 0 } },
- & ifmt_cmpd1ri, { 0x7c }
- },
-/* rol $sr,$hash$uimm4 */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (SR), ',', OP (HASH), OP (UIMM4), 0 } },
- & ifmt_cmpd1ri, { 0x1c }
- },
-/* ror $sr,$hash$uimm4 */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (SR), ',', OP (HASH), OP (UIMM4), 0 } },
- & ifmt_cmpd1ri, { 0x3c }
- },
-/* ashr $sr,$hash$uimm4 */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (SR), ',', OP (HASH), OP (UIMM4), 0 } },
- & ifmt_cmpd1ri, { 0xbc }
- },
-};
-
-#undef A
-#undef OPERAND
-#undef MNEM
-#undef OP
-
-/* Formats for ALIAS macro-insns. */
-
-#define F(f) & xc16x_cgen_ifld_table[XC16X_##f]
-#undef F
-
-/* Each non-simple macro entry points to an array of expansion possibilities. */
-
-#define A(a) (1 << CGEN_INSN_##a)
-#define OPERAND(op) XC16X_OPERAND_##op
-#define MNEM CGEN_SYNTAX_MNEMONIC /* syntax value for mnemonic */
-#define OP(field) CGEN_SYNTAX_MAKE_FIELD (OPERAND (field))
-
-/* The macro instruction table. */
-
-static const CGEN_IBASE xc16x_cgen_macro_insn_table[] =
-{
-};
-
-/* The macro instruction opcode table. */
-
-static const CGEN_OPCODE xc16x_cgen_macro_insn_opcode_table[] =
-{
-};
-
-#undef A
-#undef OPERAND
-#undef MNEM
-#undef OP
-
-#ifndef CGEN_ASM_HASH_P
-#define CGEN_ASM_HASH_P(insn) 1
-#endif
-
-#ifndef CGEN_DIS_HASH_P
-#define CGEN_DIS_HASH_P(insn) 1
-#endif
-
-/* Return non-zero if INSN is to be added to the hash table.
- Targets are free to override CGEN_{ASM,DIS}_HASH_P in the .opc file. */
-
-static int
-asm_hash_insn_p (const CGEN_INSN *insn ATTRIBUTE_UNUSED)
-{
- return CGEN_ASM_HASH_P (insn);
-}
-
-static int
-dis_hash_insn_p (const CGEN_INSN *insn)
-{
- /* If building the hash table and the NO-DIS attribute is present,
- ignore. */
- if (CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_NO_DIS))
- return 0;
- return CGEN_DIS_HASH_P (insn);
-}
-
-#ifndef CGEN_ASM_HASH
-#define CGEN_ASM_HASH_SIZE 127
-#ifdef CGEN_MNEMONIC_OPERANDS
-#define CGEN_ASM_HASH(mnem) (*(unsigned char *) (mnem) % CGEN_ASM_HASH_SIZE)
-#else
-#define CGEN_ASM_HASH(mnem) (*(unsigned char *) (mnem) % CGEN_ASM_HASH_SIZE) /*FIXME*/
-#endif
-#endif
-
-/* It doesn't make much sense to provide a default here,
- but while this is under development we do.
- BUFFER is a pointer to the bytes of the insn, target order.
- VALUE is the first base_insn_bitsize bits as an int in host order. */
-
-#ifndef CGEN_DIS_HASH
-#define CGEN_DIS_HASH_SIZE 256
-#define CGEN_DIS_HASH(buf, value) (*(unsigned char *) (buf))
-#endif
-
-/* The result is the hash value of the insn.
- Targets are free to override CGEN_{ASM,DIS}_HASH in the .opc file. */
-
-static unsigned int
-asm_hash_insn (const char *mnem)
-{
- return CGEN_ASM_HASH (mnem);
-}
-
-/* BUF is a pointer to the bytes of the insn, target order.
- VALUE is the first base_insn_bitsize bits as an int in host order. */
-
-static unsigned int
-dis_hash_insn (const char *buf ATTRIBUTE_UNUSED,
- CGEN_INSN_INT value ATTRIBUTE_UNUSED)
-{
- return CGEN_DIS_HASH (buf, value);
-}
-
-/* Set the recorded length of the insn in the CGEN_FIELDS struct. */
-
-static void
-set_fields_bitsize (CGEN_FIELDS *fields, int size)
-{
- CGEN_FIELDS_BITSIZE (fields) = size;
-}
-
-/* Function to call before using the operand instance table.
- This plugs the opcode entries and macro instructions into the cpu table. */
-
-void
-xc16x_cgen_init_opcode_table (CGEN_CPU_DESC cd)
-{
- int i;
- int num_macros = (sizeof (xc16x_cgen_macro_insn_table) /
- sizeof (xc16x_cgen_macro_insn_table[0]));
- const CGEN_IBASE *ib = & xc16x_cgen_macro_insn_table[0];
- const CGEN_OPCODE *oc = & xc16x_cgen_macro_insn_opcode_table[0];
- CGEN_INSN *insns = xmalloc (num_macros * sizeof (CGEN_INSN));
-
- /* This test has been added to avoid a warning generated
- if memset is called with a third argument of value zero. */
- if (num_macros >= 1)
- memset (insns, 0, num_macros * sizeof (CGEN_INSN));
- for (i = 0; i < num_macros; ++i)
- {
- insns[i].base = &ib[i];
- insns[i].opcode = &oc[i];
- xc16x_cgen_build_insn_regex (& insns[i]);
- }
- cd->macro_insn_table.init_entries = insns;
- cd->macro_insn_table.entry_size = sizeof (CGEN_IBASE);
- cd->macro_insn_table.num_init_entries = num_macros;
-
- oc = & xc16x_cgen_insn_opcode_table[0];
- insns = (CGEN_INSN *) cd->insn_table.init_entries;
- for (i = 0; i < MAX_INSNS; ++i)
- {
- insns[i].opcode = &oc[i];
- xc16x_cgen_build_insn_regex (& insns[i]);
- }
-
- cd->sizeof_fields = sizeof (CGEN_FIELDS);
- cd->set_fields_bitsize = set_fields_bitsize;
-
- cd->asm_hash_p = asm_hash_insn_p;
- cd->asm_hash = asm_hash_insn;
- cd->asm_hash_size = CGEN_ASM_HASH_SIZE;
-
- cd->dis_hash_p = dis_hash_insn_p;
- cd->dis_hash = dis_hash_insn;
- cd->dis_hash_size = CGEN_DIS_HASH_SIZE;
-}
+++ /dev/null
-/* DO NOT EDIT! -*- buffer-read-only: t -*- vi:set ro: */
-/* Instruction opcode header for xc16x.
-
-THIS FILE IS MACHINE GENERATED WITH CGEN.
-
-Copyright (C) 1996-2022 Free Software Foundation, Inc.
-
-This file is part of the GNU Binutils and/or GDB, the GNU debugger.
-
- This file is free software; you can redistribute it and/or modify
- it under the terms of the GNU General Public License as published by
- the Free Software Foundation; either version 3, or (at your option)
- any later version.
-
- It is distributed in the hope that it will be useful, but WITHOUT
- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
- License for more details.
-
- You should have received a copy of the GNU General Public License along
- with this program; if not, write to the Free Software Foundation, Inc.,
- 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.
-
-*/
-
-#ifndef XC16X_OPC_H
-#define XC16X_OPC_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/* -- opc.h */
-
-#define CGEN_DIS_HASH_SIZE 8
-#define CGEN_DIS_HASH(buf,value) (((* (unsigned char*) (buf)) >> 3) % CGEN_DIS_HASH_SIZE)
-
-/* -- */
-/* Enum declaration for xc16x instruction types. */
-typedef enum cgen_insn_type {
- XC16X_INSN_INVALID, XC16X_INSN_ADDRPOF, XC16X_INSN_SUBRPOF, XC16X_INSN_ADDBRPOF
- , XC16X_INSN_SUBBRPOF, XC16X_INSN_ADDRPAG, XC16X_INSN_SUBRPAG, XC16X_INSN_ADDBRPAG
- , XC16X_INSN_SUBBRPAG, XC16X_INSN_ADDCRPOF, XC16X_INSN_SUBCRPOF, XC16X_INSN_ADDCBRPOF
- , XC16X_INSN_SUBCBRPOF, XC16X_INSN_ADDCRPAG, XC16X_INSN_SUBCRPAG, XC16X_INSN_ADDCBRPAG
- , XC16X_INSN_SUBCBRPAG, XC16X_INSN_ADDRPOFR, XC16X_INSN_SUBRPOFR, XC16X_INSN_ADDBRPOFR
- , XC16X_INSN_SUBBRPOFR, XC16X_INSN_ADDCRPOFR, XC16X_INSN_SUBCRPOFR, XC16X_INSN_ADDCBRPOFR
- , XC16X_INSN_SUBCBRPOFR, XC16X_INSN_ADDRHPOF, XC16X_INSN_SUBRHPOF, XC16X_INSN_ADDBRHPOF
- , XC16X_INSN_SUBBRHPOF, XC16X_INSN_ADDRHPOF3, XC16X_INSN_SUBRHPOF3, XC16X_INSN_ADDBRHPAG3
- , XC16X_INSN_SUBBRHPAG3, XC16X_INSN_ADDRHPAG3, XC16X_INSN_SUBRHPAG3, XC16X_INSN_ADDBRHPOF3
- , XC16X_INSN_SUBBRHPOF3, XC16X_INSN_ADDRBHPOF, XC16X_INSN_SUBRBHPOF, XC16X_INSN_ADDBRHPAG
- , XC16X_INSN_SUBBRHPAG, XC16X_INSN_ADDCRHPOF, XC16X_INSN_SUBCRHPOF, XC16X_INSN_ADDCBRHPOF
- , XC16X_INSN_SUBCBRHPOF, XC16X_INSN_ADDCRHPOF3, XC16X_INSN_SUBCRHPOF3, XC16X_INSN_ADDCBRHPAG3
- , XC16X_INSN_SUBCBRHPAG3, XC16X_INSN_ADDCRHPAG3, XC16X_INSN_SUBCRHPAG3, XC16X_INSN_ADDCBRHPOF3
- , XC16X_INSN_SUBCBRHPOF3, XC16X_INSN_ADDCRBHPOF, XC16X_INSN_SUBCRBHPOF, XC16X_INSN_ADDCBRHPAG
- , XC16X_INSN_SUBCBRHPAG, XC16X_INSN_ADDRI, XC16X_INSN_SUBRI, XC16X_INSN_ADDBRI
- , XC16X_INSN_SUBBRI, XC16X_INSN_ADDRIM, XC16X_INSN_SUBRIM, XC16X_INSN_ADDBRIM
- , XC16X_INSN_SUBBRIM, XC16X_INSN_ADDCRI, XC16X_INSN_SUBCRI, XC16X_INSN_ADDCBRI
- , XC16X_INSN_SUBCBRI, XC16X_INSN_ADDCRIM, XC16X_INSN_SUBCRIM, XC16X_INSN_ADDCBRIM
- , XC16X_INSN_SUBCBRIM, XC16X_INSN_ADDR, XC16X_INSN_SUBR, XC16X_INSN_ADDBR
- , XC16X_INSN_SUBBR, XC16X_INSN_ADD2, XC16X_INSN_SUB2, XC16X_INSN_ADDB2
- , XC16X_INSN_SUBB2, XC16X_INSN_ADD2I, XC16X_INSN_SUB2I, XC16X_INSN_ADDB2I
- , XC16X_INSN_SUBB2I, XC16X_INSN_ADDCR, XC16X_INSN_SUBCR, XC16X_INSN_ADDBCR
- , XC16X_INSN_SUBBCR, XC16X_INSN_ADDCR2, XC16X_INSN_SUBCR2, XC16X_INSN_ADDBCR2
- , XC16X_INSN_SUBBCR2, XC16X_INSN_ADDCR2I, XC16X_INSN_SUBCR2I, XC16X_INSN_ADDBCR2I
- , XC16X_INSN_SUBBCR2I, XC16X_INSN_ADDRM2, XC16X_INSN_ADDRM3, XC16X_INSN_ADDRM
- , XC16X_INSN_ADDRM1, XC16X_INSN_SUBRM3, XC16X_INSN_SUBRM2, XC16X_INSN_SUBRM1
- , XC16X_INSN_SUBRM, XC16X_INSN_ADDBRM2, XC16X_INSN_ADDBRM3, XC16X_INSN_ADDBRM
- , XC16X_INSN_ADDBRM1, XC16X_INSN_SUBBRM3, XC16X_INSN_SUBBRM2, XC16X_INSN_SUBBRM1
- , XC16X_INSN_SUBBRM, XC16X_INSN_ADDCRM2, XC16X_INSN_ADDCRM3, XC16X_INSN_ADDCRM
- , XC16X_INSN_ADDCRM1, XC16X_INSN_SUBCRM3, XC16X_INSN_SUBCRM2, XC16X_INSN_SUBCRM1
- , XC16X_INSN_SUBCRM, XC16X_INSN_ADDCBRM2, XC16X_INSN_ADDCBRM3, XC16X_INSN_ADDCBRM
- , XC16X_INSN_ADDCBRM1, XC16X_INSN_SUBCBRM3, XC16X_INSN_SUBCBRM2, XC16X_INSN_SUBCBRM1
- , XC16X_INSN_SUBCBRM, XC16X_INSN_MULS, XC16X_INSN_MULU, XC16X_INSN_DIV
- , XC16X_INSN_DIVL, XC16X_INSN_DIVLU, XC16X_INSN_DIVU, XC16X_INSN_CPL
- , XC16X_INSN_CPLB, XC16X_INSN_NEG, XC16X_INSN_NEGB, XC16X_INSN_ANDR
- , XC16X_INSN_ORR, XC16X_INSN_XORR, XC16X_INSN_ANDBR, XC16X_INSN_ORBR
- , XC16X_INSN_XORBR, XC16X_INSN_ANDRI, XC16X_INSN_ORRI, XC16X_INSN_XORRI
- , XC16X_INSN_ANDBRI, XC16X_INSN_ORBRI, XC16X_INSN_XORBRI, XC16X_INSN_ANDRIM
- , XC16X_INSN_ORRIM, XC16X_INSN_XORRIM, XC16X_INSN_ANDBRIM, XC16X_INSN_ORBRIM
- , XC16X_INSN_XORBRIM, XC16X_INSN_AND2, XC16X_INSN_OR2, XC16X_INSN_XOR2
- , XC16X_INSN_ANDB2, XC16X_INSN_ORB2, XC16X_INSN_XORB2, XC16X_INSN_AND2I
- , XC16X_INSN_OR2I, XC16X_INSN_XOR2I, XC16X_INSN_ANDB2I, XC16X_INSN_ORB2I
- , XC16X_INSN_XORB2I, XC16X_INSN_ANDPOFR, XC16X_INSN_ORPOFR, XC16X_INSN_XORPOFR
- , XC16X_INSN_ANDBPOFR, XC16X_INSN_ORBPOFR, XC16X_INSN_XORBPOFR, XC16X_INSN_ANDRPOFR
- , XC16X_INSN_ORRPOFR, XC16X_INSN_XORRPOFR, XC16X_INSN_ANDBRPOFR, XC16X_INSN_ORBRPOFR
- , XC16X_INSN_XORBRPOFR, XC16X_INSN_ANDRM2, XC16X_INSN_ANDRM3, XC16X_INSN_ANDRM
- , XC16X_INSN_ANDRM1, XC16X_INSN_ORRM3, XC16X_INSN_ORRM2, XC16X_INSN_ORRM1
- , XC16X_INSN_ORRM, XC16X_INSN_XORRM3, XC16X_INSN_XORRM2, XC16X_INSN_XORRM1
- , XC16X_INSN_XORRM, XC16X_INSN_ANDBRM2, XC16X_INSN_ANDBRM3, XC16X_INSN_ANDBRM
- , XC16X_INSN_ANDBRM1, XC16X_INSN_ORBRM3, XC16X_INSN_ORBRM2, XC16X_INSN_ORBRM1
- , XC16X_INSN_ORBRM, XC16X_INSN_XORBRM3, XC16X_INSN_XORBRM2, XC16X_INSN_XORBRM1
- , XC16X_INSN_XORBRM, XC16X_INSN_MOVR, XC16X_INSN_MOVRB, XC16X_INSN_MOVRI
- , XC16X_INSN_MOVBRI, XC16X_INSN_MOVI, XC16X_INSN_MOVBI, XC16X_INSN_MOVR2
- , XC16X_INSN_MOVBR2, XC16X_INSN_MOVRI2, XC16X_INSN_MOVBRI2, XC16X_INSN_MOVRI3
- , XC16X_INSN_MOVBRI3, XC16X_INSN_MOV2I, XC16X_INSN_MOVB2I, XC16X_INSN_MOV6I
- , XC16X_INSN_MOVB6I, XC16X_INSN_MOV7I, XC16X_INSN_MOVB7I, XC16X_INSN_MOV8I
- , XC16X_INSN_MOVB8I, XC16X_INSN_MOV9I, XC16X_INSN_MOVB9I, XC16X_INSN_MOV10I
- , XC16X_INSN_MOVB10I, XC16X_INSN_MOVRI11, XC16X_INSN_MOVBRI11, XC16X_INSN_MOVRI12
- , XC16X_INSN_MOVBRI12, XC16X_INSN_MOVEHM5, XC16X_INSN_MOVEHM6, XC16X_INSN_MOVEHM7
- , XC16X_INSN_MOVEHM8, XC16X_INSN_MOVEHM9, XC16X_INSN_MOVEHM10, XC16X_INSN_MOVRMP
- , XC16X_INSN_MOVRMP1, XC16X_INSN_MOVRMP2, XC16X_INSN_MOVRMP3, XC16X_INSN_MOVRMP4
- , XC16X_INSN_MOVRMP5, XC16X_INSN_MOVEHM1, XC16X_INSN_MOVEHM2, XC16X_INSN_MOVEHM3
- , XC16X_INSN_MOVEHM4, XC16X_INSN_MVE12, XC16X_INSN_MVE13, XC16X_INSN_MOVER12
- , XC16X_INSN_MVR13, XC16X_INSN_MVER12, XC16X_INSN_MVER13, XC16X_INSN_MOVR12
- , XC16X_INSN_MOVR13, XC16X_INSN_MOVBSRR, XC16X_INSN_MOVBZRR, XC16X_INSN_MOVBSRPOFM
- , XC16X_INSN_MOVBSPOFMR, XC16X_INSN_MOVBZRPOFM, XC16X_INSN_MOVBZPOFMR, XC16X_INSN_MOVEBS14
- , XC16X_INSN_MOVEBS15, XC16X_INSN_MOVERBS14, XC16X_INSN_MOVRBS15, XC16X_INSN_MOVEBZ14
- , XC16X_INSN_MOVEBZ15, XC16X_INSN_MOVERBZ14, XC16X_INSN_MOVRBZ15, XC16X_INSN_MOVRBS
- , XC16X_INSN_MOVRBZ, XC16X_INSN_JMPA0, XC16X_INSN_JMPA1, XC16X_INSN_JMPA_
- , XC16X_INSN_JMPI, XC16X_INSN_JMPR_NENZ, XC16X_INSN_JMPR_SGT, XC16X_INSN_JMPR_Z
- , XC16X_INSN_JMPR_V, XC16X_INSN_JMPR_NV, XC16X_INSN_JMPR_N, XC16X_INSN_JMPR_NN
- , XC16X_INSN_JMPR_C, XC16X_INSN_JMPR_NC, XC16X_INSN_JMPR_EQ, XC16X_INSN_JMPR_NE
- , XC16X_INSN_JMPR_ULT, XC16X_INSN_JMPR_ULE, XC16X_INSN_JMPR_UGE, XC16X_INSN_JMPR_UGT
- , XC16X_INSN_JMPR_SLE, XC16X_INSN_JMPR_SGE, XC16X_INSN_JMPR_NET, XC16X_INSN_JMPR_UC
- , XC16X_INSN_JMPR_SLT, XC16X_INSN_JMPSEG, XC16X_INSN_JMPS, XC16X_INSN_JB
- , XC16X_INSN_JBC, XC16X_INSN_JNB, XC16X_INSN_JNBS, XC16X_INSN_CALLA0
- , XC16X_INSN_CALLA1, XC16X_INSN_CALLA_, XC16X_INSN_CALLI, XC16X_INSN_CALLR
- , XC16X_INSN_CALLSEG, XC16X_INSN_CALLS, XC16X_INSN_PCALL, XC16X_INSN_TRAP
- , XC16X_INSN_RET, XC16X_INSN_RETS, XC16X_INSN_RETP, XC16X_INSN_RETI
- , XC16X_INSN_POP, XC16X_INSN_PUSH, XC16X_INSN_SCXTI, XC16X_INSN_SCXTRPOFM
- , XC16X_INSN_SCXTMG, XC16X_INSN_SCXTM, XC16X_INSN_NOP, XC16X_INSN_SRSTM
- , XC16X_INSN_IDLEM, XC16X_INSN_PWRDNM, XC16X_INSN_DISWDTM, XC16X_INSN_ENWDTM
- , XC16X_INSN_EINITM, XC16X_INSN_SRVWDTM, XC16X_INSN_SBRK, XC16X_INSN_ATOMIC
- , XC16X_INSN_EXTR, XC16X_INSN_EXTP, XC16X_INSN_EXTP1, XC16X_INSN_EXTPG1
- , XC16X_INSN_EXTPR, XC16X_INSN_EXTPR1, XC16X_INSN_EXTS, XC16X_INSN_EXTS1
- , XC16X_INSN_EXTSR, XC16X_INSN_EXTSR1, XC16X_INSN_PRIOR, XC16X_INSN_BCLR18
- , XC16X_INSN_BCLR0, XC16X_INSN_BCLR1, XC16X_INSN_BCLR2, XC16X_INSN_BCLR3
- , XC16X_INSN_BCLR4, XC16X_INSN_BCLR5, XC16X_INSN_BCLR6, XC16X_INSN_BCLR7
- , XC16X_INSN_BCLR8, XC16X_INSN_BCLR9, XC16X_INSN_BCLR10, XC16X_INSN_BCLR11
- , XC16X_INSN_BCLR12, XC16X_INSN_BCLR13, XC16X_INSN_BCLR14, XC16X_INSN_BCLR15
- , XC16X_INSN_BSET19, XC16X_INSN_BSET0, XC16X_INSN_BSET1, XC16X_INSN_BSET2
- , XC16X_INSN_BSET3, XC16X_INSN_BSET4, XC16X_INSN_BSET5, XC16X_INSN_BSET6
- , XC16X_INSN_BSET7, XC16X_INSN_BSET8, XC16X_INSN_BSET9, XC16X_INSN_BSET10
- , XC16X_INSN_BSET11, XC16X_INSN_BSET12, XC16X_INSN_BSET13, XC16X_INSN_BSET14
- , XC16X_INSN_BSET15, XC16X_INSN_BMOV, XC16X_INSN_BMOVN, XC16X_INSN_BAND
- , XC16X_INSN_BOR, XC16X_INSN_BXOR, XC16X_INSN_BCMP, XC16X_INSN_BFLDL
- , XC16X_INSN_BFLDH, XC16X_INSN_CMPR, XC16X_INSN_CMPBR, XC16X_INSN_CMPRI
- , XC16X_INSN_CMPBRI, XC16X_INSN_CMPI, XC16X_INSN_CMPBI, XC16X_INSN_CMPR2
- , XC16X_INSN_CMPBR2, XC16X_INSN_CMP2I, XC16X_INSN_CMPB2I, XC16X_INSN_CMP04
- , XC16X_INSN_CMPB4, XC16X_INSN_CMP004, XC16X_INSN_CMP0004, XC16X_INSN_CMPB04
- , XC16X_INSN_CMPB004, XC16X_INSN_CMPD1RI, XC16X_INSN_CMPD2RI, XC16X_INSN_CMPI1RI
- , XC16X_INSN_CMPI2RI, XC16X_INSN_CMPD1RIM, XC16X_INSN_CMPD2RIM, XC16X_INSN_CMPI1RIM
- , XC16X_INSN_CMPI2RIM, XC16X_INSN_CMPD1RP, XC16X_INSN_CMPD2RP, XC16X_INSN_CMPI1RP
- , XC16X_INSN_CMPI2RP, XC16X_INSN_CMPD1RM, XC16X_INSN_CMPD2RM, XC16X_INSN_CMPI1RM
- , XC16X_INSN_CMPI2RM, XC16X_INSN_CMPD1RMI, XC16X_INSN_CMPD2RMI, XC16X_INSN_CMPI1RMI
- , XC16X_INSN_CMPI2RMI, XC16X_INSN_SHLR, XC16X_INSN_SHRR, XC16X_INSN_ROLR
- , XC16X_INSN_RORR, XC16X_INSN_ASHRR, XC16X_INSN_SHLRI, XC16X_INSN_SHRRI
- , XC16X_INSN_ROLRI, XC16X_INSN_RORRI, XC16X_INSN_ASHRRI
-} CGEN_INSN_TYPE;
-
-/* Index of `invalid' insn place holder. */
-#define CGEN_INSN_INVALID XC16X_INSN_INVALID
-
-/* Total number of insns in table. */
-#define MAX_INSNS ((int) XC16X_INSN_ASHRRI + 1)
-
-/* This struct records data prior to insertion or after extraction. */
-struct cgen_fields
-{
- int length;
- long f_nil;
- long f_anyof;
- long f_op1;
- long f_op2;
- long f_condcode;
- long f_icondcode;
- long f_rcond;
- long f_qcond;
- long f_extccode;
- long f_r0;
- long f_r1;
- long f_r2;
- long f_r3;
- long f_r4;
- long f_uimm2;
- long f_uimm3;
- long f_uimm4;
- long f_uimm7;
- long f_uimm8;
- long f_uimm16;
- long f_memory;
- long f_memgr8;
- long f_rel8;
- long f_relhi8;
- long f_reg8;
- long f_regmem8;
- long f_regoff8;
- long f_reghi8;
- long f_regb8;
- long f_seg8;
- long f_segnum8;
- long f_mask8;
- long f_pagenum;
- long f_datahi8;
- long f_data8;
- long f_offset16;
- long f_op_bit1;
- long f_op_bit2;
- long f_op_bit4;
- long f_op_bit3;
- long f_op_2bit;
- long f_op_bitone;
- long f_op_onebit;
- long f_op_1bit;
- long f_op_lbit4;
- long f_op_lbit2;
- long f_op_bit8;
- long f_op_bit16;
- long f_qbit;
- long f_qlobit;
- long f_qhibit;
- long f_qlobit2;
- long f_pof;
-};
-
-#define CGEN_INIT_PARSE(od) \
-{\
-}
-#define CGEN_INIT_INSERT(od) \
-{\
-}
-#define CGEN_INIT_EXTRACT(od) \
-{\
-}
-#define CGEN_INIT_PRINT(od) \
-{\
-}
-
-
- #ifdef __cplusplus
- }
- #endif
-
-#endif /* XC16X_OPC_H */
projects / thirdparty / binutils-gdb.git / commitdiff
