#include "d10v_sim.h"
#include "simops.h"
-#include "sys/syscall.h"
+#include "targ-vals.h"
extern char *strrchr ();
OP_R0,
OP_R1,
OP_R2,
- OP_R0R1
};
-void
-move_to_cr (int cr, reg_t val)
+enum {
+ PSW_MASK = (PSW_SM_BIT
+ | PSW_EA_BIT
+ | PSW_DB_BIT
+ | PSW_DM_BIT
+ | PSW_IE_BIT
+ | PSW_RP_BIT
+ | PSW_MD_BIT
+ | PSW_FX_BIT
+ | PSW_ST_BIT
+ | PSW_F0_BIT
+ | PSW_F1_BIT
+ | PSW_C_BIT),
+};
+
+reg_t
+move_to_cr (int cr, reg_t mask, reg_t val)
{
+ /* A MASK bit is set when the corresponding bit in the CR should
+ be left alone */
+ /* This assumes that (VAL & MASK) == 0 */
switch (cr)
{
case PSW_CR:
- State.sp[State.SM] = State.regs[SP_IDX]; /* save old SP */
- State.SM = (val & PSW_SM_BIT) != 0;
- State.EA = (val & PSW_EA_BIT) != 0;
- State.DB = (val & PSW_DB_BIT) != 0;
- State.DM = (val & PSW_DM_BIT) != 0;
- State.IE = (val & PSW_IE_BIT) != 0;
- State.RP = (val & PSW_RP_BIT) != 0;
- State.MD = (val & PSW_MD_BIT) != 0;
- State.FX = (val & PSW_FX_BIT) != 0;
- State.ST = (val & PSW_ST_BIT) != 0;
- State.F0 = (val & PSW_F0_BIT) != 0;
- State.F1 = (val & PSW_F1_BIT) != 0;
- State.C = (val & PSW_C_BIT) != 0;
- State.regs[SP_IDX] = State.sp[State.SM]; /* restore new SP */
- if (State.ST && !State.FX)
+ val &= PSW_MASK;
+ if ((mask & PSW_SM_BIT) == 0)
{
- (*d10v_callback->printf_filtered)
- (d10v_callback,
- "ERROR at PC 0x%x: ST can only be set when FX is set.\n",
- PC<<2);
- State.exception = SIGILL;
+ int new_sm = (val & PSW_SM_BIT) != 0;
+ SET_HELD_SP (PSW_SM, GPR (SP_IDX)); /* save old SP */
+ if (PSW_SM != new_sm)
+ SET_GPR (SP_IDX, HELD_SP (new_sm)); /* restore new SP */
}
- State.cregs[cr] = (val & ~0x4032);
+ if ((mask & (PSW_ST_BIT | PSW_FX_BIT)) == 0)
+ {
+ if (val & PSW_ST_BIT && !(val & PSW_FX_BIT))
+ {
+ (*d10v_callback->printf_filtered)
+ (d10v_callback,
+ "ERROR at PC 0x%x: ST can only be set when FX is set.\n",
+ PC<<2);
+ State.exception = SIGILL;
+ }
+ }
+ /* keep an up-to-date psw around for tracing */
+ State.trace.psw = (State.trace.psw & mask) | val;
break;
case BPSW_CR:
case DPSW_CR:
- State.cregs[cr] = (val & ~0x4032);
+ val &= PSW_MASK;
break;
case MOD_S_CR:
case MOD_E_CR:
- State.cregs[cr] = (val & ~0x1);
+ val &= ~1;
break;
default:
- State.cregs[cr] = val;
- break;
- }
-}
-
-reg_t
-move_from_cr (int cr)
-{
- reg_t val = 0;
- switch (cr)
- {
- case PSW_CR:
- if (State.SM) val |= PSW_SM_BIT;
- if (State.EA) val |= PSW_EA_BIT;
- if (State.DB) val |= PSW_DB_BIT;
- if (State.DM) val |= PSW_DM_BIT;
- if (State.IE) val |= PSW_IE_BIT;
- if (State.RP) val |= PSW_RP_BIT;
- if (State.MD) val |= PSW_MD_BIT;
- if (State.FX) val |= PSW_FX_BIT;
- if (State.ST) val |= PSW_ST_BIT;
- if (State.F0) val |= PSW_F0_BIT;
- if (State.F1) val |= PSW_F1_BIT;
- if (State.C) val |= PSW_C_BIT;
- break;
- default:
- val = State.cregs[cr];
break;
}
+ /* only issue an update if the register is being changed */
+ if ((State.cregs[cr] & ~mask) != val)
+ SLOT_PEND_MASK (State.cregs[cr], mask, val);
return val;
}
-
#ifdef DEBUG
static void trace_input_func PARAMS ((char *name,
enum op_types in1,
#define trace_input(name, in1, in2, in3) do { if (d10v_debug) trace_input_func (name, in1, in2, in3); } while (0)
-static void trace_output_func PARAMS ((enum op_types result));
-
-#define trace_output(result) do { if (d10v_debug) trace_output_func (result); } while (0)
-
#ifndef SIZE_INSTRUCTION
#define SIZE_INSTRUCTION 8
#endif
case OP_R0:
case OP_R1:
case OP_R2:
- case OP_R0R1:
break;
case OP_REG:
case OP_POSTINC:
case OP_PREDEC:
(*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.4x", SIZE_VALUES-6, "",
- (uint16)State.regs[OP[i]]);
+ (uint16) GPR (OP[i]));
break;
case OP_DREG:
- tmp = (long)((((uint32) State.regs[OP[i]]) << 16) | ((uint32) State.regs[OP[i]+1]));
+ tmp = (long)((((uint32) GPR (OP[i])) << 16) | ((uint32) GPR (OP[i] + 1)));
(*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.8lx", SIZE_VALUES-10, "", tmp);
break;
case OP_CR:
case OP_CR_REVERSE:
(*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.4x", SIZE_VALUES-6, "",
- (uint16)State.cregs[OP[i]]);
+ (uint16) CREG (OP[i]));
break;
case OP_ACCUM:
case OP_ACCUM_REVERSE:
(*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.2x%.8lx", SIZE_VALUES-12, "",
- ((int)(State.a[OP[i]] >> 32) & 0xff),
- ((unsigned long)State.a[OP[i]]) & 0xffffffff);
+ ((int)(ACC (OP[i]) >> 32) & 0xff),
+ ((unsigned long) ACC (OP[i])) & 0xffffffff);
break;
case OP_CONSTANT16:
case OP_FLAG:
if (OP[i] == 0)
(*d10v_callback->printf_filtered) (d10v_callback, "%*sF0 = %d", SIZE_VALUES-6, "",
- State.F0 != 0);
+ PSW_F0 != 0);
else if (OP[i] == 1)
(*d10v_callback->printf_filtered) (d10v_callback, "%*sF1 = %d", SIZE_VALUES-6, "",
- State.F1 != 0);
+ PSW_F1 != 0);
else
(*d10v_callback->printf_filtered) (d10v_callback, "%*sC = %d", SIZE_VALUES-5, "",
- State.C != 0);
+ PSW_C != 0);
break;
(*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.4x", SIZE_VALUES-6, "",
(uint16)OP[i]);
(*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.4x", SIZE_VALUES-6, "",
- (uint16)State.regs[OP[++i]]);
+ (uint16)GPR (OP[i + 1]));
+ i++;
break;
case OP_R0:
(*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.4x", SIZE_VALUES-6, "",
- (uint16)State.regs[0]);
+ (uint16) GPR (0));
break;
case OP_R1:
(*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.4x", SIZE_VALUES-6, "",
- (uint16)State.regs[1]);
+ (uint16) GPR (1));
break;
case OP_R2:
(*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.4x", SIZE_VALUES-6, "",
- (uint16)State.regs[2]);
+ (uint16) GPR (2));
break;
- case OP_R0R1:
- (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.4x", SIZE_VALUES-6, "",
- (uint16)State.regs[0]);
- (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.4x", SIZE_VALUES-6, "",
- (uint16)State.regs[1]);
- i++;
- break;
}
}
}
}
static void
-trace_output_func (result)
- enum op_types result;
+do_trace_output_flush (void)
{
- if ((d10v_debug & (DEBUG_TRACE | DEBUG_VALUES)) == (DEBUG_TRACE | DEBUG_VALUES))
- {
- long tmp;
-
- switch (result)
- {
- default:
- putchar ('\n');
- break;
-
- case OP_REG:
- case OP_REG_OUTPUT:
- (*d10v_callback->printf_filtered) (d10v_callback, " :: %*s0x%.4x F0=%d F1=%d C=%d\n", SIZE_VALUES-6, "",
- (uint16)State.regs[OP[0]],
- State.F0 != 0, State.F1 != 0, State.C != 0);
- break;
+ (*d10v_callback->flush_stdout) (d10v_callback);
+}
- case OP_DREG:
- case OP_DREG_OUTPUT:
- tmp = (long)((((uint32) State.regs[OP[0]]) << 16) | ((uint32) State.regs[OP[0]+1]));
- (*d10v_callback->printf_filtered) (d10v_callback, " :: %*s0x%.8lx F0=%d F1=%d C=%d\n", SIZE_VALUES-10, "", tmp,
- State.F0 != 0, State.F1 != 0, State.C != 0);
- break;
+static void
+do_trace_output_finish (void)
+{
+ (*d10v_callback->printf_filtered) (d10v_callback,
+ " F0=%d F1=%d C=%d\n",
+ (State.trace.psw & PSW_F0_BIT) != 0,
+ (State.trace.psw & PSW_F1_BIT) != 0,
+ (State.trace.psw & PSW_C_BIT) != 0);
+ (*d10v_callback->flush_stdout) (d10v_callback);
+}
- case OP_CR:
- case OP_CR_OUTPUT:
- (*d10v_callback->printf_filtered) (d10v_callback, " :: %*s0x%.4x F0=%d F1=%d C=%d\n", SIZE_VALUES-6, "",
- (uint16)State.cregs[OP[0]],
- State.F0 != 0, State.F1 != 0, State.C != 0);
- break;
+static void
+trace_output_40 (uint64 val)
+{
+ if ((d10v_debug & (DEBUG_TRACE | DEBUG_VALUES)) == (DEBUG_TRACE | DEBUG_VALUES))
+ {
+ (*d10v_callback->printf_filtered) (d10v_callback,
+ " :: %*s0x%.2x%.8lx",
+ SIZE_VALUES - 12,
+ "",
+ ((int)(val >> 32) & 0xff),
+ ((unsigned long) val) & 0xffffffff);
+ do_trace_output_finish ();
+ }
+}
- case OP_CR_REVERSE:
- (*d10v_callback->printf_filtered) (d10v_callback, " :: %*s0x%.4x F0=%d F1=%d C=%d\n", SIZE_VALUES-6, "",
- (uint16)State.cregs[OP[1]],
- State.F0 != 0, State.F1 != 0, State.C != 0);
- break;
+static void
+trace_output_32 (uint32 val)
+{
+ if ((d10v_debug & (DEBUG_TRACE | DEBUG_VALUES)) == (DEBUG_TRACE | DEBUG_VALUES))
+ {
+ (*d10v_callback->printf_filtered) (d10v_callback,
+ " :: %*s0x%.8x",
+ SIZE_VALUES - 10,
+ "",
+ (int) val);
+ do_trace_output_finish ();
+ }
+}
- case OP_ACCUM:
- case OP_ACCUM_OUTPUT:
- (*d10v_callback->printf_filtered) (d10v_callback, " :: %*s0x%.2x%.8lx F0=%d F1=%d C=%d\n", SIZE_VALUES-12, "",
- ((int)(State.a[OP[0]] >> 32) & 0xff),
- ((unsigned long)State.a[OP[0]]) & 0xffffffff,
- State.F0 != 0, State.F1 != 0, State.C != 0);
- break;
+static void
+trace_output_16 (uint16 val)
+{
+ if ((d10v_debug & (DEBUG_TRACE | DEBUG_VALUES)) == (DEBUG_TRACE | DEBUG_VALUES))
+ {
+ (*d10v_callback->printf_filtered) (d10v_callback,
+ " :: %*s0x%.4x",
+ SIZE_VALUES - 6,
+ "",
+ (int) val);
+ do_trace_output_finish ();
+ }
+}
- case OP_ACCUM_REVERSE:
- (*d10v_callback->printf_filtered) (d10v_callback, " :: %*s0x%.2x%.8lx F0=%d F1=%d C=%d\n", SIZE_VALUES-12, "",
- ((int)(State.a[OP[1]] >> 32) & 0xff),
- ((unsigned long)State.a[OP[1]]) & 0xffffffff,
- State.F0 != 0, State.F1 != 0, State.C != 0);
- break;
+static void
+trace_output_void ()
+{
+ if ((d10v_debug & (DEBUG_TRACE | DEBUG_VALUES)) == (DEBUG_TRACE | DEBUG_VALUES))
+ {
+ (*d10v_callback->printf_filtered) (d10v_callback, "\n");
+ do_trace_output_flush ();
+ }
+}
- case OP_FLAG:
- case OP_FLAG_OUTPUT:
- (*d10v_callback->printf_filtered) (d10v_callback, " :: %*s F0=%d F1=%d C=%d\n", SIZE_VALUES, "",
- State.F0 != 0, State.F1 != 0, State.C != 0);
- break;
+static void
+trace_output_flag ()
+{
+ if ((d10v_debug & (DEBUG_TRACE | DEBUG_VALUES)) == (DEBUG_TRACE | DEBUG_VALUES))
+ {
+ (*d10v_callback->printf_filtered) (d10v_callback,
+ " :: %*s",
+ SIZE_VALUES,
+ "");
+ do_trace_output_finish ();
+ }
+}
- case OP_R0:
- (*d10v_callback->printf_filtered) (d10v_callback, " :: %*s0x%.4x F0=%d F1=%d C=%d\n", SIZE_VALUES-6, "",
- (uint16)State.regs[0],
- State.F0 != 0, State.F1 != 0, State.C != 0);
- break;
- case OP_R0R1:
- (*d10v_callback->printf_filtered) (d10v_callback, " :: %*s0x%.4x%.4x F0=%d F1=%d C=%d\n", SIZE_VALUES-10, "",
- (uint16)State.regs[0], (uint16)State.regs[1],
- State.F0 != 0, State.F1 != 0, State.C != 0);
- break;
- }
- }
- (*d10v_callback->flush_stdout) (d10v_callback);
-}
#else
#define trace_input(NAME, IN1, IN2, IN3)
void
OP_4607 ()
{
+ int16 tmp;
trace_input ("abs", OP_REG, OP_VOID, OP_VOID);
- State.F1 = State.F0;
- if ((int16)(State.regs[OP[0]]) < 0)
+ SET_PSW_F1 (PSW_F0);
+ tmp = GPR(OP[0]);
+ if (tmp < 0)
{
- State.regs[OP[0]] = -(int16)(State.regs[OP[0]]);
- State.F0 = 1;
+ tmp = - tmp;
+ SET_PSW_F0 (1);
}
else
- State.F0 = 0;
- trace_output (OP_REG);
+ SET_PSW_F0 (0);
+ SET_GPR (OP[0], tmp);
+ trace_output_16 (tmp);
}
/* abs */
OP_5607 ()
{
int64 tmp;
-
trace_input ("abs", OP_ACCUM, OP_VOID, OP_VOID);
- State.F1 = State.F0;
- State.a[OP[0]] = SEXT40(State.a[OP[0]]);
+ SET_PSW_F1 (PSW_F0);
- if (State.a[OP[0]] < 0 )
+ tmp = SEXT40 (ACC (OP[0]));
+ if (tmp < 0 )
{
- tmp = -State.a[OP[0]];
- if (State.ST)
+ tmp = - tmp;
+ if (PSW_ST)
{
- if (tmp > MAX32)
- State.a[OP[0]] = MAX32;
- else if (tmp < MIN32)
- State.a[OP[0]] = MIN32;
+ if (tmp > SEXT40(MAX32))
+ tmp = MAX32;
+ else if (tmp < SEXT40(MIN32))
+ tmp = MIN32;
else
- State.a[OP[0]] = tmp & MASK40;
+ tmp = (tmp & MASK40);
}
else
- State.a[OP[0]] = tmp & MASK40;
- State.F0 = 1;
+ tmp = (tmp & MASK40);
+ SET_PSW_F0 (1);
}
else
- State.F0 = 0;
- trace_output (OP_ACCUM);
+ {
+ tmp = (tmp & MASK40);
+ SET_PSW_F0 (0);
+ }
+ SET_ACC (OP[0], tmp);
+ trace_output_40 (tmp);
}
/* add */
void
OP_200 ()
{
- uint16 tmp = State.regs[OP[0]];
+ uint16 a = GPR (OP[0]);
+ uint16 b = GPR (OP[1]);
+ uint16 tmp = (a + b);
trace_input ("add", OP_REG, OP_REG, OP_VOID);
- State.regs[OP[0]] += State.regs[OP[1]];
- if ( tmp > State.regs[OP[0]])
- State.C = 1;
- else
- State.C = 0;
- trace_output (OP_REG);
+ SET_PSW_C (a > tmp);
+ SET_GPR (OP[0], tmp);
+ trace_output_16 (tmp);
}
/* add */
OP_1201 ()
{
int64 tmp;
- tmp = SEXT40(State.a[OP[0]]) + (SEXT16 (State.regs[OP[1]]) << 16 | State.regs[OP[1]+1]);
+ tmp = SEXT40(ACC (OP[0])) + (SEXT16 (GPR (OP[1])) << 16 | GPR (OP[1] + 1));
trace_input ("add", OP_ACCUM, OP_REG, OP_VOID);
- if (State.ST)
+ if (PSW_ST)
{
if ( tmp > MAX32)
- State.a[OP[0]] = MAX32;
+ tmp = MAX32;
else if ( tmp < MIN32)
- State.a[OP[0]] = MIN32;
+ tmp = MIN32;
else
- State.a[OP[0]] = tmp & MASK40;
+ tmp = (tmp & MASK40);
}
else
- State.a[OP[0]] = tmp & MASK40;
- trace_output (OP_ACCUM);
+ tmp = (tmp & MASK40);
+ SET_ACC (OP[0], tmp);
+ trace_output_40 (tmp);
}
/* add */
OP_1203 ()
{
int64 tmp;
- tmp = SEXT40(State.a[OP[0]]) + SEXT40(State.a[OP[1]]);
+ tmp = SEXT40(ACC (OP[0])) + SEXT40(ACC (OP[1]));
trace_input ("add", OP_ACCUM, OP_ACCUM, OP_VOID);
- if (State.ST)
+ if (PSW_ST)
{
if (tmp > MAX32)
- State.a[OP[0]] = MAX32;
+ tmp = MAX32;
else if ( tmp < MIN32)
- State.a[OP[0]] = MIN32;
+ tmp = MIN32;
else
- State.a[OP[0]] = tmp & MASK40;
+ tmp = (tmp & MASK40);
}
else
- State.a[OP[0]] = tmp & MASK40;
- trace_output (OP_ACCUM);
+ tmp = (tmp & MASK40);
+ SET_ACC (OP[0], tmp);
+ trace_output_40 (tmp);
}
/* add2w */
OP_1200 ()
{
uint32 tmp;
- uint32 a = (State.regs[OP[0]]) << 16 | State.regs[OP[0]+1];
- uint32 b = (State.regs[OP[1]]) << 16 | State.regs[OP[1]+1];
-
+ uint32 a = (GPR (OP[0])) << 16 | GPR (OP[0] + 1);
+ uint32 b = (GPR (OP[1])) << 16 | GPR (OP[1] + 1);
trace_input ("add2w", OP_DREG, OP_DREG, OP_VOID);
tmp = a + b;
- State.C = (tmp < a);
- State.regs[OP[0]] = tmp >> 16;
- State.regs[OP[0]+1] = tmp & 0xFFFF;
- trace_output (OP_DREG);
+ SET_PSW_C (tmp < a);
+ SET_GPR (OP[0] + 0, (tmp >> 16));
+ SET_GPR (OP[0] + 1, (tmp & 0xFFFF));
+ trace_output_32 (tmp);
}
/* add3 */
void
OP_1000000 ()
{
- uint16 tmp = State.regs[OP[1]];
- State.regs[OP[0]] = tmp + OP[2];
-
+ uint16 a = GPR (OP[1]);
+ uint16 b = OP[2];
+ uint16 tmp = (a + b);
trace_input ("add3", OP_REG_OUTPUT, OP_REG, OP_CONSTANT16);
- State.C = (State.regs[OP[0]] < tmp);
- trace_output (OP_REG);
+ SET_PSW_C (tmp < a);
+ SET_GPR (OP[0], tmp);
+ trace_output_16 (tmp);
}
/* addac3 */
OP_17000200 ()
{
int64 tmp;
- tmp = SEXT40(State.a[OP[2]]) + SEXT40 ((State.regs[OP[1]] << 16) | State.regs[OP[1]+1]);
+ tmp = SEXT40(ACC (OP[2])) + SEXT40 ((GPR (OP[1]) << 16) | GPR (OP[1] + 1));
trace_input ("addac3", OP_DREG_OUTPUT, OP_DREG, OP_ACCUM);
- State.regs[OP[0]] = (tmp >> 16) & 0xffff;
- State.regs[OP[0]+1] = tmp & 0xffff;
- trace_output (OP_DREG);
+ SET_GPR (OP[0] + 0, ((tmp >> 16) & 0xffff));
+ SET_GPR (OP[0] + 1, (tmp & 0xffff));
+ trace_output_32 (tmp);
}
/* addac3 */
OP_17000202 ()
{
int64 tmp;
- tmp = SEXT40(State.a[OP[1]]) + SEXT40(State.a[OP[2]]);
+ tmp = SEXT40(ACC (OP[1])) + SEXT40(ACC (OP[2]));
trace_input ("addac3", OP_DREG_OUTPUT, OP_ACCUM, OP_ACCUM);
- State.regs[OP[0]] = (tmp >> 16) & 0xffff;
- State.regs[OP[0]+1] = tmp & 0xffff;
- trace_output (OP_DREG);
+ SET_GPR (OP[0] + 0, (tmp >> 16) & 0xffff);
+ SET_GPR (OP[0] + 1, tmp & 0xffff);
+ trace_output_32 (tmp);
}
/* addac3s */
OP_17001200 ()
{
int64 tmp;
- State.F1 = State.F0;
+ SET_PSW_F1 (PSW_F0);
trace_input ("addac3s", OP_DREG_OUTPUT, OP_DREG, OP_ACCUM);
- tmp = SEXT40(State.a[OP[2]]) + SEXT40 ((State.regs[OP[1]] << 16) | State.regs[OP[1]+1]);
+ tmp = SEXT40 (ACC (OP[2])) + SEXT40 ((GPR (OP[1]) << 16) | GPR (OP[1] + 1));
if ( tmp > MAX32)
{
- State.regs[OP[0]] = 0x7fff;
- State.regs[OP[0]+1] = 0xffff;
- State.F0 = 1;
+ tmp = 0x7fffffff;
+ SET_PSW_F0 (1);
}
else if (tmp < MIN32)
{
- State.regs[OP[0]] = 0x8000;
- State.regs[OP[0]+1] = 0;
- State.F0 = 1;
+ tmp = 0x80000000;
+ SET_PSW_F0 (1);
}
else
{
- State.regs[OP[0]] = (tmp >> 16) & 0xffff;
- State.regs[OP[0]+1] = tmp & 0xffff;
- State.F0 = 0;
+ SET_PSW_F0 (0);
}
- trace_output (OP_DREG);
+ SET_GPR (OP[0] + 0, (tmp >> 16) & 0xffff);
+ SET_GPR (OP[0] + 1, (tmp & 0xffff));
+ trace_output_32 (tmp);
}
/* addac3s */
OP_17001202 ()
{
int64 tmp;
- State.F1 = State.F0;
+ SET_PSW_F1 (PSW_F0);
trace_input ("addac3s", OP_DREG_OUTPUT, OP_ACCUM, OP_ACCUM);
- tmp = SEXT40(State.a[OP[1]]) + SEXT40(State.a[OP[2]]);
+ tmp = SEXT40(ACC (OP[1])) + SEXT40(ACC (OP[2]));
if ( tmp > MAX32)
{
- State.regs[OP[0]] = 0x7fff;
- State.regs[OP[0]+1] = 0xffff;
- State.F0 = 1;
+ tmp = 0x7fffffff;
+ SET_PSW_F0 (1);
}
else if (tmp < MIN32)
{
- State.regs[OP[0]] = 0x8000;
- State.regs[OP[0]+1] = 0;
- State.F0 = 1;
+ tmp = 0x80000000;
+ SET_PSW_F0 (1);
}
else
{
- State.regs[OP[0]] = (tmp >> 16) & 0xffff;
- State.regs[OP[0]+1] = tmp & 0xffff;
- State.F0 = 0;
+ SET_PSW_F0 (0);
}
- trace_output (OP_DREG);
+ SET_GPR (OP[0] + 0, (tmp >> 16) & 0xffff);
+ SET_GPR (OP[0] + 1, (tmp & 0xffff));
+ trace_output_32 (tmp);
}
/* addi */
void
OP_201 ()
{
- uint tmp = State.regs[OP[0]];
+ uint16 a = GPR (OP[0]);
+ uint16 b;
+ uint16 tmp;
if (OP[1] == 0)
OP[1] = 16;
-
+ b = OP[1];
+ tmp = (a + b);
trace_input ("addi", OP_REG, OP_CONSTANT16, OP_VOID);
- State.regs[OP[0]] += OP[1];
- State.C = (State.regs[OP[0]] < tmp);
- trace_output (OP_REG);
+ SET_PSW_C (tmp < a);
+ SET_GPR (OP[0], tmp);
+ trace_output_16 (tmp);
}
/* and */
void
OP_C00 ()
{
+ uint16 tmp = GPR (OP[0]) & GPR (OP[1]);
trace_input ("and", OP_REG, OP_REG, OP_VOID);
- State.regs[OP[0]] &= State.regs[OP[1]];
- trace_output (OP_REG);
+ SET_GPR (OP[0], tmp);
+ trace_output_16 (tmp);
}
/* and3 */
void
OP_6000000 ()
{
+ uint16 tmp = GPR (OP[1]) & OP[2];
trace_input ("and3", OP_REG_OUTPUT, OP_REG, OP_CONSTANT16);
- State.regs[OP[0]] = State.regs[OP[1]] & OP[2];
- trace_output (OP_REG);
+ SET_GPR (OP[0], tmp);
+ trace_output_16 (tmp);
}
/* bclri */
void
OP_C01 ()
{
+ int16 tmp;
trace_input ("bclri", OP_REG, OP_CONSTANT16, OP_VOID);
- State.regs[OP[0]] &= ~(0x8000 >> OP[1]);
- trace_output (OP_REG);
+ tmp = (GPR (OP[0]) &~(0x8000 >> OP[1]));
+ SET_GPR (OP[0], tmp);
+ trace_output_16 (tmp);
}
/* bl.s */
OP_4900 ()
{
trace_input ("bl.s", OP_CONSTANT8, OP_R0, OP_R1);
- State.regs[13] = PC+1;
+ SET_GPR (13, PC + 1);
JMP( PC + SEXT8 (OP[0]));
- trace_output (OP_VOID);
+ trace_output_void ();
}
/* bl.l */
OP_24800000 ()
{
trace_input ("bl.l", OP_CONSTANT16, OP_R0, OP_R1);
- State.regs[13] = PC+1;
+ SET_GPR (13, (PC + 1));
JMP (PC + OP[0]);
- trace_output (OP_VOID);
+ trace_output_void ();
}
/* bnoti */
void
OP_A01 ()
{
+ int16 tmp;
trace_input ("bnoti", OP_REG, OP_CONSTANT16, OP_VOID);
- State.regs[OP[0]] ^= 0x8000 >> OP[1];
- trace_output (OP_REG);
+ tmp = (GPR (OP[0]) ^ (0x8000 >> OP[1]));
+ SET_GPR (OP[0], tmp);
+ trace_output_16 (tmp);
}
/* bra.s */
{
trace_input ("bra.s", OP_CONSTANT8, OP_VOID, OP_VOID);
JMP (PC + SEXT8 (OP[0]));
- trace_output (OP_VOID);
+ trace_output_void ();
}
/* bra.l */
{
trace_input ("bra.l", OP_CONSTANT16, OP_VOID, OP_VOID);
JMP (PC + OP[0]);
- trace_output (OP_VOID);
+ trace_output_void ();
}
/* brf0f.s */
OP_4A00 ()
{
trace_input ("brf0f.s", OP_CONSTANT8, OP_VOID, OP_VOID);
- if (State.F0 == 0)
+ if (!PSW_F0)
JMP (PC + SEXT8 (OP[0]));
- trace_output (OP_FLAG);
+ trace_output_flag ();
}
/* brf0f.l */
OP_25000000 ()
{
trace_input ("brf0f.l", OP_CONSTANT16, OP_VOID, OP_VOID);
- if (State.F0 == 0)
+ if (!PSW_F0)
JMP (PC + OP[0]);
- trace_output (OP_FLAG);
+ trace_output_flag ();
}
/* brf0t.s */
OP_4B00 ()
{
trace_input ("brf0t.s", OP_CONSTANT8, OP_VOID, OP_VOID);
- if (State.F0)
+ if (PSW_F0)
JMP (PC + SEXT8 (OP[0]));
- trace_output (OP_FLAG);
+ trace_output_flag ();
}
/* brf0t.l */
OP_25800000 ()
{
trace_input ("brf0t.l", OP_CONSTANT16, OP_VOID, OP_VOID);
- if (State.F0)
+ if (PSW_F0)
JMP (PC + OP[0]);
- trace_output (OP_FLAG);
+ trace_output_flag ();
}
/* bseti */
void
OP_801 ()
{
+ int16 tmp;
trace_input ("bseti", OP_REG, OP_CONSTANT16, OP_VOID);
- State.regs[OP[0]] |= 0x8000 >> OP[1];
- trace_output (OP_REG);
+ tmp = (GPR (OP[0]) | (0x8000 >> OP[1]));
+ SET_GPR (OP[0], tmp);
+ trace_output_16 (tmp);
}
/* btsti */
OP_E01 ()
{
trace_input ("btsti", OP_REG, OP_CONSTANT16, OP_VOID);
- State.F1 = State.F0;
- State.F0 = (State.regs[OP[0]] & (0x8000 >> OP[1])) ? 1 : 0;
- trace_output (OP_FLAG);
+ SET_PSW_F1 (PSW_F0);
+ SET_PSW_F0 ((GPR (OP[0]) & (0x8000 >> OP[1])) ? 1 : 0);
+ trace_output_flag ();
}
/* clrac */
OP_5601 ()
{
trace_input ("clrac", OP_ACCUM_OUTPUT, OP_VOID, OP_VOID);
- State.a[OP[0]] = 0;
- trace_output (OP_ACCUM);
+ SET_ACC (OP[0], 0);
+ trace_output_40 (0);
}
/* cmp */
OP_600 ()
{
trace_input ("cmp", OP_REG, OP_REG, OP_VOID);
- State.F1 = State.F0;
- State.F0 = ((int16)(State.regs[OP[0]]) < (int16)(State.regs[OP[1]])) ? 1 : 0;
- trace_output (OP_FLAG);
+ SET_PSW_F1 (PSW_F0);
+ SET_PSW_F0 (((int16)(GPR (OP[0])) < (int16)(GPR (OP[1]))) ? 1 : 0);
+ trace_output_flag ();
}
/* cmp */
OP_1603 ()
{
trace_input ("cmp", OP_ACCUM, OP_ACCUM, OP_VOID);
- State.F1 = State.F0;
- State.F0 = (SEXT40(State.a[OP[0]]) < SEXT40(State.a[OP[1]])) ? 1 : 0;
- trace_output (OP_FLAG);
+ SET_PSW_F1 (PSW_F0);
+ SET_PSW_F0 ((SEXT40(ACC (OP[0])) < SEXT40(ACC (OP[1]))) ? 1 : 0);
+ trace_output_flag ();
}
/* cmpeq */
OP_400 ()
{
trace_input ("cmpeq", OP_REG, OP_REG, OP_VOID);
- State.F1 = State.F0;
- State.F0 = (State.regs[OP[0]] == State.regs[OP[1]]) ? 1 : 0;
- trace_output (OP_FLAG);
+ SET_PSW_F1 (PSW_F0);
+ SET_PSW_F0 ((GPR (OP[0]) == GPR (OP[1])) ? 1 : 0);
+ trace_output_flag ();
}
/* cmpeq */
OP_1403 ()
{
trace_input ("cmpeq", OP_ACCUM, OP_ACCUM, OP_VOID);
- State.F1 = State.F0;
- State.F0 = ((State.a[OP[0]] & MASK40) == (State.a[OP[1]] & MASK40)) ? 1 : 0;
- trace_output (OP_FLAG);
+ SET_PSW_F1 (PSW_F0);
+ SET_PSW_F0 (((ACC (OP[0]) & MASK40) == (ACC (OP[1]) & MASK40)) ? 1 : 0);
+ trace_output_flag ();
}
/* cmpeqi.s */
OP_401 ()
{
trace_input ("cmpeqi.s", OP_REG, OP_CONSTANT4, OP_VOID);
- State.F1 = State.F0;
- State.F0 = (State.regs[OP[0]] == (reg_t)SEXT4(OP[1])) ? 1 : 0;
- trace_output (OP_FLAG);
+ SET_PSW_F1 (PSW_F0);
+ SET_PSW_F0 ((GPR (OP[0]) == (reg_t) SEXT4 (OP[1])) ? 1 : 0);
+ trace_output_flag ();
}
/* cmpeqi.l */
OP_2000000 ()
{
trace_input ("cmpeqi.l", OP_REG, OP_CONSTANT16, OP_VOID);
- State.F1 = State.F0;
- State.F0 = (State.regs[OP[0]] == (reg_t)OP[1]) ? 1 : 0;
- trace_output (OP_FLAG);
+ SET_PSW_F1 (PSW_F0);
+ SET_PSW_F0 ((GPR (OP[0]) == (reg_t)OP[1]) ? 1 : 0);
+ trace_output_flag ();
}
/* cmpi.s */
OP_601 ()
{
trace_input ("cmpi.s", OP_REG, OP_CONSTANT4, OP_VOID);
- State.F1 = State.F0;
- State.F0 = ((int16)(State.regs[OP[0]]) < (int16)SEXT4(OP[1])) ? 1 : 0;
- trace_output (OP_FLAG);
+ SET_PSW_F1 (PSW_F0);
+ SET_PSW_F0 (((int16)(GPR (OP[0])) < (int16)SEXT4(OP[1])) ? 1 : 0);
+ trace_output_flag ();
}
/* cmpi.l */
OP_3000000 ()
{
trace_input ("cmpi.l", OP_REG, OP_CONSTANT16, OP_VOID);
- State.F1 = State.F0;
- State.F0 = ((int16)(State.regs[OP[0]]) < (int16)(OP[1])) ? 1 : 0;
- trace_output (OP_FLAG);
+ SET_PSW_F1 (PSW_F0);
+ SET_PSW_F0 (((int16)(GPR (OP[0])) < (int16)(OP[1])) ? 1 : 0);
+ trace_output_flag ();
}
/* cmpu */
OP_4600 ()
{
trace_input ("cmpu", OP_REG, OP_REG, OP_VOID);
- State.F1 = State.F0;
- State.F0 = (State.regs[OP[0]] < State.regs[OP[1]]) ? 1 : 0;
- trace_output (OP_FLAG);
+ SET_PSW_F1 (PSW_F0);
+ SET_PSW_F0 ((GPR (OP[0]) < GPR (OP[1])) ? 1 : 0);
+ trace_output_flag ();
}
/* cmpui */
OP_23000000 ()
{
trace_input ("cmpui", OP_REG, OP_CONSTANT16, OP_VOID);
- State.F1 = State.F0;
- State.F0 = (State.regs[OP[0]] < (reg_t)OP[1]) ? 1 : 0;
- trace_output (OP_FLAG);
+ SET_PSW_F1 (PSW_F0);
+ SET_PSW_F0 ((GPR (OP[0]) < (reg_t)OP[1]) ? 1 : 0);
+ trace_output_flag ();
}
/* cpfg */
void
OP_4E09 ()
{
- uint8 *src, *dst;
+ uint8 val;
trace_input ("cpfg", OP_FLAG_OUTPUT, OP_FLAG, OP_VOID);
- if (OP[0] == 0)
- dst = &State.F0;
- else
- dst = &State.F1;
if (OP[1] == 0)
- src = &State.F0;
+ val = PSW_F0;
else if (OP[1] == 1)
- src = &State.F1;
+ val = PSW_F1;
else
- src = &State.C;
+ val = PSW_C;
+ if (OP[0] == 0)
+ SET_PSW_F0 (val);
+ else
+ SET_PSW_F1 (val);
- *dst = *src;
- trace_output (OP_FLAG);
+ trace_output_flag ();
}
/* dbt */
OP_5F20 ()
{
/* d10v_callback->printf_filtered(d10v_callback, "***** DBT ***** PC=%x\n",PC); */
- State.exception = SIGTRAP;
+
+ /* GDB uses the instruction pair ``dbt || nop'' as a break-point.
+ The conditional below is for either of the instruction pairs
+ ``dbt -> XXX'' or ``dbt <- XXX'' and treats them as as cases
+ where the dbt instruction should be interpreted.
+
+ The module `sim-break' provides a more effective mechanism for
+ detecting GDB planted breakpoints. The code below may,
+ eventually, be changed to use that mechanism. */
+
+ if (State.ins_type == INS_LEFT
+ || State.ins_type == INS_RIGHT)
+ {
+ trace_input ("dbt", OP_VOID, OP_VOID, OP_VOID);
+ SET_DPC (PC + 1);
+ SET_DPSW (PSW);
+ SET_PSW (PSW_DM_BIT | (PSW & (PSW_F0_BIT | PSW_F1_BIT | PSW_C_BIT)));
+ JMP (DBT_VECTOR_START);
+ trace_output_void ();
+ }
+ else
+ {
+ State.exception = SIGTRAP;
+ }
}
/* divs */
OP_14002800 ()
{
uint16 foo, tmp, tmpf;
+ uint16 hi;
+ uint16 lo;
trace_input ("divs", OP_DREG, OP_REG, OP_VOID);
- foo = (State.regs[OP[0]] << 1) | (State.regs[OP[0]+1] >> 15);
- tmp = (int16)foo - (int16)(State.regs[OP[1]]);
- tmpf = (foo >= State.regs[OP[1]]) ? 1 : 0;
- State.regs[OP[0]] = (tmpf == 1) ? tmp : foo;
- State.regs[OP[0]+1] = (State.regs[OP[0]+1] << 1) | tmpf;
- trace_output (OP_DREG);
+ foo = (GPR (OP[0]) << 1) | (GPR (OP[0] + 1) >> 15);
+ tmp = (int16)foo - (int16)(GPR (OP[1]));
+ tmpf = (foo >= GPR (OP[1])) ? 1 : 0;
+ hi = ((tmpf == 1) ? tmp : foo);
+ lo = ((GPR (OP[0] + 1) << 1) | tmpf);
+ SET_GPR (OP[0] + 0, hi);
+ SET_GPR (OP[0] + 1, lo);
+ trace_output_32 (((uint32) hi << 16) | lo);
}
/* exef0f */
OP_4E04 ()
{
trace_input ("exef0f", OP_VOID, OP_VOID, OP_VOID);
- State.exe = (State.F0 == 0);
- trace_output (OP_FLAG);
+ State.exe = (PSW_F0 == 0);
+ trace_output_flag ();
}
/* exef0t */
OP_4E24 ()
{
trace_input ("exef0t", OP_VOID, OP_VOID, OP_VOID);
- State.exe = (State.F0 != 0);
- trace_output (OP_FLAG);
+ State.exe = (PSW_F0 != 0);
+ trace_output_flag ();
}
/* exef1f */
OP_4E40 ()
{
trace_input ("exef1f", OP_VOID, OP_VOID, OP_VOID);
- State.exe = (State.F1 == 0);
- trace_output (OP_FLAG);
+ State.exe = (PSW_F1 == 0);
+ trace_output_flag ();
}
/* exef1t */
OP_4E42 ()
{
trace_input ("exef1t", OP_VOID, OP_VOID, OP_VOID);
- State.exe = (State.F1 != 0);
- trace_output (OP_FLAG);
+ State.exe = (PSW_F1 != 0);
+ trace_output_flag ();
}
/* exefaf */
OP_4E00 ()
{
trace_input ("exefaf", OP_VOID, OP_VOID, OP_VOID);
- State.exe = (State.F0 == 0) & (State.F1 == 0);
- trace_output (OP_FLAG);
+ State.exe = (PSW_F0 == 0) & (PSW_F1 == 0);
+ trace_output_flag ();
}
/* exefat */
OP_4E02 ()
{
trace_input ("exefat", OP_VOID, OP_VOID, OP_VOID);
- State.exe = (State.F0 == 0) & (State.F1 != 0);
- trace_output (OP_FLAG);
+ State.exe = (PSW_F0 == 0) & (PSW_F1 != 0);
+ trace_output_flag ();
}
/* exetaf */
OP_4E20 ()
{
trace_input ("exetaf", OP_VOID, OP_VOID, OP_VOID);
- State.exe = (State.F0 != 0) & (State.F1 == 0);
- trace_output (OP_FLAG);
+ State.exe = (PSW_F0 != 0) & (PSW_F1 == 0);
+ trace_output_flag ();
}
/* exetat */
OP_4E22 ()
{
trace_input ("exetat", OP_VOID, OP_VOID, OP_VOID);
- State.exe = (State.F0 != 0) & (State.F1 != 0);
- trace_output (OP_FLAG);
+ State.exe = (PSW_F0 != 0) & (PSW_F1 != 0);
+ trace_output_flag ();
}
/* exp */
int i;
trace_input ("exp", OP_REG_OUTPUT, OP_DREG, OP_VOID);
- if (((int16)State.regs[OP[1]]) >= 0)
- tmp = (State.regs[OP[1]] << 16) | State.regs[OP[1]+1];
+ if (((int16)GPR (OP[1])) >= 0)
+ tmp = (GPR (OP[1]) << 16) | GPR (OP[1] + 1);
else
- tmp = ~((State.regs[OP[1]] << 16) | State.regs[OP[1]+1]);
+ tmp = ~((GPR (OP[1]) << 16) | GPR (OP[1] + 1));
foo = 0x40000000;
for (i=1;i<17;i++)
{
if (tmp & foo)
{
- State.regs[OP[0]] = i-1;
- trace_output (OP_REG);
+ SET_GPR (OP[0], (i - 1));
+ trace_output_16 (i - 1);
return;
}
foo >>= 1;
}
- State.regs[OP[0]] = 16;
- trace_output (OP_REG);
+ SET_GPR (OP[0], 16);
+ trace_output_16 (16);
}
/* exp */
int i;
trace_input ("exp", OP_REG_OUTPUT, OP_ACCUM, OP_VOID);
- tmp = SEXT40(State.a[OP[1]]);
+ tmp = SEXT40(ACC (OP[1]));
if (tmp < 0)
tmp = ~tmp & MASK40;
{
if (tmp & foo)
{
- State.regs[OP[0]] = i-9;
- trace_output (OP_REG);
+ SET_GPR (OP[0], i - 9);
+ trace_output_16 (i - 9);
return;
}
foo >>= 1;
}
- State.regs[OP[0]] = 16;
- trace_output (OP_REG);
+ SET_GPR (OP[0], 16);
+ trace_output_16 (16);
}
/* jl */
OP_4D00 ()
{
trace_input ("jl", OP_REG, OP_R0, OP_R1);
- State.regs[13] = PC+1;
- JMP (State.regs[OP[0]]);
- trace_output (OP_VOID);
+ SET_GPR (13, PC + 1);
+ JMP (GPR (OP[0]));
+ trace_output_void ();
}
/* jmp */
(OP[0] == 13) ? OP_R0 : OP_VOID,
(OP[0] == 13) ? OP_R1 : OP_VOID);
- JMP (State.regs[OP[0]]);
- trace_output (OP_VOID);
+ JMP (GPR (OP[0]));
+ trace_output_void ();
}
/* ld */
void
OP_30000000 ()
{
+ uint16 tmp;
trace_input ("ld", OP_REG_OUTPUT, OP_MEMREF2, OP_VOID);
- State.regs[OP[0]] = RW (OP[1] + State.regs[OP[2]]);
- trace_output (OP_REG);
+ tmp = RW (OP[1] + GPR (OP[2]));
+ SET_GPR (OP[0], tmp);
+ trace_output_16 (tmp);
}
/* ld */
void
OP_6401 ()
{
+ uint16 tmp;
trace_input ("ld", OP_REG_OUTPUT, OP_POSTDEC, OP_VOID);
- State.regs[OP[0]] = RW (State.regs[OP[1]]);
- INC_ADDR(State.regs[OP[1]],-2);
- trace_output (OP_REG);
+ tmp = RW (GPR (OP[1]));
+ SET_GPR (OP[0], tmp);
+ if (OP[0] != OP[1])
+ INC_ADDR (OP[1], -2);
+ trace_output_16 (tmp);
}
/* ld */
void
OP_6001 ()
{
+ uint16 tmp;
trace_input ("ld", OP_REG_OUTPUT, OP_POSTINC, OP_VOID);
- State.regs[OP[0]] = RW (State.regs[OP[1]]);
- INC_ADDR(State.regs[OP[1]],2);
- trace_output (OP_REG);
+ tmp = RW (GPR (OP[1]));
+ SET_GPR (OP[0], tmp);
+ if (OP[0] != OP[1])
+ INC_ADDR (OP[1], 2);
+ trace_output_16 (tmp);
}
/* ld */
void
OP_6000 ()
{
+ uint16 tmp;
trace_input ("ld", OP_REG_OUTPUT, OP_MEMREF, OP_VOID);
- State.regs[OP[0]] = RW (State.regs[OP[1]]);
- trace_output (OP_REG);
+ tmp = RW (GPR (OP[1]));
+ SET_GPR (OP[0], tmp);
+ trace_output_16 (tmp);
}
/* ld2w */
void
OP_31000000 ()
{
- uint16 addr = State.regs[OP[2]];
+ int32 tmp;
+ uint16 addr = GPR (OP[2]);
trace_input ("ld2w", OP_REG_OUTPUT, OP_MEMREF2, OP_VOID);
- State.regs[OP[0]] = RW (OP[1] + addr);
- State.regs[OP[0]+1] = RW (OP[1] + addr + 2);
- trace_output (OP_DREG);
+ tmp = RLW (OP[1] + addr);
+ SET_GPR32 (OP[0], tmp);
+ trace_output_32 (tmp);
}
/* ld2w */
void
OP_6601 ()
{
- uint16 addr = State.regs[OP[1]];
+ uint16 addr = GPR (OP[1]);
+ int32 tmp;
trace_input ("ld2w", OP_REG_OUTPUT, OP_POSTDEC, OP_VOID);
- State.regs[OP[0]] = RW (addr);
- State.regs[OP[0]+1] = RW (addr+2);
- INC_ADDR(State.regs[OP[1]],-4);
- trace_output (OP_DREG);
+ tmp = RLW (addr);
+ SET_GPR32 (OP[0], tmp);
+ INC_ADDR (OP[1], -4);
+ trace_output_32 (tmp);
}
/* ld2w */
void
OP_6201 ()
{
- uint16 addr = State.regs[OP[1]];
+ int32 tmp;
+ uint16 addr = GPR (OP[1]);
trace_input ("ld2w", OP_REG_OUTPUT, OP_POSTINC, OP_VOID);
- State.regs[OP[0]] = RW (addr);
- State.regs[OP[0]+1] = RW (addr+2);
- INC_ADDR(State.regs[OP[1]],4);
- trace_output (OP_DREG);
+ tmp = RLW (addr);
+ SET_GPR32 (OP[0], tmp);
+ INC_ADDR (OP[1], 4);
+ trace_output_32 (tmp);
}
/* ld2w */
void
OP_6200 ()
{
- uint16 addr = State.regs[OP[1]];
+ uint16 addr = GPR (OP[1]);
+ int32 tmp;
trace_input ("ld2w", OP_REG_OUTPUT, OP_MEMREF, OP_VOID);
- State.regs[OP[0]] = RW (addr);
- State.regs[OP[0]+1] = RW (addr+2);
- trace_output (OP_DREG);
+ tmp = RLW (addr + 0);
+ SET_GPR32 (OP[0], tmp);
+ trace_output_32 (tmp);
}
/* ldb */
void
OP_38000000 ()
{
+ int16 tmp;
trace_input ("ldb", OP_REG_OUTPUT, OP_MEMREF2, OP_VOID);
- State.regs[OP[0]] = SEXT8 (RB (OP[1] + State.regs[OP[2]]));
- trace_output (OP_REG);
+ tmp = SEXT8 (RB (OP[1] + GPR (OP[2])));
+ SET_GPR (OP[0], tmp);
+ trace_output_16 (tmp);
}
/* ldb */
void
OP_7000 ()
{
+ int16 tmp;
trace_input ("ldb", OP_REG_OUTPUT, OP_MEMREF, OP_VOID);
- State.regs[OP[0]] = SEXT8 (RB (State.regs[OP[1]]));
- trace_output (OP_REG);
+ tmp = SEXT8 (RB (GPR (OP[1])));
+ SET_GPR (OP[0], tmp);
+ trace_output_16 (tmp);
}
/* ldi.s */
void
OP_4001 ()
{
+ int16 tmp;
trace_input ("ldi.s", OP_REG_OUTPUT, OP_CONSTANT4, OP_VOID);
- State.regs[OP[0]] = SEXT4(OP[1]);
- trace_output (OP_REG);
+ tmp = SEXT4 (OP[1]);
+ SET_GPR (OP[0], tmp);
+ trace_output_16 (tmp);
}
/* ldi.l */
void
OP_20000000 ()
{
+ int16 tmp;
trace_input ("ldi.l", OP_REG_OUTPUT, OP_CONSTANT16, OP_VOID);
- State.regs[OP[0]] = OP[1];
- trace_output (OP_REG);
+ tmp = OP[1];
+ SET_GPR (OP[0], tmp);
+ trace_output_16 (tmp);
}
/* ldub */
void
OP_39000000 ()
{
+ int16 tmp;
trace_input ("ldub", OP_REG_OUTPUT, OP_MEMREF2, OP_VOID);
- State.regs[OP[0]] = RB (OP[1] + State.regs[OP[2]]);
- trace_output (OP_REG);
+ tmp = RB (OP[1] + GPR (OP[2]));
+ SET_GPR (OP[0], tmp);
+ trace_output_16 (tmp);
}
/* ldub */
void
OP_7200 ()
{
+ int16 tmp;
trace_input ("ldub", OP_REG_OUTPUT, OP_MEMREF, OP_VOID);
- State.regs[OP[0]] = RB (State.regs[OP[1]]);
- trace_output (OP_REG);
+ tmp = RB (GPR (OP[1]));
+ SET_GPR (OP[0], tmp);
+ trace_output_16 (tmp);
}
/* mac */
int64 tmp;
trace_input ("mac", OP_ACCUM, OP_REG, OP_REG);
- tmp = SEXT40 ((int16)(State.regs[OP[1]]) * (int16)(State.regs[OP[2]]));
+ tmp = SEXT40 ((int16)(GPR (OP[1])) * (int16)(GPR (OP[2])));
- if (State.FX)
+ if (PSW_FX)
tmp = SEXT40( (tmp << 1) & MASK40);
- if (State.ST && tmp > MAX32)
+ if (PSW_ST && tmp > SEXT40(MAX32))
tmp = MAX32;
- tmp += SEXT40(State.a[OP[0]]);
- if (State.ST)
+ tmp += SEXT40 (ACC (OP[0]));
+ if (PSW_ST)
{
- if (tmp > MAX32)
- State.a[OP[0]] = MAX32;
- else if (tmp < MIN32)
- State.a[OP[0]] = MIN32;
+ if (tmp > SEXT40(MAX32))
+ tmp = MAX32;
+ else if (tmp < SEXT40(MIN32))
+ tmp = MIN32;
else
- State.a[OP[0]] = tmp & MASK40;
+ tmp = (tmp & MASK40);
}
else
- State.a[OP[0]] = tmp & MASK40;
- trace_output (OP_ACCUM);
+ tmp = (tmp & MASK40);
+ SET_ACC (OP[0], tmp);
+ trace_output_40 (tmp);
}
/* macsu */
int64 tmp;
trace_input ("macsu", OP_ACCUM, OP_REG, OP_REG);
- tmp = SEXT40 ((int16)State.regs[OP[1]] * State.regs[OP[2]]);
- if (State.FX)
- tmp = SEXT40( (tmp << 1) & MASK40);
-
- State.a[OP[0]] = (SEXT40 (State.a[OP[0]]) + tmp) & MASK40;
- trace_output (OP_ACCUM);
+ tmp = SEXT40 ((int16) GPR (OP[1]) * GPR (OP[2]));
+ if (PSW_FX)
+ tmp = SEXT40 ((tmp << 1) & MASK40);
+ tmp = ((SEXT40 (ACC (OP[0])) + tmp) & MASK40);
+ SET_ACC (OP[0], tmp);
+ trace_output_40 (tmp);
}
/* macu */
uint32 src2;
trace_input ("macu", OP_ACCUM, OP_REG, OP_REG);
- src1 = (uint16) State.regs[OP[1]];
- src2 = (uint16) State.regs[OP[2]];
+ src1 = (uint16) GPR (OP[1]);
+ src2 = (uint16) GPR (OP[2]);
tmp = src1 * src2;
- if (State.FX)
+ if (PSW_FX)
tmp = (tmp << 1);
- State.a[OP[0]] = (State.a[OP[0]] + tmp) & MASK40;
- trace_output (OP_ACCUM);
+ tmp = ((ACC (OP[0]) + tmp) & MASK40);
+ SET_ACC (OP[0], tmp);
+ trace_output_40 (tmp);
}
/* max */
void
OP_2600 ()
{
+ int16 tmp;
trace_input ("max", OP_REG, OP_REG, OP_VOID);
- State.F1 = State.F0;
- if ((int16)State.regs[OP[1]] > (int16)State.regs[OP[0]])
+ SET_PSW_F1 (PSW_F0);
+ if ((int16) GPR (OP[1]) > (int16)GPR (OP[0]))
{
- State.regs[OP[0]] = State.regs[OP[1]];
- State.F0 = 1;
+ tmp = GPR (OP[1]);
+ SET_PSW_F0 (1);
}
else
- State.F0 = 0;
- trace_output (OP_REG);
+ {
+ tmp = GPR (OP[0]);
+ SET_PSW_F0 (0);
+ }
+ SET_GPR (OP[0], tmp);
+ trace_output_16 (tmp);
}
/* max */
int64 tmp;
trace_input ("max", OP_ACCUM, OP_DREG, OP_VOID);
- State.F1 = State.F0;
- tmp = SEXT16 (State.regs[OP[1]]) << 16 | State.regs[OP[1]+1];
- if (tmp > SEXT40(State.a[OP[0]]))
+ SET_PSW_F1 (PSW_F0);
+ tmp = SEXT16 (GPR (OP[1])) << 16 | GPR (OP[1] + 1);
+ if (tmp > SEXT40 (ACC (OP[0])))
{
- State.a[OP[0]] = tmp & MASK40;
- State.F0 = 1;
+ tmp = (tmp & MASK40);
+ SET_PSW_F0 (1);
}
else
- State.F0 = 0;
- trace_output (OP_ACCUM);
+ {
+ tmp = ACC (OP[0]);
+ SET_PSW_F0 (0);
+ }
+ SET_ACC (OP[0], tmp);
+ trace_output_40 (tmp);
}
/* max */
void
OP_3602 ()
{
+ int64 tmp;
trace_input ("max", OP_ACCUM, OP_ACCUM, OP_VOID);
- State.F1 = State.F0;
- if (SEXT40(State.a[OP[1]]) > SEXT40(State.a[OP[0]]))
+ SET_PSW_F1 (PSW_F0);
+ if (SEXT40 (ACC (OP[1])) > SEXT40 (ACC (OP[0])))
{
- State.a[OP[0]] = State.a[OP[1]];
- State.F0 = 1;
+ tmp = ACC (OP[1]);
+ SET_PSW_F0 (1);
}
else
- State.F0 = 0;
- trace_output (OP_ACCUM);
+ {
+ tmp = ACC (OP[0]);
+ SET_PSW_F0 (0);
+ }
+ SET_ACC (OP[0], tmp);
+ trace_output_40 (tmp);
}
void
OP_2601 ()
{
+ int16 tmp;
trace_input ("min", OP_REG, OP_REG, OP_VOID);
- State.F1 = State.F0;
- if ((int16)State.regs[OP[1]] < (int16)State.regs[OP[0]])
+ SET_PSW_F1 (PSW_F0);
+ if ((int16)GPR (OP[1]) < (int16)GPR (OP[0]))
{
- State.regs[OP[0]] = State.regs[OP[1]];
- State.F0 = 1;
+ tmp = GPR (OP[1]);
+ SET_PSW_F0 (1);
}
else
- State.F0 = 0;
- trace_output (OP_REG);
+ {
+ tmp = GPR (OP[0]);
+ SET_PSW_F0 (0);
+ }
+ SET_GPR (OP[0], tmp);
+ trace_output_16 (tmp);
}
/* min */
int64 tmp;
trace_input ("min", OP_ACCUM, OP_DREG, OP_VOID);
- State.F1 = State.F0;
- tmp = SEXT16 (State.regs[OP[1]]) << 16 | State.regs[OP[1]+1];
- if (tmp < SEXT40(State.a[OP[0]]))
+ SET_PSW_F1 (PSW_F0);
+ tmp = SEXT16 (GPR (OP[1])) << 16 | GPR (OP[1] + 1);
+ if (tmp < SEXT40(ACC (OP[0])))
{
- State.a[OP[0]] = tmp & MASK40;
- State.F0 = 1;
+ tmp = (tmp & MASK40);
+ SET_PSW_F0 (1);
}
else
- State.F0 = 0;
- trace_output (OP_ACCUM);
+ {
+ tmp = ACC (OP[0]);
+ SET_PSW_F0 (0);
+ }
+ SET_ACC (OP[0], tmp);
+ trace_output_40 (tmp);
}
/* min */
void
OP_3603 ()
{
+ int64 tmp;
trace_input ("min", OP_ACCUM, OP_ACCUM, OP_VOID);
- State.F1 = State.F0;
- if (SEXT40(State.a[OP[1]]) < SEXT40(State.a[OP[0]]))
+ SET_PSW_F1 (PSW_F0);
+ if (SEXT40(ACC (OP[1])) < SEXT40(ACC (OP[0])))
{
- State.a[OP[0]] = State.a[OP[1]];
- State.F0 = 1;
+ tmp = ACC (OP[1]);
+ SET_PSW_F0 (1);
}
else
- State.F0 = 0;
- trace_output (OP_ACCUM);
+ {
+ tmp = ACC (OP[0]);
+ SET_PSW_F0 (0);
+ }
+ SET_ACC (OP[0], tmp);
+ trace_output_40 (tmp);
}
/* msb */
int64 tmp;
trace_input ("msb", OP_ACCUM, OP_REG, OP_REG);
- tmp = SEXT40 ((int16)(State.regs[OP[1]]) * (int16)(State.regs[OP[2]]));
+ tmp = SEXT40 ((int16)(GPR (OP[1])) * (int16)(GPR (OP[2])));
- if (State.FX)
+ if (PSW_FX)
tmp = SEXT40 ((tmp << 1) & MASK40);
- if (State.ST && tmp > MAX32)
+ if (PSW_ST && tmp > SEXT40(MAX32))
tmp = MAX32;
- tmp = SEXT40(State.a[OP[0]]) - tmp;
- if (State.ST)
+ tmp = SEXT40(ACC (OP[0])) - tmp;
+ if (PSW_ST)
{
- if (tmp > MAX32)
- State.a[OP[0]] = MAX32;
- else if (tmp < MIN32)
- State.a[OP[0]] = MIN32;
+ if (tmp > SEXT40(MAX32))
+ tmp = MAX32;
+ else if (tmp < SEXT40(MIN32))
+ tmp = MIN32;
else
- State.a[OP[0]] = tmp & MASK40;
+ tmp = (tmp & MASK40);
}
else
- State.a[OP[0]] = tmp & MASK40;
- trace_output (OP_ACCUM);
+ {
+ tmp = (tmp & MASK40);
+ }
+ SET_ACC (OP[0], tmp);
+ trace_output_40 (tmp);
}
/* msbsu */
int64 tmp;
trace_input ("msbsu", OP_ACCUM, OP_REG, OP_REG);
- tmp = SEXT40 ((int16)State.regs[OP[1]] * State.regs[OP[2]]);
- if (State.FX)
+ tmp = SEXT40 ((int16)GPR (OP[1]) * GPR (OP[2]));
+ if (PSW_FX)
tmp = SEXT40( (tmp << 1) & MASK40);
-
- State.a[OP[0]] = (SEXT40 (State.a[OP[0]]) - tmp) & MASK40;
- trace_output (OP_ACCUM);
+ tmp = ((SEXT40 (ACC (OP[0])) - tmp) & MASK40);
+ SET_ACC (OP[0], tmp);
+ trace_output_40 (tmp);
}
/* msbu */
uint32 src2;
trace_input ("msbu", OP_ACCUM, OP_REG, OP_REG);
- src1 = (uint16) State.regs[OP[1]];
- src2 = (uint16) State.regs[OP[2]];
+ src1 = (uint16) GPR (OP[1]);
+ src2 = (uint16) GPR (OP[2]);
tmp = src1 * src2;
- if (State.FX)
+ if (PSW_FX)
tmp = (tmp << 1);
-
- State.a[OP[0]] = (State.a[OP[0]] - tmp) & MASK40;
- trace_output (OP_ACCUM);
+ tmp = ((ACC (OP[0]) - tmp) & MASK40);
+ SET_ACC (OP[0], tmp);
+ trace_output_40 (tmp);
}
/* mul */
void
OP_2E00 ()
{
+ int16 tmp;
trace_input ("mul", OP_REG, OP_REG, OP_VOID);
- State.regs[OP[0]] *= State.regs[OP[1]];
- trace_output (OP_REG);
+ tmp = GPR (OP[0]) * GPR (OP[1]);
+ SET_GPR (OP[0], tmp);
+ trace_output_16 (tmp);
}
/* mulx */
int64 tmp;
trace_input ("mulx", OP_ACCUM_OUTPUT, OP_REG, OP_REG);
- tmp = SEXT40 ((int16)(State.regs[OP[1]]) * (int16)(State.regs[OP[2]]));
+ tmp = SEXT40 ((int16)(GPR (OP[1])) * (int16)(GPR (OP[2])));
- if (State.FX)
+ if (PSW_FX)
tmp = SEXT40 ((tmp << 1) & MASK40);
- if (State.ST && tmp > MAX32)
- State.a[OP[0]] = MAX32;
+ if (PSW_ST && tmp > MAX32)
+ tmp = MAX32;
else
- State.a[OP[0]] = tmp & MASK40;
- trace_output (OP_ACCUM);
+ tmp = (tmp & MASK40);
+ SET_ACC (OP[0], tmp);
+ trace_output_40 (tmp);
}
/* mulxsu */
int64 tmp;
trace_input ("mulxsu", OP_ACCUM_OUTPUT, OP_REG, OP_REG);
- tmp = SEXT40 ((int16)(State.regs[OP[1]]) * State.regs[OP[2]]);
+ tmp = SEXT40 ((int16)(GPR (OP[1])) * GPR (OP[2]));
- if (State.FX)
+ if (PSW_FX)
tmp <<= 1;
-
- State.a[OP[0]] = tmp & MASK40;
- trace_output (OP_ACCUM);
+ tmp = (tmp & MASK40);
+ SET_ACC (OP[0], tmp);
+ trace_output_40 (tmp);
}
/* mulxu */
uint32 src2;
trace_input ("mulxu", OP_ACCUM_OUTPUT, OP_REG, OP_REG);
- src1 = (uint16) State.regs[OP[1]];
- src2 = (uint16) State.regs[OP[2]];
+ src1 = (uint16) GPR (OP[1]);
+ src2 = (uint16) GPR (OP[2]);
tmp = src1 * src2;
- if (State.FX)
+ if (PSW_FX)
tmp <<= 1;
-
- State.a[OP[0]] = tmp & MASK40;
- trace_output (OP_ACCUM);
+ tmp = (tmp & MASK40);
+ SET_ACC (OP[0], tmp);
+ trace_output_40 (tmp);
}
/* mv */
void
OP_4000 ()
{
+ int16 tmp;
trace_input ("mv", OP_REG_OUTPUT, OP_REG, OP_VOID);
- State.regs[OP[0]] = State.regs[OP[1]];
- trace_output (OP_REG);
+ tmp = GPR (OP[1]);
+ SET_GPR (OP[0], tmp);
+ trace_output_16 (tmp);
}
/* mv2w */
void
OP_5000 ()
{
+ int32 tmp;
trace_input ("mv2w", OP_DREG_OUTPUT, OP_DREG, OP_VOID);
- State.regs[OP[0]] = State.regs[OP[1]];
- State.regs[OP[0]+1] = State.regs[OP[1]+1];
- trace_output (OP_DREG);
+ tmp = GPR32 (OP[1]);
+ SET_GPR32 (OP[0], tmp);
+ trace_output_32 (tmp);
}
/* mv2wfac */
void
OP_3E00 ()
{
+ int32 tmp;
trace_input ("mv2wfac", OP_DREG_OUTPUT, OP_ACCUM, OP_VOID);
- State.regs[OP[0]] = (State.a[OP[1]] >> 16) & 0xffff;
- State.regs[OP[0]+1] = State.a[OP[1]] & 0xffff;
- trace_output (OP_DREG);
+ tmp = ACC (OP[1]);
+ SET_GPR32 (OP[0], tmp);
+ trace_output_32 (tmp);
}
/* mv2wtac */
void
OP_3E01 ()
{
+ int64 tmp;
trace_input ("mv2wtac", OP_DREG, OP_ACCUM_OUTPUT, OP_VOID);
- State.a[OP[1]] = (SEXT16 (State.regs[OP[0]]) << 16 | State.regs[OP[0]+1]) & MASK40;
- trace_output (OP_ACCUM_REVERSE);
+ tmp = ((SEXT16 (GPR (OP[0])) << 16 | GPR (OP[0] + 1)) & MASK40);
+ SET_ACC (OP[1], tmp);
+ trace_output_40 (tmp);
}
/* mvac */
void
OP_3E03 ()
{
+ int64 tmp;
trace_input ("mvac", OP_ACCUM_OUTPUT, OP_ACCUM, OP_VOID);
- State.a[OP[0]] = State.a[OP[1]];
- trace_output (OP_ACCUM);
+ tmp = ACC (OP[1]);
+ SET_ACC (OP[0], tmp);
+ trace_output_40 (tmp);
}
/* mvb */
void
OP_5400 ()
{
+ int16 tmp;
trace_input ("mvb", OP_REG_OUTPUT, OP_REG, OP_VOID);
- State.regs[OP[0]] = SEXT8 (State.regs[OP[1]] & 0xff);
- trace_output (OP_REG);
+ tmp = SEXT8 (GPR (OP[1]) & 0xff);
+ SET_GPR (OP[0], tmp);
+ trace_output_16 (tmp);
}
/* mvf0f */
void
OP_4400 ()
{
+ int16 tmp;
trace_input ("mf0f", OP_REG_OUTPUT, OP_REG, OP_VOID);
- if (State.F0 == 0)
- State.regs[OP[0]] = State.regs[OP[1]];
- trace_output (OP_REG);
+ if (PSW_F0 == 0)
+ {
+ tmp = GPR (OP[1]);
+ SET_GPR (OP[0], tmp);
+ }
+ else
+ tmp = GPR (OP[0]);
+ trace_output_16 (tmp);
}
/* mvf0t */
void
OP_4401 ()
{
+ int16 tmp;
trace_input ("mf0t", OP_REG_OUTPUT, OP_REG, OP_VOID);
- if (State.F0)
- State.regs[OP[0]] = State.regs[OP[1]];
- trace_output (OP_REG);
+ if (PSW_F0)
+ {
+ tmp = GPR (OP[1]);
+ SET_GPR (OP[0], tmp);
+ }
+ else
+ tmp = GPR (OP[0]);
+ trace_output_16 (tmp);
}
/* mvfacg */
void
OP_1E04 ()
{
+ int16 tmp;
trace_input ("mvfacg", OP_REG_OUTPUT, OP_ACCUM, OP_VOID);
- State.regs[OP[0]] = (State.a[OP[1]] >> 32) & 0xff;
- trace_output (OP_ACCUM);
+ tmp = ((ACC (OP[1]) >> 32) & 0xff);
+ SET_GPR (OP[0], tmp);
+ trace_output_16 (tmp);
}
/* mvfachi */
void
OP_1E00 ()
{
+ int16 tmp;
trace_input ("mvfachi", OP_REG_OUTPUT, OP_ACCUM, OP_VOID);
- State.regs[OP[0]] = (State.a[OP[1]] >> 16) & 0xffff;
- trace_output (OP_REG);
+ tmp = (ACC (OP[1]) >> 16);
+ SET_GPR (OP[0], tmp);
+ trace_output_16 (tmp);
}
/* mvfaclo */
void
OP_1E02 ()
{
+ int16 tmp;
trace_input ("mvfaclo", OP_REG_OUTPUT, OP_ACCUM, OP_VOID);
- State.regs[OP[0]] = State.a[OP[1]] & 0xffff;
- trace_output (OP_REG);
+ tmp = ACC (OP[1]);
+ SET_GPR (OP[0], tmp);
+ trace_output_16 (tmp);
}
/* mvfc */
void
OP_5200 ()
{
+ int16 tmp;
trace_input ("mvfc", OP_REG_OUTPUT, OP_CR, OP_VOID);
- State.regs[OP[0]] = move_from_cr (OP[1]);
- trace_output (OP_REG);
+ tmp = CREG (OP[1]);
+ SET_GPR (OP[0], tmp);
+ trace_output_16 (tmp);
}
/* mvtacg */
void
OP_1E41 ()
{
+ int64 tmp;
trace_input ("mvtacg", OP_REG, OP_ACCUM, OP_VOID);
- State.a[OP[1]] &= MASK32;
- State.a[OP[1]] |= (int64)(State.regs[OP[0]] & 0xff) << 32;
- trace_output (OP_ACCUM_REVERSE);
+ tmp = ((ACC (OP[1]) & MASK32)
+ | ((int64)(GPR (OP[0]) & 0xff) << 32));
+ SET_ACC (OP[1], tmp);
+ trace_output_40 (tmp);
}
/* mvtachi */
void
OP_1E01 ()
{
- uint16 tmp;
-
+ uint64 tmp;
trace_input ("mvtachi", OP_REG, OP_ACCUM, OP_VOID);
- tmp = State.a[OP[1]] & 0xffff;
- State.a[OP[1]] = (SEXT16 (State.regs[OP[0]]) << 16 | tmp) & MASK40;
- trace_output (OP_ACCUM_REVERSE);
+ tmp = ACC (OP[1]) & 0xffff;
+ tmp = ((SEXT16 (GPR (OP[0])) << 16 | tmp) & MASK40);
+ SET_ACC (OP[1], tmp);
+ trace_output_40 (tmp);
}
/* mvtaclo */
void
OP_1E21 ()
{
+ int64 tmp;
trace_input ("mvtaclo", OP_REG, OP_ACCUM, OP_VOID);
- State.a[OP[1]] = (SEXT16 (State.regs[OP[0]])) & MASK40;
- trace_output (OP_ACCUM_REVERSE);
+ tmp = ((SEXT16 (GPR (OP[0]))) & MASK40);
+ SET_ACC (OP[1], tmp);
+ trace_output_40 (tmp);
}
/* mvtc */
void
OP_5600 ()
{
+ int16 tmp;
trace_input ("mvtc", OP_REG, OP_CR_OUTPUT, OP_VOID);
- move_to_cr (OP[1], State.regs[OP[0]]);
- trace_output (OP_CR_REVERSE);
+ tmp = GPR (OP[0]);
+ tmp = SET_CREG (OP[1], tmp);
+ trace_output_16 (tmp);
}
/* mvub */
void
OP_5401 ()
{
+ int16 tmp;
trace_input ("mvub", OP_REG_OUTPUT, OP_REG, OP_VOID);
- State.regs[OP[0]] = State.regs[OP[1]] & 0xff;
- trace_output (OP_REG);
+ tmp = (GPR (OP[1]) & 0xff);
+ SET_GPR (OP[0], tmp);
+ trace_output_16 (tmp);
}
/* neg */
void
OP_4605 ()
{
+ int16 tmp;
trace_input ("neg", OP_REG, OP_VOID, OP_VOID);
- State.regs[OP[0]] = 0 - State.regs[OP[0]];
- trace_output (OP_REG);
+ tmp = - GPR (OP[0]);
+ SET_GPR (OP[0], tmp);
+ trace_output_16 (tmp);
}
/* neg */
int64 tmp;
trace_input ("neg", OP_ACCUM, OP_VOID, OP_VOID);
- tmp = -SEXT40(State.a[OP[0]]);
- if (State.ST)
+ tmp = -SEXT40(ACC (OP[0]));
+ if (PSW_ST)
{
- if ( tmp > MAX32)
- State.a[OP[0]] = MAX32;
- else if (tmp < MIN32)
- State.a[OP[0]] = MIN32;
+ if (tmp > SEXT40(MAX32))
+ tmp = (MAX32);
+ else if (tmp < SEXT40(MIN32))
+ tmp = (MIN32);
else
- State.a[OP[0]] = tmp & MASK40;
+ tmp = (tmp & MASK40);
}
else
- State.a[OP[0]] = tmp & MASK40;
- trace_output (OP_ACCUM);
+ tmp = (tmp & MASK40);
+ SET_ACC (OP[0], tmp);
+ trace_output_40 (tmp);
}
break;
}
- trace_output (OP_VOID);
+ trace_output_void ();
}
/* not */
void
OP_4603 ()
{
+ int16 tmp;
trace_input ("not", OP_REG, OP_VOID, OP_VOID);
- State.regs[OP[0]] = ~(State.regs[OP[0]]);
- trace_output (OP_REG);
+ tmp = ~GPR (OP[0]);
+ SET_GPR (OP[0], tmp);
+ trace_output_16 (tmp);
}
/* or */
void
OP_800 ()
{
+ int16 tmp;
trace_input ("or", OP_REG, OP_REG, OP_VOID);
- State.regs[OP[0]] |= State.regs[OP[1]];
- trace_output (OP_REG);
+ tmp = (GPR (OP[0]) | GPR (OP[1]));
+ SET_GPR (OP[0], tmp);
+ trace_output_16 (tmp);
}
/* or3 */
void
OP_4000000 ()
{
+ int16 tmp;
trace_input ("or3", OP_REG_OUTPUT, OP_REG, OP_CONSTANT16);
- State.regs[OP[0]] = State.regs[OP[1]] | OP[2];
- trace_output (OP_REG);
+ tmp = (GPR (OP[1]) | OP[2]);
+ SET_GPR (OP[0], tmp);
+ trace_output_16 (tmp);
}
/* rac */
State.exception = SIGILL;
}
- State.F1 = State.F0;
- tmp = SEXT56 ((State.a[0] << 16) | (State.a[1] & 0xffff));
+ SET_PSW_F1 (PSW_F0);
+ tmp = SEXT56 ((ACC (0) << 16) | (ACC (1) & 0xffff));
if (shift >=0)
tmp <<= shift;
else
tmp >>= 16; /* look at bits 0:43 */
if (tmp > SEXT44 (SIGNED64 (0x0007fffffff)))
{
- State.regs[OP[0]] = 0x7fff;
- State.regs[OP[0]+1] = 0xffff;
- State.F0 = 1;
+ tmp = 0x7fffffff;
+ SET_PSW_F0 (1);
}
else if (tmp < SEXT44 (SIGNED64 (0xfff80000000)))
{
- State.regs[OP[0]] = 0x8000;
- State.regs[OP[0]+1] = 0;
- State.F0 = 1;
+ tmp = 0x80000000;
+ SET_PSW_F0 (1);
}
else
{
- State.regs[OP[0]] = (tmp >> 16) & 0xffff;
- State.regs[OP[0]+1] = tmp & 0xffff;
- State.F0 = 0;
+ SET_PSW_F0 (0);
}
- trace_output (OP_DREG);
+ SET_GPR32 (OP[0], tmp);
+ trace_output_32 (tmp);
}
/* rachi */
int shift = SEXT3 (OP[2]);
trace_input ("rachi", OP_REG_OUTPUT, OP_ACCUM, OP_CONSTANT3);
- State.F1 = State.F0;
+ SET_PSW_F1 (PSW_F0);
if (shift >=0)
- tmp = SEXT40 (State.a[OP[1]]) << shift;
+ tmp = SEXT40 (ACC (OP[1])) << shift;
else
- tmp = SEXT40 (State.a[OP[1]]) >> -shift;
+ tmp = SEXT40 (ACC (OP[1])) >> -shift;
tmp += 0x8000;
if (tmp > SEXT44 (SIGNED64 (0x0007fffffff)))
{
- State.regs[OP[0]] = 0x7fff;
- State.F0 = 1;
+ tmp = 0x7fff;
+ SET_PSW_F0 (1);
}
else if (tmp < SEXT44 (SIGNED64 (0xfff80000000)))
{
- State.regs[OP[0]] = 0x8000;
- State.F0 = 1;
+ tmp = 0x8000;
+ SET_PSW_F0 (1);
}
else
{
- State.regs[OP[0]] = (tmp >> 16) & 0xffff;
- State.F0 = 0;
+ tmp = (tmp >> 16);
+ SET_PSW_F0 (0);
}
- trace_output (OP_REG);
+ SET_GPR (OP[0], tmp);
+ trace_output_16 (tmp);
}
/* rep */
OP_27000000 ()
{
trace_input ("rep", OP_REG, OP_CONSTANT16, OP_VOID);
- RPT_S = PC + 1;
- RPT_E = PC + OP[1];
- RPT_C = State.regs[OP[0]];
- State.RP = 1;
- if (RPT_C == 0)
+ SET_RPT_S (PC + 1);
+ SET_RPT_E (PC + OP[1]);
+ SET_RPT_C (GPR (OP[0]));
+ SET_PSW_RP (1);
+ if (GPR (OP[0]) == 0)
{
(*d10v_callback->printf_filtered) (d10v_callback, "ERROR: rep with count=0 is illegal.\n");
State.exception = SIGILL;
(*d10v_callback->printf_filtered) (d10v_callback, "ERROR: rep must include at least 4 instructions.\n");
State.exception = SIGILL;
}
- trace_output (OP_VOID);
+ trace_output_void ();
}
/* repi */
OP_2F000000 ()
{
trace_input ("repi", OP_CONSTANT16, OP_CONSTANT16, OP_VOID);
- RPT_S = PC + 1;
- RPT_E = PC + OP[1];
- RPT_C = OP[0];
- State.RP = 1;
- if (RPT_C == 0)
+ SET_RPT_S (PC + 1);
+ SET_RPT_E (PC + OP[1]);
+ SET_RPT_C (OP[0]);
+ SET_PSW_RP (1);
+ if (OP[0] == 0)
{
(*d10v_callback->printf_filtered) (d10v_callback, "ERROR: repi with count=0 is illegal.\n");
State.exception = SIGILL;
(*d10v_callback->printf_filtered) (d10v_callback, "ERROR: repi must include at least 4 instructions.\n");
State.exception = SIGILL;
}
- trace_output (OP_VOID);
+ trace_output_void ();
}
/* rtd */
void
OP_5F60 ()
{
- d10v_callback->printf_filtered(d10v_callback, "ERROR: rtd - NOT IMPLEMENTED\n");
- State.exception = SIGILL;
+ trace_input ("rtd", OP_VOID, OP_VOID, OP_VOID);
+ SET_CREG (PSW_CR, DPSW);
+ JMP(DPC);
+ trace_output_void ();
}
/* rte */
OP_5F40 ()
{
trace_input ("rte", OP_VOID, OP_VOID, OP_VOID);
- move_to_cr (PSW_CR, BPSW);
+ SET_CREG (PSW_CR, BPSW);
JMP(BPC);
- trace_output (OP_VOID);
+ trace_output_void ();
}
/* sadd */
int64 tmp;
trace_input ("sadd", OP_ACCUM, OP_ACCUM, OP_VOID);
- tmp = SEXT40(State.a[OP[0]]) + (SEXT40(State.a[OP[1]]) >> 16);
- if (State.ST)
+ tmp = SEXT40(ACC (OP[0])) + (SEXT40(ACC (OP[1])) >> 16);
+ if (PSW_ST)
{
- if (tmp > MAX32)
- State.a[OP[0]] = MAX32;
- else if (tmp < MIN32)
- State.a[OP[0]] = MIN32;
+ if (tmp > SEXT40(MAX32))
+ tmp = (MAX32);
+ else if (tmp < SEXT40(MIN32))
+ tmp = (MIN32);
else
- State.a[OP[0]] = tmp & MASK40;
+ tmp = (tmp & MASK40);
}
else
- State.a[OP[0]] = tmp & MASK40;
- trace_output (OP_ACCUM);
+ tmp = (tmp & MASK40);
+ SET_ACC (OP[0], tmp);
+ trace_output_40 (tmp);
}
/* setf0f */
void
OP_4611 ()
{
+ int16 tmp;
trace_input ("setf0f", OP_REG_OUTPUT, OP_VOID, OP_VOID);
- State.regs[OP[0]] = (State.F0 == 0) ? 1 : 0;
- trace_output (OP_REG);
+ tmp = ((PSW_F0 == 0) ? 1 : 0);
+ SET_GPR (OP[0], tmp);
+ trace_output_16 (tmp);
}
/* setf0t */
void
OP_4613 ()
{
+ int16 tmp;
trace_input ("setf0t", OP_REG_OUTPUT, OP_VOID, OP_VOID);
- State.regs[OP[0]] = (State.F0 == 1) ? 1 : 0;
- trace_output (OP_REG);
+ tmp = ((PSW_F0 == 1) ? 1 : 0);
+ SET_GPR (OP[0], tmp);
+ trace_output_16 (tmp);
}
/* sleep */
OP_5FC0 ()
{
trace_input ("sleep", OP_VOID, OP_VOID, OP_VOID);
- State.IE = 1;
- trace_output (OP_VOID);
+ SET_PSW_IE (1);
+ trace_output_void ();
}
/* sll */
void
OP_2200 ()
{
+ int16 tmp;
trace_input ("sll", OP_REG, OP_REG, OP_VOID);
- State.regs[OP[0]] <<= (State.regs[OP[1]] & 0xf);
- trace_output (OP_REG);
+ tmp = (GPR (OP[0]) << (GPR (OP[1]) & 0xf));
+ SET_GPR (OP[0], tmp);
+ trace_output_16 (tmp);
}
/* sll */
{
int64 tmp;
trace_input ("sll", OP_ACCUM, OP_REG, OP_VOID);
- if ((State.regs[OP[1]] & 31) <= 16)
- tmp = SEXT40 (State.a[OP[0]]) << (State.regs[OP[1]] & 31);
+ if ((GPR (OP[1]) & 31) <= 16)
+ tmp = SEXT40 (ACC (OP[0])) << (GPR (OP[1]) & 31);
else
{
- (*d10v_callback->printf_filtered) (d10v_callback, "ERROR: shift value %d too large.\n", State.regs[OP[1]] & 31);
+ (*d10v_callback->printf_filtered) (d10v_callback, "ERROR: shift value %d too large.\n", GPR (OP[1]) & 31);
State.exception = SIGILL;
return;
}
- if (State.ST)
+ if (PSW_ST)
{
if (tmp > MAX32)
- State.a[OP[0]] = MAX32;
+ tmp = (MAX32);
else if (tmp < 0xffffff80000000LL)
- State.a[OP[0]] = MIN32;
+ tmp = (MIN32);
else
- State.a[OP[0]] = tmp & MASK40;
+ tmp = (tmp & MASK40);
}
else
- State.a[OP[0]] = tmp & MASK40;
- trace_output (OP_ACCUM);
+ tmp = (tmp & MASK40);
+ SET_ACC (OP[0], tmp);
+ trace_output_40 (tmp);
}
/* slli */
void
OP_2201 ()
{
+ int16 tmp;
trace_input ("slli", OP_REG, OP_CONSTANT16, OP_VOID);
- State.regs[OP[0]] <<= OP[1];
- trace_output (OP_REG);
+ tmp = (GPR (OP[0]) << OP[1]);
+ SET_GPR (OP[0], tmp);
+ trace_output_16 (tmp);
}
/* slli */
OP[1] = 16;
trace_input ("slli", OP_ACCUM, OP_CONSTANT16, OP_VOID);
- tmp = SEXT40(State.a[OP[0]]) << OP[1];
+ tmp = SEXT40(ACC (OP[0])) << OP[1];
- if (State.ST)
+ if (PSW_ST)
{
if (tmp > MAX32)
- State.a[OP[0]] = MAX32;
+ tmp = (MAX32);
else if (tmp < 0xffffff80000000LL)
- State.a[OP[0]] = MIN32;
+ tmp = (MIN32);
else
- State.a[OP[0]] = tmp & MASK40;
+ tmp = (tmp & MASK40);
}
else
- State.a[OP[0]] = tmp & MASK40;
- trace_output (OP_ACCUM);
+ tmp = (tmp & MASK40);
+ SET_ACC (OP[0], tmp);
+ trace_output_40 (tmp);
}
/* slx */
void
OP_460B ()
{
+ int16 tmp;
trace_input ("slx", OP_REG, OP_FLAG, OP_VOID);
- State.regs[OP[0]] = (State.regs[OP[0]] << 1) | State.F0;
- trace_output (OP_REG);
+ tmp = ((GPR (OP[0]) << 1) | PSW_F0);
+ SET_GPR (OP[0], tmp);
+ trace_output_16 (tmp);
}
/* sra */
void
OP_2400 ()
{
+ int16 tmp;
trace_input ("sra", OP_REG, OP_REG, OP_VOID);
- State.regs[OP[0]] = ((int16)(State.regs[OP[0]])) >> (State.regs[OP[1]] & 0xf);
- trace_output (OP_REG);
+ tmp = (((int16)(GPR (OP[0]))) >> (GPR (OP[1]) & 0xf));
+ SET_GPR (OP[0], tmp);
+ trace_output_16 (tmp);
}
/* sra */
OP_3400 ()
{
trace_input ("sra", OP_ACCUM, OP_REG, OP_VOID);
- if ((State.regs[OP[1]] & 31) <= 16)
- State.a[OP[0]] = (SEXT40(State.a[OP[0]]) >> (State.regs[OP[1]] & 31)) & MASK40;
+ if ((GPR (OP[1]) & 31) <= 16)
+ {
+ int64 tmp = ((SEXT40(ACC (OP[0])) >> (GPR (OP[1]) & 31)) & MASK40);
+ SET_ACC (OP[0], tmp);
+ trace_output_40 (tmp);
+ }
else
{
- (*d10v_callback->printf_filtered) (d10v_callback, "ERROR: shift value %d too large.\n", State.regs[OP[1]] & 31);
+ (*d10v_callback->printf_filtered) (d10v_callback, "ERROR: shift value %d too large.\n", GPR (OP[1]) & 31);
State.exception = SIGILL;
return;
}
-
- trace_output (OP_ACCUM);
}
/* srai */
void
OP_2401 ()
{
+ int16 tmp;
trace_input ("srai", OP_REG, OP_CONSTANT16, OP_VOID);
- State.regs[OP[0]] = ((int16)(State.regs[OP[0]])) >> OP[1];
- trace_output (OP_REG);
+ tmp = (((int16)(GPR (OP[0]))) >> OP[1]);
+ SET_GPR (OP[0], tmp);
+ trace_output_16 (tmp);
}
/* srai */
void
OP_3401 ()
{
+ int64 tmp;
if (OP[1] == 0)
OP[1] = 16;
trace_input ("srai", OP_ACCUM, OP_CONSTANT16, OP_VOID);
- State.a[OP[0]] = (SEXT40(State.a[OP[0]]) >> OP[1]) & MASK40;
- trace_output (OP_ACCUM);
+ tmp = ((SEXT40(ACC (OP[0])) >> OP[1]) & MASK40);
+ SET_ACC (OP[0], tmp);
+ trace_output_40 (tmp);
}
/* srl */
void
OP_2000 ()
{
+ int16 tmp;
trace_input ("srl", OP_REG, OP_REG, OP_VOID);
- State.regs[OP[0]] >>= (State.regs[OP[1]] & 0xf);
- trace_output (OP_REG);
+ tmp = (GPR (OP[0]) >> (GPR (OP[1]) & 0xf));
+ SET_GPR (OP[0], tmp);
+ trace_output_16 (tmp);
}
/* srl */
OP_3000 ()
{
trace_input ("srl", OP_ACCUM, OP_REG, OP_VOID);
- if ((State.regs[OP[1]] & 31) <= 16)
- State.a[OP[0]] = (uint64)((State.a[OP[0]] & MASK40) >> (State.regs[OP[1]] & 31));
+ if ((GPR (OP[1]) & 31) <= 16)
+ {
+ int64 tmp = ((uint64)((ACC (OP[0]) & MASK40) >> (GPR (OP[1]) & 31)));
+ SET_ACC (OP[0], tmp);
+ trace_output_40 (tmp);
+ }
else
{
- (*d10v_callback->printf_filtered) (d10v_callback, "ERROR: shift value %d too large.\n", State.regs[OP[1]] & 31);
+ (*d10v_callback->printf_filtered) (d10v_callback, "ERROR: shift value %d too large.\n", GPR (OP[1]) & 31);
State.exception = SIGILL;
return;
}
- trace_output (OP_ACCUM);
}
/* srli */
void
OP_2001 ()
{
+ int16 tmp;
trace_input ("srli", OP_REG, OP_CONSTANT16, OP_VOID);
- State.regs[OP[0]] >>= OP[1];
- trace_output (OP_REG);
+ tmp = (GPR (OP[0]) >> OP[1]);
+ SET_GPR (OP[0], tmp);
+ trace_output_16 (tmp);
}
/* srli */
void
OP_3001 ()
{
+ int64 tmp;
if (OP[1] == 0)
OP[1] = 16;
trace_input ("srli", OP_ACCUM, OP_CONSTANT16, OP_VOID);
- State.a[OP[0]] = (uint64)(State.a[OP[0]] & MASK40) >> OP[1];
- trace_output (OP_ACCUM);
+ tmp = ((uint64)(ACC (OP[0]) & MASK40) >> OP[1]);
+ SET_ACC (OP[0], tmp);
+ trace_output_40 (tmp);
}
/* srx */
OP_4609 ()
{
uint16 tmp;
-
trace_input ("srx", OP_REG, OP_FLAG, OP_VOID);
- tmp = State.F0 << 15;
- State.regs[OP[0]] = (State.regs[OP[0]] >> 1) | tmp;
- trace_output (OP_REG);
+ tmp = PSW_F0 << 15;
+ tmp = ((GPR (OP[0]) >> 1) | tmp);
+ SET_GPR (OP[0], tmp);
+ trace_output_16 (tmp);
}
/* st */
OP_34000000 ()
{
trace_input ("st", OP_REG, OP_MEMREF2, OP_VOID);
- SW (OP[1] + State.regs[OP[2]], State.regs[OP[0]]);
- trace_output (OP_VOID);
+ SW (OP[1] + GPR (OP[2]), GPR (OP[0]));
+ trace_output_void ();
}
/* st */
OP_6800 ()
{
trace_input ("st", OP_REG, OP_MEMREF, OP_VOID);
- SW (State.regs[OP[1]], State.regs[OP[0]]);
- trace_output (OP_VOID);
+ SW (GPR (OP[1]), GPR (OP[0]));
+ trace_output_void ();
}
/* st */
void
OP_6C1F ()
{
+ uint16 addr = GPR (OP[1]) - 2;
trace_input ("st", OP_REG, OP_PREDEC, OP_VOID);
- if ( OP[1] != 15 )
+ if (OP[1] != 15)
{
(*d10v_callback->printf_filtered) (d10v_callback, "ERROR: cannot pre-decrement any registers but r15 (SP).\n");
State.exception = SIGILL;
return;
}
- State.regs[OP[1]] -= 2;
- SW (State.regs[OP[1]], State.regs[OP[0]]);
- trace_output (OP_VOID);
+ SW (addr, GPR (OP[0]));
+ SET_GPR (OP[1], addr);
+ trace_output_void ();
}
/* st */
OP_6801 ()
{
trace_input ("st", OP_REG, OP_POSTINC, OP_VOID);
- SW (State.regs[OP[1]], State.regs[OP[0]]);
- INC_ADDR (State.regs[OP[1]],2);
- trace_output (OP_VOID);
+ SW (GPR (OP[1]), GPR (OP[0]));
+ INC_ADDR (OP[1], 2);
+ trace_output_void ();
}
/* st */
State.exception = SIGILL;
return;
}
- SW (State.regs[OP[1]], State.regs[OP[0]]);
- INC_ADDR (State.regs[OP[1]],-2);
- trace_output (OP_VOID);
+ SW (GPR (OP[1]), GPR (OP[0]));
+ INC_ADDR (OP[1], -2);
+ trace_output_void ();
}
/* st2w */
OP_35000000 ()
{
trace_input ("st2w", OP_DREG, OP_MEMREF2, OP_VOID);
- SW (State.regs[OP[2]]+OP[1], State.regs[OP[0]]);
- SW (State.regs[OP[2]]+OP[1]+2, State.regs[OP[0]+1]);
- trace_output (OP_VOID);
+ SW (GPR (OP[2])+ OP[1] + 0, GPR (OP[0] + 0));
+ SW (GPR (OP[2])+ OP[1] + 2, GPR (OP[0] + 1));
+ trace_output_void ();
}
/* st2w */
OP_6A00 ()
{
trace_input ("st2w", OP_DREG, OP_MEMREF, OP_VOID);
- SW (State.regs[OP[1]], State.regs[OP[0]]);
- SW (State.regs[OP[1]]+2, State.regs[OP[0]+1]);
- trace_output (OP_VOID);
+ SW (GPR (OP[1]) + 0, GPR (OP[0] + 0));
+ SW (GPR (OP[1]) + 2, GPR (OP[0] + 1));
+ trace_output_void ();
}
/* st2w */
void
OP_6E1F ()
{
+ uint16 addr = GPR (OP[1]) - 4;
trace_input ("st2w", OP_DREG, OP_PREDEC, OP_VOID);
if ( OP[1] != 15 )
{
State.exception = SIGILL;
return;
}
- State.regs[OP[1]] -= 4;
- SW (State.regs[OP[1]], State.regs[OP[0]]);
- SW (State.regs[OP[1]]+2, State.regs[OP[0]+1]);
- trace_output (OP_VOID);
+ SW (addr + 0, GPR (OP[0] + 0));
+ SW (addr + 2, GPR (OP[0] + 1));
+ SET_GPR (OP[1], addr);
+ trace_output_void ();
}
/* st2w */
OP_6A01 ()
{
trace_input ("st2w", OP_DREG, OP_POSTINC, OP_VOID);
- SW (State.regs[OP[1]], State.regs[OP[0]]);
- SW (State.regs[OP[1]]+2, State.regs[OP[0]+1]);
- INC_ADDR (State.regs[OP[1]],4);
- trace_output (OP_VOID);
+ SW (GPR (OP[1]) + 0, GPR (OP[0] + 0));
+ SW (GPR (OP[1]) + 2, GPR (OP[0] + 1));
+ INC_ADDR (OP[1], 4);
+ trace_output_void ();
}
/* st2w */
State.exception = SIGILL;
return;
}
- SW (State.regs[OP[1]], State.regs[OP[0]]);
- SW (State.regs[OP[1]]+2, State.regs[OP[0]+1]);
- INC_ADDR (State.regs[OP[1]],-4);
- trace_output (OP_VOID);
+ SW (GPR (OP[1]) + 0, GPR (OP[0] + 0));
+ SW (GPR (OP[1]) + 2, GPR (OP[0] + 1));
+ INC_ADDR (OP[1], -4);
+ trace_output_void ();
}
/* stb */
OP_3C000000 ()
{
trace_input ("stb", OP_REG, OP_MEMREF2, OP_VOID);
- SB (State.regs[OP[2]]+OP[1], State.regs[OP[0]]);
- trace_output (OP_VOID);
+ SB (GPR (OP[2]) + OP[1], GPR (OP[0]));
+ trace_output_void ();
}
/* stb */
OP_7800 ()
{
trace_input ("stb", OP_REG, OP_MEMREF, OP_VOID);
- SB (State.regs[OP[1]], State.regs[OP[0]]);
- trace_output (OP_VOID);
+ SB (GPR (OP[1]), GPR (OP[0]));
+ trace_output_void ();
}
/* stop */
{
trace_input ("stop", OP_VOID, OP_VOID, OP_VOID);
State.exception = SIG_D10V_STOP;
- trace_output (OP_VOID);
+ trace_output_void ();
}
/* sub */
void
OP_0 ()
{
- uint16 tmp;
-
+ uint16 a = GPR (OP[0]);
+ uint16 b = GPR (OP[1]);
+ uint16 tmp = (a - b);
trace_input ("sub", OP_REG, OP_REG, OP_VOID);
/* see ../common/sim-alu.h for a more extensive discussion on how to
compute the carry/overflow bits. */
- tmp = State.regs[OP[0]] - State.regs[OP[1]];
- State.C = ((uint16) State.regs[OP[0]] >= (uint16) State.regs[OP[1]]);
- State.regs[OP[0]] = tmp;
- trace_output (OP_REG);
+ SET_PSW_C (a >= b);
+ SET_GPR (OP[0], tmp);
+ trace_output_16 (tmp);
}
/* sub */
int64 tmp;
trace_input ("sub", OP_ACCUM, OP_DREG, OP_VOID);
- tmp = SEXT40(State.a[OP[0]]) - (SEXT16 (State.regs[OP[1]]) << 16 | State.regs[OP[1]+1]);
- if (State.ST)
+ tmp = SEXT40(ACC (OP[0])) - (SEXT16 (GPR (OP[1])) << 16 | GPR (OP[1] + 1));
+ if (PSW_ST)
{
if ( tmp > MAX32)
- State.a[OP[0]] = MAX32;
+ tmp = (MAX32);
else if ( tmp < MIN32)
- State.a[OP[0]] = MIN32;
+ tmp = (MIN32);
else
- State.a[OP[0]] = tmp & MASK40;
+ tmp = (tmp & MASK40);
}
else
- State.a[OP[0]] = tmp & MASK40;
+ tmp = (tmp & MASK40);
+ SET_ACC (OP[0], tmp);
- trace_output (OP_ACCUM);
+ trace_output_40 (tmp);
}
/* sub */
int64 tmp;
trace_input ("sub", OP_ACCUM, OP_ACCUM, OP_VOID);
- tmp = SEXT40(State.a[OP[0]]) - SEXT40(State.a[OP[1]]);
- if (State.ST)
+ tmp = SEXT40(ACC (OP[0])) - SEXT40(ACC (OP[1]));
+ if (PSW_ST)
{
if (tmp > MAX32)
- State.a[OP[0]] = MAX32;
+ tmp = (MAX32);
else if ( tmp < MIN32)
- State.a[OP[0]] = MIN32;
+ tmp = (MIN32);
else
- State.a[OP[0]] = tmp & MASK40;
+ tmp = (tmp & MASK40);
}
else
- State.a[OP[0]] = tmp & MASK40;
+ tmp = (tmp & MASK40);
+ SET_ACC (OP[0], tmp);
- trace_output (OP_ACCUM);
+ trace_output_40 (tmp);
}
/* sub2w */
void
OP_1000 ()
{
- uint32 tmp,a,b;
+ uint32 tmp, a, b;
trace_input ("sub2w", OP_DREG, OP_DREG, OP_VOID);
- a = (uint32)((State.regs[OP[0]] << 16) | State.regs[OP[0]+1]);
- b = (uint32)((State.regs[OP[1]] << 16) | State.regs[OP[1]+1]);
+ a = (uint32)((GPR (OP[0]) << 16) | GPR (OP[0] + 1));
+ b = (uint32)((GPR (OP[1]) << 16) | GPR (OP[1] + 1));
/* see ../common/sim-alu.h for a more extensive discussion on how to
compute the carry/overflow bits */
tmp = a - b;
- State.C = (a >= b);
- State.regs[OP[0]] = (tmp >> 16) & 0xffff;
- State.regs[OP[0]+1] = tmp & 0xffff;
- trace_output (OP_DREG);
+ SET_PSW_C (a >= b);
+ SET_GPR32 (OP[0], tmp);
+ trace_output_32 (tmp);
}
/* subac3 */
int64 tmp;
trace_input ("subac3", OP_DREG_OUTPUT, OP_DREG, OP_ACCUM);
- tmp = SEXT40 ((State.regs[OP[1]] << 16) | State.regs[OP[1]+1]) - SEXT40 (State.a[OP[2]]);
- State.regs[OP[0]] = (tmp >> 16) & 0xffff;
- State.regs[OP[0]+1] = tmp & 0xffff;
- trace_output (OP_DREG);
+ tmp = SEXT40 ((GPR (OP[1]) << 16) | GPR (OP[1] + 1)) - SEXT40 (ACC (OP[2]));
+ SET_GPR32 (OP[0], tmp);
+ trace_output_32 (tmp);
}
/* subac3 */
int64 tmp;
trace_input ("subac3", OP_DREG_OUTPUT, OP_ACCUM, OP_ACCUM);
- tmp = SEXT40(State.a[OP[1]]) - SEXT40(State.a[OP[2]]);
- State.regs[OP[0]] = (tmp >> 16) & 0xffff;
- State.regs[OP[0]+1] = tmp & 0xffff;
- trace_output (OP_DREG);
+ tmp = SEXT40 (ACC (OP[1])) - SEXT40(ACC (OP[2]));
+ SET_GPR32 (OP[0], tmp);
+ trace_output_32 (tmp);
}
/* subac3s */
int64 tmp;
trace_input ("subac3s", OP_DREG_OUTPUT, OP_DREG, OP_ACCUM);
- State.F1 = State.F0;
- tmp = SEXT40 ((State.regs[OP[1]] << 16) | State.regs[OP[1]+1]) - SEXT40(State.a[OP[2]]);
+ SET_PSW_F1 (PSW_F0);
+ tmp = SEXT40 ((GPR (OP[1]) << 16) | GPR (OP[1] + 1)) - SEXT40(ACC (OP[2]));
if ( tmp > MAX32)
{
- State.regs[OP[0]] = 0x7fff;
- State.regs[OP[0]+1] = 0xffff;
- State.F0 = 1;
+ tmp = 0x7fffffff;
+ SET_PSW_F0 (1);
}
else if (tmp < MIN32)
{
- State.regs[OP[0]] = 0x8000;
- State.regs[OP[0]+1] = 0;
- State.F0 = 1;
+ tmp = 0x80000000;
+ SET_PSW_F0 (1);
}
else
{
- State.regs[OP[0]] = (tmp >> 16) & 0xffff;
- State.regs[OP[0]+1] = tmp & 0xffff;
- State.F0 = 0;
+ SET_PSW_F0 (0);
}
- trace_output (OP_DREG);
+ SET_GPR32 (OP[0], tmp);
+ trace_output_32 (tmp);
}
/* subac3s */
int64 tmp;
trace_input ("subac3s", OP_DREG_OUTPUT, OP_ACCUM, OP_ACCUM);
- State.F1 = State.F0;
- tmp = SEXT40(State.a[OP[1]]) - SEXT40(State.a[OP[2]]);
+ SET_PSW_F1 (PSW_F0);
+ tmp = SEXT40(ACC (OP[1])) - SEXT40(ACC (OP[2]));
if ( tmp > MAX32)
{
- State.regs[OP[0]] = 0x7fff;
- State.regs[OP[0]+1] = 0xffff;
- State.F0 = 1;
+ tmp = 0x7fffffff;
+ SET_PSW_F0 (1);
}
else if (tmp < MIN32)
{
- State.regs[OP[0]] = 0x8000;
- State.regs[OP[0]+1] = 0;
- State.F0 = 1;
+ tmp = 0x80000000;
+ SET_PSW_F0 (1);
}
else
{
- State.regs[OP[0]] = (tmp >> 16) & 0xffff;
- State.regs[OP[0]+1] = tmp & 0xffff;
- State.F0 = 0;
+ SET_PSW_F0 (0);
}
- trace_output (OP_DREG);
+ SET_GPR32 (OP[0], tmp);
+ trace_output_32 (tmp);
}
/* subi */
/* see ../common/sim-alu.h for a more extensive discussion on how to
compute the carry/overflow bits. */
/* since OP[1] is never <= 0, -OP[1] == ~OP[1]+1 can never overflow */
- tmp = ((unsigned)(unsigned16) State.regs[OP[0]]
+ tmp = ((unsigned)(unsigned16) GPR (OP[0])
+ (unsigned)(unsigned16) ( - OP[1]));
- State.C = (tmp >= (1 << 16));
- State.regs[OP[0]] = tmp;
- trace_output (OP_REG);
+ SET_PSW_C (tmp >= (1 << 16));
+ SET_GPR (OP[0], tmp);
+ trace_output_16 (tmp);
}
/* trap */
OP_5F00 ()
{
trace_input ("trap", OP_CONSTANT4, OP_VOID, OP_VOID);
- trace_output (OP_VOID);
+ trace_output_void ();
switch (OP[0])
{
#if (DEBUG & DEBUG_TRAP) == 0
{
uint16 vec = OP[0] + TRAP_VECTOR_START;
- BPC = PC + 1;
- move_to_cr (BPSW_CR, PSW);
- move_to_cr (PSW_CR, PSW & PSW_SM_BIT);
+ SET_BPC (PC + 1);
+ SET_BPSW (PSW);
+ SET_PSW (PSW & PSW_SM_BIT);
JMP (vec);
break;
}
(*d10v_callback->printf_filtered) (d10v_callback, "Trap %2d 0x%.4x:", (int)OP[0], (int)PC);
for (i = 0; i < 16; i++)
- (*d10v_callback->printf_filtered) (d10v_callback, " %.4x", (int) State.regs[i]);
+ (*d10v_callback->printf_filtered) (d10v_callback, " %.4x", (int) GPR (i));
for (i = 0; i < 2; i++)
(*d10v_callback->printf_filtered) (d10v_callback, " %.2x%.8lx",
- ((int)(State.a[i] >> 32) & 0xff),
- ((unsigned long)State.a[i]) & 0xffffffff);
+ ((int)(ACC (i) >> 32) & 0xff),
+ ((unsigned long) ACC (i)) & 0xffffffff);
(*d10v_callback->printf_filtered) (d10v_callback, " %d %d %d\n",
- State.F0 != 0, State.F1 != 0, State.C != 0);
+ PSW_F0 != 0, PSW_F1 != 0, PSW_C != 0);
(*d10v_callback->flush_stdout) (d10v_callback);
break;
}
case 15: /* new system call trap */
/* Trap 15 is used for simulating low-level I/O */
{
+ unsigned32 result = 0;
errno = 0;
/* Registers passed to trap 0 */
-#define FUNC State.regs[4] /* function number */
-#define PARM1 State.regs[0] /* optional parm 1 */
-#define PARM2 State.regs[1] /* optional parm 2 */
-#define PARM3 State.regs[2] /* optional parm 3 */
-#define PARM4 State.regs[3] /* optional parm 3 */
+#define FUNC GPR (4) /* function number */
+#define PARM1 GPR (0) /* optional parm 1 */
+#define PARM2 GPR (1) /* optional parm 2 */
+#define PARM3 GPR (2) /* optional parm 3 */
+#define PARM4 GPR (3) /* optional parm 3 */
/* Registers set by trap 0 */
-#define RETVAL State.regs[0] /* return value */
-#define RETVAL_HIGH State.regs[0] /* return value */
-#define RETVAL_LOW State.regs[1] /* return value */
-#define RETERR State.regs[4] /* return error code */
+#define RETVAL(X) do { result = (X); SET_GPR (0, result); } while (0)
+#define RETVAL32(X) do { result = (X); SET_GPR (0, result >> 16); SET_GPR (1, result); } while (0)
+#define RETERR(X) SET_GPR (4, (X)) /* return error code */
/* Turn a pointer in a register into a pointer into real memory. */
switch (FUNC)
{
#if !defined(__GO32__) && !defined(_WIN32)
- case SYS_fork:
- RETVAL = fork ();
+ case TARGET_SYS_fork:
trace_input ("<fork>", OP_VOID, OP_VOID, OP_VOID);
- trace_output (OP_R0);
+ RETVAL (fork ());
+ trace_output_16 (result);
break;
- case SYS_getpid:
+#define getpid() 47
+ case TARGET_SYS_getpid:
trace_input ("<getpid>", OP_VOID, OP_VOID, OP_VOID);
- RETVAL = getpid ();
- trace_output (OP_R0);
+ RETVAL (getpid ());
+ trace_output_16 (result);
break;
- case SYS_kill:
- trace_input ("<kill>", OP_REG, OP_REG, OP_VOID);
+ case TARGET_SYS_kill:
+ trace_input ("<kill>", OP_R0, OP_R1, OP_VOID);
if (PARM1 == getpid ())
{
- trace_output (OP_VOID);
+ trace_output_void ();
State.exception = PARM2;
}
else
if (os_sig == -1)
{
- trace_output (OP_VOID);
+ trace_output_void ();
(*d10v_callback->printf_filtered) (d10v_callback, "Unknown signal %d\n", PARM2);
(*d10v_callback->flush_stdout) (d10v_callback);
State.exception = SIGILL;
}
else
{
- RETVAL = kill (PARM1, PARM2);
- trace_output (OP_R0);
+ RETVAL (kill (PARM1, PARM2));
+ trace_output_16 (result);
}
}
break;
- case SYS_execve:
- RETVAL = execve (MEMPTR (PARM1), (char **) MEMPTR (PARM2),
- (char **)MEMPTR (PARM3));
+ case TARGET_SYS_execve:
trace_input ("<execve>", OP_R0, OP_R1, OP_R2);
- trace_output (OP_R0);
+ RETVAL (execve (MEMPTR (PARM1), (char **) MEMPTR (PARM2),
+ (char **)MEMPTR (PARM3)));
+ trace_output_16 (result);
break;
-#ifdef SYS_execv
- case SYS_execv:
- RETVAL = execve (MEMPTR (PARM1), (char **) MEMPTR (PARM2), NULL);
+#ifdef TARGET_SYS_execv
+ case TARGET_SYS_execv:
trace_input ("<execv>", OP_R0, OP_R1, OP_VOID);
- trace_output (OP_R0);
+ RETVAL (execve (MEMPTR (PARM1), (char **) MEMPTR (PARM2), NULL));
+ trace_output_16 (result);
break;
#endif
- case SYS_pipe:
+ case TARGET_SYS_pipe:
{
reg_t buf;
int host_fd[2];
+ trace_input ("<pipe>", OP_R0, OP_VOID, OP_VOID);
buf = PARM1;
- RETVAL = pipe (host_fd);
+ RETVAL (pipe (host_fd));
SW (buf, host_fd[0]);
buf += sizeof(uint16);
SW (buf, host_fd[1]);
- trace_input ("<pipe>", OP_R0, OP_VOID, OP_VOID);
- trace_output (OP_R0);
+ trace_output_16 (result);
}
break;
-#ifdef SYS_wait
- case SYS_wait:
+#if 0
+#ifdef TARGET_SYS_wait
+ case TARGET_SYS_wait:
{
int status;
-
- RETVAL = wait (&status);
+ trace_input ("<wait>", OP_R0, OP_VOID, OP_VOID);
+ RETVAL (wait (&status));
if (PARM1)
SW (PARM1, status);
- trace_input ("<wait>", OP_R0, OP_VOID, OP_VOID);
- trace_output (OP_R0);
+ trace_output_16 (result);
}
break;
#endif
+#endif
#else
- case SYS_getpid:
+ case TARGET_SYS_getpid:
trace_input ("<getpid>", OP_VOID, OP_VOID, OP_VOID);
- RETVAL = 1;
- trace_output (OP_R0);
+ RETVAL (1);
+ trace_output_16 (result);
break;
- case SYS_kill:
+ case TARGET_SYS_kill:
trace_input ("<kill>", OP_REG, OP_REG, OP_VOID);
- trace_output (OP_VOID);
+ trace_output_void ();
State.exception = PARM2;
break;
#endif
- case SYS_read:
- RETVAL = d10v_callback->read (d10v_callback, PARM1, MEMPTR (PARM2),
- PARM3);
+ case TARGET_SYS_read:
trace_input ("<read>", OP_R0, OP_R1, OP_R2);
- trace_output (OP_R0);
+ RETVAL (d10v_callback->read (d10v_callback, PARM1, MEMPTR (PARM2),
+ PARM3));
+ trace_output_16 (result);
break;
- case SYS_write:
+ case TARGET_SYS_write:
+ trace_input ("<write>", OP_R0, OP_R1, OP_R2);
if (PARM1 == 1)
- RETVAL = (int)d10v_callback->write_stdout (d10v_callback,
- MEMPTR (PARM2), PARM3);
+ RETVAL ((int)d10v_callback->write_stdout (d10v_callback,
+ MEMPTR (PARM2), PARM3));
else
- RETVAL = (int)d10v_callback->write (d10v_callback, PARM1,
- MEMPTR (PARM2), PARM3);
- trace_input ("<write>", OP_R0, OP_R1, OP_R2);
- trace_output (OP_R0);
+ RETVAL ((int)d10v_callback->write (d10v_callback, PARM1,
+ MEMPTR (PARM2), PARM3));
+ trace_output_16 (result);
break;
- case SYS_lseek:
- {
- unsigned long ret = d10v_callback->lseek (d10v_callback, PARM1,
- (((unsigned long)PARM2) << 16) || (unsigned long)PARM3,
- PARM4);
- RETVAL_HIGH = ret >> 16;
- RETVAL_LOW = ret & 0xffff;
- }
+ case TARGET_SYS_lseek:
trace_input ("<lseek>", OP_R0, OP_R1, OP_R2);
- trace_output (OP_R0R1);
+ RETVAL32 (d10v_callback->lseek (d10v_callback, PARM1,
+ ((((unsigned long) PARM2) << 16)
+ || (unsigned long) PARM3),
+ PARM4));
+ trace_output_32 (result);
break;
- case SYS_close:
- RETVAL = d10v_callback->close (d10v_callback, PARM1);
+ case TARGET_SYS_close:
trace_input ("<close>", OP_R0, OP_VOID, OP_VOID);
- trace_output (OP_R0);
+ RETVAL (d10v_callback->close (d10v_callback, PARM1));
+ trace_output_16 (result);
break;
- case SYS_open:
- RETVAL = d10v_callback->open (d10v_callback, MEMPTR (PARM1), PARM2);
- trace_input ("<open>", OP_R0, OP_R1, OP_R2);
- trace_output (OP_R0);
+ case TARGET_SYS_open:
trace_input ("<open>", OP_R0, OP_R1, OP_R2);
- trace_output (OP_R0);
+ RETVAL (d10v_callback->open (d10v_callback, MEMPTR (PARM1), PARM2));
+ trace_output_16 (result);
break;
- case SYS_exit:
- State.exception = SIG_D10V_EXIT;
+ case TARGET_SYS_exit:
trace_input ("<exit>", OP_R0, OP_VOID, OP_VOID);
- trace_output (OP_VOID);
+ State.exception = SIG_D10V_EXIT;
+ trace_output_void ();
break;
- case SYS_stat:
+ case TARGET_SYS_stat:
+ trace_input ("<stat>", OP_R0, OP_R1, OP_VOID);
/* stat system call */
{
struct stat host_stat;
reg_t buf;
- RETVAL = stat (MEMPTR (PARM1), &host_stat);
+ RETVAL (stat (MEMPTR (PARM1), &host_stat));
buf = PARM2;
SLW (buf+28, host_stat.st_mtime);
SLW (buf+36, host_stat.st_ctime);
}
- trace_input ("<stat>", OP_R0, OP_R1, OP_VOID);
- trace_output (OP_R0);
+ trace_output_16 (result);
break;
- case SYS_chown:
- RETVAL = chown (MEMPTR (PARM1), PARM2, PARM3);
+ case TARGET_SYS_chown:
trace_input ("<chown>", OP_R0, OP_R1, OP_R2);
- trace_output (OP_R0);
+ RETVAL (chown (MEMPTR (PARM1), PARM2, PARM3));
+ trace_output_16 (result);
break;
- case SYS_chmod:
- RETVAL = chmod (MEMPTR (PARM1), PARM2);
+ case TARGET_SYS_chmod:
trace_input ("<chmod>", OP_R0, OP_R1, OP_R2);
- trace_output (OP_R0);
+ RETVAL (chmod (MEMPTR (PARM1), PARM2));
+ trace_output_16 (result);
break;
-#ifdef SYS_utime
- case SYS_utime:
+#if 0
+#ifdef TARGET_SYS_utime
+ case TARGET_SYS_utime:
+ trace_input ("<utime>", OP_R0, OP_R1, OP_R2);
/* Cast the second argument to void *, to avoid type mismatch
if a prototype is present. */
- RETVAL = utime (MEMPTR (PARM1), (void *) MEMPTR (PARM2));
- trace_input ("<utime>", OP_R0, OP_R1, OP_R2);
- trace_output (OP_R0);
+ RETVAL (utime (MEMPTR (PARM1), (void *) MEMPTR (PARM2)));
+ trace_output_16 (result);
break;
#endif
+#endif
-#ifdef SYS_time
- case SYS_time:
- {
- unsigned long ret = time (PARM1 ? MEMPTR (PARM1) : NULL);
- RETVAL_HIGH = ret >> 16;
- RETVAL_LOW = ret & 0xffff;
- }
+#if 0
+#ifdef TARGET_SYS_time
+ case TARGET_SYS_time:
trace_input ("<time>", OP_R0, OP_R1, OP_R2);
- trace_output (OP_R0R1);
+ RETVAL32 (time (PARM1 ? MEMPTR (PARM1) : NULL));
+ trace_output_32 (result);
break;
+#endif
#endif
default:
d10v_callback->error (d10v_callback, "Unknown syscall %d", FUNC);
}
- RETERR = (RETVAL == (uint16) -1) ? d10v_callback->get_errno(d10v_callback) : 0;
+ if ((uint16) result == (uint16) -1)
+ RETERR (d10v_callback->get_errno(d10v_callback));
+ else
+ RETERR (0);
break;
}
}
OP_7000000 ()
{
trace_input ("tst0i", OP_REG, OP_CONSTANT16, OP_VOID);
- State.F1 = State.F0;
- State.F0 = (State.regs[OP[0]] & OP[1]) ? 1 : 0;
- trace_output (OP_FLAG);
+ SET_PSW_F1 (PSW_F0);;
+ SET_PSW_F0 ((GPR (OP[0]) & OP[1]) ? 1 : 0);
+ trace_output_flag ();
}
/* tst1i */
OP_F000000 ()
{
trace_input ("tst1i", OP_REG, OP_CONSTANT16, OP_VOID);
- State.F1 = State.F0;
- State.F0 = (~(State.regs[OP[0]]) & OP[1]) ? 1 : 0;
- trace_output (OP_FLAG);
+ SET_PSW_F1 (PSW_F0);
+ SET_PSW_F0 ((~(GPR (OP[0])) & OP[1]) ? 1 : 0);
+ trace_output_flag ();
}
/* wait */
OP_5F80 ()
{
trace_input ("wait", OP_VOID, OP_VOID, OP_VOID);
- State.IE = 1;
- trace_output (OP_VOID);
+ SET_PSW_IE (1);
+ trace_output_void ();
}
/* xor */
void
OP_A00 ()
{
+ int16 tmp;
trace_input ("xor", OP_REG, OP_REG, OP_VOID);
- State.regs[OP[0]] ^= State.regs[OP[1]];
- trace_output (OP_REG);
+ tmp = (GPR (OP[0]) ^ GPR (OP[1]));
+ SET_GPR (OP[0], tmp);
+ trace_output_16 (tmp);
}
/* xor3 */
void
OP_5000000 ()
{
+ int16 tmp;
trace_input ("xor3", OP_REG_OUTPUT, OP_REG, OP_CONSTANT16);
- State.regs[OP[0]] = State.regs[OP[1]] ^ OP[2];
- trace_output (OP_REG);
+ tmp = (GPR (OP[1]) ^ OP[2]);
+ SET_GPR (OP[0], tmp);
+ trace_output_16 (tmp);
}
projects / thirdparty / binutils-gdb.git / commitdiff
