sim: pru: Add support for LMBD instruction

Binutils support for LMBD instruction was merged [1]. So add it also
to simulator.

LMBD instruction does left-most-bit-detection. It returns 32 if
the given bit value is not found in the provided word value.

[1] https://sourceware.org/pipermail/binutils/2020-October/113901.html

sim/pru/ChangeLog:

	* pru.h (RS1SEL): New macro.
	(RS1_WIDTH): New macro.
	* pru.isa: Describe the LMBD instruction.

sim/testsuite/sim/pru/ChangeLog:

	* lmbd.s: New test.

diff --git a/sim/pru/ChangeLog b/sim/pru/ChangeLog
index bccc3efd5314d818d34744ee8988e5bc6063e9ed..ad9aff9408b1c0a20e2cb1d94760824fba512c8f 100644 (file)
--- a/sim/pru/ChangeLog
+++ b/sim/pru/ChangeLog
@@ -1,3 +1,9 @@
+2020-11-12  Dimitar Dimitrov  <dimitar@dinux.eu>
+
+       * pru.h (RS1SEL): New macro.
+       (RS1_WIDTH): New macro.
+       * pru.isa: Describe the LMBD instruction.
+
 2019-09-23  Dimitar Dimitrov  <dimitar@dinux.eu>
 
        * Makefile.in: New file.

diff --git a/sim/pru/pru.h b/sim/pru/pru.h
index 240fc30010c5c3a9daeff6aa086155fbaaef3aef..cbcc3ef9d78c3bc8716e88531e426ce0f41e16fe 100644 (file)
--- a/sim/pru/pru.h
+++ b/sim/pru/pru.h
@@ -58,6 +58,8 @@
 
 #define XBBO_BASEREG (CPU.regs[GET_INSN_FIELD (RS1, inst)])
 
+#define RS1SEL GET_INSN_FIELD (RS1SEL, inst)
+#define RS1_WIDTH regsel_width (RS1SEL)
 #define RDSEL GET_INSN_FIELD (RDSEL, inst)
 #define RD_WIDTH regsel_width (RDSEL)
 #define RD_REGN GET_INSN_FIELD (RD, inst)

diff --git a/sim/pru/pru.isa b/sim/pru/pru.isa
index 050154560bcc04168d00dcc6e41dd13e8e5c0315..c7860d0191b9fc908294d4a3bb1a8c83c603f411 100644 (file)
--- a/sim/pru/pru.isa
+++ b/sim/pru/pru.isa
@@ -247,3 +247,18 @@ INSTRUCTION (iloop,
                LOOP_IN_PROGRESS = 1;
                PC++;
             })
+
+INSTRUCTION (lmbd,
+            {
+            int lmbd_i;
+
+            OP2 = (IO ? IMM8 : RS2);
+
+            for (lmbd_i = RS1_WIDTH - 1; lmbd_i >= 0; lmbd_i--)
+              {
+                if (!(((RS1 >> lmbd_i) ^ OP2) & 1))
+                  break;
+              }
+            RD = (lmbd_i < 0) ? 32 : lmbd_i;
+            PC++;
+            })

diff --git a/sim/testsuite/sim/pru/ChangeLog b/sim/testsuite/sim/pru/ChangeLog
index d8b438bb45fc76dc449cb061a3912a7386b597e0..3d862d13da2ab1f484643d0bce91d1d955dbccbc 100644 (file)
--- a/sim/testsuite/sim/pru/ChangeLog
+++ b/sim/testsuite/sim/pru/ChangeLog
@@ -1,3 +1,7 @@
+2020-11-12  Dimitar Dimitrov  <dimitar@dinux.eu>
+
+       * lmbd.s: New test.
+
 2019-09-23  Dimitar Dimitrov  <dimitar@dinux.eu>
 
        * add.s: New test.

diff --git a/sim/testsuite/sim/pru/lmbd.s b/sim/testsuite/sim/pru/lmbd.s
new file mode 100644 (file)
index 0000000..9a9e782
--- /dev/null
+++ b/sim/testsuite/sim/pru/lmbd.s
@@ -0,0 +1,61 @@
+# Check that lmbd insn works.
+# mach: pru
+
+# Copyright (C) 2020 Free Software Foundation, Inc.
+# Contributed by Dimitar Dimitrov <dimitar@dinux.eu>
+#
+# This file is part of the GNU simulators.
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program.  If not, see <http://www.gnu.org/licenses/>.
+
+.include "testutils.inc"
+
+       start
+
+       ldi32 r14, 0xffffffff
+       ldi32 r15, 0x0
+       ldi32 r16, 0x40000000
+       ldi32 r17, 8
+
+       lmbd r0, r14, 0
+       qbne 2f, r0, 32
+
+       lmbd r0, r14, 1
+       qbne 2f, r0, 31
+
+       lmbd r0, r15, 1
+       qbne 2f, r0, 32
+
+       lmbd r0, r15, 0
+       qbne 2f, r0, 31
+
+       lmbd r0, r16, r15
+       qbne 2f, r0, 31
+
+       lmbd r0, r16, 1
+       qbne 2f, r0, 30
+
+       lmbd r0, r14.w1, 1
+       qbne 2f, r0, 15
+
+       lmbd r0, r17.b0, 1
+       qbne 2f, r0, 3
+
+       lmbd r0, r17.b0, r15
+       qbne 2f, r0, 7
+
+
+1:
+       pass
+2:     fail