This old port setup its own uintXX types, but since we require C11
now, we can assume the standard uintXX_t types exist and use them.
Also migrate off the sim-specific unsignedXX types.
#include "sim-config.h"
#include "sim-types.h"
#include "sim-config.h"
#include "sim-types.h"
-typedef unsigned8 uint8;
-typedef unsigned16 uint16;
-typedef signed16 int16;
-typedef unsigned32 uint32;
-typedef signed32 int32;
-typedef unsigned64 uint64;
-typedef signed64 int64;
-
/* FIXME: D10V defines */
/* FIXME: D10V defines */
- uint8 *insn[IMEM_SEGMENTS];
- uint8 *data[DMEM_SEGMENTS];
- uint8 *unif[UMEM_SEGMENTS];
+ uint8_t *insn[IMEM_SEGMENTS];
+ uint8_t *data[DMEM_SEGMENTS];
+ uint8_t *unif[UMEM_SEGMENTS];
#define GPR(N) (State.regs[(N)] + 0)
#define SET_GPR(N,VAL) SLOT_PEND (State.regs[(N)], (VAL))
#define GPR(N) (State.regs[(N)] + 0)
#define SET_GPR(N,VAL) SLOT_PEND (State.regs[(N)], (VAL))
-#define GPR32(N) ((((uint32) State.regs[(N) + 0]) << 16) \
- | (uint16) State.regs[(N) + 1])
+#define GPR32(N) ((((uint32_t) State.regs[(N) + 0]) << 16) \
+ | (uint16_t) State.regs[(N) + 1])
#define SET_GPR32(N,VAL) do { SET_GPR (OP[0] + 0, (VAL) >> 16); SET_GPR (OP[0] + 1, (VAL)); } while (0)
reg_t cregs[16]; /* control registers */
#define SET_GPR32(N,VAL) do { SET_GPR (OP[0] + 0, (VAL) >> 16); SET_GPR (OP[0] + 1, (VAL)); } while (0)
reg_t cregs[16]; /* control registers */
#define HELD_SP(N) (State.sp[(N)] + 0)
#define SET_HELD_SP(N,VAL) SLOT_PEND (State.sp[(N)], (VAL))
#define HELD_SP(N) (State.sp[(N)] + 0)
#define SET_HELD_SP(N,VAL) SLOT_PEND (State.sp[(N)], (VAL))
- int64 a[2]; /* accumulators */
+ int64_t a[2]; /* accumulators */
#define ACC(N) (State.a[(N)] + 0)
#define SET_ACC(N,VAL) SLOT_PEND (State.a[(N)], (VAL) & MASK40)
#define ACC(N) (State.a[(N)] + 0)
#define SET_ACC(N,VAL) SLOT_PEND (State.a[(N)], (VAL) & MASK40)
/* trace data */
struct {
/* trace data */
struct {
int pc_changed;
/* NOTE: everything below this line is not reset by
int pc_changed;
/* NOTE: everything below this line is not reset by
extern struct _state State;
extern struct _state State;
extern struct simops Simops[];
enum
extern struct simops Simops[];
enum
-extern uint8 *dmem_addr (SIM_DESC, SIM_CPU *, uint16 offset);
-extern uint8 *imem_addr (SIM_DESC, SIM_CPU *, uint32);
+extern uint8_t *dmem_addr (SIM_DESC, SIM_CPU *, uint16_t offset);
+extern uint8_t *imem_addr (SIM_DESC, SIM_CPU *, uint32_t);
#define RB(x) (*(dmem_addr (sd, cpu, x)))
#define SB(addr,data) ( RB(addr) = (data & 0xff))
#define RB(x) (*(dmem_addr (sd, cpu, x)))
#define SB(addr,data) ( RB(addr) = (data & 0xff))
#undef ENDIAN_INLINE
#else
#undef ENDIAN_INLINE
#else
-extern uint32 get_longword (uint8 *);
-extern uint16 get_word (uint8 *);
-extern int64 get_longlong (uint8 *);
-extern void write_word (uint8 *addr, uint16 data);
-extern void write_longword (uint8 *addr, uint32 data);
-extern void write_longlong (uint8 *addr, int64 data);
+extern uint32_t get_longword (uint8_t *);
+extern uint16_t get_word (uint8_t *);
+extern int64_t get_longlong (uint8_t *);
+extern void write_word (uint8_t *addr, uint16_t data);
+extern void write_longword (uint8_t *addr, uint32_t data);
+extern void write_longlong (uint8_t *addr, int64_t data);
#endif
#define SW(addr,data) write_word (dmem_addr (sd, cpu, addr), data)
#endif
#define SW(addr,data) write_word (dmem_addr (sd, cpu, addr), data)
#define ENDIAN_INLINE
#endif
#define ENDIAN_INLINE
#endif
-ENDIAN_INLINE uint16
-get_word (uint8 *x)
+ENDIAN_INLINE uint16_t
+get_word (uint8_t *x)
- return ((uint16)x[0]<<8) + x[1];
+ return ((uint16_t)x[0]<<8) + x[1];
-ENDIAN_INLINE uint32
-get_longword (uint8 *x)
+ENDIAN_INLINE uint32_t
+get_longword (uint8_t *x)
- return ((uint32)x[0]<<24) + ((uint32)x[1]<<16) + ((uint32)x[2]<<8) + ((uint32)x[3]);
+ return ((uint32_t)x[0]<<24) + ((uint32_t)x[1]<<16) + ((uint32_t)x[2]<<8) + ((uint32_t)x[3]);
-ENDIAN_INLINE int64
-get_longlong (uint8 *x)
+ENDIAN_INLINE int64_t
+get_longlong (uint8_t *x)
- uint32 top = get_longword (x);
- uint32 bottom = get_longword (x+4);
- return (((int64)top)<<32) | (int64)bottom;
+ uint32_t top = get_longword (x);
+ uint32_t bottom = get_longword (x+4);
+ return (((int64_t)top)<<32) | (int64_t)bottom;
-write_word (uint8 *addr, uint16 data)
+write_word (uint8_t *addr, uint16_t data)
{
addr[0] = (data >> 8) & 0xff;
addr[1] = data & 0xff;
}
ENDIAN_INLINE void
{
addr[0] = (data >> 8) & 0xff;
addr[1] = data & 0xff;
}
ENDIAN_INLINE void
-write_longword (uint8 *addr, uint32 data)
+write_longword (uint8_t *addr, uint32_t data)
{
addr[0] = (data >> 24) & 0xff;
addr[1] = (data >> 16) & 0xff;
{
addr[0] = (data >> 24) & 0xff;
addr[1] = (data >> 16) & 0xff;
-write_longlong (uint8 *addr, int64 data)
+write_longlong (uint8_t *addr, int64_t data)
- write_longword (addr, (uint32)(data >> 32));
- write_longword (addr+4, (uint32)data);
+ write_longword (addr, (uint32_t)(data >> 32));
+ write_longword (addr+4, (uint32_t)data);
unsigned long ins_type_counters[ (int)INS_MAX ];
unsigned long ins_type_counters[ (int)INS_MAX ];
static long hash (long insn, int format);
static long hash (long insn, int format);
-static struct hash_entry *lookup_hash (SIM_DESC, SIM_CPU *, uint32 ins, int size);
-static void get_operands (struct simops *s, uint32 ins);
-static void do_long (SIM_DESC, SIM_CPU *, uint32 ins);
-static void do_2_short (SIM_DESC, SIM_CPU *, uint16 ins1, uint16 ins2, enum _leftright leftright);
-static void do_parallel (SIM_DESC, SIM_CPU *, uint16 ins1, uint16 ins2);
+static struct hash_entry *lookup_hash (SIM_DESC, SIM_CPU *, uint32_t ins, int size);
+static void get_operands (struct simops *s, uint32_t ins);
+static void do_long (SIM_DESC, SIM_CPU *, uint32_t ins);
+static void do_2_short (SIM_DESC, SIM_CPU *, uint16_t ins1, uint16_t ins2, enum _leftright leftright);
+static void do_parallel (SIM_DESC, SIM_CPU *, uint16_t ins1, uint16_t ins2);
static char *add_commas (char *buf, int sizeof_buf, unsigned long value);
static char *add_commas (char *buf, int sizeof_buf, unsigned long value);
-static INLINE uint8 *map_memory (SIM_DESC, SIM_CPU *, unsigned phys_addr);
+static INLINE uint8_t *map_memory (SIM_DESC, SIM_CPU *, unsigned phys_addr);
#define MAX_HASH 63
struct hash_entry
{
struct hash_entry *next;
#define MAX_HASH 63
struct hash_entry
{
struct hash_entry *next;
- uint32 opcode;
- uint32 mask;
+ uint32_t opcode;
+ uint32_t mask;
int size;
struct simops *ops;
};
int size;
struct simops *ops;
};
}
INLINE static struct hash_entry *
}
INLINE static struct hash_entry *
-lookup_hash (SIM_DESC sd, SIM_CPU *cpu, uint32 ins, int size)
+lookup_hash (SIM_DESC sd, SIM_CPU *cpu, uint32_t ins, int size)
-get_operands (struct simops *s, uint32 ins)
+get_operands (struct simops *s, uint32_t ins)
{
int i, shift, bits, flags;
{
int i, shift, bits, flags;
for (i=0; i < s->numops; i++)
{
shift = s->operands[3*i];
for (i=0; i < s->numops; i++)
{
shift = s->operands[3*i];
-do_long (SIM_DESC sd, SIM_CPU *cpu, uint32 ins)
+do_long (SIM_DESC sd, SIM_CPU *cpu, uint32_t ins)
{
struct hash_entry *h;
#ifdef DEBUG
{
struct hash_entry *h;
#ifdef DEBUG
-do_2_short (SIM_DESC sd, SIM_CPU *cpu, uint16 ins1, uint16 ins2, enum _leftright leftright)
+do_2_short (SIM_DESC sd, SIM_CPU *cpu, uint16_t ins1, uint16_t ins2, enum _leftright leftright)
{
struct hash_entry *h;
enum _ins_type first, second;
{
struct hash_entry *h;
enum _ins_type first, second;
-do_parallel (SIM_DESC sd, SIM_CPU *cpu, uint16 ins1, uint16 ins2)
+do_parallel (SIM_DESC sd, SIM_CPU *cpu, uint16_t ins1, uint16_t ins2)
{
struct hash_entry *h1, *h2;
#ifdef DEBUG
{
struct hash_entry *h1, *h2;
#ifdef DEBUG
static void
set_dmap_register (SIM_DESC sd, int reg_nr, unsigned long value)
{
static void
set_dmap_register (SIM_DESC sd, int reg_nr, unsigned long value)
{
- uint8 *raw = map_memory (sd, NULL, SIM_D10V_MEMORY_DATA
+ uint8_t *raw = map_memory (sd, NULL, SIM_D10V_MEMORY_DATA
+ DMAP0_OFFSET + 2 * reg_nr);
WRITE_16 (raw, value);
#ifdef DEBUG
+ DMAP0_OFFSET + 2 * reg_nr);
WRITE_16 (raw, value);
#ifdef DEBUG
static unsigned long
dmap_register (SIM_DESC sd, SIM_CPU *cpu, void *regcache, int reg_nr)
{
static unsigned long
dmap_register (SIM_DESC sd, SIM_CPU *cpu, void *regcache, int reg_nr)
{
- uint8 *raw = map_memory (sd, cpu, SIM_D10V_MEMORY_DATA
+ uint8_t *raw = map_memory (sd, cpu, SIM_D10V_MEMORY_DATA
+ DMAP0_OFFSET + 2 * reg_nr);
return READ_16 (raw);
}
+ DMAP0_OFFSET + 2 * reg_nr);
return READ_16 (raw);
}
static void
set_imap_register (SIM_DESC sd, int reg_nr, unsigned long value)
{
static void
set_imap_register (SIM_DESC sd, int reg_nr, unsigned long value)
{
- uint8 *raw = map_memory (sd, NULL, SIM_D10V_MEMORY_DATA
+ uint8_t *raw = map_memory (sd, NULL, SIM_D10V_MEMORY_DATA
+ IMAP0_OFFSET + 2 * reg_nr);
WRITE_16 (raw, value);
#ifdef DEBUG
+ IMAP0_OFFSET + 2 * reg_nr);
WRITE_16 (raw, value);
#ifdef DEBUG
static unsigned long
imap_register (SIM_DESC sd, SIM_CPU *cpu, void *regcache, int reg_nr)
{
static unsigned long
imap_register (SIM_DESC sd, SIM_CPU *cpu, void *regcache, int reg_nr)
{
- uint8 *raw = map_memory (sd, cpu, SIM_D10V_MEMORY_DATA
+ uint8_t *raw = map_memory (sd, cpu, SIM_D10V_MEMORY_DATA
+ IMAP0_OFFSET + 2 * reg_nr);
return READ_16 (raw);
}
+ IMAP0_OFFSET + 2 * reg_nr);
return READ_16 (raw);
}
is assumed that the client has already ensured that the access
isn't going to cross a segment boundary. */
is assumed that the client has already ensured that the access
isn't going to cross a segment boundary. */
map_memory (SIM_DESC sd, SIM_CPU *cpu, unsigned phys_addr)
{
map_memory (SIM_DESC sd, SIM_CPU *cpu, unsigned phys_addr)
{
- uint8 **memory;
- uint8 *raw;
+ uint8_t **memory;
+ uint8_t *raw;
unsigned offset;
int segment = ((phys_addr >> 24) & 0xff);
unsigned offset;
int segment = ((phys_addr >> 24) & 0xff);
unsigned long phys;
int phys_size;
phys_size = sim_d10v_translate_addr (sd, NULL, virt, size, &phys, NULL,
unsigned long phys;
int phys_size;
phys_size = sim_d10v_translate_addr (sd, NULL, virt, size, &phys, NULL,
-uint8 *
-dmem_addr (SIM_DESC sd, SIM_CPU *cpu, uint16 offset)
+uint8_t *
+dmem_addr (SIM_DESC sd, SIM_CPU *cpu, uint16_t offset)
int phys_size;
/* Note: DMEM address range is 0..0x10000. Calling code can compute
things like ``0xfffe + 0x0e60 == 0x10e5d''. Since offset's type
int phys_size;
/* Note: DMEM address range is 0..0x10000. Calling code can compute
things like ``0xfffe + 0x0e60 == 0x10e5d''. Since offset's type
- is uint16 this is modulo'ed onto 0x0e5d. */
+ is uint16_t this is modulo'ed onto 0x0e5d. */
phys_size = sim_d10v_translate_dmap_addr (sd, cpu, offset, 1, &phys, NULL,
dmap_register);
phys_size = sim_d10v_translate_dmap_addr (sd, cpu, offset, 1, &phys, NULL,
dmap_register);
-uint8 *
-imem_addr (SIM_DESC sd, SIM_CPU *cpu, uint32 offset)
+uint8_t *
+imem_addr (SIM_DESC sd, SIM_CPU *cpu, uint32_t offset)
int phys_size = sim_d10v_translate_imap_addr (sd, cpu, offset, 1, &phys, NULL,
imap_register);
if (phys_size == 0)
int phys_size = sim_d10v_translate_imap_addr (sd, cpu, offset, 1, &phys, NULL,
imap_register);
if (phys_size == 0)
static void
step_once (SIM_DESC sd, SIM_CPU *cpu)
{
static void
step_once (SIM_DESC sd, SIM_CPU *cpu)
{
- uint32 inst;
- uint8 *iaddr;
+ uint32_t inst;
+ uint8_t *iaddr;
/* TODO: Unindent this block. */
{
/* TODO: Unindent this block. */
{
- iaddr = imem_addr (sd, cpu, (uint32)PC << 2);
+ iaddr = imem_addr (sd, cpu, (uint32_t)PC << 2);
inst = get_longword( iaddr );
inst = get_longword( iaddr );
- sprintf (p, "%s@(%d,r%d)", comma, (int16)OP[i], OP[i+1]);
+ sprintf (p, "%s@(%d,r%d)", comma, (int16_t)OP[i], OP[i+1]);
p += strlen (p);
comma = ",";
break;
p += strlen (p);
comma = ",";
break;
case OP_POSTINC:
case OP_PREDEC:
sim_io_printf (sd, "%*s0x%.4x", SIZE_VALUES-6, "",
case OP_POSTINC:
case OP_PREDEC:
sim_io_printf (sd, "%*s0x%.4x", SIZE_VALUES-6, "",
+ (uint16_t) GPR (OP[i]));
- sim_io_printf (sd, "%*s0x%.4x", SIZE_VALUES-6, "", (uint16) OP[i]);
+ sim_io_printf (sd, "%*s0x%.4x", SIZE_VALUES-6, "", (uint16_t) OP[i]);
- tmp = (long)((((uint32) GPR (OP[i])) << 16) | ((uint32) GPR (OP[i] + 1)));
+ tmp = (long)((((uint32_t) GPR (OP[i])) << 16) | ((uint32_t) GPR (OP[i] + 1)));
sim_io_printf (sd, "%*s0x%.8lx", SIZE_VALUES-10, "", tmp);
break;
case OP_CR:
case OP_CR_REVERSE:
sim_io_printf (sd, "%*s0x%.4x", SIZE_VALUES-6, "",
sim_io_printf (sd, "%*s0x%.8lx", SIZE_VALUES-10, "", tmp);
break;
case OP_CR:
case OP_CR_REVERSE:
sim_io_printf (sd, "%*s0x%.4x", SIZE_VALUES-6, "",
- (uint16) CREG (OP[i]));
+ (uint16_t) CREG (OP[i]));
case OP_CONSTANT16:
sim_io_printf (sd, "%*s0x%.4x", SIZE_VALUES-6, "",
case OP_CONSTANT16:
sim_io_printf (sd, "%*s0x%.4x", SIZE_VALUES-6, "",
break;
case OP_CONSTANT4:
sim_io_printf (sd, "%*s0x%.4x", SIZE_VALUES-6, "",
break;
case OP_CONSTANT4:
sim_io_printf (sd, "%*s0x%.4x", SIZE_VALUES-6, "",
+ (uint16_t)SEXT4(OP[i]));
break;
case OP_CONSTANT8:
sim_io_printf (sd, "%*s0x%.4x", SIZE_VALUES-6, "",
break;
case OP_CONSTANT8:
sim_io_printf (sd, "%*s0x%.4x", SIZE_VALUES-6, "",
+ (uint16_t)SEXT8(OP[i]));
break;
case OP_CONSTANT3:
sim_io_printf (sd, "%*s0x%.4x", SIZE_VALUES-6, "",
break;
case OP_CONSTANT3:
sim_io_printf (sd, "%*s0x%.4x", SIZE_VALUES-6, "",
+ (uint16_t)SEXT3(OP[i]));
case OP_MEMREF2:
sim_io_printf (sd, "%*s0x%.4x", SIZE_VALUES-6, "",
case OP_MEMREF2:
sim_io_printf (sd, "%*s0x%.4x", SIZE_VALUES-6, "",
sim_io_printf (sd, "%*s0x%.4x", SIZE_VALUES-6, "",
sim_io_printf (sd, "%*s0x%.4x", SIZE_VALUES-6, "",
- (uint16)GPR (OP[i + 1]));
+ (uint16_t)GPR (OP[i + 1]));
i++;
break;
case OP_R0:
sim_io_printf (sd, "%*s0x%.4x", SIZE_VALUES-6, "",
i++;
break;
case OP_R0:
sim_io_printf (sd, "%*s0x%.4x", SIZE_VALUES-6, "",
break;
case OP_R1:
sim_io_printf (sd, "%*s0x%.4x", SIZE_VALUES-6, "",
break;
case OP_R1:
sim_io_printf (sd, "%*s0x%.4x", SIZE_VALUES-6, "",
break;
case OP_R2:
sim_io_printf (sd, "%*s0x%.4x", SIZE_VALUES-6, "",
break;
case OP_R2:
sim_io_printf (sd, "%*s0x%.4x", SIZE_VALUES-6, "",
-trace_output_40 (SIM_DESC sd, uint64 val)
+trace_output_40 (SIM_DESC sd, uint64_t val)
{
if ((d10v_debug & (DEBUG_TRACE | DEBUG_VALUES)) == (DEBUG_TRACE | DEBUG_VALUES))
{
{
if ((d10v_debug & (DEBUG_TRACE | DEBUG_VALUES)) == (DEBUG_TRACE | DEBUG_VALUES))
{
-trace_output_32 (SIM_DESC sd, uint32 val)
+trace_output_32 (SIM_DESC sd, uint32_t val)
{
if ((d10v_debug & (DEBUG_TRACE | DEBUG_VALUES)) == (DEBUG_TRACE | DEBUG_VALUES))
{
{
if ((d10v_debug & (DEBUG_TRACE | DEBUG_VALUES)) == (DEBUG_TRACE | DEBUG_VALUES))
{
-trace_output_16 (SIM_DESC sd, uint16 val)
+trace_output_16 (SIM_DESC sd, uint16_t val)
{
if ((d10v_debug & (DEBUG_TRACE | DEBUG_VALUES)) == (DEBUG_TRACE | DEBUG_VALUES))
{
{
if ((d10v_debug & (DEBUG_TRACE | DEBUG_VALUES)) == (DEBUG_TRACE | DEBUG_VALUES))
{
void
OP_4607 (SIM_DESC sd, SIM_CPU *cpu)
{
void
OP_4607 (SIM_DESC sd, SIM_CPU *cpu)
{
trace_input ("abs", OP_REG, OP_VOID, OP_VOID);
SET_PSW_F1 (PSW_F0);
tmp = GPR(OP[0]);
trace_input ("abs", OP_REG, OP_VOID, OP_VOID);
SET_PSW_F1 (PSW_F0);
tmp = GPR(OP[0]);
void
OP_5607 (SIM_DESC sd, SIM_CPU *cpu)
{
void
OP_5607 (SIM_DESC sd, SIM_CPU *cpu)
{
trace_input ("abs", OP_ACCUM, OP_VOID, OP_VOID);
SET_PSW_F1 (PSW_F0);
trace_input ("abs", OP_ACCUM, OP_VOID, OP_VOID);
SET_PSW_F1 (PSW_F0);
void
OP_200 (SIM_DESC sd, SIM_CPU *cpu)
{
void
OP_200 (SIM_DESC sd, SIM_CPU *cpu)
{
- uint16 a = GPR (OP[0]);
- uint16 b = GPR (OP[1]);
- uint16 tmp = (a + b);
+ uint16_t a = GPR (OP[0]);
+ uint16_t b = GPR (OP[1]);
+ uint16_t tmp = (a + b);
trace_input ("add", OP_REG, OP_REG, OP_VOID);
SET_PSW_C (a > tmp);
SET_GPR (OP[0], tmp);
trace_input ("add", OP_REG, OP_REG, OP_VOID);
SET_PSW_C (a > tmp);
SET_GPR (OP[0], tmp);
void
OP_1201 (SIM_DESC sd, SIM_CPU *cpu)
{
void
OP_1201 (SIM_DESC sd, SIM_CPU *cpu)
{
tmp = SEXT40(ACC (OP[0])) + (SEXT16 (GPR (OP[1])) << 16 | GPR (OP[1] + 1));
trace_input ("add", OP_ACCUM, OP_REG, OP_VOID);
tmp = SEXT40(ACC (OP[0])) + (SEXT16 (GPR (OP[1])) << 16 | GPR (OP[1] + 1));
trace_input ("add", OP_ACCUM, OP_REG, OP_VOID);
void
OP_1203 (SIM_DESC sd, SIM_CPU *cpu)
{
void
OP_1203 (SIM_DESC sd, SIM_CPU *cpu)
{
tmp = SEXT40(ACC (OP[0])) + SEXT40(ACC (OP[1]));
trace_input ("add", OP_ACCUM, OP_ACCUM, OP_VOID);
tmp = SEXT40(ACC (OP[0])) + SEXT40(ACC (OP[1]));
trace_input ("add", OP_ACCUM, OP_ACCUM, OP_VOID);
void
OP_1200 (SIM_DESC sd, SIM_CPU *cpu)
{
void
OP_1200 (SIM_DESC sd, SIM_CPU *cpu)
{
- uint32 tmp;
- uint32 a = (GPR (OP[0])) << 16 | GPR (OP[0] + 1);
- uint32 b = (GPR (OP[1])) << 16 | GPR (OP[1] + 1);
+ uint32_t tmp;
+ uint32_t a = (GPR (OP[0])) << 16 | GPR (OP[0] + 1);
+ uint32_t b = (GPR (OP[1])) << 16 | GPR (OP[1] + 1);
trace_input ("add2w", OP_DREG, OP_DREG, OP_VOID);
tmp = a + b;
SET_PSW_C (tmp < a);
trace_input ("add2w", OP_DREG, OP_DREG, OP_VOID);
tmp = a + b;
SET_PSW_C (tmp < a);
void
OP_1000000 (SIM_DESC sd, SIM_CPU *cpu)
{
void
OP_1000000 (SIM_DESC sd, SIM_CPU *cpu)
{
- uint16 a = GPR (OP[1]);
- uint16 b = OP[2];
- uint16 tmp = (a + b);
+ uint16_t a = GPR (OP[1]);
+ uint16_t b = OP[2];
+ uint16_t tmp = (a + b);
trace_input ("add3", OP_REG_OUTPUT, OP_REG, OP_CONSTANT16);
SET_PSW_C (tmp < a);
SET_GPR (OP[0], tmp);
trace_input ("add3", OP_REG_OUTPUT, OP_REG, OP_CONSTANT16);
SET_PSW_C (tmp < a);
SET_GPR (OP[0], tmp);
void
OP_17000200 (SIM_DESC sd, SIM_CPU *cpu)
{
void
OP_17000200 (SIM_DESC sd, SIM_CPU *cpu)
{
tmp = SEXT40(ACC (OP[2])) + SEXT40 ((GPR (OP[1]) << 16) | GPR (OP[1] + 1));
trace_input ("addac3", OP_DREG_OUTPUT, OP_DREG, OP_ACCUM);
tmp = SEXT40(ACC (OP[2])) + SEXT40 ((GPR (OP[1]) << 16) | GPR (OP[1] + 1));
trace_input ("addac3", OP_DREG_OUTPUT, OP_DREG, OP_ACCUM);
void
OP_17000202 (SIM_DESC sd, SIM_CPU *cpu)
{
void
OP_17000202 (SIM_DESC sd, SIM_CPU *cpu)
{
tmp = SEXT40(ACC (OP[1])) + SEXT40(ACC (OP[2]));
trace_input ("addac3", OP_DREG_OUTPUT, OP_ACCUM, OP_ACCUM);
tmp = SEXT40(ACC (OP[1])) + SEXT40(ACC (OP[2]));
trace_input ("addac3", OP_DREG_OUTPUT, OP_ACCUM, OP_ACCUM);
void
OP_17001200 (SIM_DESC sd, SIM_CPU *cpu)
{
void
OP_17001200 (SIM_DESC sd, SIM_CPU *cpu)
{
SET_PSW_F1 (PSW_F0);
trace_input ("addac3s", OP_DREG_OUTPUT, OP_DREG, OP_ACCUM);
SET_PSW_F1 (PSW_F0);
trace_input ("addac3s", OP_DREG_OUTPUT, OP_DREG, OP_ACCUM);
void
OP_17001202 (SIM_DESC sd, SIM_CPU *cpu)
{
void
OP_17001202 (SIM_DESC sd, SIM_CPU *cpu)
{
SET_PSW_F1 (PSW_F0);
trace_input ("addac3s", OP_DREG_OUTPUT, OP_ACCUM, OP_ACCUM);
SET_PSW_F1 (PSW_F0);
trace_input ("addac3s", OP_DREG_OUTPUT, OP_ACCUM, OP_ACCUM);
void
OP_201 (SIM_DESC sd, SIM_CPU *cpu)
{
void
OP_201 (SIM_DESC sd, SIM_CPU *cpu)
{
- uint16 a = GPR (OP[0]);
- uint16 b;
- uint16 tmp;
+ uint16_t a = GPR (OP[0]);
+ uint16_t b;
+ uint16_t tmp;
if (OP[1] == 0)
OP[1] = 16;
b = OP[1];
if (OP[1] == 0)
OP[1] = 16;
b = OP[1];
void
OP_C00 (SIM_DESC sd, SIM_CPU *cpu)
{
void
OP_C00 (SIM_DESC sd, SIM_CPU *cpu)
{
- uint16 tmp = GPR (OP[0]) & GPR (OP[1]);
+ uint16_t tmp = GPR (OP[0]) & GPR (OP[1]);
trace_input ("and", OP_REG, OP_REG, OP_VOID);
SET_GPR (OP[0], tmp);
trace_output_16 (sd, tmp);
trace_input ("and", OP_REG, OP_REG, OP_VOID);
SET_GPR (OP[0], tmp);
trace_output_16 (sd, tmp);
void
OP_6000000 (SIM_DESC sd, SIM_CPU *cpu)
{
void
OP_6000000 (SIM_DESC sd, SIM_CPU *cpu)
{
- uint16 tmp = GPR (OP[1]) & OP[2];
+ uint16_t tmp = GPR (OP[1]) & OP[2];
trace_input ("and3", OP_REG_OUTPUT, OP_REG, OP_CONSTANT16);
SET_GPR (OP[0], tmp);
trace_output_16 (sd, tmp);
trace_input ("and3", OP_REG_OUTPUT, OP_REG, OP_CONSTANT16);
SET_GPR (OP[0], tmp);
trace_output_16 (sd, tmp);
void
OP_C01 (SIM_DESC sd, SIM_CPU *cpu)
{
void
OP_C01 (SIM_DESC sd, SIM_CPU *cpu)
{
trace_input ("bclri", OP_REG, OP_CONSTANT16, OP_VOID);
tmp = (GPR (OP[0]) &~(0x8000 >> OP[1]));
SET_GPR (OP[0], tmp);
trace_input ("bclri", OP_REG, OP_CONSTANT16, OP_VOID);
tmp = (GPR (OP[0]) &~(0x8000 >> OP[1]));
SET_GPR (OP[0], tmp);
void
OP_A01 (SIM_DESC sd, SIM_CPU *cpu)
{
void
OP_A01 (SIM_DESC sd, SIM_CPU *cpu)
{
trace_input ("bnoti", OP_REG, OP_CONSTANT16, OP_VOID);
tmp = (GPR (OP[0]) ^ (0x8000 >> OP[1]));
SET_GPR (OP[0], tmp);
trace_input ("bnoti", OP_REG, OP_CONSTANT16, OP_VOID);
tmp = (GPR (OP[0]) ^ (0x8000 >> OP[1]));
SET_GPR (OP[0], tmp);
void
OP_801 (SIM_DESC sd, SIM_CPU *cpu)
{
void
OP_801 (SIM_DESC sd, SIM_CPU *cpu)
{
trace_input ("bseti", OP_REG, OP_CONSTANT16, OP_VOID);
tmp = (GPR (OP[0]) | (0x8000 >> OP[1]));
SET_GPR (OP[0], tmp);
trace_input ("bseti", OP_REG, OP_CONSTANT16, OP_VOID);
tmp = (GPR (OP[0]) | (0x8000 >> OP[1]));
SET_GPR (OP[0], tmp);
{
trace_input ("cmp", OP_REG, OP_REG, OP_VOID);
SET_PSW_F1 (PSW_F0);
{
trace_input ("cmp", OP_REG, OP_REG, OP_VOID);
SET_PSW_F1 (PSW_F0);
- SET_PSW_F0 (((int16)(GPR (OP[0])) < (int16)(GPR (OP[1]))) ? 1 : 0);
+ SET_PSW_F0 (((int16_t)(GPR (OP[0])) < (int16_t)(GPR (OP[1]))) ? 1 : 0);
trace_output_flag (sd);
}
trace_output_flag (sd);
}
{
trace_input ("cmpi.s", OP_REG, OP_CONSTANT4, OP_VOID);
SET_PSW_F1 (PSW_F0);
{
trace_input ("cmpi.s", OP_REG, OP_CONSTANT4, OP_VOID);
SET_PSW_F1 (PSW_F0);
- SET_PSW_F0 (((int16)(GPR (OP[0])) < (int16)SEXT4(OP[1])) ? 1 : 0);
+ SET_PSW_F0 (((int16_t)(GPR (OP[0])) < (int16_t)SEXT4(OP[1])) ? 1 : 0);
trace_output_flag (sd);
}
trace_output_flag (sd);
}
{
trace_input ("cmpi.l", OP_REG, OP_CONSTANT16, OP_VOID);
SET_PSW_F1 (PSW_F0);
{
trace_input ("cmpi.l", OP_REG, OP_CONSTANT16, OP_VOID);
SET_PSW_F1 (PSW_F0);
- SET_PSW_F0 (((int16)(GPR (OP[0])) < (int16)(OP[1])) ? 1 : 0);
+ SET_PSW_F0 (((int16_t)(GPR (OP[0])) < (int16_t)(OP[1])) ? 1 : 0);
trace_output_flag (sd);
}
trace_output_flag (sd);
}
void
OP_4E09 (SIM_DESC sd, SIM_CPU *cpu)
{
void
OP_4E09 (SIM_DESC sd, SIM_CPU *cpu)
{
trace_input ("cpfg", OP_FLAG_OUTPUT, OP_FLAG, OP_VOID);
trace_input ("cpfg", OP_FLAG_OUTPUT, OP_FLAG, OP_VOID);
void
OP_4E0F (SIM_DESC sd, SIM_CPU *cpu)
{
void
OP_4E0F (SIM_DESC sd, SIM_CPU *cpu)
{
trace_input ("cpfg", OP_FLAG_OUTPUT, OP_FLAG, OP_VOID);
trace_input ("cpfg", OP_FLAG_OUTPUT, OP_FLAG, OP_VOID);
void
OP_14002800 (SIM_DESC sd, SIM_CPU *cpu)
{
void
OP_14002800 (SIM_DESC sd, SIM_CPU *cpu)
{
- uint16 foo, tmp, tmpf;
- uint16 hi;
- uint16 lo;
+ uint16_t foo, tmp, tmpf;
+ uint16_t hi;
+ uint16_t lo;
trace_input ("divs", OP_DREG, OP_REG, OP_VOID);
foo = (GPR (OP[0]) << 1) | (GPR (OP[0] + 1) >> 15);
trace_input ("divs", OP_DREG, OP_REG, OP_VOID);
foo = (GPR (OP[0]) << 1) | (GPR (OP[0] + 1) >> 15);
- tmp = (int16)foo - (int16)(GPR (OP[1]));
+ tmp = (int16_t)foo - (int16_t)(GPR (OP[1]));
tmpf = (foo >= GPR (OP[1])) ? 1 : 0;
hi = ((tmpf == 1) ? tmp : foo);
lo = ((GPR (OP[0] + 1) << 1) | tmpf);
SET_GPR (OP[0] + 0, hi);
SET_GPR (OP[0] + 1, lo);
tmpf = (foo >= GPR (OP[1])) ? 1 : 0;
hi = ((tmpf == 1) ? tmp : foo);
lo = ((GPR (OP[0] + 1) << 1) | tmpf);
SET_GPR (OP[0] + 0, hi);
SET_GPR (OP[0] + 1, lo);
- trace_output_32 (sd, ((uint32) hi << 16) | lo);
+ trace_output_32 (sd, ((uint32_t) hi << 16) | lo);
void
OP_15002A00 (SIM_DESC sd, SIM_CPU *cpu)
{
void
OP_15002A00 (SIM_DESC sd, SIM_CPU *cpu)
{
int i;
trace_input ("exp", OP_REG_OUTPUT, OP_DREG, OP_VOID);
int i;
trace_input ("exp", OP_REG_OUTPUT, OP_DREG, OP_VOID);
- if (((int16)GPR (OP[1])) >= 0)
+ if (((int16_t)GPR (OP[1])) >= 0)
tmp = (GPR (OP[1]) << 16) | GPR (OP[1] + 1);
else
tmp = ~((GPR (OP[1]) << 16) | GPR (OP[1] + 1));
tmp = (GPR (OP[1]) << 16) | GPR (OP[1] + 1);
else
tmp = ~((GPR (OP[1]) << 16) | GPR (OP[1] + 1));
void
OP_15002A02 (SIM_DESC sd, SIM_CPU *cpu)
{
void
OP_15002A02 (SIM_DESC sd, SIM_CPU *cpu)
{
int i;
trace_input ("exp", OP_REG_OUTPUT, OP_ACCUM, OP_VOID);
int i;
trace_input ("exp", OP_REG_OUTPUT, OP_ACCUM, OP_VOID);
void
OP_30000000 (SIM_DESC sd, SIM_CPU *cpu)
{
void
OP_30000000 (SIM_DESC sd, SIM_CPU *cpu)
{
- uint16 tmp;
- uint16 addr = OP[1] + GPR (OP[2]);
+ uint16_t tmp;
+ uint16_t addr = OP[1] + GPR (OP[2]);
trace_input ("ld", OP_REG_OUTPUT, OP_MEMREF2, OP_VOID);
if ((addr & 1))
{
trace_input ("ld", OP_REG_OUTPUT, OP_MEMREF2, OP_VOID);
if ((addr & 1))
{
void
OP_6401 (SIM_DESC sd, SIM_CPU *cpu)
{
void
OP_6401 (SIM_DESC sd, SIM_CPU *cpu)
{
- uint16 tmp;
- uint16 addr = GPR (OP[1]);
+ uint16_t tmp;
+ uint16_t addr = GPR (OP[1]);
trace_input ("ld", OP_REG_OUTPUT, OP_POSTDEC, OP_VOID);
if ((addr & 1))
{
trace_input ("ld", OP_REG_OUTPUT, OP_POSTDEC, OP_VOID);
if ((addr & 1))
{
void
OP_6001 (SIM_DESC sd, SIM_CPU *cpu)
{
void
OP_6001 (SIM_DESC sd, SIM_CPU *cpu)
{
- uint16 tmp;
- uint16 addr = GPR (OP[1]);
+ uint16_t tmp;
+ uint16_t addr = GPR (OP[1]);
trace_input ("ld", OP_REG_OUTPUT, OP_POSTINC, OP_VOID);
if ((addr & 1))
{
trace_input ("ld", OP_REG_OUTPUT, OP_POSTINC, OP_VOID);
if ((addr & 1))
{
void
OP_6000 (SIM_DESC sd, SIM_CPU *cpu)
{
void
OP_6000 (SIM_DESC sd, SIM_CPU *cpu)
{
- uint16 tmp;
- uint16 addr = GPR (OP[1]);
+ uint16_t tmp;
+ uint16_t addr = GPR (OP[1]);
trace_input ("ld", OP_REG_OUTPUT, OP_MEMREF, OP_VOID);
if ((addr & 1))
{
trace_input ("ld", OP_REG_OUTPUT, OP_MEMREF, OP_VOID);
if ((addr & 1))
{
void
OP_32010000 (SIM_DESC sd, SIM_CPU *cpu)
{
void
OP_32010000 (SIM_DESC sd, SIM_CPU *cpu)
{
- uint16 tmp;
- uint16 addr = OP[1];
+ uint16_t tmp;
+ uint16_t addr = OP[1];
trace_input ("ld", OP_REG_OUTPUT, OP_MEMREF3, OP_VOID);
if ((addr & 1))
{
trace_input ("ld", OP_REG_OUTPUT, OP_MEMREF3, OP_VOID);
if ((addr & 1))
{
void
OP_31000000 (SIM_DESC sd, SIM_CPU *cpu)
{
void
OP_31000000 (SIM_DESC sd, SIM_CPU *cpu)
{
- int32 tmp;
- uint16 addr = OP[1] + GPR (OP[2]);
+ int32_t tmp;
+ uint16_t addr = OP[1] + GPR (OP[2]);
trace_input ("ld2w", OP_REG_OUTPUT, OP_MEMREF2, OP_VOID);
if ((addr & 1))
{
trace_input ("ld2w", OP_REG_OUTPUT, OP_MEMREF2, OP_VOID);
if ((addr & 1))
{
void
OP_6601 (SIM_DESC sd, SIM_CPU *cpu)
{
void
OP_6601 (SIM_DESC sd, SIM_CPU *cpu)
{
- uint16 addr = GPR (OP[1]);
- int32 tmp;
+ uint16_t addr = GPR (OP[1]);
+ int32_t tmp;
trace_input ("ld2w", OP_REG_OUTPUT, OP_POSTDEC, OP_VOID);
if ((addr & 1))
{
trace_input ("ld2w", OP_REG_OUTPUT, OP_POSTDEC, OP_VOID);
if ((addr & 1))
{
void
OP_6201 (SIM_DESC sd, SIM_CPU *cpu)
{
void
OP_6201 (SIM_DESC sd, SIM_CPU *cpu)
{
- int32 tmp;
- uint16 addr = GPR (OP[1]);
+ int32_t tmp;
+ uint16_t addr = GPR (OP[1]);
trace_input ("ld2w", OP_REG_OUTPUT, OP_POSTINC, OP_VOID);
if ((addr & 1))
{
trace_input ("ld2w", OP_REG_OUTPUT, OP_POSTINC, OP_VOID);
if ((addr & 1))
{
void
OP_6200 (SIM_DESC sd, SIM_CPU *cpu)
{
void
OP_6200 (SIM_DESC sd, SIM_CPU *cpu)
{
- uint16 addr = GPR (OP[1]);
- int32 tmp;
+ uint16_t addr = GPR (OP[1]);
+ int32_t tmp;
trace_input ("ld2w", OP_REG_OUTPUT, OP_MEMREF, OP_VOID);
if ((addr & 1))
{
trace_input ("ld2w", OP_REG_OUTPUT, OP_MEMREF, OP_VOID);
if ((addr & 1))
{
void
OP_33010000 (SIM_DESC sd, SIM_CPU *cpu)
{
void
OP_33010000 (SIM_DESC sd, SIM_CPU *cpu)
{
- int32 tmp;
- uint16 addr = OP[1];
+ int32_t tmp;
+ uint16_t addr = OP[1];
trace_input ("ld2w", OP_REG_OUTPUT, OP_MEMREF3, OP_VOID);
if ((addr & 1))
{
trace_input ("ld2w", OP_REG_OUTPUT, OP_MEMREF3, OP_VOID);
if ((addr & 1))
{
void
OP_38000000 (SIM_DESC sd, SIM_CPU *cpu)
{
void
OP_38000000 (SIM_DESC sd, SIM_CPU *cpu)
{
trace_input ("ldb", OP_REG_OUTPUT, OP_MEMREF2, OP_VOID);
tmp = SEXT8 (RB (OP[1] + GPR (OP[2])));
SET_GPR (OP[0], tmp);
trace_input ("ldb", OP_REG_OUTPUT, OP_MEMREF2, OP_VOID);
tmp = SEXT8 (RB (OP[1] + GPR (OP[2])));
SET_GPR (OP[0], tmp);
void
OP_7000 (SIM_DESC sd, SIM_CPU *cpu)
{
void
OP_7000 (SIM_DESC sd, SIM_CPU *cpu)
{
trace_input ("ldb", OP_REG_OUTPUT, OP_MEMREF, OP_VOID);
tmp = SEXT8 (RB (GPR (OP[1])));
SET_GPR (OP[0], tmp);
trace_input ("ldb", OP_REG_OUTPUT, OP_MEMREF, OP_VOID);
tmp = SEXT8 (RB (GPR (OP[1])));
SET_GPR (OP[0], tmp);
void
OP_4001 (SIM_DESC sd, SIM_CPU *cpu)
{
void
OP_4001 (SIM_DESC sd, SIM_CPU *cpu)
{
trace_input ("ldi.s", OP_REG_OUTPUT, OP_CONSTANT4, OP_VOID);
tmp = SEXT4 (OP[1]);
SET_GPR (OP[0], tmp);
trace_input ("ldi.s", OP_REG_OUTPUT, OP_CONSTANT4, OP_VOID);
tmp = SEXT4 (OP[1]);
SET_GPR (OP[0], tmp);
void
OP_20000000 (SIM_DESC sd, SIM_CPU *cpu)
{
void
OP_20000000 (SIM_DESC sd, SIM_CPU *cpu)
{
trace_input ("ldi.l", OP_REG_OUTPUT, OP_CONSTANT16, OP_VOID);
tmp = OP[1];
SET_GPR (OP[0], tmp);
trace_input ("ldi.l", OP_REG_OUTPUT, OP_CONSTANT16, OP_VOID);
tmp = OP[1];
SET_GPR (OP[0], tmp);
void
OP_39000000 (SIM_DESC sd, SIM_CPU *cpu)
{
void
OP_39000000 (SIM_DESC sd, SIM_CPU *cpu)
{
trace_input ("ldub", OP_REG_OUTPUT, OP_MEMREF2, OP_VOID);
tmp = RB (OP[1] + GPR (OP[2]));
SET_GPR (OP[0], tmp);
trace_input ("ldub", OP_REG_OUTPUT, OP_MEMREF2, OP_VOID);
tmp = RB (OP[1] + GPR (OP[2]));
SET_GPR (OP[0], tmp);
void
OP_7200 (SIM_DESC sd, SIM_CPU *cpu)
{
void
OP_7200 (SIM_DESC sd, SIM_CPU *cpu)
{
trace_input ("ldub", OP_REG_OUTPUT, OP_MEMREF, OP_VOID);
tmp = RB (GPR (OP[1]));
SET_GPR (OP[0], tmp);
trace_input ("ldub", OP_REG_OUTPUT, OP_MEMREF, OP_VOID);
tmp = RB (GPR (OP[1]));
SET_GPR (OP[0], tmp);
void
OP_2A00 (SIM_DESC sd, SIM_CPU *cpu)
{
void
OP_2A00 (SIM_DESC sd, SIM_CPU *cpu)
{
trace_input ("mac", OP_ACCUM, OP_REG, OP_REG);
trace_input ("mac", OP_ACCUM, OP_REG, OP_REG);
- tmp = SEXT40 ((int16)(GPR (OP[1])) * (int16)(GPR (OP[2])));
+ tmp = SEXT40 ((int16_t)(GPR (OP[1])) * (int16_t)(GPR (OP[2])));
if (PSW_FX)
tmp = SEXT40( (tmp << 1) & MASK40);
if (PSW_FX)
tmp = SEXT40( (tmp << 1) & MASK40);
void
OP_1A00 (SIM_DESC sd, SIM_CPU *cpu)
{
void
OP_1A00 (SIM_DESC sd, SIM_CPU *cpu)
{
trace_input ("macsu", OP_ACCUM, OP_REG, OP_REG);
trace_input ("macsu", OP_ACCUM, OP_REG, OP_REG);
- tmp = SEXT40 ((int16) GPR (OP[1]) * GPR (OP[2]));
+ tmp = SEXT40 ((int16_t) GPR (OP[1]) * GPR (OP[2]));
if (PSW_FX)
tmp = SEXT40 ((tmp << 1) & MASK40);
tmp = ((SEXT40 (ACC (OP[0])) + tmp) & MASK40);
if (PSW_FX)
tmp = SEXT40 ((tmp << 1) & MASK40);
tmp = ((SEXT40 (ACC (OP[0])) + tmp) & MASK40);
void
OP_3A00 (SIM_DESC sd, SIM_CPU *cpu)
{
void
OP_3A00 (SIM_DESC sd, SIM_CPU *cpu)
{
- uint64 tmp;
- uint32 src1;
- uint32 src2;
+ uint64_t tmp;
+ uint32_t src1;
+ uint32_t src2;
trace_input ("macu", OP_ACCUM, OP_REG, OP_REG);
trace_input ("macu", OP_ACCUM, OP_REG, OP_REG);
- src1 = (uint16) GPR (OP[1]);
- src2 = (uint16) GPR (OP[2]);
+ src1 = (uint16_t) GPR (OP[1]);
+ src2 = (uint16_t) GPR (OP[2]);
tmp = src1 * src2;
if (PSW_FX)
tmp = (tmp << 1);
tmp = src1 * src2;
if (PSW_FX)
tmp = (tmp << 1);
void
OP_2600 (SIM_DESC sd, SIM_CPU *cpu)
{
void
OP_2600 (SIM_DESC sd, SIM_CPU *cpu)
{
trace_input ("max", OP_REG, OP_REG, OP_VOID);
SET_PSW_F1 (PSW_F0);
trace_input ("max", OP_REG, OP_REG, OP_VOID);
SET_PSW_F1 (PSW_F0);
- if ((int16) GPR (OP[1]) > (int16)GPR (OP[0]))
+ if ((int16_t) GPR (OP[1]) > (int16_t)GPR (OP[0]))
{
tmp = GPR (OP[1]);
SET_PSW_F0 (1);
{
tmp = GPR (OP[1]);
SET_PSW_F0 (1);
void
OP_3600 (SIM_DESC sd, SIM_CPU *cpu)
{
void
OP_3600 (SIM_DESC sd, SIM_CPU *cpu)
{
trace_input ("max", OP_ACCUM, OP_DREG, OP_VOID);
SET_PSW_F1 (PSW_F0);
trace_input ("max", OP_ACCUM, OP_DREG, OP_VOID);
SET_PSW_F1 (PSW_F0);
void
OP_3602 (SIM_DESC sd, SIM_CPU *cpu)
{
void
OP_3602 (SIM_DESC sd, SIM_CPU *cpu)
{
trace_input ("max", OP_ACCUM, OP_ACCUM, OP_VOID);
SET_PSW_F1 (PSW_F0);
if (SEXT40 (ACC (OP[1])) > SEXT40 (ACC (OP[0])))
trace_input ("max", OP_ACCUM, OP_ACCUM, OP_VOID);
SET_PSW_F1 (PSW_F0);
if (SEXT40 (ACC (OP[1])) > SEXT40 (ACC (OP[0])))
void
OP_2601 (SIM_DESC sd, SIM_CPU *cpu)
{
void
OP_2601 (SIM_DESC sd, SIM_CPU *cpu)
{
trace_input ("min", OP_REG, OP_REG, OP_VOID);
SET_PSW_F1 (PSW_F0);
trace_input ("min", OP_REG, OP_REG, OP_VOID);
SET_PSW_F1 (PSW_F0);
- if ((int16)GPR (OP[1]) < (int16)GPR (OP[0]))
+ if ((int16_t)GPR (OP[1]) < (int16_t)GPR (OP[0]))
{
tmp = GPR (OP[1]);
SET_PSW_F0 (1);
{
tmp = GPR (OP[1]);
SET_PSW_F0 (1);
void
OP_3601 (SIM_DESC sd, SIM_CPU *cpu)
{
void
OP_3601 (SIM_DESC sd, SIM_CPU *cpu)
{
trace_input ("min", OP_ACCUM, OP_DREG, OP_VOID);
SET_PSW_F1 (PSW_F0);
trace_input ("min", OP_ACCUM, OP_DREG, OP_VOID);
SET_PSW_F1 (PSW_F0);
void
OP_3603 (SIM_DESC sd, SIM_CPU *cpu)
{
void
OP_3603 (SIM_DESC sd, SIM_CPU *cpu)
{
trace_input ("min", OP_ACCUM, OP_ACCUM, OP_VOID);
SET_PSW_F1 (PSW_F0);
if (SEXT40(ACC (OP[1])) < SEXT40(ACC (OP[0])))
trace_input ("min", OP_ACCUM, OP_ACCUM, OP_VOID);
SET_PSW_F1 (PSW_F0);
if (SEXT40(ACC (OP[1])) < SEXT40(ACC (OP[0])))
void
OP_2800 (SIM_DESC sd, SIM_CPU *cpu)
{
void
OP_2800 (SIM_DESC sd, SIM_CPU *cpu)
{
trace_input ("msb", OP_ACCUM, OP_REG, OP_REG);
trace_input ("msb", OP_ACCUM, OP_REG, OP_REG);
- tmp = SEXT40 ((int16)(GPR (OP[1])) * (int16)(GPR (OP[2])));
+ tmp = SEXT40 ((int16_t)(GPR (OP[1])) * (int16_t)(GPR (OP[2])));
if (PSW_FX)
tmp = SEXT40 ((tmp << 1) & MASK40);
if (PSW_FX)
tmp = SEXT40 ((tmp << 1) & MASK40);
void
OP_1800 (SIM_DESC sd, SIM_CPU *cpu)
{
void
OP_1800 (SIM_DESC sd, SIM_CPU *cpu)
{
trace_input ("msbsu", OP_ACCUM, OP_REG, OP_REG);
trace_input ("msbsu", OP_ACCUM, OP_REG, OP_REG);
- tmp = SEXT40 ((int16)GPR (OP[1]) * GPR (OP[2]));
+ tmp = SEXT40 ((int16_t)GPR (OP[1]) * GPR (OP[2]));
if (PSW_FX)
tmp = SEXT40( (tmp << 1) & MASK40);
tmp = ((SEXT40 (ACC (OP[0])) - tmp) & MASK40);
if (PSW_FX)
tmp = SEXT40( (tmp << 1) & MASK40);
tmp = ((SEXT40 (ACC (OP[0])) - tmp) & MASK40);
void
OP_3800 (SIM_DESC sd, SIM_CPU *cpu)
{
void
OP_3800 (SIM_DESC sd, SIM_CPU *cpu)
{
- uint64 tmp;
- uint32 src1;
- uint32 src2;
+ uint64_t tmp;
+ uint32_t src1;
+ uint32_t src2;
trace_input ("msbu", OP_ACCUM, OP_REG, OP_REG);
trace_input ("msbu", OP_ACCUM, OP_REG, OP_REG);
- src1 = (uint16) GPR (OP[1]);
- src2 = (uint16) GPR (OP[2]);
+ src1 = (uint16_t) GPR (OP[1]);
+ src2 = (uint16_t) GPR (OP[2]);
tmp = src1 * src2;
if (PSW_FX)
tmp = (tmp << 1);
tmp = src1 * src2;
if (PSW_FX)
tmp = (tmp << 1);
void
OP_2E00 (SIM_DESC sd, SIM_CPU *cpu)
{
void
OP_2E00 (SIM_DESC sd, SIM_CPU *cpu)
{
trace_input ("mul", OP_REG, OP_REG, OP_VOID);
tmp = GPR (OP[0]) * GPR (OP[1]);
SET_GPR (OP[0], tmp);
trace_input ("mul", OP_REG, OP_REG, OP_VOID);
tmp = GPR (OP[0]) * GPR (OP[1]);
SET_GPR (OP[0], tmp);
void
OP_2C00 (SIM_DESC sd, SIM_CPU *cpu)
{
void
OP_2C00 (SIM_DESC sd, SIM_CPU *cpu)
{
trace_input ("mulx", OP_ACCUM_OUTPUT, OP_REG, OP_REG);
trace_input ("mulx", OP_ACCUM_OUTPUT, OP_REG, OP_REG);
- tmp = SEXT40 ((int16)(GPR (OP[1])) * (int16)(GPR (OP[2])));
+ tmp = SEXT40 ((int16_t)(GPR (OP[1])) * (int16_t)(GPR (OP[2])));
if (PSW_FX)
tmp = SEXT40 ((tmp << 1) & MASK40);
if (PSW_FX)
tmp = SEXT40 ((tmp << 1) & MASK40);
void
OP_1C00 (SIM_DESC sd, SIM_CPU *cpu)
{
void
OP_1C00 (SIM_DESC sd, SIM_CPU *cpu)
{
trace_input ("mulxsu", OP_ACCUM_OUTPUT, OP_REG, OP_REG);
trace_input ("mulxsu", OP_ACCUM_OUTPUT, OP_REG, OP_REG);
- tmp = SEXT40 ((int16)(GPR (OP[1])) * GPR (OP[2]));
+ tmp = SEXT40 ((int16_t)(GPR (OP[1])) * GPR (OP[2]));
void
OP_3C00 (SIM_DESC sd, SIM_CPU *cpu)
{
void
OP_3C00 (SIM_DESC sd, SIM_CPU *cpu)
{
- uint64 tmp;
- uint32 src1;
- uint32 src2;
+ uint64_t tmp;
+ uint32_t src1;
+ uint32_t src2;
trace_input ("mulxu", OP_ACCUM_OUTPUT, OP_REG, OP_REG);
trace_input ("mulxu", OP_ACCUM_OUTPUT, OP_REG, OP_REG);
- src1 = (uint16) GPR (OP[1]);
- src2 = (uint16) GPR (OP[2]);
+ src1 = (uint16_t) GPR (OP[1]);
+ src2 = (uint16_t) GPR (OP[2]);
tmp = src1 * src2;
if (PSW_FX)
tmp <<= 1;
tmp = src1 * src2;
if (PSW_FX)
tmp <<= 1;
void
OP_4000 (SIM_DESC sd, SIM_CPU *cpu)
{
void
OP_4000 (SIM_DESC sd, SIM_CPU *cpu)
{
trace_input ("mv", OP_REG_OUTPUT, OP_REG, OP_VOID);
tmp = GPR (OP[1]);
SET_GPR (OP[0], tmp);
trace_input ("mv", OP_REG_OUTPUT, OP_REG, OP_VOID);
tmp = GPR (OP[1]);
SET_GPR (OP[0], tmp);
void
OP_5000 (SIM_DESC sd, SIM_CPU *cpu)
{
void
OP_5000 (SIM_DESC sd, SIM_CPU *cpu)
{
trace_input ("mv2w", OP_DREG_OUTPUT, OP_DREG, OP_VOID);
tmp = GPR32 (OP[1]);
SET_GPR32 (OP[0], tmp);
trace_input ("mv2w", OP_DREG_OUTPUT, OP_DREG, OP_VOID);
tmp = GPR32 (OP[1]);
SET_GPR32 (OP[0], tmp);
void
OP_3E00 (SIM_DESC sd, SIM_CPU *cpu)
{
void
OP_3E00 (SIM_DESC sd, SIM_CPU *cpu)
{
trace_input ("mv2wfac", OP_DREG_OUTPUT, OP_ACCUM, OP_VOID);
tmp = ACC (OP[1]);
SET_GPR32 (OP[0], tmp);
trace_input ("mv2wfac", OP_DREG_OUTPUT, OP_ACCUM, OP_VOID);
tmp = ACC (OP[1]);
SET_GPR32 (OP[0], tmp);
void
OP_3E01 (SIM_DESC sd, SIM_CPU *cpu)
{
void
OP_3E01 (SIM_DESC sd, SIM_CPU *cpu)
{
trace_input ("mv2wtac", OP_DREG, OP_ACCUM_OUTPUT, OP_VOID);
tmp = ((SEXT16 (GPR (OP[0])) << 16 | GPR (OP[0] + 1)) & MASK40);
SET_ACC (OP[1], tmp);
trace_input ("mv2wtac", OP_DREG, OP_ACCUM_OUTPUT, OP_VOID);
tmp = ((SEXT16 (GPR (OP[0])) << 16 | GPR (OP[0] + 1)) & MASK40);
SET_ACC (OP[1], tmp);
void
OP_3E03 (SIM_DESC sd, SIM_CPU *cpu)
{
void
OP_3E03 (SIM_DESC sd, SIM_CPU *cpu)
{
trace_input ("mvac", OP_ACCUM_OUTPUT, OP_ACCUM, OP_VOID);
tmp = ACC (OP[1]);
SET_ACC (OP[0], tmp);
trace_input ("mvac", OP_ACCUM_OUTPUT, OP_ACCUM, OP_VOID);
tmp = ACC (OP[1]);
SET_ACC (OP[0], tmp);
void
OP_5400 (SIM_DESC sd, SIM_CPU *cpu)
{
void
OP_5400 (SIM_DESC sd, SIM_CPU *cpu)
{
trace_input ("mvb", OP_REG_OUTPUT, OP_REG, OP_VOID);
tmp = SEXT8 (GPR (OP[1]) & 0xff);
SET_GPR (OP[0], tmp);
trace_input ("mvb", OP_REG_OUTPUT, OP_REG, OP_VOID);
tmp = SEXT8 (GPR (OP[1]) & 0xff);
SET_GPR (OP[0], tmp);
void
OP_4400 (SIM_DESC sd, SIM_CPU *cpu)
{
void
OP_4400 (SIM_DESC sd, SIM_CPU *cpu)
{
trace_input ("mvf0f", OP_REG_OUTPUT, OP_REG, OP_VOID);
if (PSW_F0 == 0)
{
trace_input ("mvf0f", OP_REG_OUTPUT, OP_REG, OP_VOID);
if (PSW_F0 == 0)
{
void
OP_4401 (SIM_DESC sd, SIM_CPU *cpu)
{
void
OP_4401 (SIM_DESC sd, SIM_CPU *cpu)
{
trace_input ("mvf0t", OP_REG_OUTPUT, OP_REG, OP_VOID);
if (PSW_F0)
{
trace_input ("mvf0t", OP_REG_OUTPUT, OP_REG, OP_VOID);
if (PSW_F0)
{
void
OP_1E04 (SIM_DESC sd, SIM_CPU *cpu)
{
void
OP_1E04 (SIM_DESC sd, SIM_CPU *cpu)
{
trace_input ("mvfacg", OP_REG_OUTPUT, OP_ACCUM, OP_VOID);
tmp = ((ACC (OP[1]) >> 32) & 0xff);
SET_GPR (OP[0], tmp);
trace_input ("mvfacg", OP_REG_OUTPUT, OP_ACCUM, OP_VOID);
tmp = ((ACC (OP[1]) >> 32) & 0xff);
SET_GPR (OP[0], tmp);
void
OP_1E00 (SIM_DESC sd, SIM_CPU *cpu)
{
void
OP_1E00 (SIM_DESC sd, SIM_CPU *cpu)
{
trace_input ("mvfachi", OP_REG_OUTPUT, OP_ACCUM, OP_VOID);
tmp = (ACC (OP[1]) >> 16);
SET_GPR (OP[0], tmp);
trace_input ("mvfachi", OP_REG_OUTPUT, OP_ACCUM, OP_VOID);
tmp = (ACC (OP[1]) >> 16);
SET_GPR (OP[0], tmp);
void
OP_1E02 (SIM_DESC sd, SIM_CPU *cpu)
{
void
OP_1E02 (SIM_DESC sd, SIM_CPU *cpu)
{
trace_input ("mvfaclo", OP_REG_OUTPUT, OP_ACCUM, OP_VOID);
tmp = ACC (OP[1]);
SET_GPR (OP[0], tmp);
trace_input ("mvfaclo", OP_REG_OUTPUT, OP_ACCUM, OP_VOID);
tmp = ACC (OP[1]);
SET_GPR (OP[0], tmp);
void
OP_5200 (SIM_DESC sd, SIM_CPU *cpu)
{
void
OP_5200 (SIM_DESC sd, SIM_CPU *cpu)
{
trace_input ("mvfc", OP_REG_OUTPUT, OP_CR, OP_VOID);
tmp = CREG (OP[1]);
SET_GPR (OP[0], tmp);
trace_input ("mvfc", OP_REG_OUTPUT, OP_CR, OP_VOID);
tmp = CREG (OP[1]);
SET_GPR (OP[0], tmp);
void
OP_1E41 (SIM_DESC sd, SIM_CPU *cpu)
{
void
OP_1E41 (SIM_DESC sd, SIM_CPU *cpu)
{
trace_input ("mvtacg", OP_REG, OP_ACCUM, OP_VOID);
tmp = ((ACC (OP[1]) & MASK32)
trace_input ("mvtacg", OP_REG, OP_ACCUM, OP_VOID);
tmp = ((ACC (OP[1]) & MASK32)
- | ((int64)(GPR (OP[0]) & 0xff) << 32));
+ | ((int64_t)(GPR (OP[0]) & 0xff) << 32));
SET_ACC (OP[1], tmp);
trace_output_40 (sd, tmp);
}
SET_ACC (OP[1], tmp);
trace_output_40 (sd, tmp);
}
void
OP_1E01 (SIM_DESC sd, SIM_CPU *cpu)
{
void
OP_1E01 (SIM_DESC sd, SIM_CPU *cpu)
{
trace_input ("mvtachi", OP_REG, OP_ACCUM, OP_VOID);
tmp = ACC (OP[1]) & 0xffff;
tmp = ((SEXT16 (GPR (OP[0])) << 16 | tmp) & MASK40);
trace_input ("mvtachi", OP_REG, OP_ACCUM, OP_VOID);
tmp = ACC (OP[1]) & 0xffff;
tmp = ((SEXT16 (GPR (OP[0])) << 16 | tmp) & MASK40);
void
OP_1E21 (SIM_DESC sd, SIM_CPU *cpu)
{
void
OP_1E21 (SIM_DESC sd, SIM_CPU *cpu)
{
trace_input ("mvtaclo", OP_REG, OP_ACCUM, OP_VOID);
tmp = ((SEXT16 (GPR (OP[0]))) & MASK40);
SET_ACC (OP[1], tmp);
trace_input ("mvtaclo", OP_REG, OP_ACCUM, OP_VOID);
tmp = ((SEXT16 (GPR (OP[0]))) & MASK40);
SET_ACC (OP[1], tmp);
void
OP_5600 (SIM_DESC sd, SIM_CPU *cpu)
{
void
OP_5600 (SIM_DESC sd, SIM_CPU *cpu)
{
trace_input ("mvtc", OP_REG, OP_CR_OUTPUT, OP_VOID);
tmp = GPR (OP[0]);
tmp = SET_CREG (OP[1], tmp);
trace_input ("mvtc", OP_REG, OP_CR_OUTPUT, OP_VOID);
tmp = GPR (OP[0]);
tmp = SET_CREG (OP[1], tmp);
void
OP_5401 (SIM_DESC sd, SIM_CPU *cpu)
{
void
OP_5401 (SIM_DESC sd, SIM_CPU *cpu)
{
trace_input ("mvub", OP_REG_OUTPUT, OP_REG, OP_VOID);
tmp = (GPR (OP[1]) & 0xff);
SET_GPR (OP[0], tmp);
trace_input ("mvub", OP_REG_OUTPUT, OP_REG, OP_VOID);
tmp = (GPR (OP[1]) & 0xff);
SET_GPR (OP[0], tmp);
void
OP_4605 (SIM_DESC sd, SIM_CPU *cpu)
{
void
OP_4605 (SIM_DESC sd, SIM_CPU *cpu)
{
trace_input ("neg", OP_REG, OP_VOID, OP_VOID);
tmp = - GPR (OP[0]);
SET_GPR (OP[0], tmp);
trace_input ("neg", OP_REG, OP_VOID, OP_VOID);
tmp = - GPR (OP[0]);
SET_GPR (OP[0], tmp);
void
OP_5605 (SIM_DESC sd, SIM_CPU *cpu)
{
void
OP_5605 (SIM_DESC sd, SIM_CPU *cpu)
{
trace_input ("neg", OP_ACCUM, OP_VOID, OP_VOID);
tmp = -SEXT40(ACC (OP[0]));
trace_input ("neg", OP_ACCUM, OP_VOID, OP_VOID);
tmp = -SEXT40(ACC (OP[0]));
void
OP_4603 (SIM_DESC sd, SIM_CPU *cpu)
{
void
OP_4603 (SIM_DESC sd, SIM_CPU *cpu)
{
trace_input ("not", OP_REG, OP_VOID, OP_VOID);
tmp = ~GPR (OP[0]);
SET_GPR (OP[0], tmp);
trace_input ("not", OP_REG, OP_VOID, OP_VOID);
tmp = ~GPR (OP[0]);
SET_GPR (OP[0], tmp);
void
OP_800 (SIM_DESC sd, SIM_CPU *cpu)
{
void
OP_800 (SIM_DESC sd, SIM_CPU *cpu)
{
trace_input ("or", OP_REG, OP_REG, OP_VOID);
tmp = (GPR (OP[0]) | GPR (OP[1]));
SET_GPR (OP[0], tmp);
trace_input ("or", OP_REG, OP_REG, OP_VOID);
tmp = (GPR (OP[0]) | GPR (OP[1]));
SET_GPR (OP[0], tmp);
void
OP_4000000 (SIM_DESC sd, SIM_CPU *cpu)
{
void
OP_4000000 (SIM_DESC sd, SIM_CPU *cpu)
{
trace_input ("or3", OP_REG_OUTPUT, OP_REG, OP_CONSTANT16);
tmp = (GPR (OP[1]) | OP[2]);
SET_GPR (OP[0], tmp);
trace_input ("or3", OP_REG_OUTPUT, OP_REG, OP_CONSTANT16);
tmp = (GPR (OP[1]) | OP[2]);
SET_GPR (OP[0], tmp);
void
OP_5201 (SIM_DESC sd, SIM_CPU *cpu)
{
void
OP_5201 (SIM_DESC sd, SIM_CPU *cpu)
{
int shift = SEXT3 (OP[2]);
trace_input ("rac", OP_DREG_OUTPUT, OP_ACCUM, OP_CONSTANT3);
int shift = SEXT3 (OP[2]);
trace_input ("rac", OP_DREG_OUTPUT, OP_ACCUM, OP_CONSTANT3);
void
OP_4201 (SIM_DESC sd, SIM_CPU *cpu)
{
void
OP_4201 (SIM_DESC sd, SIM_CPU *cpu)
{
int shift = SEXT3 (OP[2]);
trace_input ("rachi", OP_REG_OUTPUT, OP_ACCUM, OP_CONSTANT3);
int shift = SEXT3 (OP[2]);
trace_input ("rachi", OP_REG_OUTPUT, OP_ACCUM, OP_CONSTANT3);
/* sac */
void OP_5209 (SIM_DESC sd, SIM_CPU *cpu)
{
/* sac */
void OP_5209 (SIM_DESC sd, SIM_CPU *cpu)
{
trace_input ("sac", OP_REG_OUTPUT, OP_ACCUM, OP_VOID);
trace_input ("sac", OP_REG_OUTPUT, OP_ACCUM, OP_VOID);
void
OP_4209 (SIM_DESC sd, SIM_CPU *cpu)
{
void
OP_4209 (SIM_DESC sd, SIM_CPU *cpu)
{
trace_input ("sachi", OP_REG_OUTPUT, OP_ACCUM, OP_VOID);
trace_input ("sachi", OP_REG_OUTPUT, OP_ACCUM, OP_VOID);
void
OP_1223 (SIM_DESC sd, SIM_CPU *cpu)
{
void
OP_1223 (SIM_DESC sd, SIM_CPU *cpu)
{
trace_input ("sadd", OP_ACCUM, OP_ACCUM, OP_VOID);
tmp = SEXT40(ACC (OP[0])) + (SEXT40(ACC (OP[1])) >> 16);
trace_input ("sadd", OP_ACCUM, OP_ACCUM, OP_VOID);
tmp = SEXT40(ACC (OP[0])) + (SEXT40(ACC (OP[1])) >> 16);
void
OP_4611 (SIM_DESC sd, SIM_CPU *cpu)
{
void
OP_4611 (SIM_DESC sd, SIM_CPU *cpu)
{
trace_input ("setf0f", OP_REG_OUTPUT, OP_VOID, OP_VOID);
tmp = ((PSW_F0 == 0) ? 1 : 0);
SET_GPR (OP[0], tmp);
trace_input ("setf0f", OP_REG_OUTPUT, OP_VOID, OP_VOID);
tmp = ((PSW_F0 == 0) ? 1 : 0);
SET_GPR (OP[0], tmp);
void
OP_4613 (SIM_DESC sd, SIM_CPU *cpu)
{
void
OP_4613 (SIM_DESC sd, SIM_CPU *cpu)
{
trace_input ("setf0t", OP_REG_OUTPUT, OP_VOID, OP_VOID);
tmp = ((PSW_F0 == 1) ? 1 : 0);
SET_GPR (OP[0], tmp);
trace_input ("setf0t", OP_REG_OUTPUT, OP_VOID, OP_VOID);
tmp = ((PSW_F0 == 1) ? 1 : 0);
SET_GPR (OP[0], tmp);
void
OP_3220 (SIM_DESC sd, SIM_CPU *cpu)
{
void
OP_3220 (SIM_DESC sd, SIM_CPU *cpu)
{
- int64 tmp;
- int16 reg;
+ int64_t tmp;
+ int16_t reg;
trace_input ("slae", OP_ACCUM, OP_REG, OP_VOID);
trace_input ("slae", OP_ACCUM, OP_REG, OP_VOID);
void
OP_2200 (SIM_DESC sd, SIM_CPU *cpu)
{
void
OP_2200 (SIM_DESC sd, SIM_CPU *cpu)
{
trace_input ("sll", OP_REG, OP_REG, OP_VOID);
tmp = (GPR (OP[0]) << (GPR (OP[1]) & 0xf));
SET_GPR (OP[0], tmp);
trace_input ("sll", OP_REG, OP_REG, OP_VOID);
tmp = (GPR (OP[0]) << (GPR (OP[1]) & 0xf));
SET_GPR (OP[0], tmp);
void
OP_3200 (SIM_DESC sd, SIM_CPU *cpu)
{
void
OP_3200 (SIM_DESC sd, SIM_CPU *cpu)
{
trace_input ("sll", OP_ACCUM, OP_REG, OP_VOID);
if ((GPR (OP[1]) & 31) <= 16)
tmp = SEXT40 (ACC (OP[0])) << (GPR (OP[1]) & 31);
trace_input ("sll", OP_ACCUM, OP_REG, OP_VOID);
if ((GPR (OP[1]) & 31) <= 16)
tmp = SEXT40 (ACC (OP[0])) << (GPR (OP[1]) & 31);
void
OP_2201 (SIM_DESC sd, SIM_CPU *cpu)
{
void
OP_2201 (SIM_DESC sd, SIM_CPU *cpu)
{
trace_input ("slli", OP_REG, OP_CONSTANT16, OP_VOID);
tmp = (GPR (OP[0]) << OP[1]);
SET_GPR (OP[0], tmp);
trace_input ("slli", OP_REG, OP_CONSTANT16, OP_VOID);
tmp = (GPR (OP[0]) << OP[1]);
SET_GPR (OP[0], tmp);
void
OP_3201 (SIM_DESC sd, SIM_CPU *cpu)
{
void
OP_3201 (SIM_DESC sd, SIM_CPU *cpu)
{
if (OP[1] == 0)
OP[1] = 16;
if (OP[1] == 0)
OP[1] = 16;
void
OP_460B (SIM_DESC sd, SIM_CPU *cpu)
{
void
OP_460B (SIM_DESC sd, SIM_CPU *cpu)
{
trace_input ("slx", OP_REG, OP_VOID, OP_VOID);
tmp = ((GPR (OP[0]) << 1) | PSW_F0);
SET_GPR (OP[0], tmp);
trace_input ("slx", OP_REG, OP_VOID, OP_VOID);
tmp = ((GPR (OP[0]) << 1) | PSW_F0);
SET_GPR (OP[0], tmp);
void
OP_2400 (SIM_DESC sd, SIM_CPU *cpu)
{
void
OP_2400 (SIM_DESC sd, SIM_CPU *cpu)
{
trace_input ("sra", OP_REG, OP_REG, OP_VOID);
trace_input ("sra", OP_REG, OP_REG, OP_VOID);
- tmp = (((int16)(GPR (OP[0]))) >> (GPR (OP[1]) & 0xf));
+ tmp = (((int16_t)(GPR (OP[0]))) >> (GPR (OP[1]) & 0xf));
SET_GPR (OP[0], tmp);
trace_output_16 (sd, tmp);
}
SET_GPR (OP[0], tmp);
trace_output_16 (sd, tmp);
}
trace_input ("sra", OP_ACCUM, OP_REG, OP_VOID);
if ((GPR (OP[1]) & 31) <= 16)
{
trace_input ("sra", OP_ACCUM, OP_REG, OP_VOID);
if ((GPR (OP[1]) & 31) <= 16)
{
- int64 tmp = ((SEXT40(ACC (OP[0])) >> (GPR (OP[1]) & 31)) & MASK40);
+ int64_t tmp = ((SEXT40(ACC (OP[0])) >> (GPR (OP[1]) & 31)) & MASK40);
SET_ACC (OP[0], tmp);
trace_output_40 (sd, tmp);
}
SET_ACC (OP[0], tmp);
trace_output_40 (sd, tmp);
}
void
OP_2401 (SIM_DESC sd, SIM_CPU *cpu)
{
void
OP_2401 (SIM_DESC sd, SIM_CPU *cpu)
{
trace_input ("srai", OP_REG, OP_CONSTANT16, OP_VOID);
trace_input ("srai", OP_REG, OP_CONSTANT16, OP_VOID);
- tmp = (((int16)(GPR (OP[0]))) >> OP[1]);
+ tmp = (((int16_t)(GPR (OP[0]))) >> OP[1]);
SET_GPR (OP[0], tmp);
trace_output_16 (sd, tmp);
}
SET_GPR (OP[0], tmp);
trace_output_16 (sd, tmp);
}
void
OP_3401 (SIM_DESC sd, SIM_CPU *cpu)
{
void
OP_3401 (SIM_DESC sd, SIM_CPU *cpu)
{
if (OP[1] == 0)
OP[1] = 16;
if (OP[1] == 0)
OP[1] = 16;
void
OP_2000 (SIM_DESC sd, SIM_CPU *cpu)
{
void
OP_2000 (SIM_DESC sd, SIM_CPU *cpu)
{
trace_input ("srl", OP_REG, OP_REG, OP_VOID);
tmp = (GPR (OP[0]) >> (GPR (OP[1]) & 0xf));
SET_GPR (OP[0], tmp);
trace_input ("srl", OP_REG, OP_REG, OP_VOID);
tmp = (GPR (OP[0]) >> (GPR (OP[1]) & 0xf));
SET_GPR (OP[0], tmp);
trace_input ("srl", OP_ACCUM, OP_REG, OP_VOID);
if ((GPR (OP[1]) & 31) <= 16)
{
trace_input ("srl", OP_ACCUM, OP_REG, OP_VOID);
if ((GPR (OP[1]) & 31) <= 16)
{
- int64 tmp = ((uint64)((ACC (OP[0]) & MASK40) >> (GPR (OP[1]) & 31)));
+ int64_t tmp = ((uint64_t)((ACC (OP[0]) & MASK40) >> (GPR (OP[1]) & 31)));
SET_ACC (OP[0], tmp);
trace_output_40 (sd, tmp);
}
SET_ACC (OP[0], tmp);
trace_output_40 (sd, tmp);
}
void
OP_2001 (SIM_DESC sd, SIM_CPU *cpu)
{
void
OP_2001 (SIM_DESC sd, SIM_CPU *cpu)
{
trace_input ("srli", OP_REG, OP_CONSTANT16, OP_VOID);
tmp = (GPR (OP[0]) >> OP[1]);
SET_GPR (OP[0], tmp);
trace_input ("srli", OP_REG, OP_CONSTANT16, OP_VOID);
tmp = (GPR (OP[0]) >> OP[1]);
SET_GPR (OP[0], tmp);
void
OP_3001 (SIM_DESC sd, SIM_CPU *cpu)
{
void
OP_3001 (SIM_DESC sd, SIM_CPU *cpu)
{
if (OP[1] == 0)
OP[1] = 16;
trace_input ("srli", OP_ACCUM, OP_CONSTANT16, OP_VOID);
if (OP[1] == 0)
OP[1] = 16;
trace_input ("srli", OP_ACCUM, OP_CONSTANT16, OP_VOID);
- tmp = ((uint64)(ACC (OP[0]) & MASK40) >> OP[1]);
+ tmp = ((uint64_t)(ACC (OP[0]) & MASK40) >> OP[1]);
SET_ACC (OP[0], tmp);
trace_output_40 (sd, tmp);
}
SET_ACC (OP[0], tmp);
trace_output_40 (sd, tmp);
}
void
OP_4609 (SIM_DESC sd, SIM_CPU *cpu)
{
void
OP_4609 (SIM_DESC sd, SIM_CPU *cpu)
{
trace_input ("srx", OP_REG, OP_VOID, OP_VOID);
tmp = PSW_F0 << 15;
tmp = ((GPR (OP[0]) >> 1) | tmp);
trace_input ("srx", OP_REG, OP_VOID, OP_VOID);
tmp = PSW_F0 << 15;
tmp = ((GPR (OP[0]) >> 1) | tmp);
void
OP_34000000 (SIM_DESC sd, SIM_CPU *cpu)
{
void
OP_34000000 (SIM_DESC sd, SIM_CPU *cpu)
{
- uint16 addr = OP[1] + GPR (OP[2]);
+ uint16_t addr = OP[1] + GPR (OP[2]);
trace_input ("st", OP_REG, OP_MEMREF2, OP_VOID);
if ((addr & 1))
{
trace_input ("st", OP_REG, OP_MEMREF2, OP_VOID);
if ((addr & 1))
{
void
OP_6800 (SIM_DESC sd, SIM_CPU *cpu)
{
void
OP_6800 (SIM_DESC sd, SIM_CPU *cpu)
{
- uint16 addr = GPR (OP[1]);
+ uint16_t addr = GPR (OP[1]);
trace_input ("st", OP_REG, OP_MEMREF, OP_VOID);
if ((addr & 1))
{
trace_input ("st", OP_REG, OP_MEMREF, OP_VOID);
if ((addr & 1))
{
void
OP_6C1F (SIM_DESC sd, SIM_CPU *cpu)
{
void
OP_6C1F (SIM_DESC sd, SIM_CPU *cpu)
{
- uint16 addr = GPR (OP[1]) - 2;
+ uint16_t addr = GPR (OP[1]) - 2;
trace_input ("st", OP_REG, OP_PREDEC, OP_VOID);
if (OP[1] != 15)
{
trace_input ("st", OP_REG, OP_PREDEC, OP_VOID);
if (OP[1] != 15)
{
void
OP_6801 (SIM_DESC sd, SIM_CPU *cpu)
{
void
OP_6801 (SIM_DESC sd, SIM_CPU *cpu)
{
- uint16 addr = GPR (OP[1]);
+ uint16_t addr = GPR (OP[1]);
trace_input ("st", OP_REG, OP_POSTINC, OP_VOID);
if ((addr & 1))
{
trace_input ("st", OP_REG, OP_POSTINC, OP_VOID);
if ((addr & 1))
{
void
OP_6C01 (SIM_DESC sd, SIM_CPU *cpu)
{
void
OP_6C01 (SIM_DESC sd, SIM_CPU *cpu)
{
- uint16 addr = GPR (OP[1]);
+ uint16_t addr = GPR (OP[1]);
trace_input ("st", OP_REG, OP_POSTDEC, OP_VOID);
if ( OP[1] == 15 )
{
trace_input ("st", OP_REG, OP_POSTDEC, OP_VOID);
if ( OP[1] == 15 )
{
void
OP_36010000 (SIM_DESC sd, SIM_CPU *cpu)
{
void
OP_36010000 (SIM_DESC sd, SIM_CPU *cpu)
{
trace_input ("st", OP_REG, OP_MEMREF3, OP_VOID);
if ((addr & 1))
{
trace_input ("st", OP_REG, OP_MEMREF3, OP_VOID);
if ((addr & 1))
{
void
OP_35000000 (SIM_DESC sd, SIM_CPU *cpu)
{
void
OP_35000000 (SIM_DESC sd, SIM_CPU *cpu)
{
- uint16 addr = GPR (OP[2])+ OP[1];
+ uint16_t addr = GPR (OP[2])+ OP[1];
trace_input ("st2w", OP_DREG, OP_MEMREF2, OP_VOID);
if ((addr & 1))
{
trace_input ("st2w", OP_DREG, OP_MEMREF2, OP_VOID);
if ((addr & 1))
{
void
OP_6A00 (SIM_DESC sd, SIM_CPU *cpu)
{
void
OP_6A00 (SIM_DESC sd, SIM_CPU *cpu)
{
- uint16 addr = GPR (OP[1]);
+ uint16_t addr = GPR (OP[1]);
trace_input ("st2w", OP_DREG, OP_MEMREF, OP_VOID);
if ((addr & 1))
{
trace_input ("st2w", OP_DREG, OP_MEMREF, OP_VOID);
if ((addr & 1))
{
void
OP_6E1F (SIM_DESC sd, SIM_CPU *cpu)
{
void
OP_6E1F (SIM_DESC sd, SIM_CPU *cpu)
{
- uint16 addr = GPR (OP[1]) - 4;
+ uint16_t addr = GPR (OP[1]) - 4;
trace_input ("st2w", OP_DREG, OP_PREDEC, OP_VOID);
if ( OP[1] != 15 )
{
trace_input ("st2w", OP_DREG, OP_PREDEC, OP_VOID);
if ( OP[1] != 15 )
{
void
OP_6A01 (SIM_DESC sd, SIM_CPU *cpu)
{
void
OP_6A01 (SIM_DESC sd, SIM_CPU *cpu)
{
- uint16 addr = GPR (OP[1]);
+ uint16_t addr = GPR (OP[1]);
trace_input ("st2w", OP_DREG, OP_POSTINC, OP_VOID);
if ((addr & 1))
{
trace_input ("st2w", OP_DREG, OP_POSTINC, OP_VOID);
if ((addr & 1))
{
void
OP_6E01 (SIM_DESC sd, SIM_CPU *cpu)
{
void
OP_6E01 (SIM_DESC sd, SIM_CPU *cpu)
{
- uint16 addr = GPR (OP[1]);
+ uint16_t addr = GPR (OP[1]);
trace_input ("st2w", OP_DREG, OP_POSTDEC, OP_VOID);
if ( OP[1] == 15 )
{
trace_input ("st2w", OP_DREG, OP_POSTDEC, OP_VOID);
if ( OP[1] == 15 )
{
void
OP_37010000 (SIM_DESC sd, SIM_CPU *cpu)
{
void
OP_37010000 (SIM_DESC sd, SIM_CPU *cpu)
{
trace_input ("st2w", OP_DREG, OP_MEMREF3, OP_VOID);
if ((addr & 1))
{
trace_input ("st2w", OP_DREG, OP_MEMREF3, OP_VOID);
if ((addr & 1))
{
void
OP_0 (SIM_DESC sd, SIM_CPU *cpu)
{
void
OP_0 (SIM_DESC sd, SIM_CPU *cpu)
{
- uint16 a = GPR (OP[0]);
- uint16 b = GPR (OP[1]);
- uint16 tmp = (a - b);
+ uint16_t a = GPR (OP[0]);
+ uint16_t b = GPR (OP[1]);
+ uint16_t tmp = (a - b);
trace_input ("sub", OP_REG, OP_REG, OP_VOID);
/* see ../common/sim-alu.h for a more extensive discussion on how to
compute the carry/overflow bits. */
trace_input ("sub", OP_REG, OP_REG, OP_VOID);
/* see ../common/sim-alu.h for a more extensive discussion on how to
compute the carry/overflow bits. */
void
OP_1001 (SIM_DESC sd, SIM_CPU *cpu)
{
void
OP_1001 (SIM_DESC sd, SIM_CPU *cpu)
{
trace_input ("sub", OP_ACCUM, OP_DREG, OP_VOID);
tmp = SEXT40(ACC (OP[0])) - (SEXT16 (GPR (OP[1])) << 16 | GPR (OP[1] + 1));
trace_input ("sub", OP_ACCUM, OP_DREG, OP_VOID);
tmp = SEXT40(ACC (OP[0])) - (SEXT16 (GPR (OP[1])) << 16 | GPR (OP[1] + 1));
void
OP_1003 (SIM_DESC sd, SIM_CPU *cpu)
{
void
OP_1003 (SIM_DESC sd, SIM_CPU *cpu)
{
trace_input ("sub", OP_ACCUM, OP_ACCUM, OP_VOID);
tmp = SEXT40(ACC (OP[0])) - SEXT40(ACC (OP[1]));
trace_input ("sub", OP_ACCUM, OP_ACCUM, OP_VOID);
tmp = SEXT40(ACC (OP[0])) - SEXT40(ACC (OP[1]));
void
OP_1000 (SIM_DESC sd, SIM_CPU *cpu)
{
void
OP_1000 (SIM_DESC sd, SIM_CPU *cpu)
{
trace_input ("sub2w", OP_DREG, OP_DREG, OP_VOID);
trace_input ("sub2w", OP_DREG, OP_DREG, OP_VOID);
- a = (uint32)((GPR (OP[0]) << 16) | GPR (OP[0] + 1));
- b = (uint32)((GPR (OP[1]) << 16) | GPR (OP[1] + 1));
+ a = (uint32_t)((GPR (OP[0]) << 16) | GPR (OP[0] + 1));
+ b = (uint32_t)((GPR (OP[1]) << 16) | GPR (OP[1] + 1));
/* see ../common/sim-alu.h for a more extensive discussion on how to
compute the carry/overflow bits */
tmp = a - b;
/* see ../common/sim-alu.h for a more extensive discussion on how to
compute the carry/overflow bits */
tmp = a - b;
void
OP_17000000 (SIM_DESC sd, SIM_CPU *cpu)
{
void
OP_17000000 (SIM_DESC sd, SIM_CPU *cpu)
{
trace_input ("subac3", OP_DREG_OUTPUT, OP_DREG, OP_ACCUM);
tmp = SEXT40 ((GPR (OP[1]) << 16) | GPR (OP[1] + 1)) - SEXT40 (ACC (OP[2]));
trace_input ("subac3", OP_DREG_OUTPUT, OP_DREG, OP_ACCUM);
tmp = SEXT40 ((GPR (OP[1]) << 16) | GPR (OP[1] + 1)) - SEXT40 (ACC (OP[2]));
void
OP_17000002 (SIM_DESC sd, SIM_CPU *cpu)
{
void
OP_17000002 (SIM_DESC sd, SIM_CPU *cpu)
{
trace_input ("subac3", OP_DREG_OUTPUT, OP_ACCUM, OP_ACCUM);
tmp = SEXT40 (ACC (OP[1])) - SEXT40(ACC (OP[2]));
trace_input ("subac3", OP_DREG_OUTPUT, OP_ACCUM, OP_ACCUM);
tmp = SEXT40 (ACC (OP[1])) - SEXT40(ACC (OP[2]));
void
OP_17001000 (SIM_DESC sd, SIM_CPU *cpu)
{
void
OP_17001000 (SIM_DESC sd, SIM_CPU *cpu)
{
trace_input ("subac3s", OP_DREG_OUTPUT, OP_DREG, OP_ACCUM);
SET_PSW_F1 (PSW_F0);
trace_input ("subac3s", OP_DREG_OUTPUT, OP_DREG, OP_ACCUM);
SET_PSW_F1 (PSW_F0);
void
OP_17001002 (SIM_DESC sd, SIM_CPU *cpu)
{
void
OP_17001002 (SIM_DESC sd, SIM_CPU *cpu)
{
trace_input ("subac3s", OP_DREG_OUTPUT, OP_ACCUM, OP_ACCUM);
SET_PSW_F1 (PSW_F0);
trace_input ("subac3s", OP_DREG_OUTPUT, OP_ACCUM, OP_ACCUM);
SET_PSW_F1 (PSW_F0);
/* see ../common/sim-alu.h for a more extensive discussion on how to
compute the carry/overflow bits. */
/* since OP[1] is never <= 0, -OP[1] == ~OP[1]+1 can never overflow */
/* see ../common/sim-alu.h for a more extensive discussion on how to
compute the carry/overflow bits. */
/* since OP[1] is never <= 0, -OP[1] == ~OP[1]+1 can never overflow */
- tmp = ((unsigned)(unsigned16) GPR (OP[0])
- + (unsigned)(unsigned16) ( - OP[1]));
+ tmp = ((unsigned)(uint16_t) GPR (OP[0])
+ + (unsigned)(uint16_t) ( - OP[1]));
SET_PSW_C (tmp >= (1 << 16));
SET_GPR (OP[0], tmp);
trace_output_16 (sd, tmp);
SET_PSW_C (tmp >= (1 << 16));
SET_GPR (OP[0], tmp);
trace_output_16 (sd, tmp);
default:
#if (DEBUG & DEBUG_TRAP) == 0
{
default:
#if (DEBUG & DEBUG_TRAP) == 0
{
- uint16 vec = OP[0] + TRAP_VECTOR_START;
+ uint16_t vec = OP[0] + TRAP_VECTOR_START;
SET_BPC (PC + 1);
SET_BPSW (PSW);
SET_PSW (PSW & PSW_SM_BIT);
SET_BPC (PC + 1);
SET_BPSW (PSW);
SET_PSW (PSW & PSW_SM_BIT);
case 15: /* new system call trap */
/* Trap 15 is used for simulating low-level I/O */
{
case 15: /* new system call trap */
/* Trap 15 is used for simulating low-level I/O */
{
errno = 0;
/* Registers passed to trap 0 */
errno = 0;
/* Registers passed to trap 0 */
buf = PARM1;
RETVAL (pipe (host_fd));
SW (buf, host_fd[0]);
buf = PARM1;
RETVAL (pipe (host_fd));
SW (buf, host_fd[0]);
+ buf += sizeof(uint16_t);
SW (buf, host_fd[1]);
trace_output_16 (sd, result);
}
SW (buf, host_fd[1]);
trace_output_16 (sd, result);
}
default:
cb->error (cb, "Unknown syscall %d", FUNC);
}
default:
cb->error (cb, "Unknown syscall %d", FUNC);
}
- if ((uint16) result == (uint16) -1)
+ if ((uint16_t) result == (uint16_t) -1)
RETERR (cb->get_errno (cb));
else
RETERR (0);
RETERR (cb->get_errno (cb));
else
RETERR (0);
void
OP_A00 (SIM_DESC sd, SIM_CPU *cpu)
{
void
OP_A00 (SIM_DESC sd, SIM_CPU *cpu)
{
trace_input ("xor", OP_REG, OP_REG, OP_VOID);
tmp = (GPR (OP[0]) ^ GPR (OP[1]));
SET_GPR (OP[0], tmp);
trace_input ("xor", OP_REG, OP_REG, OP_VOID);
tmp = (GPR (OP[0]) ^ GPR (OP[1]));
SET_GPR (OP[0], tmp);
void
OP_5000000 (SIM_DESC sd, SIM_CPU *cpu)
{
void
OP_5000000 (SIM_DESC sd, SIM_CPU *cpu)
{
trace_input ("xor3", OP_REG_OUTPUT, OP_REG, OP_CONSTANT16);
tmp = (GPR (OP[1]) ^ OP[2]);
SET_GPR (OP[0], tmp);
trace_input ("xor3", OP_REG_OUTPUT, OP_REG, OP_CONSTANT16);
tmp = (GPR (OP[1]) ^ OP[2]);
SET_GPR (OP[0], tmp);