1 ;; Machine description for AArch64 architecture.
2 ;; Copyright (C) 2009-2021 Free Software Foundation, Inc.
3 ;; Contributed by ARM Ltd.
5 ;; This file is part of GCC.
7 ;; GCC is free software; you can redistribute it and/or modify it
8 ;; under the terms of the GNU General Public License as published by
9 ;; the Free Software Foundation; either version 3, or (at your option)
12 ;; GCC is distributed in the hope that it will be useful, but
13 ;; WITHOUT ANY WARRANTY; without even the implied warranty of
14 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 ;; General Public License for more details.
17 ;; You should have received a copy of the GNU General Public License
18 ;; along with GCC; see the file COPYING3. If not see
19 ;; <http://www.gnu.org/licenses/>.
21 ;; -------------------------------------------------------------------
23 ;; -------------------------------------------------------------------
25 ;; Condition-code iterators.
26 (define_mode_iterator CC_ONLY [CC])
27 (define_mode_iterator CCFP_CCFPE [CCFP CCFPE])
29 ;; Iterator for General Purpose Integer registers (32- and 64-bit modes)
30 (define_mode_iterator GPI [SI DI])
32 ;; Iterator for HI, SI, DI, some instructions can only work on these modes.
33 (define_mode_iterator GPI_I16 [(HI "AARCH64_ISA_F16") SI DI])
35 ;; "Iterator" for just TI -- features like @pattern only work with iterators.
36 (define_mode_iterator JUST_TI [TI])
38 ;; Iterator for QI and HI modes
39 (define_mode_iterator SHORT [QI HI])
41 ;; Iterators for single modes, for "@" patterns.
42 (define_mode_iterator SI_ONLY [SI])
43 (define_mode_iterator DI_ONLY [DI])
45 ;; Iterator for all integer modes (up to 64-bit)
46 (define_mode_iterator ALLI [QI HI SI DI])
48 ;; Iterator for all integer modes (up to 128-bit)
49 (define_mode_iterator ALLI_TI [QI HI SI DI TI])
51 ;; Iterator for all integer modes that can be extended (up to 64-bit)
52 (define_mode_iterator ALLX [QI HI SI])
54 ;; Iterator for General Purpose Floating-point registers (32- and 64-bit modes)
55 (define_mode_iterator GPF [SF DF])
57 ;; Iterator for all scalar floating point modes (HF, SF, DF)
58 (define_mode_iterator GPF_F16 [(HF "AARCH64_ISA_F16") SF DF])
60 ;; Iterator for all scalar floating point modes (HF, SF, DF)
61 (define_mode_iterator GPF_HF [HF SF DF])
63 ;; Iterator for all 16-bit scalar floating point modes (HF, BF)
64 (define_mode_iterator HFBF [HF BF])
66 ;; Iterator for all scalar floating point modes (HF, SF, DF and TF)
67 (define_mode_iterator GPF_TF_F16 [HF SF DF TF])
69 ;; Iterator for all scalar floating point modes suitable for moving, including
70 ;; special BF type (HF, SF, DF, TF and BF)
71 (define_mode_iterator GPF_TF_F16_MOV [HF BF SF DF TF])
73 ;; Double vector modes.
74 (define_mode_iterator VDF [V2SF V4HF])
76 ;; Iterator for all scalar floating point modes (SF, DF and TF)
77 (define_mode_iterator GPF_TF [SF DF TF])
79 ;; Integer Advanced SIMD modes.
80 (define_mode_iterator VDQ_I [V8QI V16QI V4HI V8HI V2SI V4SI V2DI])
82 ;; Advanced SIMD and scalar, 64 & 128-bit container, all integer modes.
83 (define_mode_iterator VSDQ_I [V8QI V16QI V4HI V8HI V2SI V4SI V2DI QI HI SI DI])
85 ;; Advanced SIMD and scalar, 64 & 128-bit container: all Advanced SIMD
86 ;; integer modes; 64-bit scalar integer mode.
87 (define_mode_iterator VSDQ_I_DI [V8QI V16QI V4HI V8HI V2SI V4SI V2DI DI])
89 ;; Double vector modes.
90 (define_mode_iterator VD [V8QI V4HI V4HF V2SI V2SF V4BF])
92 ;; Double vector modes suitable for moving. Includes BFmode.
93 (define_mode_iterator VDMOV [V8QI V4HI V4HF V4BF V2SI V2SF])
95 ;; All modes stored in registers d0-d31.
96 (define_mode_iterator DREG [V8QI V4HI V4HF V2SI V2SF DF])
99 (define_mode_iterator DREG2 [V8QI V4HI V4HF V2SI V2SF DF])
101 ;; All modes suitable to store/load pair (2 elements) using STP/LDP.
102 (define_mode_iterator VP_2E [V2SI V2SF V2DI V2DF])
104 ;; Advanced SIMD, 64-bit container, all integer modes.
105 (define_mode_iterator VD_BHSI [V8QI V4HI V2SI])
107 ;; 128 and 64-bit container; 8, 16, 32-bit vector integer modes
108 (define_mode_iterator VDQ_BHSI [V8QI V16QI V4HI V8HI V2SI V4SI])
110 ;; Quad vector modes.
111 (define_mode_iterator VQ [V16QI V8HI V4SI V2DI V8HF V4SF V2DF V8BF])
113 ;; Copy of the above.
114 (define_mode_iterator VQ2 [V16QI V8HI V4SI V2DI V8HF V8BF V4SF V2DF])
116 ;; Quad vector modes suitable for moving. Includes BFmode.
117 (define_mode_iterator VQMOV [V16QI V8HI V4SI V2DI V8HF V8BF V4SF V2DF])
119 ;; VQMOV without 2-element modes.
120 (define_mode_iterator VQMOV_NO2E [V16QI V8HI V4SI V8HF V8BF V4SF])
122 ;; Quad integer vector modes.
123 (define_mode_iterator VQ_I [V16QI V8HI V4SI V2DI])
125 ;; VQ without 2 element modes.
126 (define_mode_iterator VQ_NO2E [V16QI V8HI V4SI V8HF V4SF V8BF])
128 ;; Quad vector with only 2 element modes.
129 (define_mode_iterator VQ_2E [V2DI V2DF])
131 ;; BFmode vector modes.
132 (define_mode_iterator VBF [V4BF V8BF])
134 ;; This mode iterator allows :P to be used for patterns that operate on
135 ;; addresses in different modes. In LP64, only DI will match, while in
136 ;; ILP32, either can match.
137 (define_mode_iterator P [(SI "ptr_mode == SImode || Pmode == SImode")
138 (DI "ptr_mode == DImode || Pmode == DImode")])
140 ;; This mode iterator allows :PTR to be used for patterns that operate on
141 ;; pointer-sized quantities. Exactly one of the two alternatives will match.
142 (define_mode_iterator PTR [(SI "ptr_mode == SImode") (DI "ptr_mode == DImode")])
144 ;; Advanced SIMD Float modes suitable for moving, loading and storing.
145 (define_mode_iterator VDQF_F16 [V4HF V8HF V2SF V4SF V2DF
148 ;; Advanced SIMD Float modes.
149 (define_mode_iterator VDQF [V2SF V4SF V2DF])
150 (define_mode_iterator VHSDF [(V4HF "TARGET_SIMD_F16INST")
151 (V8HF "TARGET_SIMD_F16INST")
154 ;; Advanced SIMD Float modes, and DF.
155 (define_mode_iterator VHSDF_DF [(V4HF "TARGET_SIMD_F16INST")
156 (V8HF "TARGET_SIMD_F16INST")
158 (define_mode_iterator VHSDF_HSDF [(V4HF "TARGET_SIMD_F16INST")
159 (V8HF "TARGET_SIMD_F16INST")
161 (HF "TARGET_SIMD_F16INST")
164 ;; Scalar and vetor modes for SF, DF.
165 (define_mode_iterator VSFDF [V2SF V4SF V2DF DF SF])
167 ;; Advanced SIMD single Float modes.
168 (define_mode_iterator VDQSF [V2SF V4SF])
170 ;; Quad vector Float modes with half/single elements.
171 (define_mode_iterator VQ_HSF [V8HF V4SF])
173 ;; Modes suitable to use as the return type of a vcond expression.
174 (define_mode_iterator VDQF_COND [V2SF V2SI V4SF V4SI V2DF V2DI])
176 ;; All scalar and Advanced SIMD Float modes.
177 (define_mode_iterator VALLF [V2SF V4SF V2DF SF DF])
179 ;; Advanced SIMD Float modes with 2 elements.
180 (define_mode_iterator V2F [V2SF V2DF])
182 ;; All Advanced SIMD modes on which we support any arithmetic operations.
183 (define_mode_iterator VALL [V8QI V16QI V4HI V8HI V2SI V4SI V2DI V2SF V4SF V2DF])
185 ;; All Advanced SIMD modes suitable for moving, loading, and storing.
186 (define_mode_iterator VALL_F16 [V8QI V16QI V4HI V8HI V2SI V4SI V2DI
187 V4HF V8HF V4BF V8BF V2SF V4SF V2DF])
189 ;; All Advanced SIMD modes suitable for moving, loading, and storing,
190 ;; including special Bfloat vector types.
191 (define_mode_iterator VALL_F16MOV [V8QI V16QI V4HI V8HI V2SI V4SI V2DI
192 V4HF V8HF V4BF V8BF V2SF V4SF V2DF])
194 ;; The VALL_F16 modes except the 128-bit 2-element ones.
195 (define_mode_iterator VALL_F16_NO_V2Q [V8QI V16QI V4HI V8HI V2SI V4SI
196 V4HF V8HF V2SF V4SF])
198 ;; All Advanced SIMD modes barring HF modes, plus DI.
199 (define_mode_iterator VALLDI [V8QI V16QI V4HI V8HI V2SI V4SI V2DI V2SF V4SF V2DF DI])
201 ;; All Advanced SIMD modes and DI.
202 (define_mode_iterator VALLDI_F16 [V8QI V16QI V4HI V8HI V2SI V4SI V2DI
203 V4HF V8HF V4BF V8BF V2SF V4SF V2DF DI])
205 ;; All Advanced SIMD modes, plus DI and DF.
206 (define_mode_iterator VALLDIF [V8QI V16QI V4HI V8HI V2SI V4SI V4BF V8BF
207 V2DI V4HF V8HF V2SF V4SF V2DF DI DF])
209 ;; Advanced SIMD modes for Integer reduction across lanes.
210 (define_mode_iterator VDQV [V8QI V16QI V4HI V8HI V4SI V2DI])
212 ;; Advanced SIMD modes (except V2DI) for Integer reduction across lanes.
213 (define_mode_iterator VDQV_S [V8QI V16QI V4HI V8HI V4SI])
215 ;; Advanced SIMD modes for Integer reduction across lanes (zero/sign extended).
216 (define_mode_iterator VDQV_E [V8QI V16QI V4HI V8HI])
218 ;; All double integer narrow-able modes.
219 (define_mode_iterator VDN [V4HI V2SI DI])
221 ;; All quad integer narrow-able modes.
222 (define_mode_iterator VQN [V8HI V4SI V2DI])
224 ;; Advanced SIMD and scalar 128-bit container: narrowable 16, 32, 64-bit
226 (define_mode_iterator VSQN_HSDI [V8HI V4SI V2DI HI SI DI])
228 ;; All quad integer widen-able modes.
229 (define_mode_iterator VQW [V16QI V8HI V4SI])
231 ;; Double vector modes for combines.
232 (define_mode_iterator VDC [V8QI V4HI V4BF V4HF V2SI V2SF DI DF])
234 ;; Advanced SIMD modes except double int.
235 (define_mode_iterator VDQIF [V8QI V16QI V4HI V8HI V2SI V4SI V2SF V4SF V2DF])
236 (define_mode_iterator VDQIF_F16 [V8QI V16QI V4HI V8HI V2SI V4SI
237 V4HF V8HF V2SF V4SF V2DF])
239 ;; Advanced SIMD modes for S type.
240 (define_mode_iterator VDQ_SI [V2SI V4SI])
242 ;; Advanced SIMD modes for S and D.
243 (define_mode_iterator VDQ_SDI [V2SI V4SI V2DI])
245 ;; Advanced SIMD modes for H, S and D.
246 (define_mode_iterator VDQ_HSDI [(V4HI "TARGET_SIMD_F16INST")
247 (V8HI "TARGET_SIMD_F16INST")
250 ;; Scalar and Advanced SIMD modes for S and D.
251 (define_mode_iterator VSDQ_SDI [V2SI V4SI V2DI SI DI])
253 ;; Scalar and Advanced SIMD modes for S and D, Advanced SIMD modes for H.
254 (define_mode_iterator VSDQ_HSDI [(V4HI "TARGET_SIMD_F16INST")
255 (V8HI "TARGET_SIMD_F16INST")
257 (HI "TARGET_SIMD_F16INST")
260 ;; Advanced SIMD modes for Q and H types.
261 (define_mode_iterator VDQQH [V8QI V16QI V4HI V8HI])
263 ;; Advanced SIMD modes for H and S types.
264 (define_mode_iterator VDQHS [V4HI V8HI V2SI V4SI])
266 ;; Advanced SIMD modes for H, S and D types.
267 (define_mode_iterator VDQHSD [V4HI V8HI V2SI V4SI V2DI])
269 ;; Advanced SIMD and scalar integer modes for H and S.
270 (define_mode_iterator VSDQ_HSI [V4HI V8HI V2SI V4SI HI SI])
272 ;; Advanced SIMD and scalar 64-bit container: 16, 32-bit integer modes.
273 (define_mode_iterator VSD_HSI [V4HI V2SI HI SI])
275 ;; Advanced SIMD 64-bit container: 16, 32-bit integer modes.
276 (define_mode_iterator VD_HSI [V4HI V2SI])
278 ;; Scalar 64-bit container: 16, 32-bit integer modes
279 (define_mode_iterator SD_HSI [HI SI])
281 ;; Advanced SIMD 64-bit container: 16, 32-bit integer modes.
282 (define_mode_iterator VQ_HSI [V8HI V4SI])
285 (define_mode_iterator VB [V8QI V16QI])
287 ;; 2 and 4 lane SI modes.
288 (define_mode_iterator VS [V2SI V4SI])
290 (define_mode_iterator TX [TI TF])
292 ;; Advanced SIMD opaque structure modes.
293 (define_mode_iterator VSTRUCT [OI CI XI])
295 ;; Double scalar modes
296 (define_mode_iterator DX [DI DF])
298 ;; Duplicate of the above
299 (define_mode_iterator DX2 [DI DF])
301 ;; Single scalar modes
302 (define_mode_iterator SX [SI SF])
304 ;; Duplicate of the above
305 (define_mode_iterator SX2 [SI SF])
307 ;; Single and double integer and float modes
308 (define_mode_iterator DSX [DF DI SF SI])
311 ;; Modes available for Advanced SIMD <f>mul lane operations.
312 (define_mode_iterator VMUL [V4HI V8HI V2SI V4SI
313 (V4HF "TARGET_SIMD_F16INST")
314 (V8HF "TARGET_SIMD_F16INST")
317 ;; Modes available for Advanced SIMD <f>mul lane operations changing lane
319 (define_mode_iterator VMUL_CHANGE_NLANES [V4HI V8HI V2SI V4SI V2SF V4SF])
321 ;; Iterators for single modes, for "@" patterns.
322 (define_mode_iterator VNx16QI_ONLY [VNx16QI])
323 (define_mode_iterator VNx8HI_ONLY [VNx8HI])
324 (define_mode_iterator VNx8BF_ONLY [VNx8BF])
325 (define_mode_iterator VNx4SI_ONLY [VNx4SI])
326 (define_mode_iterator VNx4SF_ONLY [VNx4SF])
327 (define_mode_iterator VNx2DI_ONLY [VNx2DI])
328 (define_mode_iterator VNx2DF_ONLY [VNx2DF])
330 ;; All SVE vector structure modes.
331 (define_mode_iterator SVE_STRUCT [VNx32QI VNx16HI VNx8SI VNx4DI
332 VNx16BF VNx16HF VNx8SF VNx4DF
333 VNx48QI VNx24HI VNx12SI VNx6DI
334 VNx24BF VNx24HF VNx12SF VNx6DF
335 VNx64QI VNx32HI VNx16SI VNx8DI
336 VNx32BF VNx32HF VNx16SF VNx8DF])
338 ;; All fully-packed SVE vector modes.
339 (define_mode_iterator SVE_FULL [VNx16QI VNx8HI VNx4SI VNx2DI
340 VNx8BF VNx8HF VNx4SF VNx2DF])
342 ;; All fully-packed SVE integer vector modes.
343 (define_mode_iterator SVE_FULL_I [VNx16QI VNx8HI VNx4SI VNx2DI])
345 ;; All fully-packed SVE floating-point vector modes.
346 (define_mode_iterator SVE_FULL_F [VNx8HF VNx4SF VNx2DF])
348 ;; Fully-packed SVE integer vector modes that have 8-bit or 16-bit elements.
349 (define_mode_iterator SVE_FULL_BHI [VNx16QI VNx8HI])
351 ;; Fully-packed SVE integer vector modes that have 8-bit, 16-bit or 32-bit
353 (define_mode_iterator SVE_FULL_BHSI [VNx16QI VNx8HI VNx4SI])
355 ;; Fully-packed SVE vector modes that have 16-bit, 32-bit or 64-bit elements.
356 (define_mode_iterator SVE_FULL_HSD [VNx8HI VNx4SI VNx2DI
357 VNx8BF VNx8HF VNx4SF VNx2DF])
359 ;; Fully-packed SVE integer vector modes that have 16-bit, 32-bit or 64-bit
361 (define_mode_iterator SVE_FULL_HSDI [VNx8HI VNx4SI VNx2DI])
363 ;; Fully-packed SVE integer vector modes that have 16-bit or 32-bit
365 (define_mode_iterator SVE_FULL_HSI [VNx8HI VNx4SI])
367 ;; Fully-packed SVE floating-point vector modes that have 16-bit or 32-bit
369 (define_mode_iterator SVE_FULL_HSF [VNx8HF VNx4SF])
371 ;; Fully-packed SVE integer vector modes that have 16-bit or 64-bit elements.
372 (define_mode_iterator SVE_FULL_HDI [VNx8HI VNx2DI])
374 ;; Fully-packed SVE vector modes that have 32-bit or 64-bit elements.
375 (define_mode_iterator SVE_FULL_SD [VNx4SI VNx2DI VNx4SF VNx2DF])
377 ;; Fully-packed SVE integer vector modes that have 32-bit or 64-bit elements.
378 (define_mode_iterator SVE_FULL_SDI [VNx4SI VNx2DI])
380 ;; Fully-packed SVE floating-point vector modes that have 32-bit or 64-bit
382 (define_mode_iterator SVE_FULL_SDF [VNx4SF VNx2DF])
384 ;; Same, but with the appropriate conditions for FMMLA support.
385 (define_mode_iterator SVE_MATMULF [(VNx4SF "TARGET_SVE_F32MM")
386 (VNx2DF "TARGET_SVE_F64MM")])
388 ;; Fully-packed SVE vector modes that have 32-bit elements.
389 (define_mode_iterator SVE_FULL_S [VNx4SI VNx4SF])
391 ;; Fully-packed SVE vector modes that have 64-bit elements.
392 (define_mode_iterator SVE_FULL_D [VNx2DI VNx2DF])
394 ;; All partial SVE integer modes.
395 (define_mode_iterator SVE_PARTIAL_I [VNx8QI VNx4QI VNx2QI
399 ;; All SVE vector modes.
400 (define_mode_iterator SVE_ALL [VNx16QI VNx8QI VNx4QI VNx2QI
409 ;; All SVE integer vector modes.
410 (define_mode_iterator SVE_I [VNx16QI VNx8QI VNx4QI VNx2QI
415 ;; SVE integer vector modes whose elements are 16 bits or wider.
416 (define_mode_iterator SVE_HSDI [VNx8HI VNx4HI VNx2HI
420 ;; SVE modes with 2 or 4 elements.
421 (define_mode_iterator SVE_24 [VNx2QI VNx2HI VNx2HF VNx2BF VNx2SI VNx2SF
423 VNx4QI VNx4HI VNx4HF VNx4BF VNx4SI VNx4SF])
425 ;; SVE modes with 2 elements.
426 (define_mode_iterator SVE_2 [VNx2QI VNx2HI VNx2HF VNx2BF
427 VNx2SI VNx2SF VNx2DI VNx2DF])
429 ;; SVE integer modes with 2 elements, excluding the widest element.
430 (define_mode_iterator SVE_2BHSI [VNx2QI VNx2HI VNx2SI])
432 ;; SVE integer modes with 2 elements, excluding the narrowest element.
433 (define_mode_iterator SVE_2HSDI [VNx2HI VNx2SI VNx2DI])
435 ;; SVE modes with 4 elements.
436 (define_mode_iterator SVE_4 [VNx4QI VNx4HI VNx4HF VNx4BF VNx4SI VNx4SF])
438 ;; SVE integer modes with 4 elements, excluding the widest element.
439 (define_mode_iterator SVE_4BHI [VNx4QI VNx4HI])
441 ;; SVE integer modes with 4 elements, excluding the narrowest element.
442 (define_mode_iterator SVE_4HSI [VNx4HI VNx4SI])
444 ;; SVE integer modes that can form the input to an SVE2 PMULL[BT] instruction.
445 (define_mode_iterator SVE2_PMULL_PAIR_I [VNx16QI VNx4SI
446 (VNx2DI "TARGET_SVE2_AES")])
448 ;; Modes involved in extending or truncating SVE data, for 8 elements per
450 (define_mode_iterator VNx8_NARROW [VNx8QI])
451 (define_mode_iterator VNx8_WIDE [VNx8HI])
453 ;; ...same for 4 elements per 128-bit block.
454 (define_mode_iterator VNx4_NARROW [VNx4QI VNx4HI])
455 (define_mode_iterator VNx4_WIDE [VNx4SI])
457 ;; ...same for 2 elements per 128-bit block.
458 (define_mode_iterator VNx2_NARROW [VNx2QI VNx2HI VNx2SI])
459 (define_mode_iterator VNx2_WIDE [VNx2DI])
461 ;; All SVE predicate modes.
462 (define_mode_iterator PRED_ALL [VNx16BI VNx8BI VNx4BI VNx2BI])
464 ;; SVE predicate modes that control 8-bit, 16-bit or 32-bit elements.
465 (define_mode_iterator PRED_BHS [VNx16BI VNx8BI VNx4BI])
467 ;; SVE predicate modes that control 16-bit, 32-bit or 64-bit elements.
468 (define_mode_iterator PRED_HSD [VNx8BI VNx4BI VNx2BI])
470 ;; Bfloat16 modes to which V4SF can be converted
471 (define_mode_iterator V4SF_TO_BF [V4BF V8BF])
473 ;; ------------------------------------------------------------------
474 ;; Unspec enumerations for Advance SIMD. These could well go into
475 ;; aarch64.md but for their use in int_iterators here.
476 ;; ------------------------------------------------------------------
478 (define_c_enum "unspec"
480 UNSPEC_ASHIFT_SIGNED ; Used in aarch-simd.md.
481 UNSPEC_ASHIFT_UNSIGNED ; Used in aarch64-simd.md.
482 UNSPEC_ABS ; Used in aarch64-simd.md.
483 UNSPEC_FMAX ; Used in aarch64-simd.md.
484 UNSPEC_FMAXNMV ; Used in aarch64-simd.md.
485 UNSPEC_FMAXV ; Used in aarch64-simd.md.
486 UNSPEC_FMIN ; Used in aarch64-simd.md.
487 UNSPEC_FMINNMV ; Used in aarch64-simd.md.
488 UNSPEC_FMINV ; Used in aarch64-simd.md.
489 UNSPEC_FADDV ; Used in aarch64-simd.md.
490 UNSPEC_ADDV ; Used in aarch64-simd.md.
491 UNSPEC_SMAXV ; Used in aarch64-simd.md.
492 UNSPEC_SMINV ; Used in aarch64-simd.md.
493 UNSPEC_UMAXV ; Used in aarch64-simd.md.
494 UNSPEC_UMINV ; Used in aarch64-simd.md.
495 UNSPEC_SHADD ; Used in aarch64-simd.md.
496 UNSPEC_UHADD ; Used in aarch64-simd.md.
497 UNSPEC_SRHADD ; Used in aarch64-simd.md.
498 UNSPEC_URHADD ; Used in aarch64-simd.md.
499 UNSPEC_SHSUB ; Used in aarch64-simd.md.
500 UNSPEC_UHSUB ; Used in aarch64-simd.md.
501 UNSPEC_ADDHN ; Used in aarch64-simd.md.
502 UNSPEC_RADDHN ; Used in aarch64-simd.md.
503 UNSPEC_SUBHN ; Used in aarch64-simd.md.
504 UNSPEC_RSUBHN ; Used in aarch64-simd.md.
505 UNSPEC_ADDHN2 ; Used in aarch64-simd.md.
506 UNSPEC_RADDHN2 ; Used in aarch64-simd.md.
507 UNSPEC_SUBHN2 ; Used in aarch64-simd.md.
508 UNSPEC_RSUBHN2 ; Used in aarch64-simd.md.
509 UNSPEC_SQDMULH ; Used in aarch64-simd.md.
510 UNSPEC_SQRDMULH ; Used in aarch64-simd.md.
511 UNSPEC_PMUL ; Used in aarch64-simd.md.
512 UNSPEC_FMULX ; Used in aarch64-simd.md.
513 UNSPEC_USQADD ; Used in aarch64-simd.md.
514 UNSPEC_SUQADD ; Used in aarch64-simd.md.
515 UNSPEC_SQXTUN ; Used in aarch64-simd.md.
516 UNSPEC_SQXTN ; Used in aarch64-simd.md.
517 UNSPEC_UQXTN ; Used in aarch64-simd.md.
518 UNSPEC_SSRA ; Used in aarch64-simd.md.
519 UNSPEC_USRA ; Used in aarch64-simd.md.
520 UNSPEC_SRSRA ; Used in aarch64-simd.md.
521 UNSPEC_URSRA ; Used in aarch64-simd.md.
522 UNSPEC_SRSHR ; Used in aarch64-simd.md.
523 UNSPEC_URSHR ; Used in aarch64-simd.md.
524 UNSPEC_SQSHLU ; Used in aarch64-simd.md.
525 UNSPEC_SQSHL ; Used in aarch64-simd.md.
526 UNSPEC_UQSHL ; Used in aarch64-simd.md.
527 UNSPEC_SQSHRUN ; Used in aarch64-simd.md.
528 UNSPEC_SQRSHRUN ; Used in aarch64-simd.md.
529 UNSPEC_SQSHRN ; Used in aarch64-simd.md.
530 UNSPEC_UQSHRN ; Used in aarch64-simd.md.
531 UNSPEC_SQRSHRN ; Used in aarch64-simd.md.
532 UNSPEC_UQRSHRN ; Used in aarch64-simd.md.
533 UNSPEC_SSHL ; Used in aarch64-simd.md.
534 UNSPEC_USHL ; Used in aarch64-simd.md.
535 UNSPEC_SRSHL ; Used in aarch64-simd.md.
536 UNSPEC_URSHL ; Used in aarch64-simd.md.
537 UNSPEC_SQRSHL ; Used in aarch64-simd.md.
538 UNSPEC_UQRSHL ; Used in aarch64-simd.md.
539 UNSPEC_SSLI ; Used in aarch64-simd.md.
540 UNSPEC_USLI ; Used in aarch64-simd.md.
541 UNSPEC_SSRI ; Used in aarch64-simd.md.
542 UNSPEC_USRI ; Used in aarch64-simd.md.
543 UNSPEC_SSHLL ; Used in aarch64-simd.md.
544 UNSPEC_USHLL ; Used in aarch64-simd.md.
545 UNSPEC_ADDP ; Used in aarch64-simd.md.
546 UNSPEC_TBL ; Used in vector permute patterns.
547 UNSPEC_TBX ; Used in vector permute patterns.
548 UNSPEC_CONCAT ; Used in vector permute patterns.
550 ;; The following permute unspecs are generated directly by
551 ;; aarch64_expand_vec_perm_const, so any changes to the underlying
552 ;; instructions would need a corresponding change there.
553 UNSPEC_ZIP1 ; Used in vector permute patterns.
554 UNSPEC_ZIP2 ; Used in vector permute patterns.
555 UNSPEC_UZP1 ; Used in vector permute patterns.
556 UNSPEC_UZP2 ; Used in vector permute patterns.
557 UNSPEC_TRN1 ; Used in vector permute patterns.
558 UNSPEC_TRN2 ; Used in vector permute patterns.
559 UNSPEC_EXT ; Used in vector permute patterns.
560 UNSPEC_REV64 ; Used in vector reverse patterns (permute).
561 UNSPEC_REV32 ; Used in vector reverse patterns (permute).
562 UNSPEC_REV16 ; Used in vector reverse patterns (permute).
564 UNSPEC_AESE ; Used in aarch64-simd.md.
565 UNSPEC_AESD ; Used in aarch64-simd.md.
566 UNSPEC_AESMC ; Used in aarch64-simd.md.
567 UNSPEC_AESIMC ; Used in aarch64-simd.md.
568 UNSPEC_SHA1C ; Used in aarch64-simd.md.
569 UNSPEC_SHA1M ; Used in aarch64-simd.md.
570 UNSPEC_SHA1P ; Used in aarch64-simd.md.
571 UNSPEC_SHA1H ; Used in aarch64-simd.md.
572 UNSPEC_SHA1SU0 ; Used in aarch64-simd.md.
573 UNSPEC_SHA1SU1 ; Used in aarch64-simd.md.
574 UNSPEC_SHA256H ; Used in aarch64-simd.md.
575 UNSPEC_SHA256H2 ; Used in aarch64-simd.md.
576 UNSPEC_SHA256SU0 ; Used in aarch64-simd.md.
577 UNSPEC_SHA256SU1 ; Used in aarch64-simd.md.
578 UNSPEC_PMULL ; Used in aarch64-simd.md.
579 UNSPEC_PMULL2 ; Used in aarch64-simd.md.
580 UNSPEC_REV_REGLIST ; Used in aarch64-simd.md.
581 UNSPEC_VEC_SHR ; Used in aarch64-simd.md.
582 UNSPEC_SQRDMLAH ; Used in aarch64-simd.md.
583 UNSPEC_SQRDMLSH ; Used in aarch64-simd.md.
584 UNSPEC_FMAXNM ; Used in aarch64-simd.md.
585 UNSPEC_FMINNM ; Used in aarch64-simd.md.
586 UNSPEC_SDOT ; Used in aarch64-simd.md.
587 UNSPEC_UDOT ; Used in aarch64-simd.md.
588 UNSPEC_SM3SS1 ; Used in aarch64-simd.md.
589 UNSPEC_SM3TT1A ; Used in aarch64-simd.md.
590 UNSPEC_SM3TT1B ; Used in aarch64-simd.md.
591 UNSPEC_SM3TT2A ; Used in aarch64-simd.md.
592 UNSPEC_SM3TT2B ; Used in aarch64-simd.md.
593 UNSPEC_SM3PARTW1 ; Used in aarch64-simd.md.
594 UNSPEC_SM3PARTW2 ; Used in aarch64-simd.md.
595 UNSPEC_SM4E ; Used in aarch64-simd.md.
596 UNSPEC_SM4EKEY ; Used in aarch64-simd.md.
597 UNSPEC_SHA512H ; Used in aarch64-simd.md.
598 UNSPEC_SHA512H2 ; Used in aarch64-simd.md.
599 UNSPEC_SHA512SU0 ; Used in aarch64-simd.md.
600 UNSPEC_SHA512SU1 ; Used in aarch64-simd.md.
601 UNSPEC_FMLAL ; Used in aarch64-simd.md.
602 UNSPEC_FMLSL ; Used in aarch64-simd.md.
603 UNSPEC_FMLAL2 ; Used in aarch64-simd.md.
604 UNSPEC_FMLSL2 ; Used in aarch64-simd.md.
605 UNSPEC_ADR ; Used in aarch64-sve.md.
606 UNSPEC_SEL ; Used in aarch64-sve.md.
607 UNSPEC_BRKA ; Used in aarch64-sve.md.
608 UNSPEC_BRKB ; Used in aarch64-sve.md.
609 UNSPEC_BRKN ; Used in aarch64-sve.md.
610 UNSPEC_BRKPA ; Used in aarch64-sve.md.
611 UNSPEC_BRKPB ; Used in aarch64-sve.md.
612 UNSPEC_PFIRST ; Used in aarch64-sve.md.
613 UNSPEC_PNEXT ; Used in aarch64-sve.md.
614 UNSPEC_CNTP ; Used in aarch64-sve.md.
615 UNSPEC_SADDV ; Used in aarch64-sve.md.
616 UNSPEC_UADDV ; Used in aarch64-sve.md.
617 UNSPEC_ANDV ; Used in aarch64-sve.md.
618 UNSPEC_IORV ; Used in aarch64-sve.md.
619 UNSPEC_XORV ; Used in aarch64-sve.md.
620 UNSPEC_ANDF ; Used in aarch64-sve.md.
621 UNSPEC_IORF ; Used in aarch64-sve.md.
622 UNSPEC_XORF ; Used in aarch64-sve.md.
623 UNSPEC_REVB ; Used in aarch64-sve.md.
624 UNSPEC_REVH ; Used in aarch64-sve.md.
625 UNSPEC_REVW ; Used in aarch64-sve.md.
626 UNSPEC_REVBHW ; Used in aarch64-sve.md.
627 UNSPEC_SMUL_HIGHPART ; Used in aarch64-sve.md.
628 UNSPEC_UMUL_HIGHPART ; Used in aarch64-sve.md.
629 UNSPEC_FMLA ; Used in aarch64-sve.md.
630 UNSPEC_FMLS ; Used in aarch64-sve.md.
631 UNSPEC_FEXPA ; Used in aarch64-sve.md.
632 UNSPEC_FMMLA ; Used in aarch64-sve.md.
633 UNSPEC_FTMAD ; Used in aarch64-sve.md.
634 UNSPEC_FTSMUL ; Used in aarch64-sve.md.
635 UNSPEC_FTSSEL ; Used in aarch64-sve.md.
636 UNSPEC_SMATMUL ; Used in aarch64-sve.md.
637 UNSPEC_UMATMUL ; Used in aarch64-sve.md.
638 UNSPEC_USMATMUL ; Used in aarch64-sve.md.
639 UNSPEC_TRN1Q ; Used in aarch64-sve.md.
640 UNSPEC_TRN2Q ; Used in aarch64-sve.md.
641 UNSPEC_UZP1Q ; Used in aarch64-sve.md.
642 UNSPEC_UZP2Q ; Used in aarch64-sve.md.
643 UNSPEC_ZIP1Q ; Used in aarch64-sve.md.
644 UNSPEC_ZIP2Q ; Used in aarch64-sve.md.
645 UNSPEC_COND_CMPEQ_WIDE ; Used in aarch64-sve.md.
646 UNSPEC_COND_CMPGE_WIDE ; Used in aarch64-sve.md.
647 UNSPEC_COND_CMPGT_WIDE ; Used in aarch64-sve.md.
648 UNSPEC_COND_CMPHI_WIDE ; Used in aarch64-sve.md.
649 UNSPEC_COND_CMPHS_WIDE ; Used in aarch64-sve.md.
650 UNSPEC_COND_CMPLE_WIDE ; Used in aarch64-sve.md.
651 UNSPEC_COND_CMPLO_WIDE ; Used in aarch64-sve.md.
652 UNSPEC_COND_CMPLS_WIDE ; Used in aarch64-sve.md.
653 UNSPEC_COND_CMPLT_WIDE ; Used in aarch64-sve.md.
654 UNSPEC_COND_CMPNE_WIDE ; Used in aarch64-sve.md.
655 UNSPEC_COND_FABS ; Used in aarch64-sve.md.
656 UNSPEC_COND_FADD ; Used in aarch64-sve.md.
657 UNSPEC_COND_FCADD90 ; Used in aarch64-sve.md.
658 UNSPEC_COND_FCADD270 ; Used in aarch64-sve.md.
659 UNSPEC_COND_FCMEQ ; Used in aarch64-sve.md.
660 UNSPEC_COND_FCMGE ; Used in aarch64-sve.md.
661 UNSPEC_COND_FCMGT ; Used in aarch64-sve.md.
662 UNSPEC_COND_FCMLA ; Used in aarch64-sve.md.
663 UNSPEC_COND_FCMLA90 ; Used in aarch64-sve.md.
664 UNSPEC_COND_FCMLA180 ; Used in aarch64-sve.md.
665 UNSPEC_COND_FCMLA270 ; Used in aarch64-sve.md.
666 UNSPEC_COND_FCMLE ; Used in aarch64-sve.md.
667 UNSPEC_COND_FCMLT ; Used in aarch64-sve.md.
668 UNSPEC_COND_FCMNE ; Used in aarch64-sve.md.
669 UNSPEC_COND_FCMUO ; Used in aarch64-sve.md.
670 UNSPEC_COND_FCVT ; Used in aarch64-sve.md.
671 UNSPEC_COND_FCVTZS ; Used in aarch64-sve.md.
672 UNSPEC_COND_FCVTZU ; Used in aarch64-sve.md.
673 UNSPEC_COND_FDIV ; Used in aarch64-sve.md.
674 UNSPEC_COND_FMAX ; Used in aarch64-sve.md.
675 UNSPEC_COND_FMAXNM ; Used in aarch64-sve.md.
676 UNSPEC_COND_FMIN ; Used in aarch64-sve.md.
677 UNSPEC_COND_FMINNM ; Used in aarch64-sve.md.
678 UNSPEC_COND_FMLA ; Used in aarch64-sve.md.
679 UNSPEC_COND_FMLS ; Used in aarch64-sve.md.
680 UNSPEC_COND_FMUL ; Used in aarch64-sve.md.
681 UNSPEC_COND_FMULX ; Used in aarch64-sve.md.
682 UNSPEC_COND_FNEG ; Used in aarch64-sve.md.
683 UNSPEC_COND_FNMLA ; Used in aarch64-sve.md.
684 UNSPEC_COND_FNMLS ; Used in aarch64-sve.md.
685 UNSPEC_COND_FRECPX ; Used in aarch64-sve.md.
686 UNSPEC_COND_FRINTA ; Used in aarch64-sve.md.
687 UNSPEC_COND_FRINTI ; Used in aarch64-sve.md.
688 UNSPEC_COND_FRINTM ; Used in aarch64-sve.md.
689 UNSPEC_COND_FRINTN ; Used in aarch64-sve.md.
690 UNSPEC_COND_FRINTP ; Used in aarch64-sve.md.
691 UNSPEC_COND_FRINTX ; Used in aarch64-sve.md.
692 UNSPEC_COND_FRINTZ ; Used in aarch64-sve.md.
693 UNSPEC_COND_FSCALE ; Used in aarch64-sve.md.
694 UNSPEC_COND_FSQRT ; Used in aarch64-sve.md.
695 UNSPEC_COND_FSUB ; Used in aarch64-sve.md.
696 UNSPEC_COND_SCVTF ; Used in aarch64-sve.md.
697 UNSPEC_COND_UCVTF ; Used in aarch64-sve.md.
698 UNSPEC_LASTA ; Used in aarch64-sve.md.
699 UNSPEC_LASTB ; Used in aarch64-sve.md.
700 UNSPEC_ASHIFT_WIDE ; Used in aarch64-sve.md.
701 UNSPEC_ASHIFTRT_WIDE ; Used in aarch64-sve.md.
702 UNSPEC_LSHIFTRT_WIDE ; Used in aarch64-sve.md.
703 UNSPEC_LDFF1 ; Used in aarch64-sve.md.
704 UNSPEC_LDNF1 ; Used in aarch64-sve.md.
705 UNSPEC_FCADD90 ; Used in aarch64-simd.md.
706 UNSPEC_FCADD270 ; Used in aarch64-simd.md.
707 UNSPEC_FCMLA ; Used in aarch64-simd.md.
708 UNSPEC_FCMLA90 ; Used in aarch64-simd.md.
709 UNSPEC_FCMLA180 ; Used in aarch64-simd.md.
710 UNSPEC_FCMLA270 ; Used in aarch64-simd.md.
711 UNSPEC_ASRD ; Used in aarch64-sve.md.
712 UNSPEC_ADCLB ; Used in aarch64-sve2.md.
713 UNSPEC_ADCLT ; Used in aarch64-sve2.md.
714 UNSPEC_ADDHNB ; Used in aarch64-sve2.md.
715 UNSPEC_ADDHNT ; Used in aarch64-sve2.md.
716 UNSPEC_BDEP ; Used in aarch64-sve2.md.
717 UNSPEC_BEXT ; Used in aarch64-sve2.md.
718 UNSPEC_BGRP ; Used in aarch64-sve2.md.
719 UNSPEC_CADD270 ; Used in aarch64-sve2.md.
720 UNSPEC_CADD90 ; Used in aarch64-sve2.md.
721 UNSPEC_CDOT ; Used in aarch64-sve2.md.
722 UNSPEC_CDOT180 ; Used in aarch64-sve2.md.
723 UNSPEC_CDOT270 ; Used in aarch64-sve2.md.
724 UNSPEC_CDOT90 ; Used in aarch64-sve2.md.
725 UNSPEC_CMLA ; Used in aarch64-sve2.md.
726 UNSPEC_CMLA180 ; Used in aarch64-sve2.md.
727 UNSPEC_CMLA270 ; Used in aarch64-sve2.md.
728 UNSPEC_CMLA90 ; Used in aarch64-sve2.md.
729 UNSPEC_COND_FCVTLT ; Used in aarch64-sve2.md.
730 UNSPEC_COND_FCVTNT ; Used in aarch64-sve2.md.
731 UNSPEC_COND_FCVTX ; Used in aarch64-sve2.md.
732 UNSPEC_COND_FCVTXNT ; Used in aarch64-sve2.md.
733 UNSPEC_COND_FLOGB ; Used in aarch64-sve2.md.
734 UNSPEC_EORBT ; Used in aarch64-sve2.md.
735 UNSPEC_EORTB ; Used in aarch64-sve2.md.
736 UNSPEC_FADDP ; Used in aarch64-sve2.md.
737 UNSPEC_FMAXNMP ; Used in aarch64-sve2.md.
738 UNSPEC_FMAXP ; Used in aarch64-sve2.md.
739 UNSPEC_FMINNMP ; Used in aarch64-sve2.md.
740 UNSPEC_FMINP ; Used in aarch64-sve2.md.
741 UNSPEC_FMLALB ; Used in aarch64-sve2.md.
742 UNSPEC_FMLALT ; Used in aarch64-sve2.md.
743 UNSPEC_FMLSLB ; Used in aarch64-sve2.md.
744 UNSPEC_FMLSLT ; Used in aarch64-sve2.md.
745 UNSPEC_HISTCNT ; Used in aarch64-sve2.md.
746 UNSPEC_HISTSEG ; Used in aarch64-sve2.md.
747 UNSPEC_MATCH ; Used in aarch64-sve2.md.
748 UNSPEC_NMATCH ; Used in aarch64-sve2.md.
749 UNSPEC_PMULLB ; Used in aarch64-sve2.md.
750 UNSPEC_PMULLB_PAIR ; Used in aarch64-sve2.md.
751 UNSPEC_PMULLT ; Used in aarch64-sve2.md.
752 UNSPEC_PMULLT_PAIR ; Used in aarch64-sve2.md.
753 UNSPEC_RADDHNB ; Used in aarch64-sve2.md.
754 UNSPEC_RADDHNT ; Used in aarch64-sve2.md.
755 UNSPEC_RSHRNB ; Used in aarch64-sve2.md.
756 UNSPEC_RSHRNT ; Used in aarch64-sve2.md.
757 UNSPEC_RSUBHNB ; Used in aarch64-sve2.md.
758 UNSPEC_RSUBHNT ; Used in aarch64-sve2.md.
759 UNSPEC_SABDLB ; Used in aarch64-sve2.md.
760 UNSPEC_SABDLT ; Used in aarch64-sve2.md.
761 UNSPEC_SADDLB ; Used in aarch64-sve2.md.
762 UNSPEC_SADDLBT ; Used in aarch64-sve2.md.
763 UNSPEC_SADDLT ; Used in aarch64-sve2.md.
764 UNSPEC_SADDWB ; Used in aarch64-sve2.md.
765 UNSPEC_SADDWT ; Used in aarch64-sve2.md.
766 UNSPEC_SBCLB ; Used in aarch64-sve2.md.
767 UNSPEC_SBCLT ; Used in aarch64-sve2.md.
768 UNSPEC_SHRNB ; Used in aarch64-sve2.md.
769 UNSPEC_SHRNT ; Used in aarch64-sve2.md.
770 UNSPEC_SLI ; Used in aarch64-sve2.md.
771 UNSPEC_SMAXP ; Used in aarch64-sve2.md.
772 UNSPEC_SMINP ; Used in aarch64-sve2.md.
773 UNSPEC_SMULHRS ; Used in aarch64-sve2.md.
774 UNSPEC_SMULHS ; Used in aarch64-sve2.md.
775 UNSPEC_SMULLB ; Used in aarch64-sve2.md.
776 UNSPEC_SMULLT ; Used in aarch64-sve2.md.
777 UNSPEC_SQCADD270 ; Used in aarch64-sve2.md.
778 UNSPEC_SQCADD90 ; Used in aarch64-sve2.md.
779 UNSPEC_SQDMULLB ; Used in aarch64-sve2.md.
780 UNSPEC_SQDMULLBT ; Used in aarch64-sve2.md.
781 UNSPEC_SQDMULLT ; Used in aarch64-sve2.md.
782 UNSPEC_SQRDCMLAH ; Used in aarch64-sve2.md.
783 UNSPEC_SQRDCMLAH180 ; Used in aarch64-sve2.md.
784 UNSPEC_SQRDCMLAH270 ; Used in aarch64-sve2.md.
785 UNSPEC_SQRDCMLAH90 ; Used in aarch64-sve2.md.
786 UNSPEC_SQRSHRNB ; Used in aarch64-sve2.md.
787 UNSPEC_SQRSHRNT ; Used in aarch64-sve2.md.
788 UNSPEC_SQRSHRUNB ; Used in aarch64-sve2.md.
789 UNSPEC_SQRSHRUNT ; Used in aarch64-sve2.md.
790 UNSPEC_SQSHRNB ; Used in aarch64-sve2.md.
791 UNSPEC_SQSHRNT ; Used in aarch64-sve2.md.
792 UNSPEC_SQSHRUNB ; Used in aarch64-sve2.md.
793 UNSPEC_SQSHRUNT ; Used in aarch64-sve2.md.
794 UNSPEC_SQXTNB ; Used in aarch64-sve2.md.
795 UNSPEC_SQXTNT ; Used in aarch64-sve2.md.
796 UNSPEC_SQXTUNB ; Used in aarch64-sve2.md.
797 UNSPEC_SQXTUNT ; Used in aarch64-sve2.md.
798 UNSPEC_SRI ; Used in aarch64-sve2.md.
799 UNSPEC_SSHLLB ; Used in aarch64-sve2.md.
800 UNSPEC_SSHLLT ; Used in aarch64-sve2.md.
801 UNSPEC_SSUBLB ; Used in aarch64-sve2.md.
802 UNSPEC_SSUBLBT ; Used in aarch64-sve2.md.
803 UNSPEC_SSUBLT ; Used in aarch64-sve2.md.
804 UNSPEC_SSUBLTB ; Used in aarch64-sve2.md.
805 UNSPEC_SSUBWB ; Used in aarch64-sve2.md.
806 UNSPEC_SSUBWT ; Used in aarch64-sve2.md.
807 UNSPEC_SUBHNB ; Used in aarch64-sve2.md.
808 UNSPEC_SUBHNT ; Used in aarch64-sve2.md.
809 UNSPEC_TBL2 ; Used in aarch64-sve2.md.
810 UNSPEC_UABDLB ; Used in aarch64-sve2.md.
811 UNSPEC_UABDLT ; Used in aarch64-sve2.md.
812 UNSPEC_UADDLB ; Used in aarch64-sve2.md.
813 UNSPEC_UADDLT ; Used in aarch64-sve2.md.
814 UNSPEC_UADDWB ; Used in aarch64-sve2.md.
815 UNSPEC_UADDWT ; Used in aarch64-sve2.md.
816 UNSPEC_UMAXP ; Used in aarch64-sve2.md.
817 UNSPEC_UMINP ; Used in aarch64-sve2.md.
818 UNSPEC_UMULHRS ; Used in aarch64-sve2.md.
819 UNSPEC_UMULHS ; Used in aarch64-sve2.md.
820 UNSPEC_UMULLB ; Used in aarch64-sve2.md.
821 UNSPEC_UMULLT ; Used in aarch64-sve2.md.
822 UNSPEC_UQRSHRNB ; Used in aarch64-sve2.md.
823 UNSPEC_UQRSHRNT ; Used in aarch64-sve2.md.
824 UNSPEC_UQSHRNB ; Used in aarch64-sve2.md.
825 UNSPEC_UQSHRNT ; Used in aarch64-sve2.md.
826 UNSPEC_UQXTNB ; Used in aarch64-sve2.md.
827 UNSPEC_UQXTNT ; Used in aarch64-sve2.md.
828 UNSPEC_USHLLB ; Used in aarch64-sve2.md.
829 UNSPEC_USHLLT ; Used in aarch64-sve2.md.
830 UNSPEC_USUBLB ; Used in aarch64-sve2.md.
831 UNSPEC_USUBLT ; Used in aarch64-sve2.md.
832 UNSPEC_USUBWB ; Used in aarch64-sve2.md.
833 UNSPEC_USUBWT ; Used in aarch64-sve2.md.
834 UNSPEC_USDOT ; Used in aarch64-simd.md.
835 UNSPEC_SUDOT ; Used in aarch64-simd.md.
836 UNSPEC_BFDOT ; Used in aarch64-simd.md.
837 UNSPEC_BFMLALB ; Used in aarch64-sve.md.
838 UNSPEC_BFMLALT ; Used in aarch64-sve.md.
839 UNSPEC_BFMMLA ; Used in aarch64-sve.md.
840 UNSPEC_BFCVTN ; Used in aarch64-simd.md.
841 UNSPEC_BFCVTN2 ; Used in aarch64-simd.md.
842 UNSPEC_BFCVT ; Used in aarch64-simd.md.
845 ;; ------------------------------------------------------------------
846 ;; Unspec enumerations for Atomics. They are here so that they can be
847 ;; used in the int_iterators for atomic operations.
848 ;; ------------------------------------------------------------------
850 (define_c_enum "unspecv"
852 UNSPECV_LX ; Represent a load-exclusive.
853 UNSPECV_SX ; Represent a store-exclusive.
854 UNSPECV_LDA ; Represent an atomic load or load-acquire.
855 UNSPECV_STL ; Represent an atomic store or store-release.
856 UNSPECV_ATOMIC_CMPSW ; Represent an atomic compare swap.
857 UNSPECV_ATOMIC_EXCHG ; Represent an atomic exchange.
858 UNSPECV_ATOMIC_CAS ; Represent an atomic CAS.
859 UNSPECV_ATOMIC_SWP ; Represent an atomic SWP.
860 UNSPECV_ATOMIC_OP ; Represent an atomic operation.
861 UNSPECV_ATOMIC_LDOP_OR ; Represent an atomic load-or
862 UNSPECV_ATOMIC_LDOP_BIC ; Represent an atomic load-bic
863 UNSPECV_ATOMIC_LDOP_XOR ; Represent an atomic load-xor
864 UNSPECV_ATOMIC_LDOP_PLUS ; Represent an atomic load-add
867 ;; -------------------------------------------------------------------
869 ;; -------------------------------------------------------------------
871 ;; "e" for signaling operations, "" for quiet operations.
872 (define_mode_attr e [(CCFP "") (CCFPE "e")])
874 ;; In GPI templates, a string like "%<w>0" will expand to "%w0" in the
875 ;; 32-bit version and "%x0" in the 64-bit version.
876 (define_mode_attr w [(QI "w") (HI "w") (SI "w") (DI "x") (SF "s") (DF "d")])
878 ;; The size of access, in bytes.
879 (define_mode_attr ldst_sz [(SI "4") (DI "8")])
880 ;; Likewise for load/store pair.
881 (define_mode_attr ldpstp_sz [(SI "8") (DI "16")])
883 ;; For inequal width int to float conversion
884 (define_mode_attr w1 [(HF "w") (SF "w") (DF "x")])
885 (define_mode_attr w2 [(HF "x") (SF "x") (DF "w")])
887 ;; For width of fp registers in fcvt instruction
888 (define_mode_attr fpw [(DI "s") (SI "d")])
890 (define_mode_attr short_mask [(HI "65535") (QI "255")])
892 ;; For constraints used in scalar immediate vector moves
893 (define_mode_attr hq [(HI "h") (QI "q")])
895 ;; For doubling width of an integer mode
896 (define_mode_attr DWI [(QI "HI") (HI "SI") (SI "DI") (DI "TI")])
898 (define_mode_attr fcvt_change_mode [(SI "df") (DI "sf")])
900 (define_mode_attr FCVT_CHANGE_MODE [(SI "DF") (DI "SF")])
902 ;; For scalar usage of vector/FP registers
903 (define_mode_attr v [(QI "b") (HI "h") (SI "s") (DI "d")
904 (HF "h") (SF "s") (DF "d")
910 (V8HF "") (V2DF "")])
912 ;; For scalar usage of vector/FP registers, narrowing
913 (define_mode_attr vn2 [(QI "") (HI "b") (SI "h") (DI "s")
918 (V4SF "") (V2DF "")])
920 ;; For scalar usage of vector/FP registers, widening
921 (define_mode_attr vw2 [(DI "") (QI "h") (HI "s") (SI "d")
926 (V4SF "") (V2DF "")])
928 ;; Register Type Name and Vector Arrangement Specifier for when
929 ;; we are doing scalar for DI and SIMD for SI (ignoring all but
931 (define_mode_attr rtn [(DI "d") (SI "")])
932 (define_mode_attr vas [(DI "") (SI ".2s")])
934 ;; Map a vector to the number of units in it, if the size of the mode
936 (define_mode_attr nunits [(V8QI "8") (V16QI "16")
937 (V4HI "4") (V8HI "8")
938 (V2SI "2") (V4SI "4")
940 (V4HF "4") (V8HF "8")
941 (V4BF "4") (V8BF "8")
942 (V2SF "2") (V4SF "4")
943 (V1DF "1") (V2DF "2")
946 ;; Map a mode to the number of bits in it, if the size of the mode
948 (define_mode_attr bitsize [(V8QI "64") (V16QI "128")
949 (V4HI "64") (V8HI "128")
950 (V2SI "64") (V4SI "128")
953 ;; Map a floating point or integer mode to the appropriate register name prefix
954 (define_mode_attr s [(HF "h") (SF "s") (DF "d") (SI "s") (DI "d")])
956 ;; Give the length suffix letter for a sign- or zero-extension.
957 (define_mode_attr size [(QI "b") (HI "h") (SI "w")])
959 ;; Give the number of bits in the mode
960 (define_mode_attr sizen [(QI "8") (HI "16") (SI "32") (DI "64")])
962 ;; Give the ordinal of the MSB in the mode
963 (define_mode_attr sizem1 [(QI "#7") (HI "#15") (SI "#31") (DI "#63")
964 (HF "#15") (SF "#31") (DF "#63")])
966 ;; The number of bits in a vector element, or controlled by a predicate
968 (define_mode_attr elem_bits [(VNx16BI "8") (VNx8BI "16")
969 (VNx4BI "32") (VNx2BI "64")
970 (VNx16QI "8") (VNx8HI "16")
971 (VNx4SI "32") (VNx2DI "64")
972 (VNx8HF "16") (VNx4SF "32") (VNx2DF "64")])
974 ;; The number of bits in a vector container.
975 (define_mode_attr container_bits [(VNx16QI "8")
976 (VNx8HI "16") (VNx8QI "16") (VNx8HF "16")
978 (VNx4SI "32") (VNx4HI "32") (VNx4QI "32")
979 (VNx4SF "32") (VNx4HF "32") (VNx4BF "32")
980 (VNx2DI "64") (VNx2SI "64") (VNx2HI "64")
981 (VNx2QI "64") (VNx2DF "64") (VNx2SF "64")
982 (VNx2HF "64") (VNx2BF "64")])
984 ;; Attribute to describe constants acceptable in logical operations
985 (define_mode_attr lconst [(SI "K") (DI "L")])
987 ;; Attribute to describe constants acceptable in logical and operations
988 (define_mode_attr lconst2 [(SI "UsO") (DI "UsP")])
990 ;; Map a mode to a specific constraint character.
991 (define_mode_attr cmode [(QI "q") (HI "h") (SI "s") (DI "d")])
993 ;; Map modes to Usg and Usj constraints for SISD right shifts
994 (define_mode_attr cmode_simd [(SI "g") (DI "j")])
996 (define_mode_attr Vtype [(V8QI "8b") (V16QI "16b")
997 (V4HI "4h") (V8HI "8h")
998 (V4BF "4h") (V8BF "8h")
999 (V2SI "2s") (V4SI "4s")
1001 (V2DI "2d") (V2SF "2s")
1002 (V4SF "4s") (V2DF "2d")
1003 (V4HF "4h") (V8HF "8h")])
1005 ;; Map mode to type used in widening multiplies.
1006 (define_mode_attr Vcondtype [(V4HI "4h") (V8HI "4h") (V2SI "2s") (V4SI "2s")])
1008 ;; Map lane mode to name
1009 (define_mode_attr Qlane [(V4HI "_v4hi") (V8HI "q_v4hi")
1010 (V2SI "_v2si") (V4SI "q_v2si")])
1012 (define_mode_attr Vrevsuff [(V4HI "16") (V8HI "16") (V2SI "32")
1013 (V4SI "32") (V2DI "64")])
1015 (define_mode_attr Vmtype [(V8QI ".8b") (V16QI ".16b")
1016 (V4HI ".4h") (V8HI ".8h")
1017 (V2SI ".2s") (V4SI ".4s")
1018 (V2DI ".2d") (V4HF ".4h")
1019 (V8HF ".8h") (V4BF ".4h")
1020 (V8BF ".8h") (V2SF ".2s")
1021 (V4SF ".4s") (V2DF ".2d")
1027 ;; Register suffix narrowed modes for VQN.
1028 (define_mode_attr Vmntype [(V8HI ".8b") (V4SI ".4h")
1033 ;; Mode-to-individual element type mapping.
1034 (define_mode_attr Vetype [(V8QI "b") (V16QI "b")
1035 (V4HI "h") (V8HI "h")
1036 (V2SI "s") (V4SI "s")
1038 (V4HF "h") (V8HF "h")
1039 (V2SF "s") (V4SF "s")
1041 (VNx16BI "b") (VNx8BI "h") (VNx4BI "s") (VNx2BI "d")
1042 (VNx16QI "b") (VNx8QI "b") (VNx4QI "b") (VNx2QI "b")
1043 (VNx8HI "h") (VNx4HI "h") (VNx2HI "h")
1044 (VNx8HF "h") (VNx4HF "h") (VNx2HF "h")
1045 (VNx8BF "h") (VNx4BF "h") (VNx2BF "h")
1046 (VNx4SI "s") (VNx2SI "s")
1047 (VNx4SF "s") (VNx2SF "s")
1050 (BF "h") (V4BF "h") (V8BF "h")
1056 ;; Like Vetype, but map to types that are a quarter of the element size.
1057 (define_mode_attr Vetype_fourth [(VNx4SI "b") (VNx2DI "h")])
1059 ;; Equivalent of "size" for a vector element.
1060 (define_mode_attr Vesize [(VNx16QI "b") (VNx8QI "b") (VNx4QI "b") (VNx2QI "b")
1061 (VNx8HI "h") (VNx4HI "h") (VNx2HI "h")
1062 (VNx8HF "h") (VNx4HF "h") (VNx2HF "h")
1063 (VNx8BF "h") (VNx4BF "h") (VNx2BF "h")
1064 (VNx4SI "w") (VNx2SI "w")
1065 (VNx4SF "w") (VNx2SF "w")
1068 (VNx32QI "b") (VNx48QI "b") (VNx64QI "b")
1069 (VNx16HI "h") (VNx24HI "h") (VNx32HI "h")
1070 (VNx16HF "h") (VNx24HF "h") (VNx32HF "h")
1071 (VNx16BF "h") (VNx24BF "h") (VNx32BF "h")
1072 (VNx8SI "w") (VNx12SI "w") (VNx16SI "w")
1073 (VNx8SF "w") (VNx12SF "w") (VNx16SF "w")
1074 (VNx4DI "d") (VNx6DI "d") (VNx8DI "d")
1075 (VNx4DF "d") (VNx6DF "d") (VNx8DF "d")])
1077 ;; The Z register suffix for an SVE mode's element container, i.e. the
1078 ;; Vetype of full SVE modes that have the same number of elements.
1079 (define_mode_attr Vctype [(VNx16QI "b") (VNx8QI "h") (VNx4QI "s") (VNx2QI "d")
1080 (VNx8HI "h") (VNx4HI "s") (VNx2HI "d")
1081 (VNx8HF "h") (VNx4HF "s") (VNx2HF "d")
1082 (VNx8BF "h") (VNx4BF "s") (VNx2BF "d")
1083 (VNx4SI "s") (VNx2SI "d")
1084 (VNx4SF "s") (VNx2SF "d")
1088 ;; The instruction mnemonic suffix for an SVE mode's element container,
1089 ;; i.e. the Vewtype of full SVE modes that have the same number of elements.
1090 (define_mode_attr Vcwtype [(VNx16QI "b") (VNx8QI "h") (VNx4QI "w") (VNx2QI "d")
1091 (VNx8HI "h") (VNx4HI "w") (VNx2HI "d")
1092 (VNx8HF "h") (VNx4HF "w") (VNx2HF "d")
1093 (VNx8BF "h") (VNx4BF "w") (VNx2BF "d")
1094 (VNx4SI "w") (VNx2SI "d")
1095 (VNx4SF "w") (VNx2SF "d")
1099 ;; Vetype is used everywhere in scheduling type and assembly output,
1100 ;; sometimes they are not the same, for example HF modes on some
1101 ;; instructions. stype is defined to represent scheduling type
1103 (define_mode_attr stype [(V8QI "b") (V16QI "b") (V4HI "s") (V8HI "s")
1104 (V2SI "s") (V4SI "s") (V2DI "d") (V4HF "s")
1105 (V8HF "s") (V2SF "s") (V4SF "s") (V2DF "d")
1106 (HF "s") (SF "s") (DF "d") (QI "b") (HI "s")
1109 ;; Mode-to-bitwise operation type mapping.
1110 (define_mode_attr Vbtype [(V8QI "8b") (V16QI "16b")
1111 (V4HI "8b") (V8HI "16b")
1112 (V2SI "8b") (V4SI "16b")
1113 (V2DI "16b") (V4HF "8b")
1114 (V8HF "16b") (V2SF "8b")
1115 (V4SF "16b") (V2DF "16b")
1118 (V4BF "8b") (V8BF "16b")])
1120 ;; Define element mode for each vector mode.
1121 (define_mode_attr VEL [(V8QI "QI") (V16QI "QI")
1122 (V4HI "HI") (V8HI "HI")
1123 (V2SI "SI") (V4SI "SI")
1124 (DI "DI") (V2DI "DI")
1125 (V4HF "HF") (V8HF "HF")
1126 (V2SF "SF") (V4SF "SF")
1127 (DF "DF") (V2DF "DF")
1130 (V4BF "BF") (V8BF "BF")
1131 (VNx16QI "QI") (VNx8QI "QI") (VNx4QI "QI") (VNx2QI "QI")
1132 (VNx8HI "HI") (VNx4HI "HI") (VNx2HI "HI")
1133 (VNx8HF "HF") (VNx4HF "HF") (VNx2HF "HF")
1134 (VNx8BF "BF") (VNx4BF "BF") (VNx2BF "BF")
1135 (VNx4SI "SI") (VNx2SI "SI")
1136 (VNx4SF "SF") (VNx2SF "SF")
1140 ;; Define element mode for each vector mode (lower case).
1141 (define_mode_attr Vel [(V8QI "qi") (V16QI "qi")
1142 (V4HI "hi") (V8HI "hi")
1143 (V2SI "si") (V4SI "si")
1144 (DI "di") (V2DI "di")
1145 (V4HF "hf") (V8HF "hf")
1146 (V2SF "sf") (V4SF "sf")
1147 (V2DF "df") (DF "df")
1150 (V4BF "bf") (V8BF "bf")
1151 (VNx16QI "qi") (VNx8QI "qi") (VNx4QI "qi") (VNx2QI "qi")
1152 (VNx8HI "hi") (VNx4HI "hi") (VNx2HI "hi")
1153 (VNx8HF "hf") (VNx4HF "hf") (VNx2HF "hf")
1154 (VNx8BF "bf") (VNx4BF "bf") (VNx2BF "bf")
1155 (VNx4SI "si") (VNx2SI "si")
1156 (VNx4SF "sf") (VNx2SF "sf")
1160 ;; Element mode with floating-point values replaced by like-sized integers.
1161 (define_mode_attr VEL_INT [(VNx16QI "QI")
1162 (VNx8HI "HI") (VNx8HF "HI") (VNx8BF "HI")
1163 (VNx4SI "SI") (VNx4SF "SI")
1164 (VNx2DI "DI") (VNx2DF "DI")])
1166 ;; Gives the mode of the 128-bit lowpart of an SVE vector.
1167 (define_mode_attr V128 [(VNx16QI "V16QI")
1168 (VNx8HI "V8HI") (VNx8HF "V8HF") (VNx8BF "V8BF")
1169 (VNx4SI "V4SI") (VNx4SF "V4SF")
1170 (VNx2DI "V2DI") (VNx2DF "V2DF")])
1172 ;; ...and again in lower case.
1173 (define_mode_attr v128 [(VNx16QI "v16qi")
1174 (VNx8HI "v8hi") (VNx8HF "v8hf") (VNx8BF "v8bf")
1175 (VNx4SI "v4si") (VNx4SF "v4sf")
1176 (VNx2DI "v2di") (VNx2DF "v2df")])
1178 ;; 64-bit container modes the inner or scalar source mode.
1179 (define_mode_attr VCOND [(HI "V4HI") (SI "V2SI")
1180 (V4HI "V4HI") (V8HI "V4HI")
1181 (V2SI "V2SI") (V4SI "V2SI")
1182 (DI "DI") (V2DI "DI")
1183 (V2SF "V2SF") (V4SF "V2SF")
1186 ;; 128-bit container modes the inner or scalar source mode.
1187 (define_mode_attr VCONQ [(V8QI "V16QI") (V16QI "V16QI")
1188 (V4HI "V8HI") (V8HI "V8HI")
1189 (V2SI "V4SI") (V4SI "V4SI")
1190 (DI "V2DI") (V2DI "V2DI")
1191 (V4HF "V8HF") (V8HF "V8HF")
1192 (V2SF "V2SF") (V4SF "V4SF")
1193 (V2DF "V2DF") (SI "V4SI")
1194 (HI "V8HI") (QI "V16QI")])
1196 ;; Half modes of all vector modes.
1197 (define_mode_attr VHALF [(V8QI "V4QI") (V16QI "V8QI")
1198 (V4HI "V2HI") (V8HI "V4HI")
1199 (V2SI "SI") (V4SI "V2SI")
1200 (V2DI "DI") (V2SF "SF")
1201 (V4SF "V2SF") (V4HF "V2HF")
1202 (V8HF "V4HF") (V2DF "DF")
1205 ;; Half modes of all vector modes, in lower-case.
1206 (define_mode_attr Vhalf [(V8QI "v4qi") (V16QI "v8qi")
1207 (V4HI "v2hi") (V8HI "v4hi")
1208 (V8HF "v4hf") (V8BF "v4bf")
1209 (V2SI "si") (V4SI "v2si")
1210 (V2DI "di") (V2SF "sf")
1211 (V4SF "v2sf") (V2DF "df")])
1213 ;; Double modes of vector modes.
1214 (define_mode_attr VDBL [(V8QI "V16QI") (V4HI "V8HI")
1215 (V4HF "V8HF") (V4BF "V8BF")
1216 (V2SI "V4SI") (V2SF "V4SF")
1217 (SI "V2SI") (DI "V2DI")
1220 ;; Register suffix for double-length mode.
1221 (define_mode_attr Vdtype [(V4HF "8h") (V2SF "4s")])
1223 ;; Double modes of vector modes (lower case).
1224 (define_mode_attr Vdbl [(V8QI "v16qi") (V4HI "v8hi")
1225 (V4HF "v8hf") (V4BF "v8bf")
1226 (V2SI "v4si") (V2SF "v4sf")
1227 (SI "v2si") (DI "v2di")
1230 ;; Modes with double-width elements.
1231 (define_mode_attr VDBLW [(V8QI "V4HI") (V16QI "V8HI")
1232 (V4HI "V2SI") (V8HI "V4SI")
1233 (V2SI "DI") (V4SI "V2DI")])
1235 ;; Narrowed modes for VDN.
1236 (define_mode_attr VNARROWD [(V4HI "V8QI") (V2SI "V4HI")
1239 ;; Narrowed double-modes for VQN (Used for XTN).
1240 (define_mode_attr VNARROWQ [(V8HI "V8QI") (V4SI "V4HI")
1244 (define_mode_attr Vnarrowq [(V8HI "v8qi") (V4SI "v4hi")
1247 ;; Narrowed quad-modes for VQN (Used for XTN2).
1248 (define_mode_attr VNARROWQ2 [(V8HI "V16QI") (V4SI "V8HI")
1251 ;; Narrowed modes of vector modes.
1252 (define_mode_attr VNARROW [(VNx8HI "VNx16QI")
1253 (VNx4SI "VNx8HI") (VNx4SF "VNx8HF")
1254 (VNx2DI "VNx4SI") (VNx2DF "VNx4SF")])
1256 ;; Register suffix narrowed modes for VQN.
1257 (define_mode_attr Vntype [(V8HI "8b") (V4SI "4h")
1260 ;; Register suffix narrowed modes for VQN.
1261 (define_mode_attr V2ntype [(V8HI "16b") (V4SI "8h")
1264 ;; Widened modes of vector modes.
1265 (define_mode_attr VWIDE [(V8QI "V8HI") (V4HI "V4SI")
1266 (V2SI "V2DI") (V16QI "V8HI")
1267 (V8HI "V4SI") (V4SI "V2DI")
1269 (V8HF "V4SF") (V4SF "V2DF")
1270 (V4HF "V4SF") (V2SF "V2DF")
1271 (VNx8HF "VNx4SF") (VNx4SF "VNx2DF")
1272 (VNx16QI "VNx8HI") (VNx8HI "VNx4SI")
1274 (VNx16BI "VNx8BI") (VNx8BI "VNx4BI")
1277 ;; Predicate mode associated with VWIDE.
1278 (define_mode_attr VWIDE_PRED [(VNx8HF "VNx4BI") (VNx4SF "VNx2BI")])
1280 ;; Widened modes of vector modes, lowercase
1281 (define_mode_attr Vwide [(V2SF "v2df") (V4HF "v4sf")
1282 (VNx16QI "vnx8hi") (VNx8HI "vnx4si")
1284 (VNx8HF "vnx4sf") (VNx4SF "vnx2df")
1285 (VNx16BI "vnx8bi") (VNx8BI "vnx4bi")
1288 ;; Widened mode register suffixes for VD_BHSI/VQW/VQ_HSF.
1289 (define_mode_attr Vwtype [(V8QI "8h") (V4HI "4s")
1290 (V2SI "2d") (V16QI "8h")
1291 (V8HI "4s") (V4SI "2d")
1292 (V8HF "4s") (V4SF "2d")])
1294 ;; SVE vector after narrowing.
1295 (define_mode_attr Ventype [(VNx8HI "b")
1296 (VNx4SI "h") (VNx4SF "h")
1297 (VNx2DI "s") (VNx2DF "s")])
1299 ;; SVE vector after widening.
1300 (define_mode_attr Vewtype [(VNx16QI "h")
1301 (VNx8HI "s") (VNx8HF "s")
1302 (VNx4SI "d") (VNx4SF "d")
1305 ;; Widened mode register suffixes for VDW/VQW.
1306 (define_mode_attr Vmwtype [(V8QI ".8h") (V4HI ".4s")
1307 (V2SI ".2d") (V16QI ".8h")
1308 (V8HI ".4s") (V4SI ".2d")
1309 (V4HF ".4s") (V2SF ".2d")
1312 ;; Lower part register suffixes for VQW/VQ_HSF.
1313 (define_mode_attr Vhalftype [(V16QI "8b") (V8HI "4h")
1314 (V4SI "2s") (V8HF "4h")
1317 ;; Define corresponding core/FP element mode for each vector mode.
1318 (define_mode_attr vw [(V8QI "w") (V16QI "w")
1319 (V4HI "w") (V8HI "w")
1320 (V2SI "w") (V4SI "w")
1322 (V2SF "s") (V4SF "s")
1325 ;; Corresponding core element mode for each vector mode. This is a
1326 ;; variation on <vw> mapping FP modes to GP regs.
1327 (define_mode_attr vwcore [(V8QI "w") (V16QI "w")
1328 (V4HI "w") (V8HI "w")
1329 (V2SI "w") (V4SI "w")
1331 (V4HF "w") (V8HF "w")
1332 (V2SF "w") (V4SF "w")
1334 (VNx16QI "w") (VNx8QI "w") (VNx4QI "w") (VNx2QI "w")
1335 (VNx8HI "w") (VNx4HI "w") (VNx2HI "w")
1336 (VNx8HF "w") (VNx4HF "w") (VNx2HF "w")
1337 (VNx8BF "w") (VNx4BF "w") (VNx2BF "w")
1338 (VNx4SI "w") (VNx2SI "w")
1339 (VNx4SF "w") (VNx2SF "w")
1343 ;; Like vwcore, but for the container mode rather than the element mode.
1344 (define_mode_attr vccore [(VNx16QI "w") (VNx8QI "w") (VNx4QI "w") (VNx2QI "x")
1345 (VNx8HI "w") (VNx4HI "w") (VNx2HI "x")
1346 (VNx4SI "w") (VNx2SI "x")
1349 ;; Double vector types for ALLX.
1350 (define_mode_attr Vallxd [(QI "8b") (HI "4h") (SI "2s")])
1352 ;; Mode with floating-point values replaced by like-sized integers.
1353 (define_mode_attr V_INT_EQUIV [(V8QI "V8QI") (V16QI "V16QI")
1354 (V4HI "V4HI") (V8HI "V8HI")
1355 (V2SI "V2SI") (V4SI "V4SI")
1356 (DI "DI") (V2DI "V2DI")
1357 (V4HF "V4HI") (V8HF "V8HI")
1358 (V4BF "V4HI") (V8BF "V8HI")
1359 (V2SF "V2SI") (V4SF "V4SI")
1360 (DF "DI") (V2DF "V2DI")
1364 (VNx8HI "VNx8HI") (VNx8HF "VNx8HI")
1366 (VNx4SI "VNx4SI") (VNx4SF "VNx4SI")
1367 (VNx2DI "VNx2DI") (VNx2DF "VNx2DI")
1370 ;; Lower case mode with floating-point values replaced by like-sized integers.
1371 (define_mode_attr v_int_equiv [(V8QI "v8qi") (V16QI "v16qi")
1372 (V4HI "v4hi") (V8HI "v8hi")
1373 (V2SI "v2si") (V4SI "v4si")
1374 (DI "di") (V2DI "v2di")
1375 (V4HF "v4hi") (V8HF "v8hi")
1376 (V4BF "v4hi") (V8BF "v8hi")
1377 (V2SF "v2si") (V4SF "v4si")
1378 (DF "di") (V2DF "v2di")
1381 (VNx8HI "vnx8hi") (VNx8HF "vnx8hi")
1383 (VNx4SI "vnx4si") (VNx4SF "vnx4si")
1384 (VNx2DI "vnx2di") (VNx2DF "vnx2di")
1387 ;; Floating-point equivalent of selected modes.
1388 (define_mode_attr V_FP_EQUIV [(VNx8HI "VNx8HF") (VNx8HF "VNx8HF")
1390 (VNx4SI "VNx4SF") (VNx4SF "VNx4SF")
1391 (VNx2DI "VNx2DF") (VNx2DF "VNx2DF")])
1392 (define_mode_attr v_fp_equiv [(VNx8HI "vnx8hf") (VNx8HF "vnx8hf")
1394 (VNx4SI "vnx4sf") (VNx4SF "vnx4sf")
1395 (VNx2DI "vnx2df") (VNx2DF "vnx2df")])
1397 ;; Maps full and partial vector modes of any element type to a full-vector
1398 ;; integer mode with the same number of units.
1399 (define_mode_attr V_INT_CONTAINER [(VNx16QI "VNx16QI") (VNx8QI "VNx8HI")
1400 (VNx4QI "VNx4SI") (VNx2QI "VNx2DI")
1401 (VNx8HI "VNx8HI") (VNx4HI "VNx4SI")
1403 (VNx4SI "VNx4SI") (VNx2SI "VNx2DI")
1405 (VNx8HF "VNx8HI") (VNx4HF "VNx4SI")
1407 (VNx8BF "VNx8HI") (VNx4BF "VNx4SI")
1409 (VNx4SF "VNx4SI") (VNx2SF "VNx2DI")
1412 ;; Lower-case version of V_INT_CONTAINER.
1413 (define_mode_attr v_int_container [(VNx16QI "vnx16qi") (VNx8QI "vnx8hi")
1414 (VNx4QI "vnx4si") (VNx2QI "vnx2di")
1415 (VNx8HI "vnx8hi") (VNx4HI "vnx4si")
1417 (VNx4SI "vnx4si") (VNx2SI "vnx2di")
1419 (VNx8HF "vnx8hi") (VNx4HF "vnx4si")
1421 (VNx8BF "vnx8hi") (VNx4BF "vnx4si")
1423 (VNx4SF "vnx4si") (VNx2SF "vnx2di")
1426 ;; Mode for vector conditional operations where the comparison has
1427 ;; different type from the lhs.
1428 (define_mode_attr V_cmp_mixed [(V2SI "V2SF") (V4SI "V4SF")
1429 (V2DI "V2DF") (V2SF "V2SI")
1430 (V4SF "V4SI") (V2DF "V2DI")])
1432 (define_mode_attr v_cmp_mixed [(V2SI "v2sf") (V4SI "v4sf")
1433 (V2DI "v2df") (V2SF "v2si")
1434 (V4SF "v4si") (V2DF "v2di")])
1436 ;; Lower case element modes (as used in shift immediate patterns).
1437 (define_mode_attr ve_mode [(V8QI "qi") (V16QI "qi")
1438 (V4HI "hi") (V8HI "hi")
1439 (V2SI "si") (V4SI "si")
1440 (DI "di") (V2DI "di")
1444 ;; Vm for lane instructions is restricted to FP_LO_REGS.
1445 (define_mode_attr vwx [(V4HI "x") (V8HI "x") (HI "x")
1446 (V2SI "w") (V4SI "w") (SI "w")])
1448 (define_mode_attr Vendreg [(OI "T") (CI "U") (XI "V")])
1450 ;; This is both the number of Q-Registers needed to hold the corresponding
1451 ;; opaque large integer mode, and the number of elements touched by the
1452 ;; ld..._lane and st..._lane operations.
1453 (define_mode_attr nregs [(OI "2") (CI "3") (XI "4")])
1455 ;; Mode for atomic operation suffixes
1456 (define_mode_attr atomic_sfx
1457 [(QI "b") (HI "h") (SI "") (DI "")])
1459 (define_mode_attr fcvt_target [(V2DF "v2di") (V4SF "v4si") (V2SF "v2si")
1460 (V2DI "v2df") (V4SI "v4sf") (V2SI "v2sf")
1461 (SF "si") (DF "di") (SI "sf") (DI "df")
1462 (V4HF "v4hi") (V8HF "v8hi") (V4HI "v4hf")
1463 (V8HI "v8hf") (HF "hi") (HI "hf")])
1464 (define_mode_attr FCVT_TARGET [(V2DF "V2DI") (V4SF "V4SI") (V2SF "V2SI")
1465 (V2DI "V2DF") (V4SI "V4SF") (V2SI "V2SF")
1466 (SF "SI") (DF "DI") (SI "SF") (DI "DF")
1467 (V4HF "V4HI") (V8HF "V8HI") (V4HI "V4HF")
1468 (V8HI "V8HF") (HF "HI") (HI "HF")])
1471 ;; for the inequal width integer to fp conversions
1472 (define_mode_attr fcvt_iesize [(HF "di") (SF "di") (DF "si")])
1473 (define_mode_attr FCVT_IESIZE [(HF "DI") (SF "DI") (DF "SI")])
1475 (define_mode_attr VSWAP_WIDTH [(V8QI "V16QI") (V16QI "V8QI")
1476 (V4HI "V8HI") (V8HI "V4HI")
1477 (V8BF "V4BF") (V4BF "V8BF")
1478 (V2SI "V4SI") (V4SI "V2SI")
1479 (DI "V2DI") (V2DI "DI")
1480 (V2SF "V4SF") (V4SF "V2SF")
1481 (V4HF "V8HF") (V8HF "V4HF")
1482 (DF "V2DF") (V2DF "DF")])
1484 (define_mode_attr vswap_width_name [(V8QI "to_128") (V16QI "to_64")
1485 (V4HI "to_128") (V8HI "to_64")
1486 (V2SI "to_128") (V4SI "to_64")
1487 (DI "to_128") (V2DI "to_64")
1488 (V4HF "to_128") (V8HF "to_64")
1489 (V2SF "to_128") (V4SF "to_64")
1490 (V4BF "to_128") (V8BF "to_64")
1491 (DF "to_128") (V2DF "to_64")])
1493 ;; For certain vector-by-element multiplication instructions we must
1494 ;; constrain the 16-bit cases to use only V0-V15. This is covered by
1495 ;; the 'x' constraint. All other modes may use the 'w' constraint.
1496 (define_mode_attr h_con [(V2SI "w") (V4SI "w")
1497 (V4HI "x") (V8HI "x")
1498 (V4HF "x") (V8HF "x")
1499 (V2SF "w") (V4SF "w")
1500 (V2DF "w") (DF "w")])
1502 ;; Defined to 'f' for types whose element type is a float type.
1503 (define_mode_attr f [(V8QI "") (V16QI "")
1507 (V4HF "f") (V8HF "f")
1508 (V2SF "f") (V4SF "f")
1509 (V2DF "f") (DF "f")])
1511 ;; Defined to '_fp' for types whose element type is a float type.
1512 (define_mode_attr fp [(V8QI "") (V16QI "")
1516 (V4HF "_fp") (V8HF "_fp")
1517 (V2SF "_fp") (V4SF "_fp")
1518 (V2DF "_fp") (DF "_fp")
1521 ;; Defined to '_q' for 128-bit types.
1522 (define_mode_attr q [(V8QI "") (V16QI "_q")
1523 (V4HI "") (V8HI "_q")
1524 (V4BF "") (V8BF "_q")
1525 (V2SI "") (V4SI "_q")
1527 (V4HF "") (V8HF "_q")
1528 (V4BF "") (V8BF "_q")
1529 (V2SF "") (V4SF "_q")
1531 (QI "") (HI "") (SI "") (DI "") (HF "") (SF "") (DF "")])
1533 (define_mode_attr vp [(V8QI "v") (V16QI "v")
1534 (V4HI "v") (V8HI "v")
1535 (V2SI "p") (V4SI "v")
1536 (V2DI "p") (V2DF "p")
1537 (V2SF "p") (V4SF "v")
1538 (V4HF "v") (V8HF "v")])
1540 (define_mode_attr vsi2qi [(V2SI "v8qi") (V4SI "v16qi")
1541 (VNx4SI "vnx16qi") (VNx2DI "vnx8hi")])
1542 (define_mode_attr VSI2QI [(V2SI "V8QI") (V4SI "V16QI")
1543 (VNx4SI "VNx16QI") (VNx2DI "VNx8HI")])
1546 ;; Register suffix for DOTPROD input types from the return type.
1547 (define_mode_attr Vdottype [(V2SI "8b") (V4SI "16b")])
1549 ;; Register suffix for BFDOT input types from the return type.
1550 (define_mode_attr Vbfdottype [(V2SF "4h") (V4SF "8h")])
1552 ;; Sum of lengths of instructions needed to move vector registers of a mode.
1553 (define_mode_attr insn_count [(OI "8") (CI "12") (XI "16")])
1555 ;; -fpic small model GOT reloc modifers: gotpage_lo15/lo14 for ILP64/32.
1556 ;; No need of iterator for -fPIC as it use got_lo12 for both modes.
1557 (define_mode_attr got_modifier [(SI "gotpage_lo14") (DI "gotpage_lo15")])
1559 ;; Width of 2nd and 3rd arguments to fp16 vector multiply add/sub
1560 (define_mode_attr VFMLA_W [(V2SF "V4HF") (V4SF "V8HF")])
1562 ;; Width of 2nd and 3rd arguments to bf16 vector multiply add/sub
1563 (define_mode_attr VBFMLA_W [(V2SF "V4BF") (V4SF "V8BF")])
1565 (define_mode_attr VFMLA_SEL_W [(V2SF "V2HF") (V4SF "V4HF")])
1567 (define_mode_attr f16quad [(V2SF "") (V4SF "q")])
1569 (define_mode_attr isquadop [(V8QI "") (V16QI "q") (V4BF "") (V8BF "q")])
1571 (define_code_attr f16mac [(plus "a") (minus "s")])
1573 ;; Map smax to smin and umax to umin.
1574 (define_code_attr max_opp [(smax "smin") (umax "umin")])
1576 ;; Same as above, but louder.
1577 (define_code_attr MAX_OPP [(smax "SMIN") (umax "UMIN")])
1579 ;; The number of subvectors in an SVE_STRUCT.
1580 (define_mode_attr vector_count [(VNx32QI "2") (VNx16HI "2")
1581 (VNx8SI "2") (VNx4DI "2")
1583 (VNx16HF "2") (VNx8SF "2") (VNx4DF "2")
1584 (VNx48QI "3") (VNx24HI "3")
1585 (VNx12SI "3") (VNx6DI "3")
1587 (VNx24HF "3") (VNx12SF "3") (VNx6DF "3")
1588 (VNx64QI "4") (VNx32HI "4")
1589 (VNx16SI "4") (VNx8DI "4")
1591 (VNx32HF "4") (VNx16SF "4") (VNx8DF "4")])
1593 ;; The number of instruction bytes needed for an SVE_STRUCT move. This is
1594 ;; equal to vector_count * 4.
1595 (define_mode_attr insn_length [(VNx32QI "8") (VNx16HI "8")
1596 (VNx8SI "8") (VNx4DI "8")
1598 (VNx16HF "8") (VNx8SF "8") (VNx4DF "8")
1599 (VNx48QI "12") (VNx24HI "12")
1600 (VNx12SI "12") (VNx6DI "12")
1602 (VNx24HF "12") (VNx12SF "12") (VNx6DF "12")
1603 (VNx64QI "16") (VNx32HI "16")
1604 (VNx16SI "16") (VNx8DI "16")
1606 (VNx32HF "16") (VNx16SF "16") (VNx8DF "16")])
1608 ;; The type of a subvector in an SVE_STRUCT.
1609 (define_mode_attr VSINGLE [(VNx32QI "VNx16QI")
1610 (VNx16HI "VNx8HI") (VNx16HF "VNx8HF")
1612 (VNx8SI "VNx4SI") (VNx8SF "VNx4SF")
1613 (VNx4DI "VNx2DI") (VNx4DF "VNx2DF")
1615 (VNx24HI "VNx8HI") (VNx24HF "VNx8HF")
1617 (VNx12SI "VNx4SI") (VNx12SF "VNx4SF")
1618 (VNx6DI "VNx2DI") (VNx6DF "VNx2DF")
1620 (VNx32HI "VNx8HI") (VNx32HF "VNx8HF")
1622 (VNx16SI "VNx4SI") (VNx16SF "VNx4SF")
1623 (VNx8DI "VNx2DI") (VNx8DF "VNx2DF")])
1625 ;; ...and again in lower case.
1626 (define_mode_attr vsingle [(VNx32QI "vnx16qi")
1627 (VNx16HI "vnx8hi") (VNx16HF "vnx8hf")
1629 (VNx8SI "vnx4si") (VNx8SF "vnx4sf")
1630 (VNx4DI "vnx2di") (VNx4DF "vnx2df")
1632 (VNx24HI "vnx8hi") (VNx24HF "vnx8hf")
1634 (VNx12SI "vnx4si") (VNx12SF "vnx4sf")
1635 (VNx6DI "vnx2di") (VNx6DF "vnx2df")
1637 (VNx32HI "vnx8hi") (VNx32HF "vnx8hf")
1639 (VNx16SI "vnx4si") (VNx16SF "vnx4sf")
1640 (VNx8DI "vnx2di") (VNx8DF "vnx2df")])
1642 ;; The predicate mode associated with an SVE data mode. For structure modes
1643 ;; this is equivalent to the <VPRED> of the subvector mode.
1644 (define_mode_attr VPRED [(VNx16QI "VNx16BI") (VNx8QI "VNx8BI")
1645 (VNx4QI "VNx4BI") (VNx2QI "VNx2BI")
1646 (VNx8HI "VNx8BI") (VNx4HI "VNx4BI") (VNx2HI "VNx2BI")
1647 (VNx8HF "VNx8BI") (VNx4HF "VNx4BI") (VNx2HF "VNx2BI")
1648 (VNx8BF "VNx8BI") (VNx4BF "VNx4BI") (VNx2BF "VNx2BI")
1649 (VNx4SI "VNx4BI") (VNx2SI "VNx2BI")
1650 (VNx4SF "VNx4BI") (VNx2SF "VNx2BI")
1654 (VNx16HI "VNx8BI") (VNx16HF "VNx8BI")
1656 (VNx8SI "VNx4BI") (VNx8SF "VNx4BI")
1657 (VNx4DI "VNx2BI") (VNx4DF "VNx2BI")
1659 (VNx24HI "VNx8BI") (VNx24HF "VNx8BI")
1661 (VNx12SI "VNx4BI") (VNx12SF "VNx4BI")
1662 (VNx6DI "VNx2BI") (VNx6DF "VNx2BI")
1664 (VNx32HI "VNx8BI") (VNx32HF "VNx8BI")
1666 (VNx16SI "VNx4BI") (VNx16SF "VNx4BI")
1667 (VNx8DI "VNx2BI") (VNx8DF "VNx2BI")])
1669 ;; ...and again in lower case.
1670 (define_mode_attr vpred [(VNx16QI "vnx16bi") (VNx8QI "vnx8bi")
1671 (VNx4QI "vnx4bi") (VNx2QI "vnx2bi")
1672 (VNx8HI "vnx8bi") (VNx4HI "vnx4bi") (VNx2HI "vnx2bi")
1673 (VNx8HF "vnx8bi") (VNx4HF "vnx4bi") (VNx2HF "vnx2bi")
1674 (VNx8BF "vnx8bi") (VNx4BF "vnx4bi") (VNx2BF "vnx2bi")
1675 (VNx4SI "vnx4bi") (VNx2SI "vnx2bi")
1676 (VNx4SF "vnx4bi") (VNx2SF "vnx2bi")
1680 (VNx16HI "vnx8bi") (VNx16HF "vnx8bi")
1682 (VNx8SI "vnx4bi") (VNx8SF "vnx4bi")
1683 (VNx4DI "vnx2bi") (VNx4DF "vnx2bi")
1685 (VNx24HI "vnx8bi") (VNx24HF "vnx8bi")
1687 (VNx12SI "vnx4bi") (VNx12SF "vnx4bi")
1688 (VNx6DI "vnx2bi") (VNx6DF "vnx2bi")
1690 (VNx32HI "vnx8bi") (VNx32HF "vnx4bi")
1692 (VNx16SI "vnx4bi") (VNx16SF "vnx4bi")
1693 (VNx8DI "vnx2bi") (VNx8DF "vnx2bi")])
1695 (define_mode_attr VDOUBLE [(VNx16QI "VNx32QI")
1696 (VNx8HI "VNx16HI") (VNx8HF "VNx16HF")
1698 (VNx4SI "VNx8SI") (VNx4SF "VNx8SF")
1699 (VNx2DI "VNx4DI") (VNx2DF "VNx4DF")])
1701 ;; On AArch64 the By element instruction doesn't have a 2S variant.
1702 ;; However because the instruction always selects a pair of values
1703 ;; The normal 3SAME instruction can be used here instead.
1704 (define_mode_attr FCMLA_maybe_lane [(V2SF "<Vtype>") (V4SF "<Vetype>[%4]")
1705 (V4HF "<Vetype>[%4]") (V8HF "<Vetype>[%4]")
1708 ;; The number of bytes controlled by a predicate
1709 (define_mode_attr data_bytes [(VNx16BI "1") (VNx8BI "2")
1710 (VNx4BI "4") (VNx2BI "8")])
1712 ;; Two-nybble mask for partial vector modes: nunits, byte size.
1713 (define_mode_attr self_mask [(VNx8QI "0x81")
1720 ;; For SVE_HSDI vector modes, the mask of narrower modes, encoded as above.
1721 (define_mode_attr narrower_mask [(VNx8HI "0x81") (VNx4HI "0x41")
1723 (VNx4SI "0x43") (VNx2SI "0x23")
1726 ;; The constraint to use for an SVE [SU]DOT, FMUL, FMLA or FMLS lane index.
1727 (define_mode_attr sve_lane_con [(VNx8HI "y") (VNx4SI "y") (VNx2DI "x")
1728 (VNx8HF "y") (VNx4SF "y") (VNx2DF "x")])
1730 ;; The constraint to use for an SVE FCMLA lane index.
1731 (define_mode_attr sve_lane_pair_con [(VNx8HF "y") (VNx4SF "x")])
1733 ;; -------------------------------------------------------------------
1735 ;; -------------------------------------------------------------------
1737 ;; This code iterator allows the various shifts supported on the core
1738 (define_code_iterator SHIFT [ashift ashiftrt lshiftrt rotatert])
1740 ;; This code iterator allows the shifts supported in arithmetic instructions
1741 (define_code_iterator ASHIFT [ashift ashiftrt lshiftrt])
1743 (define_code_iterator SHIFTRT [ashiftrt lshiftrt])
1745 ;; Code iterator for logical operations
1746 (define_code_iterator LOGICAL [and ior xor])
1748 ;; LOGICAL without AND.
1749 (define_code_iterator LOGICAL_OR [ior xor])
1751 ;; Code iterator for logical operations whose :nlogical works on SIMD registers.
1752 (define_code_iterator NLOGICAL [and ior])
1754 ;; Code iterator for unary negate and bitwise complement.
1755 (define_code_iterator NEG_NOT [neg not])
1757 ;; Code iterator for sign/zero extension
1758 (define_code_iterator ANY_EXTEND [sign_extend zero_extend])
1759 (define_code_iterator ANY_EXTEND2 [sign_extend zero_extend])
1761 ;; All division operations (signed/unsigned)
1762 (define_code_iterator ANY_DIV [div udiv])
1764 ;; Code iterator for sign/zero extraction
1765 (define_code_iterator ANY_EXTRACT [sign_extract zero_extract])
1767 ;; Code iterator for equality comparisons
1768 (define_code_iterator EQL [eq ne])
1770 ;; Code iterator for less-than and greater/equal-to
1771 (define_code_iterator LTGE [lt ge])
1773 ;; Iterator for __sync_<op> operations that where the operation can be
1774 ;; represented directly RTL. This is all of the sync operations bar
1776 (define_code_iterator atomic_op [plus minus ior xor and])
1778 ;; Iterator for integer conversions
1779 (define_code_iterator FIXUORS [fix unsigned_fix])
1781 ;; Iterator for float conversions
1782 (define_code_iterator FLOATUORS [float unsigned_float])
1784 ;; Code iterator for variants of vector max and min.
1785 (define_code_iterator MAXMIN [smax smin umax umin])
1787 (define_code_iterator FMAXMIN [smax smin])
1789 ;; Signed and unsigned max operations.
1790 (define_code_iterator USMAX [smax umax])
1792 ;; Code iterator for plus and minus.
1793 (define_code_iterator ADDSUB [plus minus])
1795 ;; Code iterator for variants of vector saturating binary ops.
1796 (define_code_iterator BINQOPS [ss_plus us_plus ss_minus us_minus])
1798 ;; Code iterator for variants of vector saturating unary ops.
1799 (define_code_iterator UNQOPS [ss_neg ss_abs])
1801 ;; Code iterator for signed variants of vector saturating binary ops.
1802 (define_code_iterator SBINQOPS [ss_plus ss_minus])
1804 ;; Code iterator for unsigned variants of vector saturating binary ops.
1805 (define_code_iterator UBINQOPS [us_plus us_minus])
1807 ;; Modular and saturating addition.
1808 (define_code_iterator ANY_PLUS [plus ss_plus us_plus])
1810 ;; Saturating addition.
1811 (define_code_iterator SAT_PLUS [ss_plus us_plus])
1813 ;; Modular and saturating subtraction.
1814 (define_code_iterator ANY_MINUS [minus ss_minus us_minus])
1816 ;; Saturating subtraction.
1817 (define_code_iterator SAT_MINUS [ss_minus us_minus])
1819 ;; Comparison operators for <F>CM.
1820 (define_code_iterator COMPARISONS [lt le eq ge gt])
1822 ;; Unsigned comparison operators.
1823 (define_code_iterator UCOMPARISONS [ltu leu geu gtu])
1825 ;; Unsigned comparison operators.
1826 (define_code_iterator FAC_COMPARISONS [lt le ge gt])
1828 ;; SVE integer unary operations.
1829 (define_code_iterator SVE_INT_UNARY [abs neg not clrsb clz popcount
1830 (ss_abs "TARGET_SVE2")
1831 (ss_neg "TARGET_SVE2")])
1833 ;; SVE integer binary operations.
1834 (define_code_iterator SVE_INT_BINARY [plus minus mult smax umax smin umin
1835 ashift ashiftrt lshiftrt
1837 (ss_plus "TARGET_SVE2")
1838 (us_plus "TARGET_SVE2")
1839 (ss_minus "TARGET_SVE2")
1840 (us_minus "TARGET_SVE2")])
1842 ;; SVE integer binary division operations.
1843 (define_code_iterator SVE_INT_BINARY_SD [div udiv])
1845 ;; SVE integer binary operations that have an immediate form.
1846 (define_code_iterator SVE_INT_BINARY_IMM [mult smax smin umax umin])
1848 ;; SVE floating-point operations with an unpredicated all-register form.
1849 (define_code_iterator SVE_UNPRED_FP_BINARY [plus minus mult])
1851 ;; SVE integer comparisons.
1852 (define_code_iterator SVE_INT_CMP [lt le eq ne ge gt ltu leu geu gtu])
1854 ;; -------------------------------------------------------------------
1856 ;; -------------------------------------------------------------------
1857 ;; Map rtl objects to optab names
1858 (define_code_attr optab [(ashift "ashl")
1862 (sign_extend "extend")
1863 (zero_extend "zero_extend")
1864 (sign_extract "extv")
1865 (zero_extract "extzv")
1867 (unsigned_fix "fixuns")
1869 (unsigned_float "floatuns")
1872 (popcount "popcount")
1905 (define_code_attr addsub [(ss_plus "add")
1910 ;; For comparison operators we use the FCM* and CM* instructions.
1911 ;; As there are no CMLE or CMLT instructions which act on 3 vector
1912 ;; operands, we must use CMGE or CMGT and swap the order of the
1915 (define_code_attr n_optab [(lt "gt") (le "ge") (eq "eq") (ge "ge") (gt "gt")
1916 (ltu "hi") (leu "hs") (geu "hs") (gtu "hi")])
1917 (define_code_attr cmp_1 [(lt "2") (le "2") (eq "1") (ge "1") (gt "1")
1918 (ltu "2") (leu "2") (geu "1") (gtu "1")])
1919 (define_code_attr cmp_2 [(lt "1") (le "1") (eq "2") (ge "2") (gt "2")
1920 (ltu "1") (leu "1") (geu "2") (gtu "2")])
1922 (define_code_attr CMP [(lt "LT") (le "LE") (eq "EQ") (ge "GE") (gt "GT")
1923 (ltu "LTU") (leu "LEU") (ne "NE") (geu "GEU")
1926 ;; The AArch64 condition associated with an rtl comparison code.
1927 (define_code_attr cmp_op [(lt "lt")
1938 (define_code_attr fix_trunc_optab [(fix "fix_trunc")
1939 (unsigned_fix "fixuns_trunc")])
1941 ;; Optab prefix for sign/zero-extending operations
1942 (define_code_attr su_optab [(sign_extend "") (zero_extend "u")
1944 (fix "") (unsigned_fix "u")
1945 (float "s") (unsigned_float "u")
1946 (ss_plus "s") (us_plus "u")
1947 (ss_minus "s") (us_minus "u")])
1949 ;; Similar for the instruction mnemonics
1950 (define_code_attr shift [(ashift "lsl") (ashiftrt "asr")
1951 (lshiftrt "lsr") (rotatert "ror")])
1953 ;; Op prefix for shift right and accumulate.
1954 (define_code_attr sra_op [(ashiftrt "s") (lshiftrt "u")])
1956 ;; Map shift operators onto underlying bit-field instructions
1957 (define_code_attr bfshift [(ashift "ubfiz") (ashiftrt "sbfx")
1958 (lshiftrt "ubfx") (rotatert "extr")])
1960 ;; Logical operator instruction mnemonics
1961 (define_code_attr logical [(and "and") (ior "orr") (xor "eor")])
1963 ;; Operation names for negate and bitwise complement.
1964 (define_code_attr neg_not_op [(neg "neg") (not "not")])
1966 ;; csinv, csneg insn suffixes.
1967 (define_code_attr neg_not_cs [(neg "neg") (not "inv")])
1969 ;; Similar, but when the second operand is inverted.
1970 (define_code_attr nlogical [(and "bic") (ior "orn") (xor "eon")])
1972 ;; Similar, but when both operands are inverted.
1973 (define_code_attr logical_nn [(and "nor") (ior "nand")])
1975 ;; Sign- or zero-extending data-op
1976 (define_code_attr su [(sign_extend "s") (zero_extend "u")
1977 (sign_extract "s") (zero_extract "u")
1978 (fix "s") (unsigned_fix "u")
1979 (div "s") (udiv "u")
1980 (smax "s") (umax "u")
1981 (smin "s") (umin "u")])
1983 ;; "s" for signed ops, empty for unsigned ones.
1984 (define_code_attr s [(sign_extend "s") (zero_extend "")])
1986 ;; Map signed/unsigned ops to the corresponding extension.
1987 (define_code_attr paired_extend [(ss_plus "sign_extend")
1988 (us_plus "zero_extend")
1989 (ss_minus "sign_extend")
1990 (us_minus "zero_extend")])
1992 ;; Whether a shift is left or right.
1993 (define_code_attr lr [(ashift "l") (ashiftrt "r") (lshiftrt "r")])
1995 ;; Emit conditional branch instructions.
1996 (define_code_attr bcond [(eq "beq") (ne "bne") (lt "bne") (ge "beq")])
1998 ;; Emit cbz/cbnz depending on comparison type.
1999 (define_code_attr cbz [(eq "cbz") (ne "cbnz") (lt "cbnz") (ge "cbz")])
2001 ;; Emit inverted cbz/cbnz depending on comparison type.
2002 (define_code_attr inv_cb [(eq "cbnz") (ne "cbz") (lt "cbz") (ge "cbnz")])
2004 ;; Emit tbz/tbnz depending on comparison type.
2005 (define_code_attr tbz [(eq "tbz") (ne "tbnz") (lt "tbnz") (ge "tbz")])
2007 ;; Emit inverted tbz/tbnz depending on comparison type.
2008 (define_code_attr inv_tb [(eq "tbnz") (ne "tbz") (lt "tbz") (ge "tbnz")])
2010 ;; Max/min attributes.
2011 (define_code_attr maxmin [(smax "max")
2016 ;; MLA/MLS attributes.
2017 (define_code_attr as [(ss_plus "a") (ss_minus "s")])
2019 ;; Atomic operations
2020 (define_code_attr atomic_optab
2021 [(ior "or") (xor "xor") (and "and") (plus "add") (minus "sub")])
2023 (define_code_attr atomic_op_operand
2024 [(ior "aarch64_logical_operand")
2025 (xor "aarch64_logical_operand")
2026 (and "aarch64_logical_operand")
2027 (plus "aarch64_plus_operand")
2028 (minus "aarch64_plus_operand")])
2030 ;; Constants acceptable for atomic operations.
2031 ;; This definition must appear in this file before the iterators it refers to.
2032 (define_code_attr const_atomic
2033 [(plus "IJ") (minus "IJ")
2034 (xor "<lconst_atomic>") (ior "<lconst_atomic>")
2035 (and "<lconst_atomic>")])
2037 ;; Attribute to describe constants acceptable in atomic logical operations
2038 (define_mode_attr lconst_atomic [(QI "K") (HI "K") (SI "K") (DI "L")])
2040 ;; The integer SVE instruction that implements an rtx code.
2041 (define_code_attr sve_int_op [(plus "add")
2069 (define_code_attr sve_int_op_rev [(plus "add")
2087 (us_minus "uqsubr")])
2089 ;; The floating-point SVE instruction that implements an rtx code.
2090 (define_code_attr sve_fp_op [(plus "fadd")
2094 ;; The SVE immediate constraint to use for an rtl code.
2095 (define_code_attr sve_imm_con [(mult "vsm")
2111 ;; The prefix letter to use when printing an immediate operand.
2112 (define_code_attr sve_imm_prefix [(mult "")
2118 ;; The predicate to use for the second input operand in a cond_<optab><mode>
2120 (define_code_attr sve_pred_int_rhs2_operand
2121 [(plus "register_operand")
2122 (minus "register_operand")
2123 (mult "register_operand")
2124 (smax "register_operand")
2125 (umax "register_operand")
2126 (smin "register_operand")
2127 (umin "register_operand")
2128 (ashift "aarch64_sve_lshift_operand")
2129 (ashiftrt "aarch64_sve_rshift_operand")
2130 (lshiftrt "aarch64_sve_rshift_operand")
2131 (and "aarch64_sve_pred_and_operand")
2132 (ior "register_operand")
2133 (xor "register_operand")
2134 (ss_plus "register_operand")
2135 (us_plus "register_operand")
2136 (ss_minus "register_operand")
2137 (us_minus "register_operand")])
2139 (define_code_attr inc_dec [(minus "dec") (ss_minus "sqdec") (us_minus "uqdec")
2140 (plus "inc") (ss_plus "sqinc") (us_plus "uqinc")])
2142 ;; -------------------------------------------------------------------
2144 ;; -------------------------------------------------------------------
2146 ;; The unspec codes for the SABAL, UABAL AdvancedSIMD instructions.
2147 (define_int_iterator ABAL [UNSPEC_SABAL UNSPEC_UABAL])
2149 ;; The unspec codes for the SABDL2, UABDL2 AdvancedSIMD instructions.
2150 (define_int_iterator ABDL2 [UNSPEC_SABDL2 UNSPEC_UABDL2])
2152 ;; The unspec codes for the SADALP, UADALP AdvancedSIMD instructions.
2153 (define_int_iterator ADALP [UNSPEC_SADALP UNSPEC_UADALP])
2155 (define_int_iterator MAXMINV [UNSPEC_UMAXV UNSPEC_UMINV
2156 UNSPEC_SMAXV UNSPEC_SMINV])
2158 (define_int_iterator FMAXMINV [UNSPEC_FMAXV UNSPEC_FMINV
2159 UNSPEC_FMAXNMV UNSPEC_FMINNMV])
2161 (define_int_iterator SVE_INT_ADDV [UNSPEC_SADDV UNSPEC_UADDV])
2163 (define_int_iterator LOGICALF [UNSPEC_ANDF UNSPEC_IORF UNSPEC_XORF])
2165 (define_int_iterator HADDSUB [UNSPEC_SHADD UNSPEC_UHADD
2166 UNSPEC_SRHADD UNSPEC_URHADD
2167 UNSPEC_SHSUB UNSPEC_UHSUB])
2169 (define_int_iterator HADD [UNSPEC_SHADD UNSPEC_UHADD])
2171 (define_int_iterator RHADD [UNSPEC_SRHADD UNSPEC_URHADD])
2173 (define_int_iterator BSL_DUP [1 2])
2175 (define_int_iterator DOTPROD [UNSPEC_SDOT UNSPEC_UDOT])
2177 (define_int_iterator DOTPROD_I8MM [UNSPEC_USDOT UNSPEC_SUDOT])
2178 (define_int_iterator DOTPROD_US_ONLY [UNSPEC_USDOT])
2180 (define_int_iterator ADDSUBHN [UNSPEC_ADDHN UNSPEC_RADDHN
2181 UNSPEC_SUBHN UNSPEC_RSUBHN])
2183 (define_int_iterator ADDSUBHN2 [UNSPEC_ADDHN2 UNSPEC_RADDHN2
2184 UNSPEC_SUBHN2 UNSPEC_RSUBHN2])
2186 (define_int_iterator FMAXMIN_UNS [UNSPEC_FMAX UNSPEC_FMIN
2187 UNSPEC_FMAXNM UNSPEC_FMINNM])
2189 (define_int_iterator PAUTH_LR_SP [UNSPEC_PACIASP UNSPEC_AUTIASP
2190 UNSPEC_PACIBSP UNSPEC_AUTIBSP])
2192 (define_int_iterator PAUTH_17_16 [UNSPEC_PACIA1716 UNSPEC_AUTIA1716
2193 UNSPEC_PACIB1716 UNSPEC_AUTIB1716])
2195 (define_int_iterator VQDMULH [UNSPEC_SQDMULH UNSPEC_SQRDMULH])
2197 (define_int_iterator MULHRS [UNSPEC_SMULHS UNSPEC_UMULHS
2198 UNSPEC_SMULHRS UNSPEC_UMULHRS])
2200 (define_int_iterator USSUQADD [UNSPEC_SUQADD UNSPEC_USQADD])
2202 (define_int_iterator SUQMOVN [UNSPEC_SQXTN UNSPEC_UQXTN])
2204 (define_int_iterator VSHL [UNSPEC_SSHL UNSPEC_USHL
2205 UNSPEC_SRSHL UNSPEC_URSHL])
2207 (define_int_iterator VSHLL [UNSPEC_SSHLL UNSPEC_USHLL])
2209 (define_int_iterator VQSHL [UNSPEC_SQSHL UNSPEC_UQSHL
2210 UNSPEC_SQRSHL UNSPEC_UQRSHL])
2212 (define_int_iterator VSRA [UNSPEC_SSRA UNSPEC_USRA
2213 UNSPEC_SRSRA UNSPEC_URSRA])
2215 (define_int_iterator VSLRI [UNSPEC_SSLI UNSPEC_USLI
2216 UNSPEC_SSRI UNSPEC_USRI])
2219 (define_int_iterator VRSHR_N [UNSPEC_SRSHR UNSPEC_URSHR])
2221 (define_int_iterator VQSHL_N [UNSPEC_SQSHLU UNSPEC_SQSHL UNSPEC_UQSHL])
2223 (define_int_iterator VQSHRN_N [UNSPEC_SQSHRUN UNSPEC_SQRSHRUN
2224 UNSPEC_SQSHRN UNSPEC_UQSHRN
2225 UNSPEC_SQRSHRN UNSPEC_UQRSHRN])
2227 (define_int_iterator SQRDMLH_AS [UNSPEC_SQRDMLAH UNSPEC_SQRDMLSH])
2229 (define_int_iterator PERMUTE [UNSPEC_ZIP1 UNSPEC_ZIP2
2230 UNSPEC_TRN1 UNSPEC_TRN2
2231 UNSPEC_UZP1 UNSPEC_UZP2])
2233 (define_int_iterator PERMUTEQ [UNSPEC_ZIP1Q UNSPEC_ZIP2Q
2234 UNSPEC_TRN1Q UNSPEC_TRN2Q
2235 UNSPEC_UZP1Q UNSPEC_UZP2Q])
2237 (define_int_iterator OPTAB_PERMUTE [UNSPEC_ZIP1 UNSPEC_ZIP2
2238 UNSPEC_UZP1 UNSPEC_UZP2])
2240 (define_int_iterator REVERSE [UNSPEC_REV64 UNSPEC_REV32 UNSPEC_REV16])
2242 (define_int_iterator FRINT [UNSPEC_FRINTZ UNSPEC_FRINTP UNSPEC_FRINTM
2243 UNSPEC_FRINTN UNSPEC_FRINTI UNSPEC_FRINTX
2246 (define_int_iterator FCVT [UNSPEC_FRINTZ UNSPEC_FRINTP UNSPEC_FRINTM
2247 UNSPEC_FRINTA UNSPEC_FRINTN])
2249 (define_int_iterator FCVT_F2FIXED [UNSPEC_FCVTZS UNSPEC_FCVTZU])
2250 (define_int_iterator FCVT_FIXED2F [UNSPEC_SCVTF UNSPEC_UCVTF])
2252 (define_int_iterator CRC [UNSPEC_CRC32B UNSPEC_CRC32H UNSPEC_CRC32W
2253 UNSPEC_CRC32X UNSPEC_CRC32CB UNSPEC_CRC32CH
2254 UNSPEC_CRC32CW UNSPEC_CRC32CX])
2256 (define_int_iterator CRYPTO_AES [UNSPEC_AESE UNSPEC_AESD])
2257 (define_int_iterator CRYPTO_AESMC [UNSPEC_AESMC UNSPEC_AESIMC])
2259 (define_int_iterator CRYPTO_SHA1 [UNSPEC_SHA1C UNSPEC_SHA1M UNSPEC_SHA1P])
2261 (define_int_iterator CRYPTO_SHA256 [UNSPEC_SHA256H UNSPEC_SHA256H2])
2263 (define_int_iterator CRYPTO_SHA512 [UNSPEC_SHA512H UNSPEC_SHA512H2])
2265 (define_int_iterator CRYPTO_SM3TT [UNSPEC_SM3TT1A UNSPEC_SM3TT1B
2266 UNSPEC_SM3TT2A UNSPEC_SM3TT2B])
2268 (define_int_iterator CRYPTO_SM3PART [UNSPEC_SM3PARTW1 UNSPEC_SM3PARTW2])
2270 ;; Iterators for fp16 operations
2272 (define_int_iterator VFMLA16_LOW [UNSPEC_FMLAL UNSPEC_FMLSL])
2274 (define_int_iterator VFMLA16_HIGH [UNSPEC_FMLAL2 UNSPEC_FMLSL2])
2276 (define_int_iterator UNPACK [UNSPEC_UNPACKSHI UNSPEC_UNPACKUHI
2277 UNSPEC_UNPACKSLO UNSPEC_UNPACKULO])
2279 (define_int_iterator UNPACK_UNSIGNED [UNSPEC_UNPACKULO UNSPEC_UNPACKUHI])
2281 (define_int_iterator MUL_HIGHPART [UNSPEC_SMUL_HIGHPART UNSPEC_UMUL_HIGHPART])
2283 (define_int_iterator CLAST [UNSPEC_CLASTA UNSPEC_CLASTB])
2285 (define_int_iterator LAST [UNSPEC_LASTA UNSPEC_LASTB])
2287 (define_int_iterator SVE_INT_UNARY [UNSPEC_RBIT UNSPEC_REVB
2288 UNSPEC_REVH UNSPEC_REVW])
2290 (define_int_iterator SVE_FP_UNARY [UNSPEC_FRECPE UNSPEC_RSQRTE])
2292 (define_int_iterator SVE_FP_UNARY_INT [UNSPEC_FEXPA])
2294 (define_int_iterator SVE_INT_SHIFT_IMM [UNSPEC_ASRD
2295 (UNSPEC_SQSHLU "TARGET_SVE2")
2296 (UNSPEC_SRSHR "TARGET_SVE2")
2297 (UNSPEC_URSHR "TARGET_SVE2")])
2299 (define_int_iterator SVE_FP_BINARY [UNSPEC_FRECPS UNSPEC_RSQRTS])
2301 (define_int_iterator SVE_FP_BINARY_INT [UNSPEC_FTSMUL UNSPEC_FTSSEL])
2303 (define_int_iterator SVE_BFLOAT_TERNARY_LONG [UNSPEC_BFDOT
2308 (define_int_iterator SVE_BFLOAT_TERNARY_LONG_LANE [UNSPEC_BFDOT
2312 (define_int_iterator SVE_INT_REDUCTION [UNSPEC_ANDV
2320 (define_int_iterator SVE_FP_REDUCTION [UNSPEC_FADDV
2326 (define_int_iterator SVE_COND_FP_UNARY [UNSPEC_COND_FABS
2338 ;; Same as SVE_COND_FP_UNARY, but without codes that have a dedicated
2339 ;; <optab><mode>2 expander.
2340 (define_int_iterator SVE_COND_FP_UNARY_OPTAB [UNSPEC_COND_FABS
2349 UNSPEC_COND_FRINTZ])
2351 (define_int_iterator SVE_COND_FCVT [UNSPEC_COND_FCVT])
2352 (define_int_iterator SVE_COND_FCVTI [UNSPEC_COND_FCVTZS UNSPEC_COND_FCVTZU])
2353 (define_int_iterator SVE_COND_ICVTF [UNSPEC_COND_SCVTF UNSPEC_COND_UCVTF])
2355 (define_int_iterator SVE_COND_FP_BINARY [UNSPEC_COND_FADD
2365 ;; Same as SVE_COND_FP_BINARY, but without codes that have a dedicated
2366 ;; <optab><mode>3 expander.
2367 (define_int_iterator SVE_COND_FP_BINARY_OPTAB [UNSPEC_COND_FADD
2376 (define_int_iterator SVE_COND_FP_BINARY_INT [UNSPEC_COND_FSCALE])
2378 (define_int_iterator SVE_COND_FP_ADD [UNSPEC_COND_FADD])
2379 (define_int_iterator SVE_COND_FP_SUB [UNSPEC_COND_FSUB])
2380 (define_int_iterator SVE_COND_FP_MUL [UNSPEC_COND_FMUL])
2382 (define_int_iterator SVE_COND_FP_BINARY_I1 [UNSPEC_COND_FMAX
2388 (define_int_iterator SVE_COND_FP_BINARY_REG [UNSPEC_COND_FDIV
2391 (define_int_iterator SVE_COND_FCADD [UNSPEC_COND_FCADD90
2392 UNSPEC_COND_FCADD270])
2394 (define_int_iterator SVE_COND_FP_MAXMIN [UNSPEC_COND_FMAX
2397 UNSPEC_COND_FMINNM])
2399 ;; Floating-point max/min operations that correspond to optabs,
2400 ;; as opposed to those that are internal to the port.
2401 (define_int_iterator SVE_COND_FP_MAXMIN_PUBLIC [UNSPEC_COND_FMAXNM
2402 UNSPEC_COND_FMINNM])
2404 (define_int_iterator SVE_COND_FP_TERNARY [UNSPEC_COND_FMLA
2409 (define_int_iterator SVE_COND_FCMLA [UNSPEC_COND_FCMLA
2411 UNSPEC_COND_FCMLA180
2412 UNSPEC_COND_FCMLA270])
2414 (define_int_iterator SVE_COND_INT_CMP_WIDE [UNSPEC_COND_CMPEQ_WIDE
2415 UNSPEC_COND_CMPGE_WIDE
2416 UNSPEC_COND_CMPGT_WIDE
2417 UNSPEC_COND_CMPHI_WIDE
2418 UNSPEC_COND_CMPHS_WIDE
2419 UNSPEC_COND_CMPLE_WIDE
2420 UNSPEC_COND_CMPLO_WIDE
2421 UNSPEC_COND_CMPLS_WIDE
2422 UNSPEC_COND_CMPLT_WIDE
2423 UNSPEC_COND_CMPNE_WIDE])
2425 ;; SVE FP comparisons that accept #0.0.
2426 (define_int_iterator SVE_COND_FP_CMP_I0 [UNSPEC_COND_FCMEQ
2433 (define_int_iterator SVE_COND_FP_ABS_CMP [UNSPEC_COND_FCMGE
2438 (define_int_iterator SVE_FP_TERNARY_LANE [UNSPEC_FMLA UNSPEC_FMLS])
2440 (define_int_iterator SVE_CFP_TERNARY_LANE [UNSPEC_FCMLA UNSPEC_FCMLA90
2441 UNSPEC_FCMLA180 UNSPEC_FCMLA270])
2443 (define_int_iterator SVE_WHILE [UNSPEC_WHILELE UNSPEC_WHILELO
2444 UNSPEC_WHILELS UNSPEC_WHILELT
2445 (UNSPEC_WHILEGE "TARGET_SVE2")
2446 (UNSPEC_WHILEGT "TARGET_SVE2")
2447 (UNSPEC_WHILEHI "TARGET_SVE2")
2448 (UNSPEC_WHILEHS "TARGET_SVE2")
2449 (UNSPEC_WHILERW "TARGET_SVE2")
2450 (UNSPEC_WHILEWR "TARGET_SVE2")])
2452 (define_int_iterator SVE2_WHILE_PTR [UNSPEC_WHILERW UNSPEC_WHILEWR])
2454 (define_int_iterator SVE_SHIFT_WIDE [UNSPEC_ASHIFT_WIDE
2455 UNSPEC_ASHIFTRT_WIDE
2456 UNSPEC_LSHIFTRT_WIDE])
2458 (define_int_iterator SVE_LDFF1_LDNF1 [UNSPEC_LDFF1 UNSPEC_LDNF1])
2460 (define_int_iterator SVE2_U32_UNARY [UNSPEC_URECPE UNSPEC_RSQRTE])
2462 (define_int_iterator SVE2_INT_UNARY_NARROWB [UNSPEC_SQXTNB
2466 (define_int_iterator SVE2_INT_UNARY_NARROWT [UNSPEC_SQXTNT
2470 (define_int_iterator SVE2_INT_BINARY [UNSPEC_SQDMULH
2473 (define_int_iterator SVE2_INT_BINARY_LANE [UNSPEC_SQDMULH
2476 (define_int_iterator SVE2_INT_BINARY_LONG [UNSPEC_SABDLB
2498 (define_int_iterator SVE2_INT_BINARY_LONG_LANE [UNSPEC_SMULLB
2505 (define_int_iterator SVE2_INT_BINARY_NARROWB [UNSPEC_ADDHNB
2510 (define_int_iterator SVE2_INT_BINARY_NARROWT [UNSPEC_ADDHNT
2515 (define_int_iterator SVE2_INT_BINARY_PAIR [UNSPEC_ADDP
2521 (define_int_iterator SVE2_FP_BINARY_PAIR [UNSPEC_FADDP
2527 (define_int_iterator SVE2_INT_BINARY_PAIR_LONG [UNSPEC_SADALP UNSPEC_UADALP])
2529 (define_int_iterator SVE2_INT_BINARY_WIDE [UNSPEC_SADDWB
2538 (define_int_iterator SVE2_INT_SHIFT_IMM_LONG [UNSPEC_SSHLLB
2543 (define_int_iterator SVE2_INT_SHIFT_IMM_NARROWB [UNSPEC_RSHRNB
2552 (define_int_iterator SVE2_INT_SHIFT_IMM_NARROWT [UNSPEC_RSHRNT
2561 (define_int_iterator SVE2_INT_SHIFT_INSERT [UNSPEC_SLI UNSPEC_SRI])
2563 (define_int_iterator SVE2_INT_CADD [UNSPEC_CADD90
2568 (define_int_iterator SVE2_INT_BITPERM [UNSPEC_BDEP UNSPEC_BEXT UNSPEC_BGRP])
2570 (define_int_iterator SVE2_INT_TERNARY [UNSPEC_ADCLB
2579 (define_int_iterator SVE2_INT_TERNARY_LANE [UNSPEC_SQRDMLAH
2582 (define_int_iterator SVE2_FP_TERNARY_LONG [UNSPEC_FMLALB
2587 (define_int_iterator SVE2_FP_TERNARY_LONG_LANE [UNSPEC_FMLALB
2592 (define_int_iterator SVE2_INT_CMLA [UNSPEC_CMLA
2599 UNSPEC_SQRDCMLAH270])
2601 ;; Same as SVE2_INT_CADD but exclude the saturating instructions
2602 (define_int_iterator SVE2_INT_CADD_OP [UNSPEC_CADD90
2605 (define_int_iterator SVE2_INT_CDOT [UNSPEC_CDOT
2610 (define_int_iterator SVE2_INT_ADD_BINARY_LONG [UNSPEC_SABDLB
2619 (define_int_iterator SVE2_INT_QADD_BINARY_LONG [UNSPEC_SQDMULLB
2623 (define_int_iterator SVE2_INT_SUB_BINARY_LONG [UNSPEC_SMULLB
2628 (define_int_iterator SVE2_INT_QSUB_BINARY_LONG [UNSPEC_SQDMULLB
2632 (define_int_iterator SVE2_INT_ADD_BINARY_LONG_LANE [UNSPEC_SMULLB
2637 (define_int_iterator SVE2_INT_QADD_BINARY_LONG_LANE [UNSPEC_SQDMULLB
2640 (define_int_iterator SVE2_INT_SUB_BINARY_LONG_LANE [UNSPEC_SMULLB
2645 (define_int_iterator SVE2_INT_QSUB_BINARY_LONG_LANE [UNSPEC_SQDMULLB
2648 (define_int_iterator SVE2_COND_INT_UNARY_FP [UNSPEC_COND_FLOGB])
2650 (define_int_iterator SVE2_COND_FP_UNARY_LONG [UNSPEC_COND_FCVTLT])
2652 (define_int_iterator SVE2_COND_FP_UNARY_NARROWB [UNSPEC_COND_FCVTX])
2654 (define_int_iterator SVE2_COND_INT_BINARY [UNSPEC_SHADD
2667 (define_int_iterator SVE2_COND_INT_BINARY_NOREV [UNSPEC_SUQADD
2670 (define_int_iterator SVE2_COND_INT_BINARY_REV [UNSPEC_SHADD
2681 (define_int_iterator SVE2_COND_INT_SHIFT [UNSPEC_SQSHL
2684 (define_int_iterator SVE2_MATCH [UNSPEC_MATCH UNSPEC_NMATCH])
2686 (define_int_iterator SVE2_PMULL [UNSPEC_PMULLB UNSPEC_PMULLT])
2688 (define_int_iterator SVE2_PMULL_PAIR [UNSPEC_PMULLB_PAIR UNSPEC_PMULLT_PAIR])
2690 (define_int_iterator FCADD [UNSPEC_FCADD90
2693 (define_int_iterator FCMLA [UNSPEC_FCMLA
2698 (define_int_iterator FRINTNZX [UNSPEC_FRINT32Z UNSPEC_FRINT32X
2699 UNSPEC_FRINT64Z UNSPEC_FRINT64X])
2701 (define_int_iterator SVE_BRK_UNARY [UNSPEC_BRKA UNSPEC_BRKB])
2703 (define_int_iterator SVE_BRK_BINARY [UNSPEC_BRKN UNSPEC_BRKPA UNSPEC_BRKPB])
2705 (define_int_iterator SVE_PITER [UNSPEC_PFIRST UNSPEC_PNEXT])
2707 (define_int_iterator MATMUL [UNSPEC_SMATMUL UNSPEC_UMATMUL
2710 (define_int_iterator FMMLA [UNSPEC_FMMLA])
2712 (define_int_iterator BF_MLA [UNSPEC_BFMLALB
2715 ;; Iterators for atomic operations.
2717 (define_int_iterator ATOMIC_LDOP
2718 [UNSPECV_ATOMIC_LDOP_OR UNSPECV_ATOMIC_LDOP_BIC
2719 UNSPECV_ATOMIC_LDOP_XOR UNSPECV_ATOMIC_LDOP_PLUS])
2721 (define_int_attr atomic_ldop
2722 [(UNSPECV_ATOMIC_LDOP_OR "set") (UNSPECV_ATOMIC_LDOP_BIC "clr")
2723 (UNSPECV_ATOMIC_LDOP_XOR "eor") (UNSPECV_ATOMIC_LDOP_PLUS "add")])
2725 (define_int_attr atomic_ldoptab
2726 [(UNSPECV_ATOMIC_LDOP_OR "ior") (UNSPECV_ATOMIC_LDOP_BIC "bic")
2727 (UNSPECV_ATOMIC_LDOP_XOR "xor") (UNSPECV_ATOMIC_LDOP_PLUS "add")])
2729 ;; -------------------------------------------------------------------
2730 ;; Int Iterators Attributes.
2731 ;; -------------------------------------------------------------------
2733 ;; The optab associated with an operation. Note that for ANDF, IORF
2734 ;; and XORF, the optab pattern is not actually defined; we just use this
2735 ;; name for consistency with the integer patterns.
2736 (define_int_attr optab [(UNSPEC_ANDF "and")
2739 (UNSPEC_SADDV "sadd")
2740 (UNSPEC_UADDV "uadd")
2744 (UNSPEC_FRECPE "frecpe")
2745 (UNSPEC_FRECPS "frecps")
2746 (UNSPEC_RSQRTE "frsqrte")
2747 (UNSPEC_RSQRTS "frsqrts")
2748 (UNSPEC_RBIT "rbit")
2749 (UNSPEC_REVB "revb")
2750 (UNSPEC_REVH "revh")
2751 (UNSPEC_REVW "revw")
2752 (UNSPEC_UMAXV "umax")
2753 (UNSPEC_UMINV "umin")
2754 (UNSPEC_SMAXV "smax")
2755 (UNSPEC_SMINV "smin")
2756 (UNSPEC_CADD90 "cadd90")
2757 (UNSPEC_CADD270 "cadd270")
2758 (UNSPEC_CDOT "cdot")
2759 (UNSPEC_CDOT90 "cdot90")
2760 (UNSPEC_CDOT180 "cdot180")
2761 (UNSPEC_CDOT270 "cdot270")
2762 (UNSPEC_CMLA "cmla")
2763 (UNSPEC_CMLA90 "cmla90")
2764 (UNSPEC_CMLA180 "cmla180")
2765 (UNSPEC_CMLA270 "cmla270")
2766 (UNSPEC_FADDV "plus")
2767 (UNSPEC_FMAXNMV "smax")
2768 (UNSPEC_FMAXV "smax_nan")
2769 (UNSPEC_FMINNMV "smin")
2770 (UNSPEC_FMINV "smin_nan")
2771 (UNSPEC_SMUL_HIGHPART "smulh")
2772 (UNSPEC_UMUL_HIGHPART "umulh")
2774 (UNSPEC_FMLS "fnma")
2775 (UNSPEC_FCMLA "fcmla")
2776 (UNSPEC_FCMLA90 "fcmla90")
2777 (UNSPEC_FCMLA180 "fcmla180")
2778 (UNSPEC_FCMLA270 "fcmla270")
2779 (UNSPEC_FEXPA "fexpa")
2780 (UNSPEC_FTSMUL "ftsmul")
2781 (UNSPEC_FTSSEL "ftssel")
2782 (UNSPEC_PMULLB "pmullb")
2783 (UNSPEC_PMULLB_PAIR "pmullb_pair")
2784 (UNSPEC_PMULLT "pmullt")
2785 (UNSPEC_PMULLT_PAIR "pmullt_pair")
2786 (UNSPEC_SMATMUL "smatmul")
2787 (UNSPEC_SQCADD90 "sqcadd90")
2788 (UNSPEC_SQCADD270 "sqcadd270")
2789 (UNSPEC_SQRDCMLAH "sqrdcmlah")
2790 (UNSPEC_SQRDCMLAH90 "sqrdcmlah90")
2791 (UNSPEC_SQRDCMLAH180 "sqrdcmlah180")
2792 (UNSPEC_SQRDCMLAH270 "sqrdcmlah270")
2793 (UNSPEC_TRN1Q "trn1q")
2794 (UNSPEC_TRN2Q "trn2q")
2795 (UNSPEC_UMATMUL "umatmul")
2796 (UNSPEC_USMATMUL "usmatmul")
2797 (UNSPEC_UZP1Q "uzp1q")
2798 (UNSPEC_UZP2Q "uzp2q")
2799 (UNSPEC_WHILERW "vec_check_raw_alias")
2800 (UNSPEC_WHILEWR "vec_check_war_alias")
2801 (UNSPEC_ZIP1Q "zip1q")
2802 (UNSPEC_ZIP2Q "zip2q")
2803 (UNSPEC_COND_FABS "abs")
2804 (UNSPEC_COND_FADD "add")
2805 (UNSPEC_COND_FCADD90 "cadd90")
2806 (UNSPEC_COND_FCADD270 "cadd270")
2807 (UNSPEC_COND_FCMLA "fcmla")
2808 (UNSPEC_COND_FCMLA90 "fcmla90")
2809 (UNSPEC_COND_FCMLA180 "fcmla180")
2810 (UNSPEC_COND_FCMLA270 "fcmla270")
2811 (UNSPEC_COND_FCVT "fcvt")
2812 (UNSPEC_COND_FCVTZS "fix_trunc")
2813 (UNSPEC_COND_FCVTZU "fixuns_trunc")
2814 (UNSPEC_COND_FDIV "div")
2815 (UNSPEC_COND_FMAX "smax_nan")
2816 (UNSPEC_COND_FMAXNM "smax")
2817 (UNSPEC_COND_FMIN "smin_nan")
2818 (UNSPEC_COND_FMINNM "smin")
2819 (UNSPEC_COND_FMLA "fma")
2820 (UNSPEC_COND_FMLS "fnma")
2821 (UNSPEC_COND_FMUL "mul")
2822 (UNSPEC_COND_FMULX "mulx")
2823 (UNSPEC_COND_FNEG "neg")
2824 (UNSPEC_COND_FNMLA "fnms")
2825 (UNSPEC_COND_FNMLS "fms")
2826 (UNSPEC_COND_FRECPX "frecpx")
2827 (UNSPEC_COND_FRINTA "round")
2828 (UNSPEC_COND_FRINTI "nearbyint")
2829 (UNSPEC_COND_FRINTM "floor")
2830 (UNSPEC_COND_FRINTN "frintn")
2831 (UNSPEC_COND_FRINTP "ceil")
2832 (UNSPEC_COND_FRINTX "rint")
2833 (UNSPEC_COND_FRINTZ "btrunc")
2834 (UNSPEC_COND_FSCALE "fscale")
2835 (UNSPEC_COND_FSQRT "sqrt")
2836 (UNSPEC_COND_FSUB "sub")
2837 (UNSPEC_COND_SCVTF "float")
2838 (UNSPEC_COND_UCVTF "floatuns")])
2840 (define_int_attr maxmin_uns [(UNSPEC_UMAXV "umax")
2841 (UNSPEC_UMINV "umin")
2842 (UNSPEC_SMAXV "smax")
2843 (UNSPEC_SMINV "smin")
2844 (UNSPEC_FMAX "smax_nan")
2845 (UNSPEC_FMAXNMV "smax")
2846 (UNSPEC_FMAXV "smax_nan")
2847 (UNSPEC_FMIN "smin_nan")
2848 (UNSPEC_FMINNMV "smin")
2849 (UNSPEC_FMINV "smin_nan")
2850 (UNSPEC_FMAXNM "fmax")
2851 (UNSPEC_FMINNM "fmin")
2852 (UNSPEC_COND_FMAX "fmax_nan")
2853 (UNSPEC_COND_FMAXNM "fmax")
2854 (UNSPEC_COND_FMIN "fmin_nan")
2855 (UNSPEC_COND_FMINNM "fmin")])
2857 (define_int_attr maxmin_uns_op [(UNSPEC_UMAXV "umax")
2858 (UNSPEC_UMINV "umin")
2859 (UNSPEC_SMAXV "smax")
2860 (UNSPEC_SMINV "smin")
2861 (UNSPEC_FMAX "fmax")
2862 (UNSPEC_FMAXNMV "fmaxnm")
2863 (UNSPEC_FMAXV "fmax")
2864 (UNSPEC_FMIN "fmin")
2865 (UNSPEC_FMINNMV "fminnm")
2866 (UNSPEC_FMINV "fmin")
2867 (UNSPEC_FMAXNM "fmaxnm")
2868 (UNSPEC_FMINNM "fminnm")])
2870 (define_code_attr binqops_op [(ss_plus "sqadd")
2873 (us_minus "uqsub")])
2875 (define_code_attr binqops_op_rev [(ss_plus "sqsub")
2876 (ss_minus "sqadd")])
2878 ;; The SVE logical instruction that implements an unspec.
2879 (define_int_attr logicalf_op [(UNSPEC_ANDF "and")
2881 (UNSPEC_XORF "eor")])
2883 (define_int_attr last_op [(UNSPEC_CLASTA "after_last")
2884 (UNSPEC_CLASTB "last")
2885 (UNSPEC_LASTA "after_last")
2886 (UNSPEC_LASTB "last")])
2888 ;; "s" for signed operations and "u" for unsigned ones.
2889 (define_int_attr su [(UNSPEC_SADDV "s")
2891 (UNSPEC_UNPACKSHI "s")
2892 (UNSPEC_UNPACKUHI "u")
2893 (UNSPEC_UNPACKSLO "s")
2894 (UNSPEC_UNPACKULO "u")
2895 (UNSPEC_SMUL_HIGHPART "s")
2896 (UNSPEC_UMUL_HIGHPART "u")
2897 (UNSPEC_COND_FCVTZS "s")
2898 (UNSPEC_COND_FCVTZU "u")
2899 (UNSPEC_COND_SCVTF "s")
2900 (UNSPEC_COND_UCVTF "u")
2901 (UNSPEC_SMULHS "s") (UNSPEC_UMULHS "u")
2902 (UNSPEC_SMULHRS "s") (UNSPEC_UMULHRS "u")])
2904 (define_int_attr sur [(UNSPEC_SHADD "s") (UNSPEC_UHADD "u")
2905 (UNSPEC_SRHADD "sr") (UNSPEC_URHADD "ur")
2906 (UNSPEC_SHSUB "s") (UNSPEC_UHSUB "u")
2907 (UNSPEC_ADDHN "") (UNSPEC_RADDHN "r")
2908 (UNSPEC_SABAL "s") (UNSPEC_UABAL "u")
2909 (UNSPEC_SABDL2 "s") (UNSPEC_UABDL2 "u")
2910 (UNSPEC_SADALP "s") (UNSPEC_UADALP "u")
2911 (UNSPEC_SUBHN "") (UNSPEC_RSUBHN "r")
2912 (UNSPEC_ADDHN2 "") (UNSPEC_RADDHN2 "r")
2913 (UNSPEC_SUBHN2 "") (UNSPEC_RSUBHN2 "r")
2914 (UNSPEC_SQXTN "s") (UNSPEC_UQXTN "u")
2915 (UNSPEC_USQADD "us") (UNSPEC_SUQADD "su")
2916 (UNSPEC_SSLI "s") (UNSPEC_USLI "u")
2917 (UNSPEC_SSRI "s") (UNSPEC_USRI "u")
2918 (UNSPEC_USRA "u") (UNSPEC_SSRA "s")
2919 (UNSPEC_URSRA "ur") (UNSPEC_SRSRA "sr")
2920 (UNSPEC_URSHR "ur") (UNSPEC_SRSHR "sr")
2921 (UNSPEC_SQSHLU "s") (UNSPEC_SQSHL "s")
2923 (UNSPEC_SQSHRUN "s") (UNSPEC_SQRSHRUN "s")
2924 (UNSPEC_SQSHRN "s") (UNSPEC_UQSHRN "u")
2925 (UNSPEC_SQRSHRN "s") (UNSPEC_UQRSHRN "u")
2926 (UNSPEC_USHL "u") (UNSPEC_SSHL "s")
2927 (UNSPEC_USHLL "u") (UNSPEC_SSHLL "s")
2928 (UNSPEC_URSHL "ur") (UNSPEC_SRSHL "sr")
2929 (UNSPEC_UQRSHL "u") (UNSPEC_SQRSHL "s")
2930 (UNSPEC_SDOT "s") (UNSPEC_UDOT "u")
2931 (UNSPEC_USDOT "us") (UNSPEC_SUDOT "su")
2932 (UNSPEC_SMATMUL "s") (UNSPEC_UMATMUL "u")
2933 (UNSPEC_USMATMUL "us")
2936 (define_int_attr r [(UNSPEC_SQDMULH "") (UNSPEC_SQRDMULH "r")
2937 (UNSPEC_SQSHRUN "") (UNSPEC_SQRSHRUN "r")
2938 (UNSPEC_SQSHRN "") (UNSPEC_UQSHRN "")
2939 (UNSPEC_SQRSHRN "r") (UNSPEC_UQRSHRN "r")
2940 (UNSPEC_SQSHL "") (UNSPEC_UQSHL "")
2941 (UNSPEC_SQRSHL "r")(UNSPEC_UQRSHL "r")
2942 (UNSPEC_SMULHS "") (UNSPEC_UMULHS "")
2943 (UNSPEC_SMULHRS "r") (UNSPEC_UMULHRS "r")
2946 (define_int_attr lr [(UNSPEC_SSLI "l") (UNSPEC_USLI "l")
2947 (UNSPEC_SSRI "r") (UNSPEC_USRI "r")
2948 (UNSPEC_SQSHL "l") (UNSPEC_UQSHL "l")
2950 (UNSPEC_SRSHR "r") (UNSPEC_URSHR "r")
2952 (UNSPEC_SLI "l") (UNSPEC_SRI "r")])
2954 (define_int_attr u [(UNSPEC_SQSHLU "u") (UNSPEC_SQSHL "") (UNSPEC_UQSHL "")
2955 (UNSPEC_SQSHRUN "u") (UNSPEC_SQRSHRUN "u")
2956 (UNSPEC_SQSHRN "") (UNSPEC_UQSHRN "")
2957 (UNSPEC_SQRSHRN "") (UNSPEC_UQRSHRN "")
2958 (UNSPEC_SHADD "") (UNSPEC_UHADD "u")
2959 (UNSPEC_SRHADD "") (UNSPEC_URHADD "u")])
2961 (define_int_attr fn [(UNSPEC_LDFF1 "f") (UNSPEC_LDNF1 "n")])
2963 (define_int_attr ab [(UNSPEC_CLASTA "a") (UNSPEC_CLASTB "b")
2964 (UNSPEC_LASTA "a") (UNSPEC_LASTB "b")])
2966 (define_int_attr bt [(UNSPEC_BFMLALB "b") (UNSPEC_BFMLALT "t")])
2968 (define_int_attr addsub [(UNSPEC_SHADD "add")
2969 (UNSPEC_UHADD "add")
2970 (UNSPEC_SRHADD "add")
2971 (UNSPEC_URHADD "add")
2972 (UNSPEC_SHSUB "sub")
2973 (UNSPEC_UHSUB "sub")
2974 (UNSPEC_ADDHN "add")
2975 (UNSPEC_SUBHN "sub")
2976 (UNSPEC_RADDHN "add")
2977 (UNSPEC_RSUBHN "sub")
2978 (UNSPEC_ADDHN2 "add")
2979 (UNSPEC_SUBHN2 "sub")
2980 (UNSPEC_RADDHN2 "add")
2981 (UNSPEC_RSUBHN2 "sub")])
2983 ;; BSL variants: first commutative operand.
2984 (define_int_attr bsl_1st [(1 "w") (2 "0")])
2986 ;; BSL variants: second commutative operand.
2987 (define_int_attr bsl_2nd [(1 "0") (2 "w")])
2989 ;; BSL variants: duplicated input operand.
2990 (define_int_attr bsl_dup [(1 "1") (2 "2")])
2992 ;; BSL variants: operand which requires preserving via movprfx.
2993 (define_int_attr bsl_mov [(1 "2") (2 "1")])
2995 (define_int_attr offsetlr [(UNSPEC_SSLI "") (UNSPEC_USLI "")
2996 (UNSPEC_SSRI "offset_")
2997 (UNSPEC_USRI "offset_")])
2999 ;; Standard pattern names for floating-point rounding instructions.
3000 (define_int_attr frint_pattern [(UNSPEC_FRINTZ "btrunc")
3001 (UNSPEC_FRINTP "ceil")
3002 (UNSPEC_FRINTM "floor")
3003 (UNSPEC_FRINTI "nearbyint")
3004 (UNSPEC_FRINTX "rint")
3005 (UNSPEC_FRINTA "round")
3006 (UNSPEC_FRINTN "frintn")])
3008 ;; frint suffix for floating-point rounding instructions.
3009 (define_int_attr frint_suffix [(UNSPEC_FRINTZ "z") (UNSPEC_FRINTP "p")
3010 (UNSPEC_FRINTM "m") (UNSPEC_FRINTI "i")
3011 (UNSPEC_FRINTX "x") (UNSPEC_FRINTA "a")
3012 (UNSPEC_FRINTN "n")])
3014 (define_int_attr fcvt_pattern [(UNSPEC_FRINTZ "btrunc") (UNSPEC_FRINTA "round")
3015 (UNSPEC_FRINTP "ceil") (UNSPEC_FRINTM "floor")
3016 (UNSPEC_FRINTN "frintn")])
3018 (define_int_attr fcvt_fixed_insn [(UNSPEC_SCVTF "scvtf")
3019 (UNSPEC_UCVTF "ucvtf")
3020 (UNSPEC_FCVTZS "fcvtzs")
3021 (UNSPEC_FCVTZU "fcvtzu")])
3023 ;; Pointer authentication mnemonic prefix.
3024 (define_int_attr pauth_mnem_prefix [(UNSPEC_PACIASP "pacia")
3025 (UNSPEC_PACIBSP "pacib")
3026 (UNSPEC_PACIA1716 "pacia")
3027 (UNSPEC_PACIB1716 "pacib")
3028 (UNSPEC_AUTIASP "autia")
3029 (UNSPEC_AUTIBSP "autib")
3030 (UNSPEC_AUTIA1716 "autia")
3031 (UNSPEC_AUTIB1716 "autib")])
3033 (define_int_attr pauth_key [(UNSPEC_PACIASP "AARCH64_KEY_A")
3034 (UNSPEC_PACIBSP "AARCH64_KEY_B")
3035 (UNSPEC_PACIA1716 "AARCH64_KEY_A")
3036 (UNSPEC_PACIB1716 "AARCH64_KEY_B")
3037 (UNSPEC_AUTIASP "AARCH64_KEY_A")
3038 (UNSPEC_AUTIBSP "AARCH64_KEY_B")
3039 (UNSPEC_AUTIA1716 "AARCH64_KEY_A")
3040 (UNSPEC_AUTIB1716 "AARCH64_KEY_B")])
3042 ;; Pointer authentication HINT number for NOP space instructions using A and
3044 (define_int_attr pauth_hint_num [(UNSPEC_PACIASP "25")
3045 (UNSPEC_PACIBSP "27")
3046 (UNSPEC_AUTIASP "29")
3047 (UNSPEC_AUTIBSP "31")
3048 (UNSPEC_PACIA1716 "8")
3049 (UNSPEC_PACIB1716 "10")
3050 (UNSPEC_AUTIA1716 "12")
3051 (UNSPEC_AUTIB1716 "14")])
3053 (define_int_attr perm_insn [(UNSPEC_ZIP1 "zip1") (UNSPEC_ZIP2 "zip2")
3054 (UNSPEC_ZIP1Q "zip1") (UNSPEC_ZIP2Q "zip2")
3055 (UNSPEC_TRN1 "trn1") (UNSPEC_TRN2 "trn2")
3056 (UNSPEC_TRN1Q "trn1") (UNSPEC_TRN2Q "trn2")
3057 (UNSPEC_UZP1 "uzp1") (UNSPEC_UZP2 "uzp2")
3058 (UNSPEC_UZP1Q "uzp1") (UNSPEC_UZP2Q "uzp2")])
3060 ; op code for REV instructions (size within which elements are reversed).
3061 (define_int_attr rev_op [(UNSPEC_REV64 "64") (UNSPEC_REV32 "32")
3062 (UNSPEC_REV16 "16")])
3064 (define_int_attr perm_hilo [(UNSPEC_UNPACKSHI "hi") (UNSPEC_UNPACKUHI "hi")
3065 (UNSPEC_UNPACKSLO "lo") (UNSPEC_UNPACKULO "lo")])
3067 ;; Return true if the associated optab refers to the high-numbered lanes,
3068 ;; false if it refers to the low-numbered lanes. The convention is for
3069 ;; "hi" to refer to the low-numbered lanes (the first ones in memory)
3071 (define_int_attr hi_lanes_optab [(UNSPEC_UNPACKSHI "!BYTES_BIG_ENDIAN")
3072 (UNSPEC_UNPACKUHI "!BYTES_BIG_ENDIAN")
3073 (UNSPEC_UNPACKSLO "BYTES_BIG_ENDIAN")
3074 (UNSPEC_UNPACKULO "BYTES_BIG_ENDIAN")])
3076 (define_int_attr crc_variant [(UNSPEC_CRC32B "crc32b") (UNSPEC_CRC32H "crc32h")
3077 (UNSPEC_CRC32W "crc32w") (UNSPEC_CRC32X "crc32x")
3078 (UNSPEC_CRC32CB "crc32cb") (UNSPEC_CRC32CH "crc32ch")
3079 (UNSPEC_CRC32CW "crc32cw") (UNSPEC_CRC32CX "crc32cx")])
3081 (define_int_attr crc_mode [(UNSPEC_CRC32B "QI") (UNSPEC_CRC32H "HI")
3082 (UNSPEC_CRC32W "SI") (UNSPEC_CRC32X "DI")
3083 (UNSPEC_CRC32CB "QI") (UNSPEC_CRC32CH "HI")
3084 (UNSPEC_CRC32CW "SI") (UNSPEC_CRC32CX "DI")])
3086 (define_int_attr aes_op [(UNSPEC_AESE "e") (UNSPEC_AESD "d")])
3087 (define_int_attr aesmc_op [(UNSPEC_AESMC "mc") (UNSPEC_AESIMC "imc")])
3089 (define_int_attr sha1_op [(UNSPEC_SHA1C "c") (UNSPEC_SHA1P "p")
3090 (UNSPEC_SHA1M "m")])
3092 (define_int_attr sha256_op [(UNSPEC_SHA256H "") (UNSPEC_SHA256H2 "2")])
3094 (define_int_attr rdma_as [(UNSPEC_SQRDMLAH "a") (UNSPEC_SQRDMLSH "s")])
3096 (define_int_attr sha512_op [(UNSPEC_SHA512H "") (UNSPEC_SHA512H2 "2")])
3098 (define_int_attr sm3tt_op [(UNSPEC_SM3TT1A "1a") (UNSPEC_SM3TT1B "1b")
3099 (UNSPEC_SM3TT2A "2a") (UNSPEC_SM3TT2B "2b")])
3101 (define_int_attr sm3part_op [(UNSPEC_SM3PARTW1 "1") (UNSPEC_SM3PARTW2 "2")])
3103 (define_int_attr f16mac1 [(UNSPEC_FMLAL "a") (UNSPEC_FMLSL "s")
3104 (UNSPEC_FMLAL2 "a") (UNSPEC_FMLSL2 "s")])
3106 (define_int_attr frintnzs_op [(UNSPEC_FRINT32Z "frint32z") (UNSPEC_FRINT32X "frint32x")
3107 (UNSPEC_FRINT64Z "frint64z") (UNSPEC_FRINT64X "frint64x")])
3109 ;; The condition associated with an UNSPEC_COND_<xx>.
3110 (define_int_attr cmp_op [(UNSPEC_COND_CMPEQ_WIDE "eq")
3111 (UNSPEC_COND_CMPGE_WIDE "ge")
3112 (UNSPEC_COND_CMPGT_WIDE "gt")
3113 (UNSPEC_COND_CMPHI_WIDE "hi")
3114 (UNSPEC_COND_CMPHS_WIDE "hs")
3115 (UNSPEC_COND_CMPLE_WIDE "le")
3116 (UNSPEC_COND_CMPLO_WIDE "lo")
3117 (UNSPEC_COND_CMPLS_WIDE "ls")
3118 (UNSPEC_COND_CMPLT_WIDE "lt")
3119 (UNSPEC_COND_CMPNE_WIDE "ne")
3120 (UNSPEC_COND_FCMEQ "eq")
3121 (UNSPEC_COND_FCMGE "ge")
3122 (UNSPEC_COND_FCMGT "gt")
3123 (UNSPEC_COND_FCMLE "le")
3124 (UNSPEC_COND_FCMLT "lt")
3125 (UNSPEC_COND_FCMNE "ne")
3126 (UNSPEC_WHILEGE "ge")
3127 (UNSPEC_WHILEGT "gt")
3128 (UNSPEC_WHILEHI "hi")
3129 (UNSPEC_WHILEHS "hs")
3130 (UNSPEC_WHILELE "le")
3131 (UNSPEC_WHILELO "lo")
3132 (UNSPEC_WHILELS "ls")
3133 (UNSPEC_WHILELT "lt")
3134 (UNSPEC_WHILERW "rw")
3135 (UNSPEC_WHILEWR "wr")])
3137 (define_int_attr while_optab_cmp [(UNSPEC_WHILEGE "ge")
3138 (UNSPEC_WHILEGT "gt")
3139 (UNSPEC_WHILEHI "ugt")
3140 (UNSPEC_WHILEHS "uge")
3141 (UNSPEC_WHILELE "le")
3142 (UNSPEC_WHILELO "ult")
3143 (UNSPEC_WHILELS "ule")
3144 (UNSPEC_WHILELT "lt")
3145 (UNSPEC_WHILERW "rw")
3146 (UNSPEC_WHILEWR "wr")])
3148 (define_int_attr raw_war [(UNSPEC_WHILERW "raw")
3149 (UNSPEC_WHILEWR "war")])
3151 (define_int_attr brk_op [(UNSPEC_BRKA "a") (UNSPEC_BRKB "b")
3153 (UNSPEC_BRKPA "pa") (UNSPEC_BRKPB "pb")])
3155 (define_int_attr sve_pred_op [(UNSPEC_PFIRST "pfirst") (UNSPEC_PNEXT "pnext")])
3157 (define_int_attr sve_int_op [(UNSPEC_ADCLB "adclb")
3158 (UNSPEC_ADCLT "adclt")
3159 (UNSPEC_ADDHNB "addhnb")
3160 (UNSPEC_ADDHNT "addhnt")
3161 (UNSPEC_ADDP "addp")
3162 (UNSPEC_ANDV "andv")
3163 (UNSPEC_ASHIFTRT_WIDE "asr")
3164 (UNSPEC_ASHIFT_WIDE "lsl")
3165 (UNSPEC_ASRD "asrd")
3166 (UNSPEC_BDEP "bdep")
3167 (UNSPEC_BEXT "bext")
3168 (UNSPEC_BGRP "bgrp")
3169 (UNSPEC_CADD90 "cadd")
3170 (UNSPEC_CADD270 "cadd")
3171 (UNSPEC_CDOT "cdot")
3172 (UNSPEC_CDOT90 "cdot")
3173 (UNSPEC_CDOT180 "cdot")
3174 (UNSPEC_CDOT270 "cdot")
3175 (UNSPEC_CMLA "cmla")
3176 (UNSPEC_CMLA90 "cmla")
3177 (UNSPEC_CMLA180 "cmla")
3178 (UNSPEC_CMLA270 "cmla")
3179 (UNSPEC_EORBT "eorbt")
3180 (UNSPEC_EORTB "eortb")
3182 (UNSPEC_LSHIFTRT_WIDE "lsr")
3183 (UNSPEC_MATCH "match")
3184 (UNSPEC_NMATCH "nmatch")
3185 (UNSPEC_PMULLB "pmullb")
3186 (UNSPEC_PMULLB_PAIR "pmullb")
3187 (UNSPEC_PMULLT "pmullt")
3188 (UNSPEC_PMULLT_PAIR "pmullt")
3189 (UNSPEC_RADDHNB "raddhnb")
3190 (UNSPEC_RADDHNT "raddhnt")
3191 (UNSPEC_RBIT "rbit")
3192 (UNSPEC_REVB "revb")
3193 (UNSPEC_REVH "revh")
3194 (UNSPEC_REVW "revw")
3195 (UNSPEC_RSHRNB "rshrnb")
3196 (UNSPEC_RSHRNT "rshrnt")
3197 (UNSPEC_RSQRTE "ursqrte")
3198 (UNSPEC_RSUBHNB "rsubhnb")
3199 (UNSPEC_RSUBHNT "rsubhnt")
3200 (UNSPEC_SABDLB "sabdlb")
3201 (UNSPEC_SABDLT "sabdlt")
3202 (UNSPEC_SADALP "sadalp")
3203 (UNSPEC_SADDLB "saddlb")
3204 (UNSPEC_SADDLBT "saddlbt")
3205 (UNSPEC_SADDLT "saddlt")
3206 (UNSPEC_SADDWB "saddwb")
3207 (UNSPEC_SADDWT "saddwt")
3208 (UNSPEC_SBCLB "sbclb")
3209 (UNSPEC_SBCLT "sbclt")
3210 (UNSPEC_SHADD "shadd")
3211 (UNSPEC_SHRNB "shrnb")
3212 (UNSPEC_SHRNT "shrnt")
3213 (UNSPEC_SHSUB "shsub")
3215 (UNSPEC_SMAXP "smaxp")
3216 (UNSPEC_SMAXV "smaxv")
3217 (UNSPEC_SMINP "sminp")
3218 (UNSPEC_SMINV "sminv")
3219 (UNSPEC_SMUL_HIGHPART "smulh")
3220 (UNSPEC_SMULLB "smullb")
3221 (UNSPEC_SMULLT "smullt")
3222 (UNSPEC_SQCADD90 "sqcadd")
3223 (UNSPEC_SQCADD270 "sqcadd")
3224 (UNSPEC_SQDMULH "sqdmulh")
3225 (UNSPEC_SQDMULLB "sqdmullb")
3226 (UNSPEC_SQDMULLBT "sqdmullbt")
3227 (UNSPEC_SQDMULLT "sqdmullt")
3228 (UNSPEC_SQRDCMLAH "sqrdcmlah")
3229 (UNSPEC_SQRDCMLAH90 "sqrdcmlah")
3230 (UNSPEC_SQRDCMLAH180 "sqrdcmlah")
3231 (UNSPEC_SQRDCMLAH270 "sqrdcmlah")
3232 (UNSPEC_SQRDMLAH "sqrdmlah")
3233 (UNSPEC_SQRDMLSH "sqrdmlsh")
3234 (UNSPEC_SQRDMULH "sqrdmulh")
3235 (UNSPEC_SQRSHL "sqrshl")
3236 (UNSPEC_SQRSHRNB "sqrshrnb")
3237 (UNSPEC_SQRSHRNT "sqrshrnt")
3238 (UNSPEC_SQRSHRUNB "sqrshrunb")
3239 (UNSPEC_SQRSHRUNT "sqrshrunt")
3240 (UNSPEC_SQSHL "sqshl")
3241 (UNSPEC_SQSHLU "sqshlu")
3242 (UNSPEC_SQSHRNB "sqshrnb")
3243 (UNSPEC_SQSHRNT "sqshrnt")
3244 (UNSPEC_SQSHRUNB "sqshrunb")
3245 (UNSPEC_SQSHRUNT "sqshrunt")
3246 (UNSPEC_SQXTNB "sqxtnb")
3247 (UNSPEC_SQXTNT "sqxtnt")
3248 (UNSPEC_SQXTUNB "sqxtunb")
3249 (UNSPEC_SQXTUNT "sqxtunt")
3250 (UNSPEC_SRHADD "srhadd")
3252 (UNSPEC_SRSHL "srshl")
3253 (UNSPEC_SRSHR "srshr")
3254 (UNSPEC_SSHLLB "sshllb")
3255 (UNSPEC_SSHLLT "sshllt")
3256 (UNSPEC_SSUBLB "ssublb")
3257 (UNSPEC_SSUBLBT "ssublbt")
3258 (UNSPEC_SSUBLT "ssublt")
3259 (UNSPEC_SSUBLTB "ssubltb")
3260 (UNSPEC_SSUBWB "ssubwb")
3261 (UNSPEC_SSUBWT "ssubwt")
3262 (UNSPEC_SUBHNB "subhnb")
3263 (UNSPEC_SUBHNT "subhnt")
3264 (UNSPEC_SUQADD "suqadd")
3265 (UNSPEC_UABDLB "uabdlb")
3266 (UNSPEC_UABDLT "uabdlt")
3267 (UNSPEC_UADALP "uadalp")
3268 (UNSPEC_UADDLB "uaddlb")
3269 (UNSPEC_UADDLT "uaddlt")
3270 (UNSPEC_UADDWB "uaddwb")
3271 (UNSPEC_UADDWT "uaddwt")
3272 (UNSPEC_UHADD "uhadd")
3273 (UNSPEC_UHSUB "uhsub")
3274 (UNSPEC_UMAXP "umaxp")
3275 (UNSPEC_UMAXV "umaxv")
3276 (UNSPEC_UMINP "uminp")
3277 (UNSPEC_UMINV "uminv")
3278 (UNSPEC_UMUL_HIGHPART "umulh")
3279 (UNSPEC_UMULLB "umullb")
3280 (UNSPEC_UMULLT "umullt")
3281 (UNSPEC_UQRSHL "uqrshl")
3282 (UNSPEC_UQRSHRNB "uqrshrnb")
3283 (UNSPEC_UQRSHRNT "uqrshrnt")
3284 (UNSPEC_UQSHL "uqshl")
3285 (UNSPEC_UQSHRNB "uqshrnb")
3286 (UNSPEC_UQSHRNT "uqshrnt")
3287 (UNSPEC_UQXTNB "uqxtnb")
3288 (UNSPEC_UQXTNT "uqxtnt")
3289 (UNSPEC_URECPE "urecpe")
3290 (UNSPEC_URHADD "urhadd")
3291 (UNSPEC_URSHL "urshl")
3292 (UNSPEC_URSHR "urshr")
3293 (UNSPEC_USHLLB "ushllb")
3294 (UNSPEC_USHLLT "ushllt")
3295 (UNSPEC_USQADD "usqadd")
3296 (UNSPEC_USUBLB "usublb")
3297 (UNSPEC_USUBLT "usublt")
3298 (UNSPEC_USUBWB "usubwb")
3299 (UNSPEC_USUBWT "usubwt")
3300 (UNSPEC_XORV "eorv")])
3302 (define_int_attr sve_int_op_rev [(UNSPEC_SHADD "shadd")
3303 (UNSPEC_SHSUB "shsubr")
3304 (UNSPEC_SQRSHL "sqrshlr")
3305 (UNSPEC_SRHADD "srhadd")
3306 (UNSPEC_SRSHL "srshlr")
3307 (UNSPEC_UHADD "uhadd")
3308 (UNSPEC_UHSUB "uhsubr")
3309 (UNSPEC_UQRSHL "uqrshlr")
3310 (UNSPEC_URHADD "urhadd")
3311 (UNSPEC_URSHL "urshlr")])
3313 (define_int_attr sve_int_add_op [(UNSPEC_SABDLB "sabalb")
3314 (UNSPEC_SABDLT "sabalt")
3315 (UNSPEC_SMULLB "smlalb")
3316 (UNSPEC_SMULLT "smlalt")
3317 (UNSPEC_UABDLB "uabalb")
3318 (UNSPEC_UABDLT "uabalt")
3319 (UNSPEC_UMULLB "umlalb")
3320 (UNSPEC_UMULLT "umlalt")])
3322 (define_int_attr sve_int_qadd_op [(UNSPEC_SQDMULLB "sqdmlalb")
3323 (UNSPEC_SQDMULLBT "sqdmlalbt")
3324 (UNSPEC_SQDMULLT "sqdmlalt")])
3326 (define_int_attr sve_int_sub_op [(UNSPEC_SMULLB "smlslb")
3327 (UNSPEC_SMULLT "smlslt")
3328 (UNSPEC_UMULLB "umlslb")
3329 (UNSPEC_UMULLT "umlslt")])
3331 (define_int_attr sve_int_qsub_op [(UNSPEC_SQDMULLB "sqdmlslb")
3332 (UNSPEC_SQDMULLBT "sqdmlslbt")
3333 (UNSPEC_SQDMULLT "sqdmlslt")])
3335 (define_int_attr sve_fp_op [(UNSPEC_BFDOT "bfdot")
3336 (UNSPEC_BFMLALB "bfmlalb")
3337 (UNSPEC_BFMLALT "bfmlalt")
3338 (UNSPEC_BFMMLA "bfmmla")
3339 (UNSPEC_FRECPE "frecpe")
3340 (UNSPEC_FRECPS "frecps")
3341 (UNSPEC_RSQRTE "frsqrte")
3342 (UNSPEC_RSQRTS "frsqrts")
3343 (UNSPEC_FADDP "faddp")
3344 (UNSPEC_FADDV "faddv")
3345 (UNSPEC_FEXPA "fexpa")
3346 (UNSPEC_FMAXNMP "fmaxnmp")
3347 (UNSPEC_FMAXNMV "fmaxnmv")
3348 (UNSPEC_FMAXP "fmaxp")
3349 (UNSPEC_FMAXV "fmaxv")
3350 (UNSPEC_FMINNMP "fminnmp")
3351 (UNSPEC_FMINNMV "fminnmv")
3352 (UNSPEC_FMINP "fminp")
3353 (UNSPEC_FMINV "fminv")
3354 (UNSPEC_FMLA "fmla")
3355 (UNSPEC_FMLALB "fmlalb")
3356 (UNSPEC_FMLALT "fmlalt")
3357 (UNSPEC_FMLS "fmls")
3358 (UNSPEC_FMLSLB "fmlslb")
3359 (UNSPEC_FMLSLT "fmlslt")
3360 (UNSPEC_FMMLA "fmmla")
3361 (UNSPEC_FTSMUL "ftsmul")
3362 (UNSPEC_FTSSEL "ftssel")
3363 (UNSPEC_COND_FABS "fabs")
3364 (UNSPEC_COND_FADD "fadd")
3365 (UNSPEC_COND_FCVTLT "fcvtlt")
3366 (UNSPEC_COND_FCVTX "fcvtx")
3367 (UNSPEC_COND_FDIV "fdiv")
3368 (UNSPEC_COND_FLOGB "flogb")
3369 (UNSPEC_COND_FMAX "fmax")
3370 (UNSPEC_COND_FMAXNM "fmaxnm")
3371 (UNSPEC_COND_FMIN "fmin")
3372 (UNSPEC_COND_FMINNM "fminnm")
3373 (UNSPEC_COND_FMUL "fmul")
3374 (UNSPEC_COND_FMULX "fmulx")
3375 (UNSPEC_COND_FNEG "fneg")
3376 (UNSPEC_COND_FRECPX "frecpx")
3377 (UNSPEC_COND_FRINTA "frinta")
3378 (UNSPEC_COND_FRINTI "frinti")
3379 (UNSPEC_COND_FRINTM "frintm")
3380 (UNSPEC_COND_FRINTN "frintn")
3381 (UNSPEC_COND_FRINTP "frintp")
3382 (UNSPEC_COND_FRINTX "frintx")
3383 (UNSPEC_COND_FRINTZ "frintz")
3384 (UNSPEC_COND_FSCALE "fscale")
3385 (UNSPEC_COND_FSQRT "fsqrt")
3386 (UNSPEC_COND_FSUB "fsub")])
3388 (define_int_attr sve_fp_op_rev [(UNSPEC_COND_FADD "fadd")
3389 (UNSPEC_COND_FDIV "fdivr")
3390 (UNSPEC_COND_FMAX "fmax")
3391 (UNSPEC_COND_FMAXNM "fmaxnm")
3392 (UNSPEC_COND_FMIN "fmin")
3393 (UNSPEC_COND_FMINNM "fminnm")
3394 (UNSPEC_COND_FMUL "fmul")
3395 (UNSPEC_COND_FMULX "fmulx")
3396 (UNSPEC_COND_FSUB "fsubr")])
3398 (define_int_attr rot [(UNSPEC_CADD90 "90")
3399 (UNSPEC_CADD270 "270")
3401 (UNSPEC_CDOT90 "90")
3402 (UNSPEC_CDOT180 "180")
3403 (UNSPEC_CDOT270 "270")
3405 (UNSPEC_CMLA90 "90")
3406 (UNSPEC_CMLA180 "180")
3407 (UNSPEC_CMLA270 "270")
3408 (UNSPEC_FCADD90 "90")
3409 (UNSPEC_FCADD270 "270")
3411 (UNSPEC_FCMLA90 "90")
3412 (UNSPEC_FCMLA180 "180")
3413 (UNSPEC_FCMLA270 "270")
3414 (UNSPEC_SQCADD90 "90")
3415 (UNSPEC_SQCADD270 "270")
3416 (UNSPEC_SQRDCMLAH "0")
3417 (UNSPEC_SQRDCMLAH90 "90")
3418 (UNSPEC_SQRDCMLAH180 "180")
3419 (UNSPEC_SQRDCMLAH270 "270")
3420 (UNSPEC_COND_FCADD90 "90")
3421 (UNSPEC_COND_FCADD270 "270")
3422 (UNSPEC_COND_FCMLA "0")
3423 (UNSPEC_COND_FCMLA90 "90")
3424 (UNSPEC_COND_FCMLA180 "180")
3425 (UNSPEC_COND_FCMLA270 "270")])
3427 (define_int_attr sve_fmla_op [(UNSPEC_COND_FMLA "fmla")
3428 (UNSPEC_COND_FMLS "fmls")
3429 (UNSPEC_COND_FNMLA "fnmla")
3430 (UNSPEC_COND_FNMLS "fnmls")])
3432 (define_int_attr sve_fmad_op [(UNSPEC_COND_FMLA "fmad")
3433 (UNSPEC_COND_FMLS "fmsb")
3434 (UNSPEC_COND_FNMLA "fnmad")
3435 (UNSPEC_COND_FNMLS "fnmsb")])
3437 ;; The register constraint to use for the final operand in a binary BRK.
3438 (define_int_attr brk_reg_con [(UNSPEC_BRKN "0")
3439 (UNSPEC_BRKPA "Upa") (UNSPEC_BRKPB "Upa")])
3441 ;; The register number to print for the above.
3442 (define_int_attr brk_reg_opno [(UNSPEC_BRKN "0")
3443 (UNSPEC_BRKPA "3") (UNSPEC_BRKPB "3")])
3445 ;; The predicate to use for the first input operand in a floating-point
3446 ;; <optab><mode>3 pattern.
3447 (define_int_attr sve_pred_fp_rhs1_operand
3448 [(UNSPEC_COND_FADD "register_operand")
3449 (UNSPEC_COND_FDIV "register_operand")
3450 (UNSPEC_COND_FMAX "register_operand")
3451 (UNSPEC_COND_FMAXNM "register_operand")
3452 (UNSPEC_COND_FMIN "register_operand")
3453 (UNSPEC_COND_FMINNM "register_operand")
3454 (UNSPEC_COND_FMUL "register_operand")
3455 (UNSPEC_COND_FMULX "register_operand")
3456 (UNSPEC_COND_FSUB "aarch64_sve_float_arith_operand")])
3458 ;; The predicate to use for the second input operand in a floating-point
3459 ;; <optab><mode>3 pattern.
3460 (define_int_attr sve_pred_fp_rhs2_operand
3461 [(UNSPEC_COND_FADD "aarch64_sve_float_arith_with_sub_operand")
3462 (UNSPEC_COND_FDIV "register_operand")
3463 (UNSPEC_COND_FMAX "aarch64_sve_float_maxmin_operand")
3464 (UNSPEC_COND_FMAXNM "aarch64_sve_float_maxmin_operand")
3465 (UNSPEC_COND_FMIN "aarch64_sve_float_maxmin_operand")
3466 (UNSPEC_COND_FMINNM "aarch64_sve_float_maxmin_operand")
3467 (UNSPEC_COND_FMUL "aarch64_sve_float_mul_operand")
3468 (UNSPEC_COND_FMULX "register_operand")
3469 (UNSPEC_COND_FSUB "register_operand")])
3471 ;; Likewise for immediates only.
3472 (define_int_attr sve_pred_fp_rhs2_immediate
3473 [(UNSPEC_COND_FMAX "aarch64_sve_float_maxmin_immediate")
3474 (UNSPEC_COND_FMAXNM "aarch64_sve_float_maxmin_immediate")
3475 (UNSPEC_COND_FMIN "aarch64_sve_float_maxmin_immediate")
3476 (UNSPEC_COND_FMINNM "aarch64_sve_float_maxmin_immediate")
3477 (UNSPEC_COND_FMUL "aarch64_sve_float_mul_immediate")])
3479 ;; The maximum number of element bits that an instruction can handle.
3480 (define_int_attr max_elem_bits [(UNSPEC_UADDV "64") (UNSPEC_SADDV "32")
3481 (UNSPEC_PFIRST "8") (UNSPEC_PNEXT "64")])
3483 ;; The minimum number of element bits that an instruction can handle.
3484 (define_int_attr min_elem_bits [(UNSPEC_RBIT "8")
3487 (UNSPEC_REVW "64")])
3489 (define_int_attr unspec [(UNSPEC_WHILERW "UNSPEC_WHILERW")
3490 (UNSPEC_WHILEWR "UNSPEC_WHILEWR")])
3492 ;; Iterators and attributes for fpcr fpsr getter setters
3494 (define_int_iterator GET_FPSCR
3495 [UNSPECV_GET_FPSR UNSPECV_GET_FPCR])
3497 (define_int_iterator SET_FPSCR
3498 [UNSPECV_SET_FPSR UNSPECV_SET_FPCR])
3500 (define_int_attr fpscr_name
3501 [(UNSPECV_GET_FPSR "fpsr")
3502 (UNSPECV_SET_FPSR "fpsr")
3503 (UNSPECV_GET_FPCR "fpcr")
3504 (UNSPECV_SET_FPCR "fpcr")])