gcc/config/mips/octeon.md

   1 ;;  Octeon pipeline description.
   2 ;;  Copyright (C) 2008-2021 Free Software Foundation, Inc.
   3
   4 ;; This file is part of GCC.
   5
   6 ;; GCC is free software; you can redistribute it and/or modify
   7 ;; it under the terms of the GNU General Public License as published by
   8 ;; the Free Software Foundation; either version 3, or (at your option)
   9 ;; any later version.
  10
  11 ;; GCC is distributed in the hope that it will be useful,
  12 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
  13 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14 ;; GNU General Public License for more details.
  15
  16 ;; You should have received a copy of the GNU General Public License
  17 ;; along with GCC; see the file COPYING3.  If not see
  18 ;; <http://www.gnu.org/licenses/>.
  19 ;;   Copyright (C) 2004, 2005, 2006 Cavium Networks.
  20
  21
  22 ;; Octeon is a dual-issue processor that can issue all instructions on
  23 ;; pipe0 and a subset on pipe1.
  24
  25 (define_automaton "octeon_main, octeon_mult, octeon_fpu")
  26
  27 (define_cpu_unit "octeon_pipe0" "octeon_main")
  28 (define_cpu_unit "octeon_pipe1" "octeon_main")
  29 (define_cpu_unit "octeon_mult" "octeon_mult")
  30 (define_cpu_unit "octeon_fpu" "octeon_fpu")
  31
  32 (define_insn_reservation "octeon_arith" 1
  33   (and (eq_attr "cpu" "octeon,octeon2,octeon3")
  34        (eq_attr "type" "arith,const,logical,move,shift,signext,slt,nop"))
  35   "octeon_pipe0 | octeon_pipe1")
  36
  37 (define_insn_reservation "octeon_condmove_o1" 2
  38   (and (eq_attr "cpu" "octeon")
  39        (eq_attr "type" "condmove"))
  40   "octeon_pipe0 | octeon_pipe1")
  41
  42 (define_insn_reservation "octeon_condmove_o2" 3
  43   (and (eq_attr "cpu" "octeon2,octeon3")
  44        (eq_attr "type" "condmove")
  45        (not (eq_attr "mode" "SF, DF")))
  46   "octeon_pipe0 | octeon_pipe1")
  47
  48 ;; movt/movf can only issue in pipe1
  49 (define_insn_reservation "octeon_condmove_o3_int_on_cc" 3
  50   (and (eq_attr "cpu" "octeon2,octeon3")
  51        (eq_attr "type" "condmove")
  52        (not (eq_attr "mode" "SF, DF")))
  53   "octeon_pipe1")
  54
  55 (define_insn_reservation "octeon_load_o1" 2
  56   (and (eq_attr "cpu" "octeon")
  57        (eq_attr "type" "load,prefetch,mtc,mfc"))
  58   "octeon_pipe0")
  59
  60 (define_insn_reservation "octeon_load_o2" 3
  61   (and (eq_attr "cpu" "octeon2,octeon3")
  62        (eq_attr "type" "load,prefetch"))
  63   "octeon_pipe0")
  64
  65 ;; ??? memory-related cop0 reads are pipe0 with 3-cycle latency.
  66 ;; Front-end-related ones are 1-cycle on pipe1.  Assume front-end for now.
  67 (define_insn_reservation "octeon_cop_o2" 1
  68   (and (eq_attr "cpu" "octeon2,octeon3")
  69        (eq_attr "type" "mtc,mfc"))
  70   "octeon_pipe1")
  71
  72 (define_insn_reservation "octeon_store" 1
  73   (and (eq_attr "cpu" "octeon,octeon2,octeon3")
  74        (eq_attr "type" "store"))
  75   "octeon_pipe0")
  76
  77 (define_insn_reservation "octeon_brj_o1" 1
  78   (and (eq_attr "cpu" "octeon")
  79        (eq_attr "type" "branch,jump,call,trap"))
  80   "octeon_pipe0")
  81
  82 (define_insn_reservation "octeon_brj_o2" 2
  83   (and (eq_attr "cpu" "octeon2,octeon3")
  84        (eq_attr "type" "branch,jump,call,trap"))
  85   "octeon_pipe1")
  86
  87 (define_insn_reservation "octeon_imul3_o1" 5
  88   (and (eq_attr "cpu" "octeon")
  89        (eq_attr "type" "imul3,pop,clz"))
  90   "(octeon_pipe0 | octeon_pipe1) + octeon_mult")
  91
  92 (define_insn_reservation "octeon_imul3_o2" 6
  93   (and (eq_attr "cpu" "octeon2,octeon3")
  94        (eq_attr "type" "imul3,pop,clz"))
  95   "octeon_pipe1 + octeon_mult")
  96
  97 (define_insn_reservation "octeon_imul_o1" 2
  98   (and (eq_attr "cpu" "octeon")
  99        (eq_attr "type" "imul,mthi,mtlo"))
 100   "(octeon_pipe0 | octeon_pipe1) + octeon_mult, octeon_mult")
 101
 102 (define_insn_reservation "octeon_imul_o2" 1
 103   (and (eq_attr "cpu" "octeon2,octeon3")
 104        (eq_attr "type" "imul,mthi,mtlo"))
 105   "octeon_pipe1 + octeon_mult")
 106
 107 (define_insn_reservation "octeon_mfhilo_o1" 5
 108   (and (eq_attr "cpu" "octeon")
 109        (eq_attr "type" "mfhi,mflo"))
 110   "(octeon_pipe0 | octeon_pipe1) + octeon_mult")
 111
 112 (define_insn_reservation "octeon_mfhilo_o2" 6
 113   (and (eq_attr "cpu" "octeon2,octeon3")
 114        (eq_attr "type" "mfhi,mflo"))
 115   "octeon_pipe1 + octeon_mult")
 116
 117 (define_insn_reservation "octeon_imadd_o1" 4
 118   (and (eq_attr "cpu" "octeon")
 119        (eq_attr "type" "imadd"))
 120   "(octeon_pipe0 | octeon_pipe1) + octeon_mult, octeon_mult*3")
 121
 122 (define_insn_reservation "octeon_imadd_o2" 1
 123   (and (eq_attr "cpu" "octeon2,octeon3")
 124        (eq_attr "type" "imadd"))
 125   "octeon_pipe1 + octeon_mult")
 126
 127 (define_insn_reservation "octeon_idiv_o1" 72
 128   (and (eq_attr "cpu" "octeon")
 129        (eq_attr "type" "idiv"))
 130   "(octeon_pipe0 | octeon_pipe1) + octeon_mult, octeon_mult*71")
 131
 132 (define_insn_reservation "octeon_idiv_o2_si" 18
 133   (and (eq_attr "cpu" "octeon2,octeon3")
 134        (eq_attr "mode" "SI")
 135        (eq_attr "type" "idiv"))
 136   "octeon_pipe1 + octeon_mult, octeon_mult*17")
 137
 138 (define_insn_reservation "octeon_idiv_o2_di" 35
 139   (and (eq_attr "cpu" "octeon2,octeon3")
 140        (eq_attr "mode" "DI")
 141        (eq_attr "type" "idiv"))
 142   "octeon_pipe1 + octeon_mult, octeon_mult*34")
 143
 144 ;; Assume both pipes are needed for unknown and multiple-instruction
 145 ;; patterns.
 146
 147 (define_insn_reservation "octeon_unknown" 1
 148   (and (eq_attr "cpu" "octeon,octeon2,octeon3")
 149        (eq_attr "type" "unknown,multi,atomic,syncloop"))
 150   "octeon_pipe0 + octeon_pipe1")
 151
 152 ;; Octeon3 FPU
 153
 154 (define_insn_reservation "octeon3_faddsubcvt" 4
 155   (and (eq_attr "cpu" "octeon3")
 156        (eq_attr "type" "fadd, fcvt"))
 157   "octeon_pipe1 + octeon_fpu")
 158
 159 (define_insn_reservation "octeon3_fmul" 5
 160   (and (eq_attr "cpu" "octeon3")
 161        (eq_attr "type" "fmul"))
 162   "octeon_pipe1 + octeon_fpu")
 163
 164 (define_insn_reservation "octeon3_fmadd" 9
 165   (and (eq_attr "cpu" "octeon3")
 166        (eq_attr "type" "fmadd"))
 167   "octeon_pipe1 + octeon_fpu, octeon_fpu")
 168
 169 (define_insn_reservation "octeon3_div_sf" 12
 170   (and (eq_attr "cpu" "octeon3")
 171        (eq_attr "type" "fdiv, frdiv")
 172        (eq_attr "mode" "SF"))
 173   "octeon_pipe1 + octeon_fpu, octeon_fpu*8")
 174
 175 (define_insn_reservation "octeon3_div_df" 22
 176   (and (eq_attr "cpu" "octeon3")
 177        (eq_attr "type" "fdiv, frdiv")
 178        (eq_attr "mode" "SF"))
 179   "octeon_pipe1 + octeon_fpu, octeon_fpu*18")
 180
 181 (define_insn_reservation "octeon3_sqrt_sf" 16
 182   (and (eq_attr "cpu" "octeon3")
 183        (eq_attr "type" "fsqrt")
 184        (eq_attr "mode" "SF"))
 185   "octeon_pipe1 + octeon_fpu, octeon_fpu*12")
 186
 187 (define_insn_reservation "octeon3_sqrt_df" 30
 188   (and (eq_attr "cpu" "octeon3")
 189        (eq_attr "type" "fsqrt")
 190        (eq_attr "mode" "DF"))
 191   "octeon_pipe1 + octeon_fpu, octeon_fpu*26")
 192
 193 (define_insn_reservation "octeon3_rsqrt_sf" 27
 194   (and (eq_attr "cpu" "octeon3")
 195        (eq_attr "type" "frsqrt")
 196        (eq_attr "mode" "SF"))
 197   "octeon_pipe1 + octeon_fpu, octeon_fpu*23")
 198
 199 (define_insn_reservation "octeon3_rsqrt_df" 51
 200   (and (eq_attr "cpu" "octeon3")
 201        (eq_attr "type" "frsqrt")
 202        (eq_attr "mode" "DF"))
 203   "octeon_pipe1 + octeon_fpu, octeon_fpu*47")
 204
 205 (define_insn_reservation "octeon3_fabsnegmov" 2
 206   (and (eq_attr "cpu" "octeon3")
 207        (eq_attr "type" "fabs, fneg, fmove"))
 208   "octeon_pipe1 + octeon_fpu")
 209
 210 (define_insn_reservation "octeon_fcond" 1
 211   (and (eq_attr "cpu" "octeon3")
 212        (eq_attr "type" "fcmp"))
 213   "octeon_pipe1 + octeon_fpu")
 214
 215 (define_insn_reservation "octeon_fcondmov" 2
 216   (and (eq_attr "cpu" "octeon3")
 217        (eq_attr "type" "condmove")
 218        (eq_attr "mode" "SF,DF"))
 219   "octeon_pipe1 + octeon_fpu")
 220
 221 (define_insn_reservation "octeon_fpmtc1" 2
 222   (and (eq_attr "cpu" "octeon3")
 223        (eq_attr "type" "mtc"))
 224   "octeon_pipe1 + octeon_fpu")
 225
 226 (define_insn_reservation "octeon_fpmfc1" 6
 227   (and (eq_attr "cpu" "octeon3")
 228        (eq_attr "type" "mtc"))
 229   "octeon_pipe1 + octeon_fpu")
 230
 231 (define_insn_reservation "octeon_fpload" 3
 232   (and (eq_attr "cpu" "octeon3")
 233        (eq_attr "type" "fpload,fpidxload"))
 234   "octeon_pipe0 + octeon_fpu")
 235
 236 (define_insn_reservation "octeon_fpstore" 3
 237   (and (eq_attr "cpu" "octeon3")
 238        (eq_attr "type" "fpstore,fpidxstore"))
 239   "octeon_pipe0 + octeon_pipe1")