1 ;;- Machine description for HP PA-RISC architecture for GCC compiler
2 ;; Copyright (C) 1992-2021 Free Software Foundation, Inc.
3 ;; Contributed by the Center for Software Science at the University
6 ;; This file is part of GCC.
8 ;; GCC is free software; you can redistribute it and/or modify
9 ;; it under the terms of the GNU General Public License as published by
10 ;; the Free Software Foundation; either version 3, or (at your option)
13 ;; GCC is distributed in the hope that it will be useful,
14 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
15 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 ;; GNU General Public License for more details.
18 ;; You should have received a copy of the GNU General Public License
19 ;; along with GCC; see the file COPYING3. If not see
20 ;; <http://www.gnu.org/licenses/>.
22 ;; This machine description is inspired by sparc.md and to a lesser
25 ;; Possible improvements:
27 ;; * With PA1.1, most computational instructions can conditionally nullify
28 ;; the execution of the following instruction. A nullified instruction
29 ;; does not cause the instruction pipeline to stall, making it a very
30 ;; efficient alternative to e.g. branching or conditional moves.
32 ;; Nullification is performed conditionally based on the outcome of a
33 ;; test specified in the opcode. The test result is stored in PSW[N]
34 ;; and can only be used to nullify the instruction following immediately
35 ;; after the test. For example:
39 ;; sub,< %r26,%r25,%r28
40 ;; sub %r28,%r25,%r28 ; %r28 == 0
41 ;; sub,> %r26,%r25,%r29
42 ;; sub %r29,%r25,%r29 ; %r29 == 5
44 ;; This could be tricky to implement because the result of the test has
45 ;; to be propagated one instruction forward, which, in the worst case,
46 ;; would involve (1) adding a fake register for PSW[N]; (2) adding the
47 ;; variants of the computational instructions that set or consume this
48 ;; fake register. The cond_exec infrastructure is probably not helpful
51 ;; * PA-RISC includes a set of conventions for branch instruction usage
52 ;; to indicate whether a particular branch is more likely to be taken
53 ;; or not taken. For example, the prediction for CMPB instructions
54 ;; (CMPB,cond,n r1,r2,target) depends on the direction of the branch
55 ;; (forward or backward) and on the order of the operands:
57 ;; | branch | operand | branch |
58 ;; | direction | compare | prediction |
59 ;; +-----------+----------+------------+
60 ;; | backward | r1 < r2 | taken |
61 ;; | backward | r1 >= r2 | not taken |
62 ;; | forward | r1 < r2 | not taken |
63 ;; | forward | r1 >= r2 | taken |
65 ;; By choosing instructions and operand order carefully, the compiler
66 ;; could give the CPU branch predictor some help.
69 ;;- See file "rtl.def" for documentation on define_insn, match_*, et. al.
71 ;; Uses of UNSPEC in this file:
73 (define_c_enum "unspec"
74 [UNSPEC_CFFC ; canonicalize_funcptr_for_compare
75 UNSPEC_GOTO ; indirect_goto
92 (define_c_enum "unspecv"
93 [UNSPECV_BLOCKAGE ; blockage
94 UNSPECV_DCACHE ; dcacheflush
95 UNSPECV_ICACHE ; icacheflush
96 UNSPECV_OPC ; outline_prologue_call
97 UNSPECV_OEC ; outline_epilogue_call
98 UNSPECV_LONGJMP ; builtin_longjmp
101 ;; Maximum pc-relative branch offsets.
103 ;; These numbers are a bit smaller than the maximum allowable offsets
104 ;; so that a few instructions may be inserted before the actual branch.
107 [(MAX_12BIT_OFFSET 8184) ; 12-bit branch
108 (MAX_17BIT_OFFSET 262100) ; 17-bit branch
111 ;; Mode and code iterators
113 ;; This mode iterator allows :P to be used for patterns that operate on
114 ;; pointer-sized quantities. Exactly one of the two alternatives will match.
115 (define_mode_iterator P [(SI "Pmode == SImode") (DI "Pmode == DImode")])
117 ;; This attribute defines the condition prefix for word and double word
118 ;; add, compare, subtract and logical instructions.
119 (define_mode_attr dwc [(SI "") (DI "*")])
121 ;; Insn type. Used to default other attribute values.
123 ;; type "unary" insns have one input operand (1) and one output operand (0)
124 ;; type "binary" insns have two input operands (1,2) and one output (0)
127 "move,unary,binary,shift,nullshift,compare,load,store,uncond_branch,branch,cbranch,fbranch,call,sibcall,dyncall,fpload,fpstore,fpalu,fpcc,fpmulsgl,fpmuldbl,fpdivsgl,fpdivdbl,fpsqrtsgl,fpsqrtdbl,multi,milli,sh_func_adrs,parallel_branch,fpstore_load,store_fpload,trap"
128 (const_string "binary"))
130 (define_attr "pa_combine_type"
131 "fmpy,faddsub,uncond_branch,addmove,none"
132 (const_string "none"))
134 ;; Processor type (for scheduling, not code generation) -- this attribute
135 ;; must exactly match the processor_type enumeration in pa.h.
137 ;; FIXME: Add 800 scheduling for completeness?
139 (define_attr "cpu" "700,7100,7100LC,7200,7300,8000" (const (symbol_ref "pa_cpu_attr")))
141 ;; Length (in # of bytes).
142 (define_attr "length" ""
143 (cond [(eq_attr "type" "load,fpload")
144 (if_then_else (match_operand 1 "symbolic_memory_operand" "")
145 (const_int 8) (const_int 4))
147 (eq_attr "type" "store,fpstore")
148 (if_then_else (match_operand 0 "symbolic_memory_operand" "")
149 (const_int 8) (const_int 4))
151 (eq_attr "type" "binary,shift,nullshift")
152 (if_then_else (match_operand 2 "arith14_operand" "")
153 (const_int 4) (const_int 12))
155 (eq_attr "type" "move,unary,shift,nullshift")
156 (if_then_else (match_operand 1 "arith14_operand" "")
157 (const_int 4) (const_int 8))]
161 (define_asm_attributes
162 [(set_attr "length" "4")
163 (set_attr "type" "multi")])
165 ;; Attributes for instruction and branch scheduling
167 ;; For conditional branches. Frame related instructions are not allowed
168 ;; because they confuse the unwind support.
169 (define_attr "in_branch_delay" "false,true"
170 (if_then_else (and (eq_attr "type" "!uncond_branch,branch,cbranch,fbranch,call,sibcall,dyncall,multi,milli,sh_func_adrs,parallel_branch,trap")
171 (eq_attr "length" "4")
172 (not (match_test "RTX_FRAME_RELATED_P (insn)")))
173 (const_string "true")
174 (const_string "false")))
176 ;; Disallow instructions which use the FPU since they will tie up the FPU
177 ;; even if the instruction is nullified.
178 (define_attr "in_nullified_branch_delay" "false,true"
179 (if_then_else (and (eq_attr "type" "!uncond_branch,branch,cbranch,fbranch,call,sibcall,dyncall,multi,milli,sh_func_adrs,fpcc,fpalu,fpmulsgl,fpmuldbl,fpdivsgl,fpdivdbl,fpsqrtsgl,fpsqrtdbl,parallel_branch,trap")
180 (eq_attr "length" "4")
181 (not (match_test "RTX_FRAME_RELATED_P (insn)")))
182 (const_string "true")
183 (const_string "false")))
185 ;; For calls and millicode calls.
186 (define_attr "in_call_delay" "false,true"
187 (if_then_else (and (eq_attr "type" "!uncond_branch,branch,cbranch,fbranch,call,sibcall,dyncall,multi,milli,sh_func_adrs,parallel_branch,trap")
188 (eq_attr "length" "4")
189 (not (match_test "RTX_FRAME_RELATED_P (insn)")))
190 (const_string "true")
191 (const_string "false")))
193 ;; Call delay slot description.
194 (define_delay (eq_attr "type" "call")
195 [(eq_attr "in_call_delay" "true") (nil) (nil)])
197 ;; Sibcall delay slot description.
198 (define_delay (eq_attr "type" "sibcall")
199 [(eq_attr "in_call_delay" "true") (nil) (nil)])
201 ;; Millicode call delay slot description.
202 (define_delay (eq_attr "type" "milli")
203 [(eq_attr "in_call_delay" "true") (nil) (nil)])
205 ;; Return and other similar instructions.
206 (define_delay (eq_attr "type" "branch,parallel_branch")
207 [(eq_attr "in_branch_delay" "true") (nil) (nil)])
209 ;; Floating point conditional branch delay slot description.
210 (define_delay (eq_attr "type" "fbranch")
211 [(eq_attr "in_branch_delay" "true")
212 (eq_attr "in_nullified_branch_delay" "true")
215 ;; Integer conditional branch delay slot description.
216 ;; Nullification of conditional branches on the PA is dependent on the
217 ;; direction of the branch. Forward branches nullify true and
218 ;; backward branches nullify false. If the direction is unknown
219 ;; then nullification is not allowed.
220 (define_delay (eq_attr "type" "cbranch")
221 [(eq_attr "in_branch_delay" "true")
222 (and (eq_attr "in_nullified_branch_delay" "true")
223 (attr_flag "forward"))
224 (and (eq_attr "in_nullified_branch_delay" "true")
225 (attr_flag "backward"))])
227 (define_delay (eq_attr "type" "uncond_branch")
228 [(eq_attr "in_branch_delay" "true") (nil) (nil)])
230 ;; Memory. Disregarding Cache misses, the Mustang memory times are:
231 ;; load: 2, fpload: 3
232 ;; store, fpstore: 3, no D-cache operations should be scheduled.
234 ;; The Timex (aka 700) has two floating-point units: ALU, and MUL/DIV/SQRT.
236 ;; Instruction Time Unit Minimum Distance (unit contention)
243 ;; fmpyadd 3 ALU,MPY 2
244 ;; fmpysub 3 ALU,MPY 2
245 ;; fmpycfxt 3 ALU,MPY 2
248 ;; fdiv,sgl 10 MPY 10
249 ;; fdiv,dbl 12 MPY 12
250 ;; fsqrt,sgl 14 MPY 14
251 ;; fsqrt,dbl 18 MPY 18
253 ;; We don't model fmpyadd/fmpysub properly as those instructions
254 ;; keep both the FP ALU and MPY units busy. Given that these
255 ;; processors are obsolete, I'm not going to spend the time to
256 ;; model those instructions correctly.
258 (define_automaton "pa700")
259 (define_cpu_unit "dummy_700,mem_700,fpalu_700,fpmpy_700" "pa700")
261 (define_insn_reservation "W0" 4
262 (and (eq_attr "type" "fpcc")
263 (eq_attr "cpu" "700"))
266 (define_insn_reservation "W1" 3
267 (and (eq_attr "type" "fpalu")
268 (eq_attr "cpu" "700"))
271 (define_insn_reservation "W2" 3
272 (and (eq_attr "type" "fpmulsgl,fpmuldbl")
273 (eq_attr "cpu" "700"))
276 (define_insn_reservation "W3" 10
277 (and (eq_attr "type" "fpdivsgl")
278 (eq_attr "cpu" "700"))
281 (define_insn_reservation "W4" 12
282 (and (eq_attr "type" "fpdivdbl")
283 (eq_attr "cpu" "700"))
286 (define_insn_reservation "W5" 14
287 (and (eq_attr "type" "fpsqrtsgl")
288 (eq_attr "cpu" "700"))
291 (define_insn_reservation "W6" 18
292 (and (eq_attr "type" "fpsqrtdbl")
293 (eq_attr "cpu" "700"))
296 (define_insn_reservation "W7" 2
297 (and (eq_attr "type" "load")
298 (eq_attr "cpu" "700"))
301 (define_insn_reservation "W8" 2
302 (and (eq_attr "type" "fpload")
303 (eq_attr "cpu" "700"))
306 (define_insn_reservation "W9" 3
307 (and (eq_attr "type" "store")
308 (eq_attr "cpu" "700"))
311 (define_insn_reservation "W10" 3
312 (and (eq_attr "type" "fpstore")
313 (eq_attr "cpu" "700"))
316 (define_insn_reservation "W11" 5
317 (and (eq_attr "type" "fpstore_load")
318 (eq_attr "cpu" "700"))
321 (define_insn_reservation "W12" 6
322 (and (eq_attr "type" "store_fpload")
323 (eq_attr "cpu" "700"))
326 (define_insn_reservation "W13" 1
327 (and (eq_attr "type" "!fpcc,fpalu,fpmulsgl,fpmuldbl,fpdivsgl,fpdivdbl,fpsqrtsgl,fpsqrtdbl,load,fpload,store,fpstore,fpstore_load,store_fpload")
328 (eq_attr "cpu" "700"))
331 ;; We have a bypass for all computations in the FP unit which feed an
332 ;; FP store as long as the sizes are the same.
333 (define_bypass 2 "W1,W2" "W10,W11" "pa_fpstore_bypass_p")
334 (define_bypass 9 "W3" "W10,W11" "pa_fpstore_bypass_p")
335 (define_bypass 11 "W4" "W10,W11" "pa_fpstore_bypass_p")
336 (define_bypass 13 "W5" "W10,W11" "pa_fpstore_bypass_p")
337 (define_bypass 17 "W6" "W10,W11" "pa_fpstore_bypass_p")
339 ;; We have an "anti-bypass" for FP loads which feed an FP store.
340 (define_bypass 4 "W8,W12" "W10,W11" "pa_fpstore_bypass_p")
342 ;; Function units for the 7100 and 7150. The 7100/7150 can dual-issue
343 ;; floating point computations with non-floating point computations (fp loads
344 ;; and stores are not fp computations).
346 ;; Memory. Disregarding Cache misses, memory loads take two cycles; stores also
347 ;; take two cycles, during which no Dcache operations should be scheduled.
348 ;; Any special cases are handled in pa_adjust_cost. The 7100, 7150 and 7100LC
349 ;; all have the same memory characteristics if one disregards cache misses.
351 ;; The 7100/7150 has three floating-point units: ALU, MUL, and DIV.
352 ;; There's no value in modeling the ALU and MUL separately though
353 ;; since there can never be a functional unit conflict given the
354 ;; latency and issue rates for those units.
357 ;; Instruction Time Unit Minimum Distance (unit contention)
364 ;; fmpyadd 2 ALU,MPY 1
365 ;; fmpysub 2 ALU,MPY 1
366 ;; fmpycfxt 2 ALU,MPY 1
370 ;; fdiv,dbl 15 DIV 15
372 ;; fsqrt,dbl 15 DIV 15
374 (define_automaton "pa7100")
375 (define_cpu_unit "i_7100, f_7100,fpmac_7100,fpdivsqrt_7100,mem_7100" "pa7100")
377 (define_insn_reservation "X0" 2
378 (and (eq_attr "type" "fpcc,fpalu,fpmulsgl,fpmuldbl")
379 (eq_attr "cpu" "7100"))
382 (define_insn_reservation "X1" 8
383 (and (eq_attr "type" "fpdivsgl,fpsqrtsgl")
384 (eq_attr "cpu" "7100"))
385 "f_7100+fpdivsqrt_7100,fpdivsqrt_7100*7")
387 (define_insn_reservation "X2" 15
388 (and (eq_attr "type" "fpdivdbl,fpsqrtdbl")
389 (eq_attr "cpu" "7100"))
390 "f_7100+fpdivsqrt_7100,fpdivsqrt_7100*14")
392 (define_insn_reservation "X3" 2
393 (and (eq_attr "type" "load")
394 (eq_attr "cpu" "7100"))
397 (define_insn_reservation "X4" 2
398 (and (eq_attr "type" "fpload")
399 (eq_attr "cpu" "7100"))
402 (define_insn_reservation "X5" 2
403 (and (eq_attr "type" "store")
404 (eq_attr "cpu" "7100"))
405 "i_7100+mem_7100,mem_7100")
407 (define_insn_reservation "X6" 2
408 (and (eq_attr "type" "fpstore")
409 (eq_attr "cpu" "7100"))
410 "i_7100+mem_7100,mem_7100")
412 (define_insn_reservation "X7" 4
413 (and (eq_attr "type" "fpstore_load")
414 (eq_attr "cpu" "7100"))
415 "i_7100+mem_7100,mem_7100*3")
417 (define_insn_reservation "X8" 4
418 (and (eq_attr "type" "store_fpload")
419 (eq_attr "cpu" "7100"))
420 "i_7100+mem_7100,mem_7100*3")
422 (define_insn_reservation "X9" 1
423 (and (eq_attr "type" "!fpcc,fpalu,fpmulsgl,fpmuldbl,fpdivsgl,fpsqrtsgl,fpdivdbl,fpsqrtdbl,load,fpload,store,fpstore,fpstore_load,store_fpload")
424 (eq_attr "cpu" "7100"))
427 ;; We have a bypass for all computations in the FP unit which feed an
428 ;; FP store as long as the sizes are the same.
429 (define_bypass 1 "X0" "X6,X7" "pa_fpstore_bypass_p")
430 (define_bypass 7 "X1" "X6,X7" "pa_fpstore_bypass_p")
431 (define_bypass 14 "X2" "X6,X7" "pa_fpstore_bypass_p")
433 ;; We have an "anti-bypass" for FP loads which feed an FP store.
434 (define_bypass 3 "X4,X8" "X6,X7" "pa_fpstore_bypass_p")
436 ;; The 7100LC has three floating-point units: ALU, MUL, and DIV.
437 ;; There's no value in modeling the ALU and MUL separately though
438 ;; since there can never be a functional unit conflict that
439 ;; can be avoided given the latency, issue rates and mandatory
440 ;; one cycle cpu-wide lock for a double precision fp multiply.
443 ;; Instruction Time Unit Minimum Distance (unit contention)
450 ;; fmpyadd,sgl 2 ALU,MPY 1
451 ;; fmpyadd,dbl 3 ALU,MPY 2
452 ;; fmpysub,sgl 2 ALU,MPY 1
453 ;; fmpysub,dbl 3 ALU,MPY 2
454 ;; fmpycfxt,sgl 2 ALU,MPY 1
455 ;; fmpycfxt,dbl 3 ALU,MPY 2
460 ;; fdiv,dbl 15 DIV 15
462 ;; fsqrt,dbl 15 DIV 15
464 ;; The PA7200 is just like the PA7100LC except that there is
465 ;; no store-store penalty.
467 ;; The PA7300 is just like the PA7200 except that there is
468 ;; no store-load penalty.
470 ;; Note there are some aspects of the 7100LC we are not modeling
471 ;; at the moment. I'll be reviewing the 7100LC scheduling info
472 ;; shortly and updating this description.
476 ;; other issue modeling
478 (define_automaton "pa7100lc")
479 (define_cpu_unit "i0_7100lc, i1_7100lc, f_7100lc" "pa7100lc")
480 (define_cpu_unit "fpmac_7100lc" "pa7100lc")
481 (define_cpu_unit "mem_7100lc" "pa7100lc")
483 ;; Double precision multiplies lock the entire CPU for one
484 ;; cycle. There is no way to avoid this lock and trying to
485 ;; schedule around the lock is pointless and thus there is no
486 ;; value in trying to model this lock.
488 ;; Not modeling the lock allows us to treat fp multiplies just
489 ;; like any other FP alu instruction. It allows for a smaller
490 ;; DFA and may reduce register pressure.
491 (define_insn_reservation "Y0" 2
492 (and (eq_attr "type" "fpcc,fpalu,fpmulsgl,fpmuldbl")
493 (eq_attr "cpu" "7100LC,7200,7300"))
494 "f_7100lc,fpmac_7100lc")
496 ;; fp division and sqrt instructions lock the entire CPU for
497 ;; 7 cycles (single precision) or 14 cycles (double precision).
498 ;; There is no way to avoid this lock and trying to schedule
499 ;; around the lock is pointless and thus there is no value in
500 ;; trying to model this lock. Not modeling the lock allows
501 ;; for a smaller DFA and may reduce register pressure.
502 (define_insn_reservation "Y1" 1
503 (and (eq_attr "type" "fpdivsgl,fpsqrtsgl,fpdivdbl,fpsqrtdbl")
504 (eq_attr "cpu" "7100LC,7200,7300"))
507 (define_insn_reservation "Y2" 2
508 (and (eq_attr "type" "load")
509 (eq_attr "cpu" "7100LC,7200,7300"))
510 "i1_7100lc+mem_7100lc")
512 (define_insn_reservation "Y3" 2
513 (and (eq_attr "type" "fpload")
514 (eq_attr "cpu" "7100LC,7200,7300"))
515 "i1_7100lc+mem_7100lc")
517 (define_insn_reservation "Y4" 2
518 (and (eq_attr "type" "store")
519 (eq_attr "cpu" "7100LC"))
520 "i1_7100lc+mem_7100lc,mem_7100lc")
522 (define_insn_reservation "Y5" 2
523 (and (eq_attr "type" "fpstore")
524 (eq_attr "cpu" "7100LC"))
525 "i1_7100lc+mem_7100lc,mem_7100lc")
527 (define_insn_reservation "Y6" 4
528 (and (eq_attr "type" "fpstore_load")
529 (eq_attr "cpu" "7100LC"))
530 "i1_7100lc+mem_7100lc,mem_7100lc*3")
532 (define_insn_reservation "Y7" 4
533 (and (eq_attr "type" "store_fpload")
534 (eq_attr "cpu" "7100LC"))
535 "i1_7100lc+mem_7100lc,mem_7100lc*3")
537 (define_insn_reservation "Y8" 1
538 (and (eq_attr "type" "shift,nullshift")
539 (eq_attr "cpu" "7100LC,7200,7300"))
542 (define_insn_reservation "Y9" 1
543 (and (eq_attr "type" "!fpcc,fpalu,fpmulsgl,fpmuldbl,fpdivsgl,fpsqrtsgl,fpdivdbl,fpsqrtdbl,load,fpload,store,fpstore,shift,nullshift")
544 (eq_attr "cpu" "7100LC,7200,7300"))
545 "(i0_7100lc|i1_7100lc)")
547 ;; The 7200 has a store-load penalty
548 (define_insn_reservation "Y10" 2
549 (and (eq_attr "type" "store")
550 (eq_attr "cpu" "7200"))
551 "i1_7100lc,mem_7100lc")
553 (define_insn_reservation "Y11" 2
554 (and (eq_attr "type" "fpstore")
555 (eq_attr "cpu" "7200"))
556 "i1_7100lc,mem_7100lc")
558 (define_insn_reservation "Y12" 4
559 (and (eq_attr "type" "fpstore_load")
560 (eq_attr "cpu" "7200"))
561 "i1_7100lc,mem_7100lc,i1_7100lc+mem_7100lc")
563 (define_insn_reservation "Y13" 4
564 (and (eq_attr "type" "store_fpload")
565 (eq_attr "cpu" "7200"))
566 "i1_7100lc,mem_7100lc,i1_7100lc+mem_7100lc")
568 ;; The 7300 has no penalty for store-store or store-load
569 (define_insn_reservation "Y14" 2
570 (and (eq_attr "type" "store")
571 (eq_attr "cpu" "7300"))
574 (define_insn_reservation "Y15" 2
575 (and (eq_attr "type" "fpstore")
576 (eq_attr "cpu" "7300"))
579 (define_insn_reservation "Y16" 4
580 (and (eq_attr "type" "fpstore_load")
581 (eq_attr "cpu" "7300"))
582 "i1_7100lc,i1_7100lc+mem_7100lc")
584 (define_insn_reservation "Y17" 4
585 (and (eq_attr "type" "store_fpload")
586 (eq_attr "cpu" "7300"))
587 "i1_7100lc,i1_7100lc+mem_7100lc")
589 ;; We have an "anti-bypass" for FP loads which feed an FP store.
590 (define_bypass 3 "Y3,Y7,Y13,Y17" "Y5,Y6,Y11,Y12,Y15,Y16" "pa_fpstore_bypass_p")
592 ;; Scheduling for the PA8000 is somewhat different than scheduling for a
593 ;; traditional architecture.
595 ;; The PA8000 has a large (56) entry reorder buffer that is split between
596 ;; memory and non-memory operations.
598 ;; The PA8000 can issue two memory and two non-memory operations per cycle to
599 ;; the function units, with the exception of branches and multi-output
600 ;; instructions. The PA8000 can retire two non-memory operations per cycle
601 ;; and two memory operations per cycle, only one of which may be a store.
603 ;; Given the large reorder buffer, the processor can hide most latencies.
604 ;; According to HP, they've got the best results by scheduling for retirement
605 ;; bandwidth with limited latency scheduling for floating point operations.
606 ;; Latency for integer operations and memory references is ignored.
609 ;; We claim floating point operations have a 2 cycle latency and are
610 ;; fully pipelined, except for div and sqrt which are not pipelined and
611 ;; take from 17 to 31 cycles to complete.
613 ;; It's worth noting that there is no way to saturate all the functional
614 ;; units on the PA8000 as there is not enough issue bandwidth.
616 (define_automaton "pa8000")
617 (define_cpu_unit "inm0_8000, inm1_8000, im0_8000, im1_8000" "pa8000")
618 (define_cpu_unit "rnm0_8000, rnm1_8000, rm0_8000, rm1_8000" "pa8000")
619 (define_cpu_unit "store_8000" "pa8000")
620 (define_cpu_unit "f0_8000, f1_8000" "pa8000")
621 (define_cpu_unit "fdivsqrt0_8000, fdivsqrt1_8000" "pa8000")
622 (define_reservation "inm_8000" "inm0_8000 | inm1_8000")
623 (define_reservation "im_8000" "im0_8000 | im1_8000")
624 (define_reservation "rnm_8000" "rnm0_8000 | rnm1_8000")
625 (define_reservation "rm_8000" "rm0_8000 | rm1_8000")
626 (define_reservation "f_8000" "f0_8000 | f1_8000")
627 (define_reservation "fdivsqrt_8000" "fdivsqrt0_8000 | fdivsqrt1_8000")
629 ;; We can issue any two memops per cycle, but we can only retire
630 ;; one memory store per cycle. We assume that the reorder buffer
631 ;; will hide any memory latencies per HP's recommendation.
632 (define_insn_reservation "Z0" 0
634 (eq_attr "type" "load,fpload")
635 (eq_attr "cpu" "8000"))
638 (define_insn_reservation "Z1" 0
640 (eq_attr "type" "store,fpstore")
641 (eq_attr "cpu" "8000"))
642 "im_8000,rm_8000+store_8000")
644 (define_insn_reservation "Z2" 0
645 (and (eq_attr "type" "fpstore_load,store_fpload")
646 (eq_attr "cpu" "8000"))
647 "im_8000,rm_8000+store_8000,im_8000,rm_8000")
649 ;; We can issue and retire two non-memory operations per cycle with
650 ;; a few exceptions (branches). This group catches those we want
651 ;; to assume have zero latency.
652 (define_insn_reservation "Z3" 0
654 (eq_attr "type" "!load,fpload,store,fpstore,uncond_branch,branch,cbranch,fbranch,call,sibcall,dyncall,multi,milli,sh_func_adrs,parallel_branch,fpcc,fpalu,fpmulsgl,fpmuldbl,fpsqrtsgl,fpsqrtdbl,fpdivsgl,fpdivdbl,fpstore_load,store_fpload")
655 (eq_attr "cpu" "8000"))
658 ;; Branches use both slots in the non-memory issue and
660 (define_insn_reservation "Z4" 0
662 (eq_attr "type" "uncond_branch,branch,cbranch,fbranch,call,sibcall,dyncall,multi,milli,sh_func_adrs,parallel_branch")
663 (eq_attr "cpu" "8000"))
664 "inm0_8000+inm1_8000,rnm0_8000+rnm1_8000")
666 ;; We partial latency schedule the floating point units.
667 ;; They can issue/retire two at a time in the non-memory
668 ;; units. We fix their latency at 2 cycles and they
669 ;; are fully pipelined.
670 (define_insn_reservation "Z5" 1
672 (eq_attr "type" "fpcc,fpalu,fpmulsgl,fpmuldbl")
673 (eq_attr "cpu" "8000"))
674 "inm_8000,f_8000,rnm_8000")
676 ;; The fdivsqrt units are not pipelined and have a very long latency.
677 ;; To keep the DFA from exploding, we do not show all the
678 ;; reservations for the divsqrt unit.
679 (define_insn_reservation "Z6" 17
681 (eq_attr "type" "fpdivsgl,fpsqrtsgl")
682 (eq_attr "cpu" "8000"))
683 "inm_8000,fdivsqrt_8000*6,rnm_8000")
685 (define_insn_reservation "Z7" 31
687 (eq_attr "type" "fpdivdbl,fpsqrtdbl")
688 (eq_attr "cpu" "8000"))
689 "inm_8000,fdivsqrt_8000*6,rnm_8000")
691 ;; Operand and operator predicates and constraints
693 (include "predicates.md")
694 (include "constraints.md")
696 ;; Compare instructions.
697 ;; This controls RTL generation and register allocation.
701 (match_operator:CCFP 2 "comparison_operator"
702 [(match_operand:SF 0 "reg_or_0_operand" "fG")
703 (match_operand:SF 1 "reg_or_0_operand" "fG")]))]
704 "! TARGET_SOFT_FLOAT"
705 "fcmp,sgl,%Y2 %f0,%f1"
706 [(set_attr "length" "4")
707 (set_attr "type" "fpcc")])
711 (match_operator:CCFP 2 "comparison_operator"
712 [(match_operand:DF 0 "reg_or_0_operand" "fG")
713 (match_operand:DF 1 "reg_or_0_operand" "fG")]))]
714 "! TARGET_SOFT_FLOAT"
715 "fcmp,dbl,%Y2 %f0,%f1"
716 [(set_attr "length" "4")
717 (set_attr "type" "fpcc")])
719 ;; Provide a means to emit the movccfp0 and movccfp1 optimization
720 ;; placeholders. This is necessary in rare situations when a
721 ;; placeholder is re-emitted (see PR 8705).
723 (define_expand "movccfp"
725 (match_operand 0 "const_int_operand" ""))]
726 "! TARGET_SOFT_FLOAT"
729 if ((unsigned HOST_WIDE_INT) INTVAL (operands[0]) > 1)
733 ;; The following patterns are optimization placeholders. In almost
734 ;; all cases, the user of the condition code will be simplified and the
735 ;; original condition code setting insn should be eliminated.
737 (define_insn "*movccfp0"
740 "! TARGET_SOFT_FLOAT"
741 "fcmp,dbl,= %%fr0,%%fr0"
742 [(set_attr "length" "4")
743 (set_attr "type" "fpcc")])
745 (define_insn "*movccfp1"
748 "! TARGET_SOFT_FLOAT"
749 "fcmp,dbl,!= %%fr0,%%fr0"
750 [(set_attr "length" "4")
751 (set_attr "type" "fpcc")])
755 (define_expand "cstoresi4"
756 [(set (match_operand:SI 0 "register_operand")
757 (match_operator:SI 1 "ordered_comparison_operator"
758 [(match_operand:SI 2 "reg_or_0_operand" "")
759 (match_operand:SI 3 "arith5_operand" "")]))]
763 ;; Instruction canonicalization puts immediate operands second, which
764 ;; is the reverse of what we want.
767 [(set (match_operand:SI 0 "register_operand" "=r")
768 (match_operator:SI 3 "ordered_comparison_operator"
769 [(match_operand:SI 1 "reg_or_0_operand" "rM")
770 (match_operand:SI 2 "arith11_operand" "rI")]))]
772 "{com%I2clr|cmp%I2clr},%B3 %2,%r1,%0\;ldi 1,%0"
773 [(set_attr "type" "binary")
774 (set_attr "length" "8")])
777 [(set (match_operand:DI 0 "register_operand" "=r")
778 (match_operator:DI 3 "ordered_comparison_operator"
779 [(match_operand:DI 1 "reg_or_0_operand" "rM")
780 (match_operand:DI 2 "arith11_operand" "rI")]))]
782 "cmp%I2clr,*%B3 %2,%r1,%0\;ldi 1,%0"
783 [(set_attr "type" "binary")
784 (set_attr "length" "8")])
786 (define_insn "iorscc"
787 [(set (match_operand:SI 0 "register_operand" "=r")
788 (ior:SI (match_operator:SI 3 "ordered_comparison_operator"
789 [(match_operand:SI 1 "reg_or_0_operand" "rM")
790 (match_operand:SI 2 "arith11_operand" "rI")])
791 (match_operator:SI 6 "ordered_comparison_operator"
792 [(match_operand:SI 4 "reg_or_0_operand" "rM")
793 (match_operand:SI 5 "arith11_operand" "rI")])))]
795 "{com%I2clr|cmp%I2clr},%S3 %2,%r1,%%r0\;{com%I5clr|cmp%I5clr},%B6 %5,%r4,%0\;ldi 1,%0"
796 [(set_attr "type" "binary")
797 (set_attr "length" "12")])
800 [(set (match_operand:DI 0 "register_operand" "=r")
801 (ior:DI (match_operator:DI 3 "ordered_comparison_operator"
802 [(match_operand:DI 1 "reg_or_0_operand" "rM")
803 (match_operand:DI 2 "arith11_operand" "rI")])
804 (match_operator:DI 6 "ordered_comparison_operator"
805 [(match_operand:DI 4 "reg_or_0_operand" "rM")
806 (match_operand:DI 5 "arith11_operand" "rI")])))]
808 "cmp%I2clr,*%S3 %2,%r1,%%r0\;cmp%I5clr,*%B6 %5,%r4,%0\;ldi 1,%0"
809 [(set_attr "type" "binary")
810 (set_attr "length" "12")])
812 ;; Combiner patterns for common operations performed with the output
813 ;; from an scc insn (negscc and incscc).
814 (define_insn "negscc"
815 [(set (match_operand:SI 0 "register_operand" "=r")
816 (neg:SI (match_operator:SI 3 "ordered_comparison_operator"
817 [(match_operand:SI 1 "reg_or_0_operand" "rM")
818 (match_operand:SI 2 "arith11_operand" "rI")])))]
820 "{com%I2clr|cmp%I2clr},%B3 %2,%r1,%0\;ldi -1,%0"
821 [(set_attr "type" "binary")
822 (set_attr "length" "8")])
825 [(set (match_operand:DI 0 "register_operand" "=r")
826 (neg:DI (match_operator:DI 3 "ordered_comparison_operator"
827 [(match_operand:DI 1 "reg_or_0_operand" "rM")
828 (match_operand:DI 2 "arith11_operand" "rI")])))]
830 "cmp%I2clr,*%B3 %2,%r1,%0\;ldi -1,%0"
831 [(set_attr "type" "binary")
832 (set_attr "length" "8")])
834 ;; Patterns for adding/subtracting the result of a boolean expression from
835 ;; a register. First we have special patterns that make use of the carry
836 ;; bit, and output only two instructions. For the cases we can't in
837 ;; general do in two instructions, the incscc pattern at the end outputs
838 ;; two or three instructions.
841 [(set (match_operand:SI 0 "register_operand" "=r")
842 (plus:SI (leu:SI (match_operand:SI 2 "register_operand" "r")
843 (match_operand:SI 3 "arith11_operand" "rI"))
844 (match_operand:SI 1 "register_operand" "r")))]
846 "sub%I3 %3,%2,%%r0\;{addc|add,c} %%r0,%1,%0"
847 [(set_attr "type" "binary")
848 (set_attr "length" "8")])
851 [(set (match_operand:DI 0 "register_operand" "=r")
852 (plus:DI (leu:DI (match_operand:DI 2 "register_operand" "r")
853 (match_operand:DI 3 "arith11_operand" "rI"))
854 (match_operand:DI 1 "register_operand" "r")))]
856 "sub%I3 %3,%2,%%r0\;add,dc %%r0,%1,%0"
857 [(set_attr "type" "binary")
858 (set_attr "length" "8")])
860 ; This need only accept registers for op3, since canonicalization
861 ; replaces geu with gtu when op3 is an integer.
863 [(set (match_operand:SI 0 "register_operand" "=r")
864 (plus:SI (geu:SI (match_operand:SI 2 "register_operand" "r")
865 (match_operand:SI 3 "register_operand" "r"))
866 (match_operand:SI 1 "register_operand" "r")))]
868 "sub %2,%3,%%r0\;{addc|add,c} %%r0,%1,%0"
869 [(set_attr "type" "binary")
870 (set_attr "length" "8")])
873 [(set (match_operand:DI 0 "register_operand" "=r")
874 (plus:DI (geu:DI (match_operand:DI 2 "register_operand" "r")
875 (match_operand:DI 3 "register_operand" "r"))
876 (match_operand:DI 1 "register_operand" "r")))]
878 "sub %2,%3,%%r0\;add,dc %%r0,%1,%0"
879 [(set_attr "type" "binary")
880 (set_attr "length" "8")])
882 ; Match only integers for op3 here. This is used as canonical form of the
883 ; geu pattern when op3 is an integer. Don't match registers since we can't
884 ; make better code than the general incscc pattern.
886 [(set (match_operand:SI 0 "register_operand" "=r")
887 (plus:SI (gtu:SI (match_operand:SI 2 "register_operand" "r")
888 (match_operand:SI 3 "int11_operand" "I"))
889 (match_operand:SI 1 "register_operand" "r")))]
891 "addi %k3,%2,%%r0\;{addc|add,c} %%r0,%1,%0"
892 [(set_attr "type" "binary")
893 (set_attr "length" "8")])
896 [(set (match_operand:DI 0 "register_operand" "=r")
897 (plus:DI (gtu:DI (match_operand:DI 2 "register_operand" "r")
898 (match_operand:DI 3 "int11_operand" "I"))
899 (match_operand:DI 1 "register_operand" "r")))]
901 "addi %k3,%2,%%r0\;add,dc %%r0,%1,%0"
902 [(set_attr "type" "binary")
903 (set_attr "length" "8")])
905 (define_insn "incscc"
906 [(set (match_operand:SI 0 "register_operand" "=r,r")
907 (plus:SI (match_operator:SI 4 "ordered_comparison_operator"
908 [(match_operand:SI 2 "register_operand" "r,r")
909 (match_operand:SI 3 "arith11_operand" "rI,rI")])
910 (match_operand:SI 1 "register_operand" "0,?r")))]
913 {com%I3clr|cmp%I3clr},%B4 %3,%2,%%r0\;addi 1,%0,%0
914 {com%I3clr|cmp%I3clr},%B4 %3,%2,%%r0\;addi,tr 1,%1,%0\;copy %1,%0"
915 [(set_attr "type" "binary,binary")
916 (set_attr "length" "8,12")])
919 [(set (match_operand:DI 0 "register_operand" "=r,r")
920 (plus:DI (match_operator:DI 4 "ordered_comparison_operator"
921 [(match_operand:DI 2 "register_operand" "r,r")
922 (match_operand:DI 3 "arith11_operand" "rI,rI")])
923 (match_operand:DI 1 "register_operand" "0,?r")))]
926 cmp%I3clr,*%B4 %3,%2,%%r0\;addi 1,%0,%0
927 cmp%I3clr,*%B4 %3,%2,%%r0\;addi,tr 1,%1,%0\;copy %1,%0"
928 [(set_attr "type" "binary,binary")
929 (set_attr "length" "8,12")])
932 [(set (match_operand:SI 0 "register_operand" "=r")
933 (minus:SI (match_operand:SI 1 "register_operand" "r")
934 (gtu:SI (match_operand:SI 2 "register_operand" "r")
935 (match_operand:SI 3 "arith11_operand" "rI"))))]
937 "sub%I3 %3,%2,%%r0\;{subb|sub,b} %1,%%r0,%0"
938 [(set_attr "type" "binary")
939 (set_attr "length" "8")])
942 [(set (match_operand:DI 0 "register_operand" "=r")
943 (minus:DI (match_operand:DI 1 "register_operand" "r")
944 (gtu:DI (match_operand:DI 2 "register_operand" "r")
945 (match_operand:DI 3 "arith11_operand" "rI"))))]
947 "sub%I3 %3,%2,%%r0\;sub,db %1,%%r0,%0"
948 [(set_attr "type" "binary")
949 (set_attr "length" "8")])
952 [(set (match_operand:SI 0 "register_operand" "=r")
953 (minus:SI (minus:SI (match_operand:SI 1 "register_operand" "r")
954 (gtu:SI (match_operand:SI 2 "register_operand" "r")
955 (match_operand:SI 3 "arith11_operand" "rI")))
956 (match_operand:SI 4 "register_operand" "r")))]
958 "sub%I3 %3,%2,%%r0\;{subb|sub,b} %1,%4,%0"
959 [(set_attr "type" "binary")
960 (set_attr "length" "8")])
963 [(set (match_operand:DI 0 "register_operand" "=r")
964 (minus:DI (minus:DI (match_operand:DI 1 "register_operand" "r")
965 (gtu:DI (match_operand:DI 2 "register_operand" "r")
966 (match_operand:DI 3 "arith11_operand" "rI")))
967 (match_operand:DI 4 "register_operand" "r")))]
969 "sub%I3 %3,%2,%%r0\;sub,db %1,%4,%0"
970 [(set_attr "type" "binary")
971 (set_attr "length" "8")])
973 ; This need only accept registers for op3, since canonicalization
974 ; replaces ltu with leu when op3 is an integer.
976 [(set (match_operand:SI 0 "register_operand" "=r")
977 (minus:SI (match_operand:SI 1 "register_operand" "r")
978 (ltu:SI (match_operand:SI 2 "register_operand" "r")
979 (match_operand:SI 3 "register_operand" "r"))))]
981 "sub %2,%3,%%r0\;{subb|sub,b} %1,%%r0,%0"
982 [(set_attr "type" "binary")
983 (set_attr "length" "8")])
986 [(set (match_operand:DI 0 "register_operand" "=r")
987 (minus:DI (match_operand:DI 1 "register_operand" "r")
988 (ltu:DI (match_operand:DI 2 "register_operand" "r")
989 (match_operand:DI 3 "register_operand" "r"))))]
991 "sub %2,%3,%%r0\;sub,db %1,%%r0,%0"
992 [(set_attr "type" "binary")
993 (set_attr "length" "8")])
996 [(set (match_operand:SI 0 "register_operand" "=r")
997 (minus:SI (minus:SI (match_operand:SI 1 "register_operand" "r")
998 (ltu:SI (match_operand:SI 2 "register_operand" "r")
999 (match_operand:SI 3 "register_operand" "r")))
1000 (match_operand:SI 4 "register_operand" "r")))]
1002 "sub %2,%3,%%r0\;{subb|sub,b} %1,%4,%0"
1003 [(set_attr "type" "binary")
1004 (set_attr "length" "8")])
1007 [(set (match_operand:DI 0 "register_operand" "=r")
1008 (minus:DI (minus:DI (match_operand:DI 1 "register_operand" "r")
1009 (ltu:DI (match_operand:DI 2 "register_operand" "r")
1010 (match_operand:DI 3 "register_operand" "r")))
1011 (match_operand:DI 4 "register_operand" "r")))]
1013 "sub %2,%3,%%r0\;sub,db %1,%4,%0"
1014 [(set_attr "type" "binary")
1015 (set_attr "length" "8")])
1017 ; Match only integers for op3 here. This is used as canonical form of the
1018 ; ltu pattern when op3 is an integer. Don't match registers since we can't
1019 ; make better code than the general incscc pattern.
1021 [(set (match_operand:SI 0 "register_operand" "=r")
1022 (minus:SI (match_operand:SI 1 "register_operand" "r")
1023 (leu:SI (match_operand:SI 2 "register_operand" "r")
1024 (match_operand:SI 3 "int11_operand" "I"))))]
1026 "addi %k3,%2,%%r0\;{subb|sub,b} %1,%%r0,%0"
1027 [(set_attr "type" "binary")
1028 (set_attr "length" "8")])
1031 [(set (match_operand:DI 0 "register_operand" "=r")
1032 (minus:DI (match_operand:DI 1 "register_operand" "r")
1033 (leu:DI (match_operand:DI 2 "register_operand" "r")
1034 (match_operand:DI 3 "int11_operand" "I"))))]
1036 "addi %k3,%2,%%r0\;sub,db %1,%%r0,%0"
1037 [(set_attr "type" "binary")
1038 (set_attr "length" "8")])
1041 [(set (match_operand:SI 0 "register_operand" "=r")
1042 (minus:SI (minus:SI (match_operand:SI 1 "register_operand" "r")
1043 (leu:SI (match_operand:SI 2 "register_operand" "r")
1044 (match_operand:SI 3 "int11_operand" "I")))
1045 (match_operand:SI 4 "register_operand" "r")))]
1047 "addi %k3,%2,%%r0\;{subb|sub,b} %1,%4,%0"
1048 [(set_attr "type" "binary")
1049 (set_attr "length" "8")])
1052 [(set (match_operand:DI 0 "register_operand" "=r")
1053 (minus:DI (minus:DI (match_operand:DI 1 "register_operand" "r")
1054 (leu:DI (match_operand:DI 2 "register_operand" "r")
1055 (match_operand:DI 3 "int11_operand" "I")))
1056 (match_operand:DI 4 "register_operand" "r")))]
1058 "addi %k3,%2,%%r0\;sub,db %1,%4,%0"
1059 [(set_attr "type" "binary")
1060 (set_attr "length" "8")])
1062 (define_insn "decscc"
1063 [(set (match_operand:SI 0 "register_operand" "=r,r")
1064 (minus:SI (match_operand:SI 1 "register_operand" "0,?r")
1065 (match_operator:SI 4 "ordered_comparison_operator"
1066 [(match_operand:SI 2 "register_operand" "r,r")
1067 (match_operand:SI 3 "arith11_operand" "rI,rI")])))]
1070 {com%I3clr|cmp%I3clr},%B4 %3,%2,%%r0\;addi -1,%0,%0
1071 {com%I3clr|cmp%I3clr},%B4 %3,%2,%%r0\;addi,tr -1,%1,%0\;copy %1,%0"
1072 [(set_attr "type" "binary,binary")
1073 (set_attr "length" "8,12")])
1076 [(set (match_operand:DI 0 "register_operand" "=r,r")
1077 (minus:DI (match_operand:DI 1 "register_operand" "0,?r")
1078 (match_operator:DI 4 "ordered_comparison_operator"
1079 [(match_operand:DI 2 "register_operand" "r,r")
1080 (match_operand:DI 3 "arith11_operand" "rI,rI")])))]
1083 cmp%I3clr,*%B4 %3,%2,%%r0\;addi -1,%0,%0
1084 cmp%I3clr,*%B4 %3,%2,%%r0\;addi,tr -1,%1,%0\;copy %1,%0"
1085 [(set_attr "type" "binary,binary")
1086 (set_attr "length" "8,12")])
1088 ; Patterns for max and min. (There is no need for an earlyclobber in the
1089 ; last alternative since the middle alternative will match if op0 == op1.)
1091 (define_insn "sminsi3"
1092 [(set (match_operand:SI 0 "register_operand" "=r,r,r")
1093 (smin:SI (match_operand:SI 1 "register_operand" "%0,0,r")
1094 (match_operand:SI 2 "arith11_operand" "r,I,M")))]
1097 {comclr|cmpclr},> %2,%0,%%r0\;copy %2,%0
1098 {comiclr|cmpiclr},> %2,%0,%%r0\;ldi %2,%0
1099 {comclr|cmpclr},> %1,%r2,%0\;copy %1,%0"
1100 [(set_attr "type" "multi,multi,multi")
1101 (set_attr "length" "8,8,8")])
1103 (define_insn "smindi3"
1104 [(set (match_operand:DI 0 "register_operand" "=r,r,r")
1105 (smin:DI (match_operand:DI 1 "register_operand" "%0,0,r")
1106 (match_operand:DI 2 "arith11_operand" "r,I,M")))]
1109 cmpclr,*> %2,%0,%%r0\;copy %2,%0
1110 cmpiclr,*> %2,%0,%%r0\;ldi %2,%0
1111 cmpclr,*> %1,%r2,%0\;copy %1,%0"
1112 [(set_attr "type" "multi,multi,multi")
1113 (set_attr "length" "8,8,8")])
1115 (define_insn "uminsi3"
1116 [(set (match_operand:SI 0 "register_operand" "=r,r")
1117 (umin:SI (match_operand:SI 1 "register_operand" "%0,0")
1118 (match_operand:SI 2 "arith11_operand" "r,I")))]
1121 {comclr|cmpclr},>> %2,%0,%%r0\;copy %2,%0
1122 {comiclr|cmpiclr},>> %2,%0,%%r0\;ldi %2,%0"
1123 [(set_attr "type" "multi,multi")
1124 (set_attr "length" "8,8")])
1126 (define_insn "umindi3"
1127 [(set (match_operand:DI 0 "register_operand" "=r,r")
1128 (umin:DI (match_operand:DI 1 "register_operand" "%0,0")
1129 (match_operand:DI 2 "arith11_operand" "r,I")))]
1132 cmpclr,*>> %2,%0,%%r0\;copy %2,%0
1133 cmpiclr,*>> %2,%0,%%r0\;ldi %2,%0"
1134 [(set_attr "type" "multi,multi")
1135 (set_attr "length" "8,8")])
1137 (define_insn "smaxsi3"
1138 [(set (match_operand:SI 0 "register_operand" "=r,r,r")
1139 (smax:SI (match_operand:SI 1 "register_operand" "%0,0,r")
1140 (match_operand:SI 2 "arith11_operand" "r,I,M")))]
1143 {comclr|cmpclr},< %2,%0,%%r0\;copy %2,%0
1144 {comiclr|cmpiclr},< %2,%0,%%r0\;ldi %2,%0
1145 {comclr|cmpclr},< %1,%r2,%0\;copy %1,%0"
1146 [(set_attr "type" "multi,multi,multi")
1147 (set_attr "length" "8,8,8")])
1149 (define_insn "smaxdi3"
1150 [(set (match_operand:DI 0 "register_operand" "=r,r,r")
1151 (smax:DI (match_operand:DI 1 "register_operand" "%0,0,r")
1152 (match_operand:DI 2 "arith11_operand" "r,I,M")))]
1155 cmpclr,*< %2,%0,%%r0\;copy %2,%0
1156 cmpiclr,*< %2,%0,%%r0\;ldi %2,%0
1157 cmpclr,*< %1,%r2,%0\;copy %1,%0"
1158 [(set_attr "type" "multi,multi,multi")
1159 (set_attr "length" "8,8,8")])
1161 (define_insn "umaxsi3"
1162 [(set (match_operand:SI 0 "register_operand" "=r,r")
1163 (umax:SI (match_operand:SI 1 "register_operand" "%0,0")
1164 (match_operand:SI 2 "arith11_operand" "r,I")))]
1167 {comclr|cmpclr},<< %2,%0,%%r0\;copy %2,%0
1168 {comiclr|cmpiclr},<< %2,%0,%%r0\;ldi %2,%0"
1169 [(set_attr "type" "multi,multi")
1170 (set_attr "length" "8,8")])
1172 (define_insn "umaxdi3"
1173 [(set (match_operand:DI 0 "register_operand" "=r,r")
1174 (umax:DI (match_operand:DI 1 "register_operand" "%0,0")
1175 (match_operand:DI 2 "arith11_operand" "r,I")))]
1178 cmpclr,*<< %2,%0,%%r0\;copy %2,%0
1179 cmpiclr,*<< %2,%0,%%r0\;ldi %2,%0"
1180 [(set_attr "type" "multi,multi")
1181 (set_attr "length" "8,8")])
1183 (define_insn "absqi2"
1184 [(set (match_operand:QI 0 "register_operand" "=r")
1185 (abs:QI (match_operand:QI 1 "register_operand" "r")))]
1187 "{extrs|extrw,s},>= %1,31,8,%0\;subi 0,%0,%0"
1188 [(set_attr "type" "multi")
1189 (set_attr "length" "8")])
1191 (define_insn "abshi2"
1192 [(set (match_operand:HI 0 "register_operand" "=r")
1193 (abs:HI (match_operand:HI 1 "register_operand" "r")))]
1195 "{extrs|extrw,s},>= %1,31,16,%0\;subi 0,%0,%0"
1196 [(set_attr "type" "multi")
1197 (set_attr "length" "8")])
1199 (define_insn "abssi2"
1200 [(set (match_operand:SI 0 "register_operand" "=r")
1201 (abs:SI (match_operand:SI 1 "register_operand" "r")))]
1203 "or,>= %%r0,%1,%0\;subi 0,%0,%0"
1204 [(set_attr "type" "multi")
1205 (set_attr "length" "8")])
1207 (define_insn "absdi2"
1208 [(set (match_operand:DI 0 "register_operand" "=r")
1209 (abs:DI (match_operand:DI 1 "register_operand" "r")))]
1211 "or,*>= %%r0,%1,%0\;subi 0,%0,%0"
1212 [(set_attr "type" "multi")
1213 (set_attr "length" "8")])
1215 (define_insn "bswaphi2"
1216 [(set (match_operand:HI 0 "register_operand" "=&r")
1217 (bswap:HI (match_operand:HI 1 "register_operand" "r")))]
1219 "{extru|extrw,u} %1,23,8,%0\;{dep|depw} %1,23,8,%0"
1220 [(set_attr "type" "multi")
1221 (set_attr "length" "8")])
1223 (define_insn "bswapsi2"
1224 [(set (match_operand:SI 0 "register_operand" "=&r")
1225 (bswap:SI (match_operand:SI 1 "register_operand" "r")))]
1227 "{shd|shrpw} %1,%1,16,%0\;{dep|depw} %0,15,8,%0\;{shd|shrpw} %1,%0,8,%0"
1228 [(set_attr "type" "multi")
1229 (set_attr "length" "12")])
1231 (define_insn "bswapdi2"
1232 [(set (match_operand:DI 0 "register_operand" "=&r")
1233 (bswap:DI (match_operand:DI 1 "register_operand" "r")))
1234 (clobber (match_scratch:DI 2 "=r"))]
1236 "permh,3210 %1,%2\;hshl %2,8,%0\;hshr,u %2,8,%2\;or %0,%2,%0"
1237 [(set_attr "type" "multi")
1238 (set_attr "length" "16")])
1240 ;;; Experimental conditional move patterns
1242 (define_expand "movsicc"
1243 [(set (match_operand:SI 0 "register_operand" "")
1245 (match_operand 1 "ordered_comparison_operator" "")
1246 (match_operand:SI 2 "reg_or_cint_move_operand" "")
1247 (match_operand:SI 3 "reg_or_cint_move_operand" "")))]
1251 if (GET_MODE (XEXP (operands[1], 0)) != SImode
1252 || GET_MODE (XEXP (operands[1], 0)) != GET_MODE (XEXP (operands[1], 1)))
1256 ;; We used to accept any register for op1.
1258 ;; However, it loses sometimes because the compiler will end up using
1259 ;; different registers for op0 and op1 in some critical cases. local-alloc
1260 ;; will not tie op0 and op1 because op0 is used in multiple basic blocks.
1262 ;; If/when global register allocation supports tying we should allow any
1263 ;; register for op1 again.
1265 [(set (match_operand:SI 0 "register_operand" "=r,r,r,r")
1267 (match_operator 2 "ordered_comparison_operator"
1268 [(match_operand:SI 3 "register_operand" "r,r,r,r")
1269 (match_operand:SI 4 "arith11_operand" "rI,rI,rI,rI")])
1270 (match_operand:SI 1 "reg_or_cint_move_operand" "0,J,N,K")
1274 {com%I4clr|cmp%I4clr},%S2 %4,%3,%%r0\;ldi 0,%0
1275 {com%I4clr|cmp%I4clr},%B2 %4,%3,%0\;ldi %1,%0
1276 {com%I4clr|cmp%I4clr},%B2 %4,%3,%0\;ldil L'%1,%0
1277 {com%I4clr|cmp%I4clr},%B2 %4,%3,%0\;{zdepi|depwi,z} %Z1,%0"
1278 [(set_attr "type" "multi,multi,multi,nullshift")
1279 (set_attr "length" "8,8,8,8")])
1282 [(set (match_operand:SI 0 "register_operand" "=r,r,r,r,r,r,r,r")
1284 (match_operator 5 "ordered_comparison_operator"
1285 [(match_operand:SI 3 "register_operand" "r,r,r,r,r,r,r,r")
1286 (match_operand:SI 4 "arith11_operand" "rI,rI,rI,rI,rI,rI,rI,rI")])
1287 (match_operand:SI 1 "reg_or_cint_move_operand" "0,0,0,0,r,J,N,K")
1288 (match_operand:SI 2 "reg_or_cint_move_operand" "r,J,N,K,0,0,0,0")))]
1291 {com%I4clr|cmp%I4clr},%S5 %4,%3,%%r0\;copy %2,%0
1292 {com%I4clr|cmp%I4clr},%S5 %4,%3,%%r0\;ldi %2,%0
1293 {com%I4clr|cmp%I4clr},%S5 %4,%3,%%r0\;ldil L'%2,%0
1294 {com%I4clr|cmp%I4clr},%S5 %4,%3,%%r0\;{zdepi|depwi,z} %Z2,%0
1295 {com%I4clr|cmp%I4clr},%B5 %4,%3,%%r0\;copy %1,%0
1296 {com%I4clr|cmp%I4clr},%B5 %4,%3,%%r0\;ldi %1,%0
1297 {com%I4clr|cmp%I4clr},%B5 %4,%3,%%r0\;ldil L'%1,%0
1298 {com%I4clr|cmp%I4clr},%B5 %4,%3,%%r0\;{zdepi|depwi,z} %Z1,%0"
1299 [(set_attr "type" "multi,multi,multi,nullshift,multi,multi,multi,nullshift")
1300 (set_attr "length" "8,8,8,8,8,8,8,8")])
1302 (define_expand "movdicc"
1303 [(set (match_operand:DI 0 "register_operand" "")
1305 (match_operand 1 "ordered_comparison_operator" "")
1306 (match_operand:DI 2 "reg_or_cint_move_operand" "")
1307 (match_operand:DI 3 "reg_or_cint_move_operand" "")))]
1311 if (GET_MODE (XEXP (operands[1], 0)) != DImode
1312 || GET_MODE (XEXP (operands[1], 0)) != GET_MODE (XEXP (operands[1], 1)))
1316 ; We need the first constraint alternative in order to avoid
1317 ; earlyclobbers on all other alternatives.
1319 [(set (match_operand:DI 0 "register_operand" "=r,r,r,r,r")
1321 (match_operator 2 "ordered_comparison_operator"
1322 [(match_operand:DI 3 "register_operand" "r,r,r,r,r")
1323 (match_operand:DI 4 "arith11_operand" "rI,rI,rI,rI,rI")])
1324 (match_operand:DI 1 "reg_or_cint_move_operand" "0,r,J,N,K")
1328 cmp%I4clr,*%S2 %4,%3,%%r0\;ldi 0,%0
1329 cmp%I4clr,*%B2 %4,%3,%0\;copy %1,%0
1330 cmp%I4clr,*%B2 %4,%3,%0\;ldi %1,%0
1331 cmp%I4clr,*%B2 %4,%3,%0\;ldil L'%1,%0
1332 cmp%I4clr,*%B2 %4,%3,%0\;depdi,z %z1,%0"
1333 [(set_attr "type" "multi,multi,multi,multi,nullshift")
1334 (set_attr "length" "8,8,8,8,8")])
1337 [(set (match_operand:DI 0 "register_operand" "=r,r,r,r,r,r,r,r")
1339 (match_operator 5 "ordered_comparison_operator"
1340 [(match_operand:DI 3 "register_operand" "r,r,r,r,r,r,r,r")
1341 (match_operand:DI 4 "arith11_operand" "rI,rI,rI,rI,rI,rI,rI,rI")])
1342 (match_operand:DI 1 "reg_or_cint_move_operand" "0,0,0,0,r,J,N,K")
1343 (match_operand:DI 2 "reg_or_cint_move_operand" "r,J,N,K,0,0,0,0")))]
1346 cmp%I4clr,*%S5 %4,%3,%%r0\;copy %2,%0
1347 cmp%I4clr,*%S5 %4,%3,%%r0\;ldi %2,%0
1348 cmp%I4clr,*%S5 %4,%3,%%r0\;ldil L'%2,%0
1349 cmp%I4clr,*%S5 %4,%3,%%r0\;depdi,z %z2,%0
1350 cmp%I4clr,*%B5 %4,%3,%%r0\;copy %1,%0
1351 cmp%I4clr,*%B5 %4,%3,%%r0\;ldi %1,%0
1352 cmp%I4clr,*%B5 %4,%3,%%r0\;ldil L'%1,%0
1353 cmp%I4clr,*%B5 %4,%3,%%r0\;depdi,z %z1,%0"
1354 [(set_attr "type" "multi,multi,multi,nullshift,multi,multi,multi,nullshift")
1355 (set_attr "length" "8,8,8,8,8,8,8,8")])
1357 ;; Conditional Branches
1359 (define_expand "cbranchdi4"
1361 (if_then_else (match_operator 0 "ordered_comparison_operator"
1362 [(match_operand:DI 1 "reg_or_0_operand" "")
1363 (match_operand:DI 2 "register_operand" "")])
1364 (label_ref (match_operand 3 "" ""))
1369 (define_expand "cbranchsi4"
1371 (if_then_else (match_operator 0 "ordered_comparison_operator"
1372 [(match_operand:SI 1 "reg_or_0_operand" "")
1373 (match_operand:SI 2 "arith5_operand" "")])
1374 (label_ref (match_operand 3 "" ""))
1379 (define_expand "cbranchsf4"
1381 (if_then_else (match_operator 0 "comparison_operator"
1382 [(match_operand:SF 1 "reg_or_0_operand" "")
1383 (match_operand:SF 2 "reg_or_0_operand" "")])
1384 (label_ref (match_operand 3 "" ""))
1389 pa_emit_bcond_fp (operands);
1394 (define_expand "cbranchdf4"
1396 (if_then_else (match_operator 0 "comparison_operator"
1397 [(match_operand:DF 1 "reg_or_0_operand" "")
1398 (match_operand:DF 2 "reg_or_0_operand" "")])
1399 (label_ref (match_operand 3 "" ""))
1404 pa_emit_bcond_fp (operands);
1408 ;; Match the branch patterns.
1411 ;; Note a long backward conditional branch with an annulled delay slot
1412 ;; has a length of 12.
1416 (match_operator 3 "ordered_comparison_operator"
1417 [(match_operand:SI 1 "reg_or_0_operand" "rM")
1418 (match_operand:SI 2 "arith5_operand" "rL")])
1419 (label_ref (match_operand 0 "" ""))
1424 return pa_output_cbranch (operands, 0, insn);
1426 [(set_attr "type" "cbranch")
1427 (set (attr "length")
1428 (cond [(lt (abs (minus (match_dup 0) (plus (pc) (const_int 8))))
1429 (const_int MAX_12BIT_OFFSET))
1431 (lt (abs (minus (match_dup 0) (plus (pc) (const_int 8))))
1432 (const_int MAX_17BIT_OFFSET))
1434 (match_test "TARGET_PORTABLE_RUNTIME")
1436 (not (match_test "flag_pic"))
1440 ;; Match the negated branch.
1445 (match_operator 3 "ordered_comparison_operator"
1446 [(match_operand:SI 1 "reg_or_0_operand" "rM")
1447 (match_operand:SI 2 "arith5_operand" "rL")])
1449 (label_ref (match_operand 0 "" ""))))]
1453 return pa_output_cbranch (operands, 1, insn);
1455 [(set_attr "type" "cbranch")
1456 (set (attr "length")
1457 (cond [(lt (abs (minus (match_dup 0) (plus (pc) (const_int 8))))
1458 (const_int MAX_12BIT_OFFSET))
1460 (lt (abs (minus (match_dup 0) (plus (pc) (const_int 8))))
1461 (const_int MAX_17BIT_OFFSET))
1463 (match_test "TARGET_PORTABLE_RUNTIME")
1465 (not (match_test "flag_pic"))
1472 (match_operator 3 "ordered_comparison_operator"
1473 [(match_operand:DI 1 "reg_or_0_operand" "rM")
1474 (match_operand:DI 2 "reg_or_0_operand" "rM")])
1475 (label_ref (match_operand 0 "" ""))
1480 return pa_output_cbranch (operands, 0, insn);
1482 [(set_attr "type" "cbranch")
1483 (set (attr "length")
1484 (cond [(lt (abs (minus (match_dup 0) (plus (pc) (const_int 8))))
1485 (const_int MAX_12BIT_OFFSET))
1487 (lt (abs (minus (match_dup 0) (plus (pc) (const_int 8))))
1488 (const_int MAX_17BIT_OFFSET))
1490 (match_test "TARGET_PORTABLE_RUNTIME")
1492 (not (match_test "flag_pic"))
1496 ;; Match the negated branch.
1501 (match_operator 3 "ordered_comparison_operator"
1502 [(match_operand:DI 1 "reg_or_0_operand" "rM")
1503 (match_operand:DI 2 "reg_or_0_operand" "rM")])
1505 (label_ref (match_operand 0 "" ""))))]
1509 return pa_output_cbranch (operands, 1, insn);
1511 [(set_attr "type" "cbranch")
1512 (set (attr "length")
1513 (cond [(lt (abs (minus (match_dup 0) (plus (pc) (const_int 8))))
1514 (const_int MAX_12BIT_OFFSET))
1516 (lt (abs (minus (match_dup 0) (plus (pc) (const_int 8))))
1517 (const_int MAX_17BIT_OFFSET))
1519 (match_test "TARGET_PORTABLE_RUNTIME")
1521 (not (match_test "flag_pic"))
1527 (match_operator 3 "cmpib_comparison_operator"
1528 [(match_operand:DI 1 "reg_or_0_operand" "rM")
1529 (match_operand:DI 2 "arith5_operand" "rL")])
1530 (label_ref (match_operand 0 "" ""))
1535 return pa_output_cbranch (operands, 0, insn);
1537 [(set_attr "type" "cbranch")
1538 (set (attr "length")
1539 (cond [(lt (abs (minus (match_dup 0) (plus (pc) (const_int 8))))
1540 (const_int MAX_12BIT_OFFSET))
1542 (lt (abs (minus (match_dup 0) (plus (pc) (const_int 8))))
1543 (const_int MAX_17BIT_OFFSET))
1545 (match_test "TARGET_PORTABLE_RUNTIME")
1547 (not (match_test "flag_pic"))
1551 ;; Match the negated branch.
1556 (match_operator 3 "cmpib_comparison_operator"
1557 [(match_operand:DI 1 "reg_or_0_operand" "rM")
1558 (match_operand:DI 2 "arith5_operand" "rL")])
1560 (label_ref (match_operand 0 "" ""))))]
1564 return pa_output_cbranch (operands, 1, insn);
1566 [(set_attr "type" "cbranch")
1567 (set (attr "length")
1568 (cond [(lt (abs (minus (match_dup 0) (plus (pc) (const_int 8))))
1569 (const_int MAX_12BIT_OFFSET))
1571 (lt (abs (minus (match_dup 0) (plus (pc) (const_int 8))))
1572 (const_int MAX_17BIT_OFFSET))
1574 (match_test "TARGET_PORTABLE_RUNTIME")
1576 (not (match_test "flag_pic"))
1580 ;; Branch on Bit patterns.
1584 (ne (zero_extract:SI (match_operand:SI 0 "register_operand" "r")
1586 (match_operand:SI 1 "uint5_operand" ""))
1588 (label_ref (match_operand 2 "" ""))
1593 return pa_output_bb (operands, 0, insn, 0);
1595 [(set_attr "type" "cbranch")
1596 (set (attr "length")
1597 (cond [(lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
1598 (const_int MAX_12BIT_OFFSET))
1600 (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
1601 (const_int MAX_17BIT_OFFSET))
1603 (match_test "TARGET_PORTABLE_RUNTIME")
1605 (not (match_test "flag_pic"))
1612 (ne (zero_extract:DI (match_operand:DI 0 "register_operand" "r")
1614 (match_operand:DI 1 "uint32_operand" ""))
1616 (label_ref (match_operand 2 "" ""))
1621 return pa_output_bb (operands, 0, insn, 0);
1623 [(set_attr "type" "cbranch")
1624 (set (attr "length")
1625 (cond [(lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
1626 (const_int MAX_12BIT_OFFSET))
1628 (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
1629 (const_int MAX_17BIT_OFFSET))
1631 (match_test "TARGET_PORTABLE_RUNTIME")
1633 (not (match_test "flag_pic"))
1640 (ne (zero_extract:SI (match_operand:SI 0 "register_operand" "r")
1642 (match_operand:SI 1 "uint5_operand" ""))
1645 (label_ref (match_operand 2 "" ""))))]
1649 return pa_output_bb (operands, 1, insn, 0);
1651 [(set_attr "type" "cbranch")
1652 (set (attr "length")
1653 (cond [(lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
1654 (const_int MAX_12BIT_OFFSET))
1656 (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
1657 (const_int MAX_17BIT_OFFSET))
1659 (match_test "TARGET_PORTABLE_RUNTIME")
1661 (not (match_test "flag_pic"))
1668 (ne (zero_extract:DI (match_operand:DI 0 "register_operand" "r")
1670 (match_operand:DI 1 "uint32_operand" ""))
1673 (label_ref (match_operand 2 "" ""))))]
1677 return pa_output_bb (operands, 1, insn, 0);
1679 [(set_attr "type" "cbranch")
1680 (set (attr "length")
1681 (cond [(lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
1682 (const_int MAX_12BIT_OFFSET))
1684 (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
1685 (const_int MAX_17BIT_OFFSET))
1687 (match_test "TARGET_PORTABLE_RUNTIME")
1689 (not (match_test "flag_pic"))
1696 (eq (zero_extract:SI (match_operand:SI 0 "register_operand" "r")
1698 (match_operand:SI 1 "uint5_operand" ""))
1700 (label_ref (match_operand 2 "" ""))
1705 return pa_output_bb (operands, 0, insn, 1);
1707 [(set_attr "type" "cbranch")
1708 (set (attr "length")
1709 (cond [(lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
1710 (const_int MAX_12BIT_OFFSET))
1712 (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
1713 (const_int MAX_17BIT_OFFSET))
1715 (match_test "TARGET_PORTABLE_RUNTIME")
1717 (not (match_test "flag_pic"))
1724 (eq (zero_extract:DI (match_operand:DI 0 "register_operand" "r")
1726 (match_operand:DI 1 "uint32_operand" ""))
1728 (label_ref (match_operand 2 "" ""))
1733 return pa_output_bb (operands, 0, insn, 1);
1735 [(set_attr "type" "cbranch")
1736 (set (attr "length")
1737 (cond [(lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
1738 (const_int MAX_12BIT_OFFSET))
1740 (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
1741 (const_int MAX_17BIT_OFFSET))
1743 (match_test "TARGET_PORTABLE_RUNTIME")
1745 (not (match_test "flag_pic"))
1752 (eq (zero_extract:SI (match_operand:SI 0 "register_operand" "r")
1754 (match_operand:SI 1 "uint5_operand" ""))
1757 (label_ref (match_operand 2 "" ""))))]
1761 return pa_output_bb (operands, 1, insn, 1);
1763 [(set_attr "type" "cbranch")
1764 (set (attr "length")
1765 (cond [(lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
1766 (const_int MAX_12BIT_OFFSET))
1768 (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
1769 (const_int MAX_17BIT_OFFSET))
1771 (match_test "TARGET_PORTABLE_RUNTIME")
1773 (not (match_test "flag_pic"))
1780 (eq (zero_extract:DI (match_operand:DI 0 "register_operand" "r")
1782 (match_operand:DI 1 "uint32_operand" ""))
1785 (label_ref (match_operand 2 "" ""))))]
1789 return pa_output_bb (operands, 1, insn, 1);
1791 [(set_attr "type" "cbranch")
1792 (set (attr "length")
1793 (cond [(lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
1794 (const_int MAX_12BIT_OFFSET))
1796 (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
1797 (const_int MAX_17BIT_OFFSET))
1799 (match_test "TARGET_PORTABLE_RUNTIME")
1801 (not (match_test "flag_pic"))
1805 ;; Branch on Variable Bit patterns.
1809 (ne (zero_extract:SI (match_operand:SI 0 "register_operand" "r")
1811 (match_operand:SI 1 "register_operand" "q"))
1813 (label_ref (match_operand 2 "" ""))
1818 return pa_output_bvb (operands, 0, insn, 0);
1820 [(set_attr "type" "cbranch")
1821 (set (attr "length")
1822 (cond [(lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
1823 (const_int MAX_12BIT_OFFSET))
1825 (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
1826 (const_int MAX_17BIT_OFFSET))
1828 (match_test "TARGET_PORTABLE_RUNTIME")
1830 (not (match_test "flag_pic"))
1837 (ne (zero_extract:DI (match_operand:DI 0 "register_operand" "r")
1839 (match_operand:DI 1 "register_operand" "q"))
1841 (label_ref (match_operand 2 "" ""))
1846 return pa_output_bvb (operands, 0, insn, 0);
1848 [(set_attr "type" "cbranch")
1849 (set (attr "length")
1850 (cond [(lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
1851 (const_int MAX_12BIT_OFFSET))
1853 (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
1854 (const_int MAX_17BIT_OFFSET))
1856 (match_test "TARGET_PORTABLE_RUNTIME")
1858 (not (match_test "flag_pic"))
1865 (ne (zero_extract:SI (match_operand:SI 0 "register_operand" "r")
1867 (match_operand:SI 1 "register_operand" "q"))
1870 (label_ref (match_operand 2 "" ""))))]
1874 return pa_output_bvb (operands, 1, insn, 0);
1876 [(set_attr "type" "cbranch")
1877 (set (attr "length")
1878 (cond [(lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
1879 (const_int MAX_12BIT_OFFSET))
1881 (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
1882 (const_int MAX_17BIT_OFFSET))
1884 (match_test "TARGET_PORTABLE_RUNTIME")
1886 (not (match_test "flag_pic"))
1893 (ne (zero_extract:DI (match_operand:DI 0 "register_operand" "r")
1895 (match_operand:DI 1 "register_operand" "q"))
1898 (label_ref (match_operand 2 "" ""))))]
1902 return pa_output_bvb (operands, 1, insn, 0);
1904 [(set_attr "type" "cbranch")
1905 (set (attr "length")
1906 (cond [(lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
1907 (const_int MAX_12BIT_OFFSET))
1909 (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
1910 (const_int MAX_17BIT_OFFSET))
1912 (match_test "TARGET_PORTABLE_RUNTIME")
1914 (not (match_test "flag_pic"))
1921 (eq (zero_extract:SI (match_operand:SI 0 "register_operand" "r")
1923 (match_operand:SI 1 "register_operand" "q"))
1925 (label_ref (match_operand 2 "" ""))
1930 return pa_output_bvb (operands, 0, insn, 1);
1932 [(set_attr "type" "cbranch")
1933 (set (attr "length")
1934 (cond [(lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
1935 (const_int MAX_12BIT_OFFSET))
1937 (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
1938 (const_int MAX_17BIT_OFFSET))
1940 (match_test "TARGET_PORTABLE_RUNTIME")
1942 (not (match_test "flag_pic"))
1949 (eq (zero_extract:DI (match_operand:DI 0 "register_operand" "r")
1951 (match_operand:DI 1 "register_operand" "q"))
1953 (label_ref (match_operand 2 "" ""))
1958 return pa_output_bvb (operands, 0, insn, 1);
1960 [(set_attr "type" "cbranch")
1961 (set (attr "length")
1962 (cond [(lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
1963 (const_int MAX_12BIT_OFFSET))
1965 (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
1966 (const_int MAX_17BIT_OFFSET))
1968 (match_test "TARGET_PORTABLE_RUNTIME")
1970 (not (match_test "flag_pic"))
1977 (eq (zero_extract:SI (match_operand:SI 0 "register_operand" "r")
1979 (match_operand:SI 1 "register_operand" "q"))
1982 (label_ref (match_operand 2 "" ""))))]
1986 return pa_output_bvb (operands, 1, insn, 1);
1988 [(set_attr "type" "cbranch")
1989 (set (attr "length")
1990 (cond [(lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
1991 (const_int MAX_12BIT_OFFSET))
1993 (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
1994 (const_int MAX_17BIT_OFFSET))
1996 (match_test "TARGET_PORTABLE_RUNTIME")
1998 (not (match_test "flag_pic"))
2005 (eq (zero_extract:DI (match_operand:DI 0 "register_operand" "r")
2007 (match_operand:DI 1 "register_operand" "q"))
2010 (label_ref (match_operand 2 "" ""))))]
2014 return pa_output_bvb (operands, 1, insn, 1);
2016 [(set_attr "type" "cbranch")
2017 (set (attr "length")
2018 (cond [(lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
2019 (const_int MAX_12BIT_OFFSET))
2021 (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
2022 (const_int MAX_17BIT_OFFSET))
2024 (match_test "TARGET_PORTABLE_RUNTIME")
2026 (not (match_test "flag_pic"))
2030 ;; Floating point branches
2032 ;; ??? Nullification is handled differently from other branches.
2033 ;; If nullification is specified, the delay slot is nullified on any
2034 ;; taken branch regardless of branch direction.
2036 [(set (pc) (if_then_else (ne (reg:CCFP 0) (const_int 0))
2037 (label_ref (match_operand 0 "" ""))
2039 "!TARGET_SOFT_FLOAT"
2042 int length = get_attr_length (insn);
2044 int nullify, xdelay;
2047 return \"ftest\;b%* %l0\";
2049 if (dbr_sequence_length () == 0 || INSN_ANNULLED_BRANCH_P (insn))
2053 xoperands[0] = GEN_INT (length - 8);
2059 xoperands[0] = GEN_INT (length - 4);
2063 output_asm_insn (\"ftest\;add,tr %%r0,%%r0,%%r0\;b,n .+%0\", xoperands);
2065 output_asm_insn (\"ftest\;add,tr %%r0,%%r0,%%r0\;b .+%0\", xoperands);
2066 return pa_output_lbranch (operands[0], insn, xdelay);
2068 [(set_attr "type" "fbranch")
2069 (set (attr "length")
2070 (cond [(lt (abs (minus (match_dup 0) (plus (pc) (const_int 8))))
2071 (const_int MAX_17BIT_OFFSET))
2073 (match_test "TARGET_PORTABLE_RUNTIME")
2075 (not (match_test "flag_pic"))
2080 [(set (pc) (if_then_else (ne (reg:CCFP 0) (const_int 0))
2082 (label_ref (match_operand 0 "" ""))))]
2083 "!TARGET_SOFT_FLOAT"
2086 int length = get_attr_length (insn);
2088 int nullify, xdelay;
2091 return \"ftest\;add,tr %%r0,%%r0,%%r0\;b%* %0\";
2093 if (dbr_sequence_length () == 0 || INSN_ANNULLED_BRANCH_P (insn))
2097 xoperands[0] = GEN_INT (length - 4);
2103 xoperands[0] = GEN_INT (length);
2107 output_asm_insn (\"ftest\;b,n .+%0\", xoperands);
2109 output_asm_insn (\"ftest\;b .+%0\", xoperands);
2110 return pa_output_lbranch (operands[0], insn, xdelay);
2112 [(set_attr "type" "fbranch")
2113 (set (attr "length")
2114 (cond [(lt (abs (minus (match_dup 0) (plus (pc) (const_int 8))))
2115 (const_int MAX_17BIT_OFFSET))
2117 (match_test "TARGET_PORTABLE_RUNTIME")
2119 (not (match_test "flag_pic"))
2123 ;; Move instructions
2125 (define_expand "movsi"
2126 [(set (match_operand:SI 0 "general_operand" "")
2127 (match_operand:SI 1 "general_operand" ""))]
2131 if (pa_emit_move_sequence (operands, SImode, 0))
2135 ;; Handle SImode input reloads requiring %r1 as a scratch register.
2136 (define_expand "reload_insi_r1"
2137 [(set (match_operand:SI 0 "register_operand" "=Z")
2138 (match_operand:SI 1 "non_hard_reg_operand" ""))
2139 (clobber (match_operand:SI 2 "register_operand" "=&a"))]
2143 if (pa_emit_move_sequence (operands, SImode, operands[2]))
2146 /* We don't want the clobber emitted, so handle this ourselves. */
2147 emit_insn (gen_rtx_SET (operands[0], operands[1]));
2151 ;; Handle SImode input reloads requiring a general register as a
2152 ;; scratch register.
2153 (define_expand "reload_insi"
2154 [(set (match_operand:SI 0 "register_operand" "=Z")
2155 (match_operand:SI 1 "non_hard_reg_operand" ""))
2156 (clobber (match_operand:SI 2 "register_operand" "=&r"))]
2160 if (pa_emit_move_sequence (operands, SImode, operands[2]))
2163 /* We don't want the clobber emitted, so handle this ourselves. */
2164 emit_insn (gen_rtx_SET (operands[0], operands[1]));
2168 ;; Handle SImode output reloads requiring a general register as a
2169 ;; scratch register.
2170 (define_expand "reload_outsi"
2171 [(set (match_operand:SI 0 "non_hard_reg_operand" "")
2172 (match_operand:SI 1 "register_operand" "Z"))
2173 (clobber (match_operand:SI 2 "register_operand" "=&r"))]
2177 if (pa_emit_move_sequence (operands, SImode, operands[2]))
2180 /* We don't want the clobber emitted, so handle this ourselves. */
2181 emit_insn (gen_rtx_SET (operands[0], operands[1]));
2186 [(set (match_operand:SI 0 "move_dest_operand"
2187 "=r,r,r,r,r,r,Q,!*q,!r,!*f,*f,T,?r,?*f")
2188 (match_operand:SI 1 "move_src_operand"
2189 "A,r,J,N,K,RQ,rM,!rM,!*q,!*fM,RT,*f,*f,r"))]
2190 "(register_operand (operands[0], SImode)
2191 || reg_or_0_operand (operands[1], SImode))
2192 && !TARGET_SOFT_FLOAT
2199 {zdepi|depwi,z} %Z1,%0
2203 {mfctl|mfctl,w} %%sar,%0
2207 {fstws|fstw} %1,-16(%%sp)\n\t{ldws|ldw} -16(%%sp),%0
2208 {stws|stw} %1,-16(%%sp)\n\t{fldws|fldw} -16(%%sp),%0"
2209 [(set_attr "type" "load,move,move,move,shift,load,store,move,move,fpalu,fpload,fpstore,fpstore_load,store_fpload")
2210 (set_attr "pa_combine_type" "addmove")
2211 (set_attr "length" "4,4,4,4,4,4,4,4,4,4,4,4,8,8")])
2214 [(set (match_operand:SI 0 "move_dest_operand"
2215 "=r,r,r,r,r,r,Q,!*q,!r,!*f,*f,T")
2216 (match_operand:SI 1 "move_src_operand"
2217 "A,r,J,N,K,RQ,rM,!rM,!*q,!*fM,RT,*f"))]
2218 "(register_operand (operands[0], SImode)
2219 || reg_or_0_operand (operands[1], SImode))
2220 && !TARGET_SOFT_FLOAT
2227 {zdepi|depwi,z} %Z1,%0
2231 {mfctl|mfctl,w} %%sar,%0
2235 [(set_attr "type" "load,move,move,move,shift,load,store,move,move,fpalu,fpload,fpstore")
2236 (set_attr "pa_combine_type" "addmove")
2237 (set_attr "length" "4,4,4,4,4,4,4,4,4,4,4,4")])
2240 [(set (match_operand:SI 0 "indexed_memory_operand" "=R")
2241 (match_operand:SI 1 "register_operand" "f"))]
2243 && !TARGET_DISABLE_INDEXING
2244 && reload_completed"
2246 [(set_attr "type" "fpstore")
2247 (set_attr "pa_combine_type" "addmove")
2248 (set_attr "length" "4")])
2250 ; Rewrite RTL using an indexed store. This will allow the insn that
2251 ; computes the address to be deleted if the register it sets is dead.
2253 [(set (match_operand:SI 0 "register_operand" "")
2254 (plus:SI (ashift:SI (match_operand:SI 1 "register_operand" "")
2256 (match_operand:SI 2 "register_operand" "")))
2257 (set (mem:SI (match_dup 0))
2258 (match_operand:SI 3 "register_operand" ""))]
2260 && !TARGET_DISABLE_INDEXING
2261 && REG_OK_FOR_BASE_P (operands[2])
2262 && FP_REGNO_P (REGNO (operands[3]))"
2263 [(set (mem:SI (plus:SI (mult:SI (match_dup 1) (const_int 4)) (match_dup 2)))
2265 (set (match_dup 0) (plus:SI (ashift:SI (match_dup 1) (const_int 2))
2270 [(set (match_operand:DI 0 "register_operand" "")
2271 (plus:DI (ashift:DI (match_operand:DI 1 "register_operand" "")
2273 (match_operand:DI 2 "register_operand" "")))
2274 (set (mem:SI (match_dup 0))
2275 (match_operand:SI 3 "register_operand" ""))]
2277 && !TARGET_DISABLE_INDEXING
2279 && REG_OK_FOR_BASE_P (operands[2])
2280 && FP_REGNO_P (REGNO (operands[3]))"
2281 [(set (mem:SI (plus:DI (mult:DI (match_dup 1) (const_int 4)) (match_dup 2)))
2283 (set (match_dup 0) (plus:DI (ashift:DI (match_dup 1) (const_int 2))
2288 [(set (match_operand:SI 0 "register_operand" "")
2289 (plus:SI (match_operand:SI 1 "register_operand" "")
2290 (match_operand:SI 2 "register_operand" "")))
2291 (set (mem:SI (match_dup 0))
2292 (match_operand:SI 3 "register_operand" ""))]
2294 && !TARGET_DISABLE_INDEXING
2295 && TARGET_NO_SPACE_REGS
2296 && REG_OK_FOR_INDEX_P (operands[1])
2297 && REG_OK_FOR_BASE_P (operands[2])
2298 && FP_REGNO_P (REGNO (operands[3]))"
2299 [(set (mem:SI (plus:SI (match_dup 1) (match_dup 2)))
2301 (set (match_dup 0) (plus:SI (match_dup 1) (match_dup 2)))]
2305 [(set (match_operand:SI 0 "register_operand" "")
2306 (plus:SI (match_operand:SI 1 "register_operand" "")
2307 (match_operand:SI 2 "register_operand" "")))
2308 (set (mem:SI (match_dup 0))
2309 (match_operand:SI 3 "register_operand" ""))]
2311 && !TARGET_DISABLE_INDEXING
2312 && TARGET_NO_SPACE_REGS
2313 && REG_OK_FOR_BASE_P (operands[1])
2314 && REG_OK_FOR_INDEX_P (operands[2])
2315 && FP_REGNO_P (REGNO (operands[3]))"
2316 [(set (mem:SI (plus:SI (match_dup 2) (match_dup 1)))
2318 (set (match_dup 0) (plus:SI (match_dup 2) (match_dup 1)))]
2322 [(set (match_operand:DI 0 "register_operand" "")
2323 (plus:DI (match_operand:DI 1 "register_operand" "")
2324 (match_operand:DI 2 "register_operand" "")))
2325 (set (mem:SI (match_dup 0))
2326 (match_operand:SI 3 "register_operand" ""))]
2328 && !TARGET_DISABLE_INDEXING
2330 && TARGET_NO_SPACE_REGS
2331 && REG_OK_FOR_INDEX_P (operands[1])
2332 && REG_OK_FOR_BASE_P (operands[2])
2333 && FP_REGNO_P (REGNO (operands[3]))"
2334 [(set (mem:SI (plus:DI (match_dup 1) (match_dup 2)))
2336 (set (match_dup 0) (plus:DI (match_dup 1) (match_dup 2)))]
2340 [(set (match_operand:DI 0 "register_operand" "")
2341 (plus:DI (match_operand:DI 1 "register_operand" "")
2342 (match_operand:DI 2 "register_operand" "")))
2343 (set (mem:SI (match_dup 0))
2344 (match_operand:SI 3 "register_operand" ""))]
2346 && !TARGET_DISABLE_INDEXING
2348 && TARGET_NO_SPACE_REGS
2349 && REG_OK_FOR_BASE_P (operands[1])
2350 && REG_OK_FOR_INDEX_P (operands[2])
2351 && FP_REGNO_P (REGNO (operands[3]))"
2352 [(set (mem:SI (plus:DI (match_dup 2) (match_dup 1)))
2354 (set (match_dup 0) (plus:DI (match_dup 2) (match_dup 1)))]
2358 [(set (match_operand:SI 0 "move_dest_operand"
2359 "=r,r,r,r,r,r,Q,!*q,!r")
2360 (match_operand:SI 1 "move_src_operand"
2361 "A,r,J,N,K,RQ,rM,!rM,!*q"))]
2362 "(register_operand (operands[0], SImode)
2363 || reg_or_0_operand (operands[1], SImode))
2364 && TARGET_SOFT_FLOAT"
2370 {zdepi|depwi,z} %Z1,%0
2374 {mfctl|mfctl,w} %%sar,%0"
2375 [(set_attr "type" "load,move,move,move,move,load,store,move,move")
2376 (set_attr "pa_combine_type" "addmove")
2377 (set_attr "length" "4,4,4,4,4,4,4,4,4")])
2379 ;; Load or store with base-register modification.
2381 [(set (match_operand:SI 0 "register_operand" "=r")
2382 (mem:SI (plus:DI (match_operand:DI 1 "register_operand" "+r")
2383 (match_operand:DI 2 "int5_operand" "L"))))
2385 (plus:DI (match_dup 1) (match_dup 2)))]
2388 [(set_attr "type" "load")
2389 (set_attr "length" "4")])
2391 ; And a zero extended variant.
2393 [(set (match_operand:DI 0 "register_operand" "=r")
2394 (zero_extend:DI (mem:SI
2396 (match_operand:DI 1 "register_operand" "+r")
2397 (match_operand:DI 2 "int5_operand" "L")))))
2399 (plus:DI (match_dup 1) (match_dup 2)))]
2402 [(set_attr "type" "load")
2403 (set_attr "length" "4")])
2405 (define_expand "pre_load"
2406 [(parallel [(set (match_operand:SI 0 "register_operand" "")
2407 (mem (plus (match_operand 1 "register_operand" "")
2408 (match_operand 2 "pre_cint_operand" ""))))
2410 (plus (match_dup 1) (match_dup 2)))])]
2416 emit_insn (gen_pre_ldd (operands[0], operands[1], operands[2]));
2419 emit_insn (gen_pre_ldw (operands[0], operands[1], operands[2]));
2423 (define_insn "pre_ldw"
2424 [(set (match_operand:SI 0 "register_operand" "=r")
2425 (mem:SI (plus:SI (match_operand:SI 1 "register_operand" "+r")
2426 (match_operand:SI 2 "pre_cint_operand" ""))))
2428 (plus:SI (match_dup 1) (match_dup 2)))]
2432 if (INTVAL (operands[2]) < 0)
2433 return \"{ldwm|ldw,mb} %2(%1),%0\";
2434 return \"{ldws|ldw},mb %2(%1),%0\";
2436 [(set_attr "type" "load")
2437 (set_attr "length" "4")])
2439 (define_insn "pre_ldd"
2440 [(set (match_operand:DI 0 "register_operand" "=r")
2441 (mem:DI (plus:DI (match_operand:DI 1 "register_operand" "+r")
2442 (match_operand:DI 2 "pre_cint_operand" ""))))
2444 (plus:DI (match_dup 1) (match_dup 2)))]
2447 [(set_attr "type" "load")
2448 (set_attr "length" "4")])
2451 [(set (mem:SI (plus:SI (match_operand:SI 0 "register_operand" "+r")
2452 (match_operand:SI 1 "pre_cint_operand" "")))
2453 (match_operand:SI 2 "reg_or_0_operand" "rM"))
2455 (plus:SI (match_dup 0) (match_dup 1)))]
2459 if (INTVAL (operands[1]) < 0)
2460 return \"{stwm|stw,mb} %r2,%1(%0)\";
2461 return \"{stws|stw},mb %r2,%1(%0)\";
2463 [(set_attr "type" "store")
2464 (set_attr "length" "4")])
2467 [(set (match_operand:SI 0 "register_operand" "=r")
2468 (mem:SI (match_operand:SI 1 "register_operand" "+r")))
2470 (plus:SI (match_dup 1)
2471 (match_operand:SI 2 "post_cint_operand" "")))]
2475 if (INTVAL (operands[2]) > 0)
2476 return \"{ldwm|ldw,ma} %2(%1),%0\";
2477 return \"{ldws|ldw},ma %2(%1),%0\";
2479 [(set_attr "type" "load")
2480 (set_attr "length" "4")])
2482 (define_expand "post_store"
2483 [(parallel [(set (mem (match_operand 0 "register_operand" ""))
2484 (match_operand 1 "reg_or_0_operand" ""))
2487 (match_operand 2 "post_cint_operand" "")))])]
2493 emit_insn (gen_post_std (operands[0], operands[1], operands[2]));
2496 emit_insn (gen_post_stw (operands[0], operands[1], operands[2]));
2500 (define_insn "post_stw"
2501 [(set (mem:SI (match_operand:SI 0 "register_operand" "+r"))
2502 (match_operand:SI 1 "reg_or_0_operand" "rM"))
2504 (plus:SI (match_dup 0)
2505 (match_operand:SI 2 "post_cint_operand" "")))]
2509 if (INTVAL (operands[2]) > 0)
2510 return \"{stwm|stw,ma} %r1,%2(%0)\";
2511 return \"{stws|stw},ma %r1,%2(%0)\";
2513 [(set_attr "type" "store")
2514 (set_attr "length" "4")])
2516 (define_insn "post_std"
2517 [(set (mem:DI (match_operand:DI 0 "register_operand" "+r"))
2518 (match_operand:DI 1 "reg_or_0_operand" "rM"))
2520 (plus:DI (match_dup 0)
2521 (match_operand:DI 2 "post_cint_operand" "")))]
2524 [(set_attr "type" "store")
2525 (set_attr "length" "4")])
2527 ;; For loading the address of a label while generating PIC code.
2528 ;; Note since this pattern can be created at reload time (via movsi), all
2529 ;; the same rules for movsi apply here. (no new pseudos, no temporaries).
2531 [(set (match_operand 0 "pmode_register_operand" "=a")
2532 (match_operand 1 "pic_label_operand" ""))]
2538 xoperands[0] = operands[0];
2539 xoperands[1] = operands[1];
2541 if (GET_CODE (operands[1]) == LABEL_REF
2542 && !LABEL_REF_NONLOCAL_P (operands[1]))
2544 xoperands[2] = gen_label_rtx ();
2545 (*targetm.asm_out.internal_label) (asm_out_file, \"L\",
2546 CODE_LABEL_NUMBER (xoperands[2]));
2547 output_asm_insn (\"mfia %0\", xoperands);
2549 /* If we're trying to load the address of a label that happens to be
2550 close, then we can use a shorter sequence. */
2551 if (INSN_ADDRESSES_SET_P ()
2552 && abs (INSN_ADDRESSES (INSN_UID (XEXP (operands[1], 0)))
2553 - INSN_ADDRESSES (INSN_UID (insn))) < 8100)
2554 output_asm_insn (\"ldo %1-%2(%0),%0\", xoperands);
2557 output_asm_insn (\"addil L%%%1-%2,%0\", xoperands);
2558 output_asm_insn (\"ldo R%%%1-%2(%0),%0\", xoperands);
2563 /* Load using linkage table. */
2566 output_asm_insn (\"addil LT%%%1,%%r27\", xoperands);
2567 output_asm_insn (\"ldd RT%%%1(%0),%0\", xoperands);
2571 output_asm_insn (\"addil LT%%%1,%%r19\", xoperands);
2572 output_asm_insn (\"ldw RT%%%1(%0),%0\", xoperands);
2577 [(set_attr "type" "multi")
2578 (set_attr "length" "12")]) ; 8 or 12
2581 [(set (match_operand 0 "pmode_register_operand" "=a")
2582 (match_operand 1 "pic_label_operand" ""))]
2588 xoperands[0] = operands[0];
2589 xoperands[1] = operands[1];
2591 if (GET_CODE (operands[1]) == LABEL_REF
2592 && !LABEL_REF_NONLOCAL_P (operands[1]))
2594 xoperands[2] = gen_label_rtx ();
2595 output_asm_insn (\"bl .+8,%0\", xoperands);
2596 output_asm_insn (\"depi 0,31,2,%0\", xoperands);
2597 (*targetm.asm_out.internal_label) (asm_out_file, \"L\",
2598 CODE_LABEL_NUMBER (xoperands[2]));
2600 /* If we're trying to load the address of a label that happens to be
2601 close, then we can use a shorter sequence. */
2602 if (INSN_ADDRESSES_SET_P ()
2603 && abs (INSN_ADDRESSES (INSN_UID (XEXP (operands[1], 0)))
2604 - INSN_ADDRESSES (INSN_UID (insn))) < 8100)
2605 output_asm_insn (\"ldo %1-%2(%0),%0\", xoperands);
2608 output_asm_insn (\"addil L%%%1-%2,%0\", xoperands);
2609 output_asm_insn (\"ldo R%%%1-%2(%0),%0\", xoperands);
2614 /* Load using linkage table. */
2615 output_asm_insn (\"addil LT%%%1,%%r19\", xoperands);
2616 output_asm_insn (\"ldw RT%%%1(%0),%0\", xoperands);
2620 [(set_attr "type" "multi")
2621 (set_attr "length" "16")]) ; 12 or 16
2624 [(set (match_operand:SI 0 "register_operand" "=a")
2625 (plus:SI (match_operand:SI 1 "register_operand" "r")
2626 (high:SI (match_operand 2 "" ""))))]
2627 "symbolic_operand (operands[2], Pmode)
2628 && ! function_label_operand (operands[2], Pmode)
2631 [(set_attr "type" "binary")
2632 (set_attr "length" "4")])
2635 [(set (match_operand:DI 0 "register_operand" "=a")
2636 (plus:DI (match_operand:DI 1 "register_operand" "r")
2637 (high:DI (match_operand 2 "" ""))))]
2638 "symbolic_operand (operands[2], Pmode)
2639 && ! function_label_operand (operands[2], Pmode)
2643 [(set_attr "type" "binary")
2644 (set_attr "length" "4")])
2647 [(set (match_operand:SI 0 "register_operand" "=r")
2648 (lo_sum:SI (match_operand:SI 1 "register_operand" "r")
2649 (unspec:SI [(match_operand 2 "" "")] UNSPEC_DLTIND14R)))]
2650 "symbolic_operand (operands[2], Pmode)
2651 && ! function_label_operand (operands[2], Pmode)
2654 [(set_attr "type" "binary")
2655 (set_attr "length" "4")])
2658 [(set (match_operand:DI 0 "register_operand" "=r")
2659 (lo_sum:DI (match_operand:DI 1 "register_operand" "r")
2660 (unspec:DI [(match_operand 2 "" "")] UNSPEC_DLTIND14R)))]
2661 "symbolic_operand (operands[2], Pmode)
2662 && ! function_label_operand (operands[2], Pmode)
2666 [(set_attr "type" "binary")
2667 (set_attr "length" "4")])
2669 ;; Always use addil rather than ldil;add sequences. This allows the
2670 ;; HP linker to eliminate the dp relocation if the symbolic operand
2671 ;; lives in the TEXT space.
2673 [(set (match_operand:SI 0 "register_operand" "=a")
2674 (high:SI (match_operand 1 "" "")))]
2675 "symbolic_operand (operands[1], Pmode)
2676 && ! function_label_operand (operands[1], Pmode)
2677 && ! read_only_operand (operands[1], Pmode)
2681 if (TARGET_LONG_LOAD_STORE)
2682 return \"addil NLR'%H1,%%r27\;ldo N'%H1(%%r1),%%r1\";
2684 return \"addil LR'%H1,%%r27\";
2686 [(set_attr "type" "binary")
2687 (set (attr "length")
2688 (if_then_else (not (match_test "TARGET_LONG_LOAD_STORE"))
2693 ;; This is for use in the prologue/epilogue code. We need it
2694 ;; to add large constants to a stack pointer or frame pointer.
2695 ;; Because of the additional %r1 pressure, we probably do not
2696 ;; want to use this in general code, so make it available
2697 ;; only after reload.
2699 [(set (match_operand:SI 0 "register_operand" "=!a,*r")
2700 (plus:SI (match_operand:SI 1 "register_operand" "r,r")
2701 (high:SI (match_operand 2 "const_int_operand" ""))))]
2705 ldil L'%G2,%0\;{addl|add,l} %0,%1,%0"
2706 [(set_attr "type" "binary,binary")
2707 (set_attr "length" "4,8")])
2710 [(set (match_operand:DI 0 "register_operand" "=!a,*r")
2711 (plus:DI (match_operand:DI 1 "register_operand" "r,r")
2712 (high:DI (match_operand 2 "const_int_operand" ""))))]
2713 "reload_completed && TARGET_64BIT"
2716 ldil L'%G2,%0\;{addl|add,l} %0,%1,%0"
2717 [(set_attr "type" "binary,binary")
2718 (set_attr "length" "4,8")])
2721 [(set (match_operand:SI 0 "register_operand" "=r")
2722 (high:SI (match_operand 1 "" "")))]
2723 "(!flag_pic || !symbolic_operand (operands[1], Pmode))
2724 && !pa_is_function_label_plus_const (operands[1])"
2727 if (symbolic_operand (operands[1], Pmode))
2728 return \"ldil LR'%H1,%0\";
2730 return \"ldil L'%G1,%0\";
2732 [(set_attr "type" "move")
2733 (set_attr "length" "4")])
2736 [(set (match_operand:DI 0 "register_operand" "=r")
2737 (high:DI (match_operand 1 "const_int_operand" "")))]
2740 [(set_attr "type" "move")
2741 (set_attr "length" "4")])
2744 [(set (match_operand:DI 0 "register_operand" "=r")
2745 (lo_sum:DI (match_operand:DI 1 "register_operand" "r")
2746 (match_operand:DI 2 "const_int_operand" "i")))]
2749 [(set_attr "type" "move")
2750 (set_attr "length" "4")])
2753 [(set (match_operand:SI 0 "register_operand" "=r")
2754 (lo_sum:SI (match_operand:SI 1 "register_operand" "r")
2755 (match_operand:SI 2 "immediate_operand" "i")))]
2756 "!pa_is_function_label_plus_const (operands[2])"
2759 gcc_assert (!flag_pic || !symbolic_operand (operands[2], Pmode));
2761 if (symbolic_operand (operands[2], Pmode))
2762 return \"ldo RR'%G2(%1),%0\";
2764 return \"ldo R'%G2(%1),%0\";
2766 [(set_attr "type" "move")
2767 (set_attr "length" "4")])
2769 ;; Now that a symbolic_address plus a constant is broken up early
2770 ;; in the compilation phase (for better CSE) we need a special
2771 ;; combiner pattern to load the symbolic address plus the constant
2772 ;; in only 2 instructions. (For cases where the symbolic address
2773 ;; was not a common subexpression.)
2775 [(set (match_operand:SI 0 "register_operand" "")
2776 (match_operand:SI 1 "symbolic_operand" ""))
2777 (clobber (match_operand:SI 2 "register_operand" ""))]
2778 "! (flag_pic && pic_label_operand (operands[1], SImode))"
2779 [(set (match_dup 2) (high:SI (match_dup 1)))
2780 (set (match_dup 0) (lo_sum:SI (match_dup 2) (match_dup 1)))]
2783 ;; hppa_legitimize_address goes to a great deal of trouble to
2784 ;; create addresses which use indexing. In some cases, this
2785 ;; is a lose because there isn't any store instructions which
2786 ;; allow indexed addresses (with integer register source).
2788 ;; These define_splits try to turn a 3 insn store into
2789 ;; a 2 insn store with some creative RTL rewriting.
2791 [(set (mem:SI (plus:SI (mult:SI (match_operand:SI 0 "register_operand" "")
2792 (match_operand:SI 1 "mem_shadd_operand" ""))
2793 (plus:SI (match_operand:SI 2 "register_operand" "")
2794 (match_operand:SI 3 "const_int_operand" ""))))
2795 (match_operand:SI 4 "register_operand" ""))
2796 (clobber (match_operand:SI 5 "register_operand" ""))]
2798 [(set (match_dup 5) (plus:SI (ashift:SI (match_dup 0) (match_dup 1))
2800 (set (mem:SI (plus:SI (match_dup 5) (match_dup 3))) (match_dup 4))]
2803 operands[1] = GEN_INT (exact_log2 (INTVAL (operands[1])));
2808 [(set (mem:HI (plus:SI (mult:SI (match_operand:SI 0 "register_operand" "")
2809 (match_operand:SI 1 "mem_shadd_operand" ""))
2810 (plus:SI (match_operand:SI 2 "register_operand" "")
2811 (match_operand:SI 3 "const_int_operand" ""))))
2812 (match_operand:HI 4 "register_operand" ""))
2813 (clobber (match_operand:SI 5 "register_operand" ""))]
2815 [(set (match_dup 5) (plus:SI (ashift:SI (match_dup 0) (match_dup 1))
2817 (set (mem:HI (plus:SI (match_dup 5) (match_dup 3))) (match_dup 4))]
2820 operands[1] = GEN_INT (exact_log2 (INTVAL (operands[1])));
2825 [(set (mem:QI (plus:SI (mult:SI (match_operand:SI 0 "register_operand" "")
2826 (match_operand:SI 1 "mem_shadd_operand" ""))
2827 (plus:SI (match_operand:SI 2 "register_operand" "")
2828 (match_operand:SI 3 "const_int_operand" ""))))
2829 (match_operand:QI 4 "register_operand" ""))
2830 (clobber (match_operand:SI 5 "register_operand" ""))]
2832 [(set (match_dup 5) (plus:SI (ashift:SI (match_dup 0) (match_dup 1))
2834 (set (mem:QI (plus:SI (match_dup 5) (match_dup 3))) (match_dup 4))]
2837 operands[1] = GEN_INT (exact_log2 (INTVAL (operands[1])));
2841 (define_expand "movhi"
2842 [(set (match_operand:HI 0 "general_operand" "")
2843 (match_operand:HI 1 "general_operand" ""))]
2847 if (pa_emit_move_sequence (operands, HImode, 0))
2851 ;; Handle HImode input reloads requiring a general register as a
2852 ;; scratch register.
2853 (define_expand "reload_inhi"
2854 [(set (match_operand:HI 0 "register_operand" "=Z")
2855 (match_operand:HI 1 "non_hard_reg_operand" ""))
2856 (clobber (match_operand:HI 2 "register_operand" "=&r"))]
2860 if (pa_emit_move_sequence (operands, HImode, operands[2]))
2863 /* We don't want the clobber emitted, so handle this ourselves. */
2864 emit_insn (gen_rtx_SET (operands[0], operands[1]));
2868 ;; Handle HImode output reloads requiring a general register as a
2869 ;; scratch register.
2870 (define_expand "reload_outhi"
2871 [(set (match_operand:HI 0 "non_hard_reg_operand" "")
2872 (match_operand:HI 1 "register_operand" "Z"))
2873 (clobber (match_operand:HI 2 "register_operand" "=&r"))]
2877 if (pa_emit_move_sequence (operands, HImode, operands[2]))
2880 /* We don't want the clobber emitted, so handle this ourselves. */
2881 emit_insn (gen_rtx_SET (operands[0], operands[1]));
2886 [(set (match_operand:HI 0 "move_dest_operand"
2887 "=r,r,r,r,r,Q,!*q,!r")
2888 (match_operand:HI 1 "move_src_operand"
2889 "r,J,N,K,RQ,rM,!rM,!*q"))]
2890 "(register_operand (operands[0], HImode)
2891 || reg_or_0_operand (operands[1], HImode))"
2896 {zdepi|depwi,z} %Z1,%0
2900 {mfctl|mfctl,w} %sar,%0"
2901 [(set_attr "type" "move,move,move,shift,load,store,move,move")
2902 (set_attr "pa_combine_type" "addmove")
2903 (set_attr "length" "4,4,4,4,4,4,4,4")])
2906 [(set (match_operand:HI 0 "register_operand" "=r")
2907 (mem:HI (plus:SI (match_operand:SI 1 "register_operand" "+r")
2908 (match_operand:SI 2 "int5_operand" "L"))))
2910 (plus:SI (match_dup 1) (match_dup 2)))]
2912 "{ldhs|ldh},mb %2(%1),%0"
2913 [(set_attr "type" "load")
2914 (set_attr "length" "4")])
2917 [(set (match_operand:HI 0 "register_operand" "=r")
2918 (mem:HI (plus:DI (match_operand:DI 1 "register_operand" "+r")
2919 (match_operand:DI 2 "int5_operand" "L"))))
2921 (plus:DI (match_dup 1) (match_dup 2)))]
2924 [(set_attr "type" "load")
2925 (set_attr "length" "4")])
2927 ; And a zero extended variant.
2929 [(set (match_operand:DI 0 "register_operand" "=r")
2930 (zero_extend:DI (mem:HI
2932 (match_operand:DI 1 "register_operand" "+r")
2933 (match_operand:DI 2 "int5_operand" "L")))))
2935 (plus:DI (match_dup 1) (match_dup 2)))]
2938 [(set_attr "type" "load")
2939 (set_attr "length" "4")])
2942 [(set (match_operand:SI 0 "register_operand" "=r")
2943 (zero_extend:SI (mem:HI
2945 (match_operand:SI 1 "register_operand" "+r")
2946 (match_operand:SI 2 "int5_operand" "L")))))
2948 (plus:SI (match_dup 1) (match_dup 2)))]
2950 "{ldhs|ldh},mb %2(%1),%0"
2951 [(set_attr "type" "load")
2952 (set_attr "length" "4")])
2955 [(set (match_operand:SI 0 "register_operand" "=r")
2956 (zero_extend:SI (mem:HI
2958 (match_operand:DI 1 "register_operand" "+r")
2959 (match_operand:DI 2 "int5_operand" "L")))))
2961 (plus:DI (match_dup 1) (match_dup 2)))]
2964 [(set_attr "type" "load")
2965 (set_attr "length" "4")])
2968 [(set (mem:HI (plus:SI (match_operand:SI 0 "register_operand" "+r")
2969 (match_operand:SI 1 "int5_operand" "L")))
2970 (match_operand:HI 2 "reg_or_0_operand" "rM"))
2972 (plus:SI (match_dup 0) (match_dup 1)))]
2974 "{sths|sth},mb %r2,%1(%0)"
2975 [(set_attr "type" "store")
2976 (set_attr "length" "4")])
2979 [(set (mem:HI (plus:DI (match_operand:DI 0 "register_operand" "+r")
2980 (match_operand:DI 1 "int5_operand" "L")))
2981 (match_operand:HI 2 "reg_or_0_operand" "rM"))
2983 (plus:DI (match_dup 0) (match_dup 1)))]
2986 [(set_attr "type" "store")
2987 (set_attr "length" "4")])
2989 (define_insn "addhi3"
2990 [(set (match_operand:HI 0 "register_operand" "=r,r")
2991 (plus:HI (match_operand:HI 1 "register_operand" "%r,r")
2992 (match_operand:HI 2 "arith14_operand" "r,J")))]
2995 {addl|add,l} %1,%2,%0
2997 [(set_attr "type" "binary,binary")
2998 (set_attr "pa_combine_type" "addmove")
2999 (set_attr "length" "4,4")])
3001 (define_expand "movqi"
3002 [(set (match_operand:QI 0 "general_operand" "")
3003 (match_operand:QI 1 "general_operand" ""))]
3007 if (pa_emit_move_sequence (operands, QImode, 0))
3011 ;; Handle QImode input reloads requiring a general register as a
3012 ;; scratch register.
3013 (define_expand "reload_inqi"
3014 [(set (match_operand:QI 0 "register_operand" "=Z")
3015 (match_operand:QI 1 "non_hard_reg_operand" ""))
3016 (clobber (match_operand:QI 2 "register_operand" "=&r"))]
3020 if (pa_emit_move_sequence (operands, QImode, operands[2]))
3023 /* We don't want the clobber emitted, so handle this ourselves. */
3024 emit_insn (gen_rtx_SET (operands[0], operands[1]));
3028 ;; Handle QImode output reloads requiring a general register as a
3029 ;; scratch register.
3030 (define_expand "reload_outqi"
3031 [(set (match_operand:QI 0 "non_hard_reg_operand" "")
3032 (match_operand:QI 1 "register_operand" "Z"))
3033 (clobber (match_operand:QI 2 "register_operand" "=&r"))]
3037 if (pa_emit_move_sequence (operands, QImode, operands[2]))
3040 /* We don't want the clobber emitted, so handle this ourselves. */
3041 emit_insn (gen_rtx_SET (operands[0], operands[1]));
3046 [(set (match_operand:QI 0 "move_dest_operand"
3047 "=r,r,r,r,r,Q,!*q,!r")
3048 (match_operand:QI 1 "move_src_operand"
3049 "r,J,N,K,RQ,rM,!rM,!*q"))]
3050 "(register_operand (operands[0], QImode)
3051 || reg_or_0_operand (operands[1], QImode))"
3056 {zdepi|depwi,z} %Z1,%0
3060 {mfctl|mfctl,w} %%sar,%0"
3061 [(set_attr "type" "move,move,move,shift,load,store,move,move")
3062 (set_attr "pa_combine_type" "addmove")
3063 (set_attr "length" "4,4,4,4,4,4,4,4")])
3066 [(set (match_operand:QI 0 "register_operand" "=r")
3067 (mem:QI (plus:SI (match_operand:SI 1 "register_operand" "+r")
3068 (match_operand:SI 2 "int5_operand" "L"))))
3069 (set (match_dup 1) (plus:SI (match_dup 1) (match_dup 2)))]
3071 "{ldbs|ldb},mb %2(%1),%0"
3072 [(set_attr "type" "load")
3073 (set_attr "length" "4")])
3076 [(set (match_operand:QI 0 "register_operand" "=r")
3077 (mem:QI (plus:DI (match_operand:DI 1 "register_operand" "+r")
3078 (match_operand:DI 2 "int5_operand" "L"))))
3079 (set (match_dup 1) (plus:DI (match_dup 1) (match_dup 2)))]
3082 [(set_attr "type" "load")
3083 (set_attr "length" "4")])
3085 ; Now the same thing with zero extensions.
3087 [(set (match_operand:DI 0 "register_operand" "=r")
3088 (zero_extend:DI (mem:QI (plus:DI
3089 (match_operand:DI 1 "register_operand" "+r")
3090 (match_operand:DI 2 "int5_operand" "L")))))
3091 (set (match_dup 1) (plus:DI (match_dup 1) (match_dup 2)))]
3094 [(set_attr "type" "load")
3095 (set_attr "length" "4")])
3098 [(set (match_operand:SI 0 "register_operand" "=r")
3099 (zero_extend:SI (mem:QI (plus:SI
3100 (match_operand:SI 1 "register_operand" "+r")
3101 (match_operand:SI 2 "int5_operand" "L")))))
3102 (set (match_dup 1) (plus:SI (match_dup 1) (match_dup 2)))]
3104 "{ldbs|ldb},mb %2(%1),%0"
3105 [(set_attr "type" "load")
3106 (set_attr "length" "4")])
3109 [(set (match_operand:SI 0 "register_operand" "=r")
3110 (zero_extend:SI (mem:QI (plus:DI
3111 (match_operand:DI 1 "register_operand" "+r")
3112 (match_operand:DI 2 "int5_operand" "L")))))
3113 (set (match_dup 1) (plus:DI (match_dup 1) (match_dup 2)))]
3116 [(set_attr "type" "load")
3117 (set_attr "length" "4")])
3120 [(set (match_operand:HI 0 "register_operand" "=r")
3121 (zero_extend:HI (mem:QI (plus:SI
3122 (match_operand:SI 1 "register_operand" "+r")
3123 (match_operand:SI 2 "int5_operand" "L")))))
3124 (set (match_dup 1) (plus:SI (match_dup 1) (match_dup 2)))]
3126 "{ldbs|ldb},mb %2(%1),%0"
3127 [(set_attr "type" "load")
3128 (set_attr "length" "4")])
3131 [(set (match_operand:HI 0 "register_operand" "=r")
3132 (zero_extend:HI (mem:QI (plus:DI
3133 (match_operand:DI 1 "register_operand" "+r")
3134 (match_operand:DI 2 "int5_operand" "L")))))
3135 (set (match_dup 1) (plus:DI (match_dup 1) (match_dup 2)))]
3138 [(set_attr "type" "load")
3139 (set_attr "length" "4")])
3142 [(set (mem:QI (plus:SI (match_operand:SI 0 "register_operand" "+r")
3143 (match_operand:SI 1 "int5_operand" "L")))
3144 (match_operand:QI 2 "reg_or_0_operand" "rM"))
3146 (plus:SI (match_dup 0) (match_dup 1)))]
3148 "{stbs|stb},mb %r2,%1(%0)"
3149 [(set_attr "type" "store")
3150 (set_attr "length" "4")])
3153 [(set (mem:QI (plus:DI (match_operand:DI 0 "register_operand" "+r")
3154 (match_operand:DI 1 "int5_operand" "L")))
3155 (match_operand:QI 2 "reg_or_0_operand" "rM"))
3157 (plus:DI (match_dup 0) (match_dup 1)))]
3160 [(set_attr "type" "store")
3161 (set_attr "length" "4")])
3163 ;; The definition of this insn does not really explain what it does,
3164 ;; but it should suffice that anything generated as this insn will be
3165 ;; recognized as a cpymemsi operation, and that it will not successfully
3166 ;; combine with anything.
3167 (define_expand "cpymemsi"
3168 [(parallel [(set (match_operand:BLK 0 "" "")
3169 (match_operand:BLK 1 "" ""))
3170 (clobber (match_dup 4))
3171 (clobber (match_dup 5))
3172 (clobber (match_dup 6))
3173 (clobber (match_dup 7))
3174 (clobber (match_dup 8))
3175 (use (match_operand:SI 2 "arith14_operand" ""))
3176 (use (match_operand:SI 3 "const_int_operand" ""))])]
3177 "!TARGET_64BIT && optimize > 0"
3182 /* HP provides very fast block move library routine for the PA;
3183 this routine includes:
3185 4x4 byte at a time block moves,
3186 1x4 byte at a time with alignment checked at runtime with
3187 attempts to align the source and destination as needed
3190 With that in mind, here's the heuristics to try and guess when
3191 the inlined block move will be better than the library block
3194 If the size isn't constant, then always use the library routines.
3196 If the size is large in respect to the known alignment, then use
3197 the library routines.
3199 If the size is small in respect to the known alignment, then open
3200 code the copy (since that will lead to better scheduling).
3202 Else use the block move pattern. */
3204 /* Undetermined size, use the library routine. */
3205 if (GET_CODE (operands[2]) != CONST_INT)
3208 size = INTVAL (operands[2]);
3209 align = INTVAL (operands[3]);
3210 align = align > 4 ? 4 : (align ? align : 1);
3212 /* If size/alignment is large, then use the library routines. */
3213 if (size / align > 16)
3216 /* This does happen, but not often enough to worry much about. */
3217 if (size / align < MOVE_RATIO (optimize_insn_for_speed_p ()))
3220 /* Fall through means we're going to use our block move pattern. */
3222 = replace_equiv_address (operands[0],
3223 copy_to_mode_reg (SImode, XEXP (operands[0], 0)));
3225 = replace_equiv_address (operands[1],
3226 copy_to_mode_reg (SImode, XEXP (operands[1], 0)));
3227 operands[4] = gen_reg_rtx (SImode);
3228 operands[5] = gen_reg_rtx (SImode);
3229 operands[6] = gen_reg_rtx (SImode);
3230 operands[7] = gen_reg_rtx (SImode);
3231 operands[8] = gen_reg_rtx (SImode);
3234 ;; The operand constraints are written like this to support both compile-time
3235 ;; and run-time determined byte counts. The expander and pa_output_block_move
3236 ;; only support compile-time determined counts at this time.
3238 ;; If the count is run-time determined, the register with the byte count
3239 ;; is clobbered by the copying code, and therefore it is forced to operand 2.
3241 ;; We used to clobber operands 0 and 1. However, a change to regrename.c
3242 ;; broke this semantic for pseudo registers. We can't use match_scratch
3243 ;; as this requires two registers in the class R1_REGS when the MEMs for
3244 ;; operands 0 and 1 are both equivalent to symbolic MEMs. Thus, we are
3245 ;; forced to internally copy operands 0 and 1 to operands 7 and 8,
3246 ;; respectively. We then split or peephole optimize after reload.
3247 (define_insn "cpymemsi_prereload"
3248 [(set (mem:BLK (match_operand:SI 0 "register_operand" "r,r"))
3249 (mem:BLK (match_operand:SI 1 "register_operand" "r,r")))
3250 (clobber (match_operand:SI 2 "register_operand" "=&r,&r")) ;loop cnt/tmp
3251 (clobber (match_operand:SI 3 "register_operand" "=&r,&r")) ;item tmp1
3252 (clobber (match_operand:SI 6 "register_operand" "=&r,&r")) ;item tmp2
3253 (clobber (match_operand:SI 7 "register_operand" "=&r,&r")) ;item tmp3
3254 (clobber (match_operand:SI 8 "register_operand" "=&r,&r")) ;item tmp4
3255 (use (match_operand:SI 4 "arith14_operand" "J,2")) ;byte count
3256 (use (match_operand:SI 5 "const_int_operand" "n,n"))] ;alignment
3259 [(set_attr "type" "multi,multi")])
3262 [(parallel [(set (match_operand:BLK 0 "memory_operand" "")
3263 (match_operand:BLK 1 "memory_operand" ""))
3264 (clobber (match_operand:SI 2 "register_operand" ""))
3265 (clobber (match_operand:SI 3 "register_operand" ""))
3266 (clobber (match_operand:SI 6 "register_operand" ""))
3267 (clobber (match_operand:SI 7 "register_operand" ""))
3268 (clobber (match_operand:SI 8 "register_operand" ""))
3269 (use (match_operand:SI 4 "arith14_operand" ""))
3270 (use (match_operand:SI 5 "const_int_operand" ""))])]
3271 "!TARGET_64BIT && reload_completed && !flag_peephole2
3272 && GET_CODE (operands[0]) == MEM
3273 && register_operand (XEXP (operands[0], 0), SImode)
3274 && GET_CODE (operands[1]) == MEM
3275 && register_operand (XEXP (operands[1], 0), SImode)"
3276 [(set (match_dup 7) (match_dup 9))
3277 (set (match_dup 8) (match_dup 10))
3278 (parallel [(set (match_dup 0) (match_dup 1))
3279 (clobber (match_dup 2))
3280 (clobber (match_dup 3))
3281 (clobber (match_dup 6))
3282 (clobber (match_dup 7))
3283 (clobber (match_dup 8))
3289 operands[9] = XEXP (operands[0], 0);
3290 operands[10] = XEXP (operands[1], 0);
3291 operands[0] = replace_equiv_address (operands[0], operands[7]);
3292 operands[1] = replace_equiv_address (operands[1], operands[8]);
3296 [(parallel [(set (match_operand:BLK 0 "memory_operand" "")
3297 (match_operand:BLK 1 "memory_operand" ""))
3298 (clobber (match_operand:SI 2 "register_operand" ""))
3299 (clobber (match_operand:SI 3 "register_operand" ""))
3300 (clobber (match_operand:SI 6 "register_operand" ""))
3301 (clobber (match_operand:SI 7 "register_operand" ""))
3302 (clobber (match_operand:SI 8 "register_operand" ""))
3303 (use (match_operand:SI 4 "arith14_operand" ""))
3304 (use (match_operand:SI 5 "const_int_operand" ""))])]
3306 && GET_CODE (operands[0]) == MEM
3307 && register_operand (XEXP (operands[0], 0), SImode)
3308 && GET_CODE (operands[1]) == MEM
3309 && register_operand (XEXP (operands[1], 0), SImode)"
3310 [(parallel [(set (match_dup 0) (match_dup 1))
3311 (clobber (match_dup 2))
3312 (clobber (match_dup 3))
3313 (clobber (match_dup 6))
3314 (clobber (match_dup 7))
3315 (clobber (match_dup 8))
3321 rtx addr = XEXP (operands[0], 0);
3322 if (dead_or_set_p (curr_insn, addr))
3326 emit_insn (gen_rtx_SET (operands[7], addr));
3327 operands[0] = replace_equiv_address (operands[0], operands[7]);
3330 addr = XEXP (operands[1], 0);
3331 if (dead_or_set_p (curr_insn, addr))
3335 emit_insn (gen_rtx_SET (operands[8], addr));
3336 operands[1] = replace_equiv_address (operands[1], operands[8]);
3340 (define_insn "cpymemsi_postreload"
3341 [(set (mem:BLK (match_operand:SI 0 "register_operand" "+r,r"))
3342 (mem:BLK (match_operand:SI 1 "register_operand" "+r,r")))
3343 (clobber (match_operand:SI 2 "register_operand" "=&r,&r")) ;loop cnt/tmp
3344 (clobber (match_operand:SI 3 "register_operand" "=&r,&r")) ;item tmp1
3345 (clobber (match_operand:SI 6 "register_operand" "=&r,&r")) ;item tmp2
3346 (clobber (match_dup 0))
3347 (clobber (match_dup 1))
3348 (use (match_operand:SI 4 "arith14_operand" "J,2")) ;byte count
3349 (use (match_operand:SI 5 "const_int_operand" "n,n")) ;alignment
3351 "!TARGET_64BIT && reload_completed"
3352 "* return pa_output_block_move (operands, !which_alternative);"
3353 [(set_attr "type" "multi,multi")])
3355 (define_expand "cpymemdi"
3356 [(parallel [(set (match_operand:BLK 0 "" "")
3357 (match_operand:BLK 1 "" ""))
3358 (clobber (match_dup 4))
3359 (clobber (match_dup 5))
3360 (clobber (match_dup 6))
3361 (clobber (match_dup 7))
3362 (clobber (match_dup 8))
3363 (use (match_operand:DI 2 "arith14_operand" ""))
3364 (use (match_operand:DI 3 "const_int_operand" ""))])]
3365 "TARGET_64BIT && optimize > 0"
3370 /* HP provides very fast block move library routine for the PA;
3371 this routine includes:
3373 4x4 byte at a time block moves,
3374 1x4 byte at a time with alignment checked at runtime with
3375 attempts to align the source and destination as needed
3378 With that in mind, here's the heuristics to try and guess when
3379 the inlined block move will be better than the library block
3382 If the size isn't constant, then always use the library routines.
3384 If the size is large in respect to the known alignment, then use
3385 the library routines.
3387 If the size is small in respect to the known alignment, then open
3388 code the copy (since that will lead to better scheduling).
3390 Else use the block move pattern. */
3392 /* Undetermined size, use the library routine. */
3393 if (GET_CODE (operands[2]) != CONST_INT)
3396 size = INTVAL (operands[2]);
3397 align = INTVAL (operands[3]);
3398 align = align > 8 ? 8 : (align ? align : 1);
3400 /* If size/alignment is large, then use the library routines. */
3401 if (size / align > 16)
3404 /* This does happen, but not often enough to worry much about. */
3405 if (size / align < MOVE_RATIO (optimize_insn_for_speed_p ()))
3408 /* Fall through means we're going to use our block move pattern. */
3410 = replace_equiv_address (operands[0],
3411 copy_to_mode_reg (DImode, XEXP (operands[0], 0)));
3413 = replace_equiv_address (operands[1],
3414 copy_to_mode_reg (DImode, XEXP (operands[1], 0)));
3415 operands[4] = gen_reg_rtx (DImode);
3416 operands[5] = gen_reg_rtx (DImode);
3417 operands[6] = gen_reg_rtx (DImode);
3418 operands[7] = gen_reg_rtx (DImode);
3419 operands[8] = gen_reg_rtx (DImode);
3422 ;; The operand constraints are written like this to support both compile-time
3423 ;; and run-time determined byte counts. The expander and pa_output_block_move
3424 ;; only support compile-time determined counts at this time.
3426 ;; If the count is run-time determined, the register with the byte count
3427 ;; is clobbered by the copying code, and therefore it is forced to operand 2.
3429 ;; We used to clobber operands 0 and 1. However, a change to regrename.c
3430 ;; broke this semantic for pseudo registers. We can't use match_scratch
3431 ;; as this requires two registers in the class R1_REGS when the MEMs for
3432 ;; operands 0 and 1 are both equivalent to symbolic MEMs. Thus, we are
3433 ;; forced to internally copy operands 0 and 1 to operands 7 and 8,
3434 ;; respectively. We then split or peephole optimize after reload.
3435 (define_insn "cpymemdi_prereload"
3436 [(set (mem:BLK (match_operand:DI 0 "register_operand" "r,r"))
3437 (mem:BLK (match_operand:DI 1 "register_operand" "r,r")))
3438 (clobber (match_operand:DI 2 "register_operand" "=&r,&r")) ;loop cnt/tmp
3439 (clobber (match_operand:DI 3 "register_operand" "=&r,&r")) ;item tmp1
3440 (clobber (match_operand:DI 6 "register_operand" "=&r,&r")) ;item tmp2
3441 (clobber (match_operand:DI 7 "register_operand" "=&r,&r")) ;item tmp3
3442 (clobber (match_operand:DI 8 "register_operand" "=&r,&r")) ;item tmp4
3443 (use (match_operand:DI 4 "arith14_operand" "J,2")) ;byte count
3444 (use (match_operand:DI 5 "const_int_operand" "n,n"))] ;alignment
3447 [(set_attr "type" "multi,multi")])
3450 [(parallel [(set (match_operand:BLK 0 "memory_operand" "")
3451 (match_operand:BLK 1 "memory_operand" ""))
3452 (clobber (match_operand:DI 2 "register_operand" ""))
3453 (clobber (match_operand:DI 3 "register_operand" ""))
3454 (clobber (match_operand:DI 6 "register_operand" ""))
3455 (clobber (match_operand:DI 7 "register_operand" ""))
3456 (clobber (match_operand:DI 8 "register_operand" ""))
3457 (use (match_operand:DI 4 "arith14_operand" ""))
3458 (use (match_operand:DI 5 "const_int_operand" ""))])]
3459 "TARGET_64BIT && reload_completed && !flag_peephole2
3460 && GET_CODE (operands[0]) == MEM
3461 && register_operand (XEXP (operands[0], 0), DImode)
3462 && GET_CODE (operands[1]) == MEM
3463 && register_operand (XEXP (operands[1], 0), DImode)"
3464 [(set (match_dup 7) (match_dup 9))
3465 (set (match_dup 8) (match_dup 10))
3466 (parallel [(set (match_dup 0) (match_dup 1))
3467 (clobber (match_dup 2))
3468 (clobber (match_dup 3))
3469 (clobber (match_dup 6))
3470 (clobber (match_dup 7))
3471 (clobber (match_dup 8))
3477 operands[9] = XEXP (operands[0], 0);
3478 operands[10] = XEXP (operands[1], 0);
3479 operands[0] = replace_equiv_address (operands[0], operands[7]);
3480 operands[1] = replace_equiv_address (operands[1], operands[8]);
3484 [(parallel [(set (match_operand:BLK 0 "memory_operand" "")
3485 (match_operand:BLK 1 "memory_operand" ""))
3486 (clobber (match_operand:DI 2 "register_operand" ""))
3487 (clobber (match_operand:DI 3 "register_operand" ""))
3488 (clobber (match_operand:DI 6 "register_operand" ""))
3489 (clobber (match_operand:DI 7 "register_operand" ""))
3490 (clobber (match_operand:DI 8 "register_operand" ""))
3491 (use (match_operand:DI 4 "arith14_operand" ""))
3492 (use (match_operand:DI 5 "const_int_operand" ""))])]
3494 && GET_CODE (operands[0]) == MEM
3495 && register_operand (XEXP (operands[0], 0), DImode)
3496 && GET_CODE (operands[1]) == MEM
3497 && register_operand (XEXP (operands[1], 0), DImode)"
3498 [(parallel [(set (match_dup 0) (match_dup 1))
3499 (clobber (match_dup 2))
3500 (clobber (match_dup 3))
3501 (clobber (match_dup 6))
3502 (clobber (match_dup 7))
3503 (clobber (match_dup 8))
3509 rtx addr = XEXP (operands[0], 0);
3510 if (dead_or_set_p (curr_insn, addr))
3514 emit_insn (gen_rtx_SET (operands[7], addr));
3515 operands[0] = replace_equiv_address (operands[0], operands[7]);
3518 addr = XEXP (operands[1], 0);
3519 if (dead_or_set_p (curr_insn, addr))
3523 emit_insn (gen_rtx_SET (operands[8], addr));
3524 operands[1] = replace_equiv_address (operands[1], operands[8]);
3528 (define_insn "cpymemdi_postreload"
3529 [(set (mem:BLK (match_operand:DI 0 "register_operand" "+r,r"))
3530 (mem:BLK (match_operand:DI 1 "register_operand" "+r,r")))
3531 (clobber (match_operand:DI 2 "register_operand" "=&r,&r")) ;loop cnt/tmp
3532 (clobber (match_operand:DI 3 "register_operand" "=&r,&r")) ;item tmp1
3533 (clobber (match_operand:DI 6 "register_operand" "=&r,&r")) ;item tmp2
3534 (clobber (match_dup 0))
3535 (clobber (match_dup 1))
3536 (use (match_operand:DI 4 "arith14_operand" "J,2")) ;byte count
3537 (use (match_operand:DI 5 "const_int_operand" "n,n")) ;alignment
3539 "TARGET_64BIT && reload_completed"
3540 "* return pa_output_block_move (operands, !which_alternative);"
3541 [(set_attr "type" "multi,multi")])
3543 (define_expand "setmemsi"
3544 [(parallel [(set (match_operand:BLK 0 "" "")
3545 (match_operand 2 "const_int_operand" ""))
3546 (clobber (match_dup 4))
3547 (clobber (match_dup 5))
3548 (use (match_operand:SI 1 "arith14_operand" ""))
3549 (use (match_operand:SI 3 "const_int_operand" ""))])]
3550 "!TARGET_64BIT && optimize > 0"
3555 /* If value to set is not zero, use the library routine. */
3556 if (operands[2] != const0_rtx)
3559 /* Undetermined size, use the library routine. */
3560 if (GET_CODE (operands[1]) != CONST_INT)
3563 size = INTVAL (operands[1]);
3564 align = INTVAL (operands[3]);
3565 align = align > 4 ? 4 : align;
3567 /* If size/alignment is large, then use the library routines. */
3568 if (size / align > 16)
3571 /* This does happen, but not often enough to worry much about. */
3572 if (size / align < MOVE_RATIO (optimize_insn_for_speed_p ()))
3575 /* Fall through means we're going to use our block clear pattern. */
3577 = replace_equiv_address (operands[0],
3578 copy_to_mode_reg (SImode, XEXP (operands[0], 0)));
3579 operands[4] = gen_reg_rtx (SImode);
3580 operands[5] = gen_reg_rtx (SImode);
3583 (define_insn "clrmemsi_prereload"
3584 [(set (mem:BLK (match_operand:SI 0 "register_operand" "r,r"))
3586 (clobber (match_operand:SI 1 "register_operand" "=&r,&r")) ;loop cnt/tmp
3587 (clobber (match_operand:SI 4 "register_operand" "=&r,&r")) ;tmp1
3588 (use (match_operand:SI 2 "arith14_operand" "J,1")) ;byte count
3589 (use (match_operand:SI 3 "const_int_operand" "n,n"))] ;alignment
3592 [(set_attr "type" "multi,multi")])
3595 [(parallel [(set (match_operand:BLK 0 "memory_operand" "")
3597 (clobber (match_operand:SI 1 "register_operand" ""))
3598 (clobber (match_operand:SI 4 "register_operand" ""))
3599 (use (match_operand:SI 2 "arith14_operand" ""))
3600 (use (match_operand:SI 3 "const_int_operand" ""))])]
3601 "!TARGET_64BIT && reload_completed && !flag_peephole2
3602 && GET_CODE (operands[0]) == MEM
3603 && register_operand (XEXP (operands[0], 0), SImode)"
3604 [(set (match_dup 4) (match_dup 5))
3605 (parallel [(set (match_dup 0) (const_int 0))
3606 (clobber (match_dup 1))
3607 (clobber (match_dup 4))
3613 operands[5] = XEXP (operands[0], 0);
3614 operands[0] = replace_equiv_address (operands[0], operands[4]);
3618 [(parallel [(set (match_operand:BLK 0 "memory_operand" "")
3620 (clobber (match_operand:SI 1 "register_operand" ""))
3621 (clobber (match_operand:SI 4 "register_operand" ""))
3622 (use (match_operand:SI 2 "arith14_operand" ""))
3623 (use (match_operand:SI 3 "const_int_operand" ""))])]
3625 && GET_CODE (operands[0]) == MEM
3626 && register_operand (XEXP (operands[0], 0), SImode)"
3627 [(parallel [(set (match_dup 0) (const_int 0))
3628 (clobber (match_dup 1))
3629 (clobber (match_dup 4))
3635 rtx addr = XEXP (operands[0], 0);
3636 if (dead_or_set_p (curr_insn, addr))
3640 emit_insn (gen_rtx_SET (operands[4], addr));
3641 operands[0] = replace_equiv_address (operands[0], operands[4]);
3645 (define_insn "clrmemsi_postreload"
3646 [(set (mem:BLK (match_operand:SI 0 "register_operand" "+r,r"))
3648 (clobber (match_operand:SI 1 "register_operand" "=&r,&r")) ;loop cnt/tmp
3649 (clobber (match_dup 0))
3650 (use (match_operand:SI 2 "arith14_operand" "J,1")) ;byte count
3651 (use (match_operand:SI 3 "const_int_operand" "n,n")) ;alignment
3653 "!TARGET_64BIT && reload_completed"
3654 "* return pa_output_block_clear (operands, !which_alternative);"
3655 [(set_attr "type" "multi,multi")])
3657 (define_expand "setmemdi"
3658 [(parallel [(set (match_operand:BLK 0 "" "")
3659 (match_operand 2 "const_int_operand" ""))
3660 (clobber (match_dup 4))
3661 (clobber (match_dup 5))
3662 (use (match_operand:DI 1 "arith14_operand" ""))
3663 (use (match_operand:DI 3 "const_int_operand" ""))])]
3664 "TARGET_64BIT && optimize > 0"
3669 /* If value to set is not zero, use the library routine. */
3670 if (operands[2] != const0_rtx)
3673 /* Undetermined size, use the library routine. */
3674 if (GET_CODE (operands[1]) != CONST_INT)
3677 size = INTVAL (operands[1]);
3678 align = INTVAL (operands[3]);
3679 align = align > 8 ? 8 : align;
3681 /* If size/alignment is large, then use the library routines. */
3682 if (size / align > 16)
3685 /* This does happen, but not often enough to worry much about. */
3686 if (size / align < MOVE_RATIO (optimize_insn_for_speed_p ()))
3689 /* Fall through means we're going to use our block clear pattern. */
3691 = replace_equiv_address (operands[0],
3692 copy_to_mode_reg (DImode, XEXP (operands[0], 0)));
3693 operands[4] = gen_reg_rtx (DImode);
3694 operands[5] = gen_reg_rtx (DImode);
3697 (define_insn "clrmemdi_prereload"
3698 [(set (mem:BLK (match_operand:DI 0 "register_operand" "r,r"))
3700 (clobber (match_operand:DI 1 "register_operand" "=&r,&r")) ;loop cnt/tmp
3701 (clobber (match_operand:DI 4 "register_operand" "=&r,&r")) ;item tmp1
3702 (use (match_operand:DI 2 "arith14_operand" "J,1")) ;byte count
3703 (use (match_operand:DI 3 "const_int_operand" "n,n"))] ;alignment
3706 [(set_attr "type" "multi,multi")])
3709 [(parallel [(set (match_operand:BLK 0 "memory_operand" "")
3711 (clobber (match_operand:DI 1 "register_operand" ""))
3712 (clobber (match_operand:DI 4 "register_operand" ""))
3713 (use (match_operand:DI 2 "arith14_operand" ""))
3714 (use (match_operand:DI 3 "const_int_operand" ""))])]
3715 "TARGET_64BIT && reload_completed && !flag_peephole2
3716 && GET_CODE (operands[0]) == MEM
3717 && register_operand (XEXP (operands[0], 0), DImode)"
3718 [(set (match_dup 4) (match_dup 5))
3719 (parallel [(set (match_dup 0) (const_int 0))
3720 (clobber (match_dup 1))
3721 (clobber (match_dup 4))
3727 operands[5] = XEXP (operands[0], 0);
3728 operands[0] = replace_equiv_address (operands[0], operands[4]);
3732 [(parallel [(set (match_operand:BLK 0 "memory_operand" "")
3734 (clobber (match_operand:DI 1 "register_operand" ""))
3735 (clobber (match_operand:DI 4 "register_operand" ""))
3736 (use (match_operand:DI 2 "arith14_operand" ""))
3737 (use (match_operand:DI 3 "const_int_operand" ""))])]
3739 && GET_CODE (operands[0]) == MEM
3740 && register_operand (XEXP (operands[0], 0), DImode)"
3741 [(parallel [(set (match_dup 0) (const_int 0))
3742 (clobber (match_dup 1))
3743 (clobber (match_dup 4))
3749 rtx addr = XEXP (operands[0], 0);
3750 if (dead_or_set_p (curr_insn, addr))
3754 emit_insn (gen_rtx_SET (operands[4], addr));
3755 operands[0] = replace_equiv_address (operands[0], operands[4]);
3759 (define_insn "clrmemdi_postreload"
3760 [(set (mem:BLK (match_operand:DI 0 "register_operand" "+r,r"))
3762 (clobber (match_operand:DI 1 "register_operand" "=&r,&r")) ;loop cnt/tmp
3763 (clobber (match_dup 0))
3764 (use (match_operand:DI 2 "arith14_operand" "J,1")) ;byte count
3765 (use (match_operand:DI 3 "const_int_operand" "n,n")) ;alignment
3767 "TARGET_64BIT && reload_completed"
3768 "* return pa_output_block_clear (operands, !which_alternative);"
3769 [(set_attr "type" "multi,multi")])
3771 ;; Floating point move insns
3773 (define_expand "movdf"
3774 [(set (match_operand:DF 0 "general_operand" "")
3775 (match_operand:DF 1 "general_operand" ""))]
3779 if (pa_emit_move_sequence (operands, DFmode, 0))
3783 ;; Handle DFmode input reloads requiring %r1 as a scratch register.
3784 (define_expand "reload_indf_r1"
3785 [(set (match_operand:DF 0 "register_operand" "=Z")
3786 (match_operand:DF 1 "non_hard_reg_operand" ""))
3787 (clobber (match_operand:SI 2 "register_operand" "=&a"))]
3791 if (pa_emit_move_sequence (operands, DFmode, operands[2]))
3794 /* We don't want the clobber emitted, so handle this ourselves. */
3795 emit_insn (gen_rtx_SET (operands[0], operands[1]));
3799 ;; Handle DFmode input reloads requiring a general register as a
3800 ;; scratch register.
3801 (define_expand "reload_indf"
3802 [(set (match_operand:DF 0 "register_operand" "=Z")
3803 (match_operand:DF 1 "non_hard_reg_operand" ""))
3804 (clobber (match_operand:DF 2 "register_operand" "=&r"))]
3808 if (pa_emit_move_sequence (operands, DFmode, operands[2]))
3811 /* We don't want the clobber emitted, so handle this ourselves. */
3812 emit_insn (gen_rtx_SET (operands[0], operands[1]));
3816 ;; Handle DFmode output reloads requiring a general register as a
3817 ;; scratch register.
3818 (define_expand "reload_outdf"
3819 [(set (match_operand:DF 0 "non_hard_reg_operand" "")
3820 (match_operand:DF 1 "register_operand" "Z"))
3821 (clobber (match_operand:DF 2 "register_operand" "=&r"))]
3825 if (pa_emit_move_sequence (operands, DFmode, operands[2]))
3828 /* We don't want the clobber emitted, so handle this ourselves. */
3829 emit_insn (gen_rtx_SET (operands[0], operands[1]));
3834 [(set (match_operand:DF 0 "move_dest_operand"
3835 "=f,*r,T,?o,?Q,f,*r,*r,?*r,?f")
3836 (match_operand:DF 1 "reg_or_0_or_nonsymb_mem_operand"
3837 "fG,*rG,f,*r,*r,RT,o,RQ,f,*r"))]
3838 "(register_operand (operands[0], DFmode)
3839 || reg_or_0_operand (operands[1], DFmode))
3840 && !(GET_CODE (operands[1]) == CONST_DOUBLE
3841 && GET_CODE (operands[0]) == MEM)
3843 && !TARGET_SOFT_FLOAT"
3846 if ((FP_REG_P (operands[0]) || FP_REG_P (operands[1])
3847 || operands[1] == CONST0_RTX (DFmode))
3848 && !(REG_P (operands[0]) && REG_P (operands[1])
3849 && FP_REG_P (operands[0]) ^ FP_REG_P (operands[1])))
3850 return pa_output_fp_move_double (operands);
3851 return pa_output_move_double (operands);
3853 [(set_attr "type" "fpalu,move,fpstore,store,store,fpload,load,load,fpstore_load,store_fpload")
3854 (set_attr "length" "4,8,4,8,16,4,8,16,12,12")])
3857 [(set (match_operand:DF 0 "indexed_memory_operand" "=R")
3858 (match_operand:DF 1 "reg_or_0_operand" "f"))]
3860 && !TARGET_DISABLE_INDEXING
3861 && reload_completed"
3863 [(set_attr "type" "fpstore")
3864 (set_attr "pa_combine_type" "addmove")
3865 (set_attr "length" "4")])
3868 [(set (match_operand:SI 0 "register_operand" "")
3869 (plus:SI (ashift:SI (match_operand:SI 1 "register_operand" "")
3871 (match_operand:SI 2 "register_operand" "")))
3872 (set (mem:DF (match_dup 0))
3873 (match_operand:DF 3 "register_operand" ""))]
3875 && !TARGET_DISABLE_INDEXING
3876 && REG_OK_FOR_BASE_P (operands[2])
3877 && FP_REGNO_P (REGNO (operands[3]))"
3878 [(set (mem:DF (plus:SI (mult:SI (match_dup 1) (const_int 8)) (match_dup 2)))
3880 (set (match_dup 0) (plus:SI (ashift:SI (match_dup 1) (const_int 3))
3885 [(set (match_operand:SI 0 "register_operand" "")
3886 (plus:SI (match_operand:SI 2 "register_operand" "")
3887 (ashift:SI (match_operand:SI 1 "register_operand" "")
3889 (set (mem:DF (match_dup 0))
3890 (match_operand:DF 3 "register_operand" ""))]
3892 && !TARGET_DISABLE_INDEXING
3893 && REG_OK_FOR_BASE_P (operands[2])
3894 && FP_REGNO_P (REGNO (operands[3]))"
3895 [(set (mem:DF (plus:SI (mult:SI (match_dup 1) (const_int 8)) (match_dup 2)))
3897 (set (match_dup 0) (plus:SI (ashift:SI (match_dup 1) (const_int 3))
3902 [(set (match_operand:DI 0 "register_operand" "")
3903 (plus:DI (ashift:DI (match_operand:DI 1 "register_operand" "")
3905 (match_operand:DI 2 "register_operand" "")))
3906 (set (mem:DF (match_dup 0))
3907 (match_operand:DF 3 "register_operand" ""))]
3909 && !TARGET_DISABLE_INDEXING
3911 && REG_OK_FOR_BASE_P (operands[2])
3912 && FP_REGNO_P (REGNO (operands[3]))"
3913 [(set (mem:DF (plus:DI (mult:DI (match_dup 1) (const_int 8)) (match_dup 2)))
3915 (set (match_dup 0) (plus:DI (ashift:DI (match_dup 1) (const_int 3))
3920 [(set (match_operand:DI 0 "register_operand" "")
3921 (plus:DI (match_operand:DI 2 "register_operand" "")
3922 (ashift:DI (match_operand:DI 1 "register_operand" "")
3924 (set (mem:DF (match_dup 0))
3925 (match_operand:DF 3 "register_operand" ""))]
3927 && !TARGET_DISABLE_INDEXING
3929 && REG_OK_FOR_BASE_P (operands[2])
3930 && FP_REGNO_P (REGNO (operands[3]))"
3931 [(set (mem:DF (plus:DI (mult:DI (match_dup 1) (const_int 8)) (match_dup 2)))
3933 (set (match_dup 0) (plus:DI (ashift:DI (match_dup 1) (const_int 3))
3938 [(set (match_operand:SI 0 "register_operand" "")
3939 (plus:SI (match_operand:SI 1 "register_operand" "")
3940 (match_operand:SI 2 "register_operand" "")))
3941 (set (mem:DF (match_dup 0))
3942 (match_operand:DF 3 "register_operand" ""))]
3944 && !TARGET_DISABLE_INDEXING
3945 && TARGET_NO_SPACE_REGS
3946 && REG_OK_FOR_INDEX_P (operands[1])
3947 && REG_OK_FOR_BASE_P (operands[2])
3948 && FP_REGNO_P (REGNO (operands[3]))"
3949 [(set (mem:DF (plus:SI (match_dup 1) (match_dup 2)))
3951 (set (match_dup 0) (plus:SI (match_dup 1) (match_dup 2)))]
3955 [(set (match_operand:SI 0 "register_operand" "")
3956 (plus:SI (match_operand:SI 1 "register_operand" "")
3957 (match_operand:SI 2 "register_operand" "")))
3958 (set (mem:DF (match_dup 0))
3959 (match_operand:DF 3 "register_operand" ""))]
3961 && !TARGET_DISABLE_INDEXING
3962 && TARGET_NO_SPACE_REGS
3963 && REG_OK_FOR_BASE_P (operands[1])
3964 && REG_OK_FOR_INDEX_P (operands[2])
3965 && FP_REGNO_P (REGNO (operands[3]))"
3966 [(set (mem:DF (plus:SI (match_dup 2) (match_dup 1)))
3968 (set (match_dup 0) (plus:SI (match_dup 2) (match_dup 1)))]
3972 [(set (match_operand:DI 0 "register_operand" "")
3973 (plus:DI (match_operand:DI 1 "register_operand" "")
3974 (match_operand:DI 2 "register_operand" "")))
3975 (set (mem:DF (match_dup 0))
3976 (match_operand:DF 3 "register_operand" ""))]
3978 && !TARGET_DISABLE_INDEXING
3980 && TARGET_NO_SPACE_REGS
3981 && REG_OK_FOR_INDEX_P (operands[1])
3982 && REG_OK_FOR_BASE_P (operands[2])
3983 && FP_REGNO_P (REGNO (operands[3]))"
3984 [(set (mem:DF (plus:DI (match_dup 1) (match_dup 2)))
3986 (set (match_dup 0) (plus:DI (match_dup 1) (match_dup 2)))]
3990 [(set (match_operand:DI 0 "register_operand" "")
3991 (plus:DI (match_operand:DI 1 "register_operand" "")
3992 (match_operand:DI 2 "register_operand" "")))
3993 (set (mem:DF (match_dup 0))
3994 (match_operand:DF 3 "register_operand" ""))]
3996 && !TARGET_DISABLE_INDEXING
3998 && TARGET_NO_SPACE_REGS
3999 && REG_OK_FOR_BASE_P (operands[1])
4000 && REG_OK_FOR_INDEX_P (operands[2])
4001 && FP_REGNO_P (REGNO (operands[3]))"
4002 [(set (mem:DF (plus:DI (match_dup 2) (match_dup 1)))
4004 (set (match_dup 0) (plus:DI (match_dup 2) (match_dup 1)))]
4008 [(set (match_operand:DF 0 "move_dest_operand"
4010 (match_operand:DF 1 "reg_or_0_or_nonsymb_mem_operand"
4012 "(register_operand (operands[0], DFmode)
4013 || reg_or_0_operand (operands[1], DFmode))
4015 && TARGET_SOFT_FLOAT"
4018 return pa_output_move_double (operands);
4020 [(set_attr "type" "move,store,store,load,load")
4021 (set_attr "length" "8,8,16,8,16")])
4024 [(set (match_operand:DF 0 "move_dest_operand"
4025 "=!*r,*r,*r,*r,*r,Q,f,f,T")
4026 (match_operand:DF 1 "move_src_operand"
4027 "!*r,J,N,K,RQ,*rG,fG,RT,f"))]
4028 "(register_operand (operands[0], DFmode)
4029 || reg_or_0_operand (operands[1], DFmode))
4030 && !TARGET_SOFT_FLOAT && TARGET_64BIT"
4041 [(set_attr "type" "move,move,move,shift,load,store,fpalu,fpload,fpstore")
4042 (set_attr "pa_combine_type" "addmove")
4043 (set_attr "length" "4,4,4,4,4,4,4,4,4")])
4046 (define_expand "movdi"
4047 [(set (match_operand:DI 0 "general_operand" "")
4048 (match_operand:DI 1 "general_operand" ""))]
4052 if (pa_emit_move_sequence (operands, DImode, 0))
4056 ;; Handle DImode input reloads requiring %r1 as a scratch register.
4057 (define_expand "reload_indi_r1"
4058 [(set (match_operand:DI 0 "register_operand" "=Z")
4059 (match_operand:DI 1 "non_hard_reg_operand" ""))
4060 (clobber (match_operand:SI 2 "register_operand" "=&a"))]
4064 if (pa_emit_move_sequence (operands, DImode, operands[2]))
4067 /* We don't want the clobber emitted, so handle this ourselves. */
4068 emit_insn (gen_rtx_SET (operands[0], operands[1]));
4072 ;; Handle DImode input reloads requiring a general register as a
4073 ;; scratch register.
4074 (define_expand "reload_indi"
4075 [(set (match_operand:DI 0 "register_operand" "=Z")
4076 (match_operand:DI 1 "non_hard_reg_operand" ""))
4077 (clobber (match_operand:SI 2 "register_operand" "=&r"))]
4081 if (pa_emit_move_sequence (operands, DImode, operands[2]))
4084 /* We don't want the clobber emitted, so handle this ourselves. */
4085 emit_insn (gen_rtx_SET (operands[0], operands[1]));
4089 ;; Handle DImode output reloads requiring a general register as a
4090 ;; scratch register.
4091 (define_expand "reload_outdi"
4092 [(set (match_operand:DI 0 "non_hard_reg_operand" "")
4093 (match_operand:DI 1 "register_operand" "Z"))
4094 (clobber (match_operand:SI 2 "register_operand" "=&r"))]
4098 if (pa_emit_move_sequence (operands, DImode, operands[2]))
4101 /* We don't want the clobber emitted, so handle this ourselves. */
4102 emit_insn (gen_rtx_SET (operands[0], operands[1]));
4107 [(set (match_operand:DI 0 "register_operand" "=r")
4108 (high:DI (match_operand 1 "" "")))]
4112 rtx op0 = operands[0];
4113 rtx op1 = operands[1];
4115 switch (GET_CODE (op1))
4118 #if HOST_BITS_PER_WIDE_INT <= 32
4119 operands[0] = operand_subword (op0, 1, 0, DImode);
4120 output_asm_insn (\"ldil L'%1,%0\", operands);
4122 operands[0] = operand_subword (op0, 0, 0, DImode);
4123 if (INTVAL (op1) < 0)
4124 output_asm_insn (\"ldi -1,%0\", operands);
4126 output_asm_insn (\"ldi 0,%0\", operands);
4128 operands[0] = operand_subword (op0, 1, 0, DImode);
4129 operands[1] = GEN_INT (INTVAL (op1) & 0xffffffff);
4130 output_asm_insn (\"ldil L'%1,%0\", operands);
4132 operands[0] = operand_subword (op0, 0, 0, DImode);
4133 operands[1] = GEN_INT (INTVAL (op1) >> 32);
4134 output_asm_insn (pa_singlemove_string (operands), operands);
4139 operands[0] = operand_subword (op0, 1, 0, DImode);
4140 operands[1] = GEN_INT (CONST_DOUBLE_LOW (op1));
4141 output_asm_insn (\"ldil L'%1,%0\", operands);
4143 operands[0] = operand_subword (op0, 0, 0, DImode);
4144 operands[1] = GEN_INT (CONST_DOUBLE_HIGH (op1));
4145 output_asm_insn (pa_singlemove_string (operands), operands);
4153 [(set_attr "type" "move")
4154 (set_attr "length" "12")])
4157 [(set (match_operand:DI 0 "move_dest_operand"
4158 "=r,o,Q,r,r,r,*f,*f,T,?r,?*f")
4159 (match_operand:DI 1 "move_src_operand"
4160 "rM,r,r,o*R,Q,i,*fM,RT,*f,*f,r"))]
4161 "(register_operand (operands[0], DImode)
4162 || reg_or_0_operand (operands[1], DImode))
4164 && !TARGET_SOFT_FLOAT"
4167 if ((FP_REG_P (operands[0]) || FP_REG_P (operands[1])
4168 || operands[1] == CONST0_RTX (DFmode))
4169 && !(REG_P (operands[0]) && REG_P (operands[1])
4170 && FP_REG_P (operands[0]) ^ FP_REG_P (operands[1])))
4171 return pa_output_fp_move_double (operands);
4172 return pa_output_move_double (operands);
4175 "move,store,store,load,load,multi,fpalu,fpload,fpstore,fpstore_load,store_fpload")
4176 (set_attr "length" "8,8,16,8,16,16,4,4,4,12,12")])
4179 [(set (match_operand:DI 0 "move_dest_operand"
4180 "=r,r,r,r,r,r,Q,!*q,!r,!*f,*f,T")
4181 (match_operand:DI 1 "move_src_operand"
4182 "A,r,J,N,K,RQ,rM,!rM,!*q,!*fM,RT,*f"))]
4183 "(register_operand (operands[0], DImode)
4184 || reg_or_0_operand (operands[1], DImode))
4185 && !TARGET_SOFT_FLOAT && TARGET_64BIT"
4195 {mfctl|mfctl,w} %%sar,%0
4199 [(set_attr "type" "load,move,move,move,shift,load,store,move,move,fpalu,fpload,fpstore")
4200 (set_attr "pa_combine_type" "addmove")
4201 (set_attr "length" "4,4,4,4,4,4,4,4,4,4,4,4")])
4204 [(set (match_operand:DI 0 "indexed_memory_operand" "=R")
4205 (match_operand:DI 1 "register_operand" "f"))]
4208 && !TARGET_DISABLE_INDEXING
4209 && reload_completed"
4211 [(set_attr "type" "fpstore")
4212 (set_attr "pa_combine_type" "addmove")
4213 (set_attr "length" "4")])
4216 [(set (match_operand:DI 0 "register_operand" "")
4217 (plus:DI (ashift:DI (match_operand:DI 1 "register_operand" "")
4219 (match_operand:DI 2 "register_operand" "")))
4220 (set (mem:DI (match_dup 0))
4221 (match_operand:DI 3 "register_operand" ""))]
4223 && !TARGET_DISABLE_INDEXING
4225 && REG_OK_FOR_BASE_P (operands[2])
4226 && FP_REGNO_P (REGNO (operands[3]))"
4227 [(set (mem:DI (plus:DI (mult:DI (match_dup 1) (const_int 8)) (match_dup 2)))
4229 (set (match_dup 0) (plus:DI (ashift:DI (match_dup 1) (const_int 3))
4234 [(set (match_operand:DI 0 "register_operand" "")
4235 (plus:DI (match_operand:DI 1 "register_operand" "")
4236 (match_operand:DI 2 "register_operand" "")))
4237 (set (mem:DI (match_dup 0))
4238 (match_operand:DI 3 "register_operand" ""))]
4240 && !TARGET_DISABLE_INDEXING
4242 && TARGET_NO_SPACE_REGS
4243 && REG_OK_FOR_INDEX_P (operands[1])
4244 && REG_OK_FOR_BASE_P (operands[2])
4245 && FP_REGNO_P (REGNO (operands[3]))"
4246 [(set (mem:DI (plus:DI (match_dup 1) (match_dup 2)))
4248 (set (match_dup 0) (plus:DI (match_dup 1) (match_dup 2)))]
4252 [(set (match_operand:DI 0 "register_operand" "")
4253 (plus:DI (match_operand:DI 1 "register_operand" "")
4254 (match_operand:DI 2 "register_operand" "")))
4255 (set (mem:DI (match_dup 0))
4256 (match_operand:DI 3 "register_operand" ""))]
4258 && !TARGET_DISABLE_INDEXING
4260 && TARGET_NO_SPACE_REGS
4261 && REG_OK_FOR_BASE_P (operands[1])
4262 && REG_OK_FOR_INDEX_P (operands[2])
4263 && FP_REGNO_P (REGNO (operands[3]))"
4264 [(set (mem:DI (plus:DI (match_dup 2) (match_dup 1)))
4266 (set (match_dup 0) (plus:DI (match_dup 2) (match_dup 1)))]
4270 [(set (match_operand:DI 0 "move_dest_operand"
4272 (match_operand:DI 1 "general_operand"
4274 "(register_operand (operands[0], DImode)
4275 || reg_or_0_operand (operands[1], DImode))
4277 && TARGET_SOFT_FLOAT"
4280 return pa_output_move_double (operands);
4282 [(set_attr "type" "move,store,store,load,load,multi")
4283 (set_attr "length" "8,8,16,8,16,16")])
4286 [(set (match_operand:DI 0 "register_operand" "=r,&r")
4287 (lo_sum:DI (match_operand:DI 1 "register_operand" "0,r")
4288 (match_operand:DI 2 "immediate_operand" "i,i")))]
4292 /* Don't output a 64-bit constant, since we can't trust the assembler to
4293 handle it correctly. */
4294 if (GET_CODE (operands[2]) == CONST_DOUBLE)
4295 operands[2] = GEN_INT (CONST_DOUBLE_LOW (operands[2]));
4296 else if (HOST_BITS_PER_WIDE_INT > 32
4297 && GET_CODE (operands[2]) == CONST_INT)
4298 operands[2] = GEN_INT (INTVAL (operands[2]) & 0xffffffff);
4299 if (which_alternative == 1)
4300 output_asm_insn (\"copy %1,%0\", operands);
4301 return \"ldo R'%G2(%R1),%R0\";
4303 [(set_attr "type" "move,move")
4304 (set_attr "length" "4,8")])
4306 (define_expand "movsf"
4307 [(set (match_operand:SF 0 "general_operand" "")
4308 (match_operand:SF 1 "general_operand" ""))]
4312 if (pa_emit_move_sequence (operands, SFmode, 0))
4316 ;; Handle SFmode input reloads requiring %r1 as a scratch register.
4317 (define_expand "reload_insf_r1"
4318 [(set (match_operand:SF 0 "register_operand" "=Z")
4319 (match_operand:SF 1 "non_hard_reg_operand" ""))
4320 (clobber (match_operand:SI 2 "register_operand" "=&a"))]
4324 if (pa_emit_move_sequence (operands, SFmode, operands[2]))
4327 /* We don't want the clobber emitted, so handle this ourselves. */
4328 emit_insn (gen_rtx_SET (operands[0], operands[1]));
4332 ;; Handle SFmode input reloads requiring a general register as a
4333 ;; scratch register.
4334 (define_expand "reload_insf"
4335 [(set (match_operand:SF 0 "register_operand" "=Z")
4336 (match_operand:SF 1 "non_hard_reg_operand" ""))
4337 (clobber (match_operand:SF 2 "register_operand" "=&r"))]
4341 if (pa_emit_move_sequence (operands, SFmode, operands[2]))
4344 /* We don't want the clobber emitted, so handle this ourselves. */
4345 emit_insn (gen_rtx_SET (operands[0], operands[1]));
4349 ;; Handle SFmode output reloads requiring a general register as a
4350 ;; scratch register.
4351 (define_expand "reload_outsf"
4352 [(set (match_operand:SF 0 "non_hard_reg_operand" "")
4353 (match_operand:SF 1 "register_operand" "Z"))
4354 (clobber (match_operand:SF 2 "register_operand" "=&r"))]
4358 if (pa_emit_move_sequence (operands, SFmode, operands[2]))
4361 /* We don't want the clobber emitted, so handle this ourselves. */
4362 emit_insn (gen_rtx_SET (operands[0], operands[1]));
4367 [(set (match_operand:SF 0 "move_dest_operand"
4368 "=f,!*r,f,*r,T,Q,?*r,?f")
4369 (match_operand:SF 1 "reg_or_0_or_nonsymb_mem_operand"
4370 "fG,!*rG,RT,RQ,f,*rG,f,*r"))]
4371 "(register_operand (operands[0], SFmode)
4372 || reg_or_0_operand (operands[1], SFmode))
4373 && !TARGET_SOFT_FLOAT
4382 {fstws|fstw} %1,-16(%%sp)\n\t{ldws|ldw} -16(%%sp),%0
4383 {stws|stw} %1,-16(%%sp)\n\t{fldws|fldw} -16(%%sp),%0"
4384 [(set_attr "type" "fpalu,move,fpload,load,fpstore,store,fpstore_load,store_fpload")
4385 (set_attr "pa_combine_type" "addmove")
4386 (set_attr "length" "4,4,4,4,4,4,8,8")])
4389 [(set (match_operand:SF 0 "move_dest_operand"
4391 (match_operand:SF 1 "reg_or_0_or_nonsymb_mem_operand"
4392 "fG,!*rG,RT,RQ,f,*rG"))]
4393 "(register_operand (operands[0], SFmode)
4394 || reg_or_0_operand (operands[1], SFmode))
4395 && !TARGET_SOFT_FLOAT
4404 [(set_attr "type" "fpalu,move,fpload,load,fpstore,store")
4405 (set_attr "pa_combine_type" "addmove")
4406 (set_attr "length" "4,4,4,4,4,4")])
4409 [(set (match_operand:SF 0 "indexed_memory_operand" "=R")
4410 (match_operand:SF 1 "register_operand" "f"))]
4412 && !TARGET_DISABLE_INDEXING
4413 && reload_completed"
4415 [(set_attr "type" "fpstore")
4416 (set_attr "pa_combine_type" "addmove")
4417 (set_attr "length" "4")])
4420 [(set (match_operand:SI 0 "register_operand" "")
4421 (plus:SI (ashift:SI (match_operand:SI 1 "register_operand" "")
4423 (match_operand:SI 2 "register_operand" "")))
4424 (set (mem:SF (match_dup 0))
4425 (match_operand:SF 3 "register_operand" ""))]
4427 && !TARGET_DISABLE_INDEXING
4428 && REG_OK_FOR_BASE_P (operands[2])
4429 && FP_REGNO_P (REGNO (operands[3]))"
4430 [(set (mem:SF (plus:SI (mult:SI (match_dup 1) (const_int 4)) (match_dup 2)))
4432 (set (match_dup 0) (plus:SI (ashift:SI (match_dup 1) (const_int 2))
4437 [(set (match_operand:DI 0 "register_operand" "")
4438 (plus:DI (ashift:DI (match_operand:DI 1 "register_operand" "")
4440 (match_operand:DI 2 "register_operand" "")))
4441 (set (mem:SF (match_dup 0))
4442 (match_operand:SF 3 "register_operand" ""))]
4444 && !TARGET_DISABLE_INDEXING
4446 && REG_OK_FOR_BASE_P (operands[2])
4447 && FP_REGNO_P (REGNO (operands[3]))"
4448 [(set (mem:SF (plus:DI (mult:DI (match_dup 1) (const_int 4)) (match_dup 2)))
4450 (set (match_dup 0) (plus:DI (ashift:DI (match_dup 1) (const_int 2))
4455 [(set (match_operand:SI 0 "register_operand" "")
4456 (plus:SI (match_operand:SI 1 "register_operand" "")
4457 (match_operand:SI 2 "register_operand" "")))
4458 (set (mem:SF (match_dup 0))
4459 (match_operand:SF 3 "register_operand" ""))]
4461 && !TARGET_DISABLE_INDEXING
4462 && TARGET_NO_SPACE_REGS
4463 && REG_OK_FOR_INDEX_P (operands[1])
4464 && REG_OK_FOR_BASE_P (operands[2])
4465 && FP_REGNO_P (REGNO (operands[3]))"
4466 [(set (mem:SF (plus:SI (match_dup 1) (match_dup 2)))
4468 (set (match_dup 0) (plus:SI (match_dup 1) (match_dup 2)))]
4472 [(set (match_operand:SI 0 "register_operand" "")
4473 (plus:SI (match_operand:SI 1 "register_operand" "")
4474 (match_operand:SI 2 "register_operand" "")))
4475 (set (mem:SF (match_dup 0))
4476 (match_operand:SF 3 "register_operand" ""))]
4478 && !TARGET_DISABLE_INDEXING
4479 && TARGET_NO_SPACE_REGS
4480 && REG_OK_FOR_BASE_P (operands[1])
4481 && REG_OK_FOR_INDEX_P (operands[2])
4482 && FP_REGNO_P (REGNO (operands[3]))"
4483 [(set (mem:SF (plus:SI (match_dup 2) (match_dup 1)))
4485 (set (match_dup 0) (plus:SI (match_dup 2) (match_dup 1)))]
4489 [(set (match_operand:DI 0 "register_operand" "")
4490 (plus:DI (match_operand:DI 1 "register_operand" "")
4491 (match_operand:DI 2 "register_operand" "")))
4492 (set (mem:SF (match_dup 0))
4493 (match_operand:SF 3 "register_operand" ""))]
4495 && !TARGET_DISABLE_INDEXING
4497 && TARGET_NO_SPACE_REGS
4498 && REG_OK_FOR_INDEX_P (operands[1])
4499 && REG_OK_FOR_BASE_P (operands[2])
4500 && FP_REGNO_P (REGNO (operands[3]))"
4501 [(set (mem:SF (plus:DI (match_dup 1) (match_dup 2)))
4503 (set (match_dup 0) (plus:DI (match_dup 1) (match_dup 2)))]
4507 [(set (match_operand:DI 0 "register_operand" "")
4508 (plus:DI (match_operand:DI 1 "register_operand" "")
4509 (match_operand:DI 2 "register_operand" "")))
4510 (set (mem:SF (match_dup 0))
4511 (match_operand:SF 3 "register_operand" ""))]
4513 && !TARGET_DISABLE_INDEXING
4515 && TARGET_NO_SPACE_REGS
4516 && REG_OK_FOR_BASE_P (operands[1])
4517 && REG_OK_FOR_INDEX_P (operands[2])
4518 && FP_REGNO_P (REGNO (operands[3]))"
4519 [(set (mem:SF (plus:DI (match_dup 2) (match_dup 1)))
4521 (set (match_dup 0) (plus:DI (match_dup 2) (match_dup 1)))]
4525 [(set (match_operand:SF 0 "move_dest_operand"
4527 (match_operand:SF 1 "reg_or_0_or_nonsymb_mem_operand"
4529 "(register_operand (operands[0], SFmode)
4530 || reg_or_0_operand (operands[1], SFmode))
4531 && TARGET_SOFT_FLOAT"
4536 [(set_attr "type" "move,load,store")
4537 (set_attr "pa_combine_type" "addmove")
4538 (set_attr "length" "4,4,4")])
4542 ;;- zero extension instructions
4543 ;; We have define_expand for zero extension patterns to make sure the
4544 ;; operands get loaded into registers. The define_insns accept
4545 ;; memory operands. This gives us better overall code than just
4546 ;; having a pattern that does or does not accept memory operands.
4548 (define_expand "zero_extendqihi2"
4549 [(set (match_operand:HI 0 "register_operand" "")
4551 (match_operand:QI 1 "register_operand" "")))]
4556 [(set (match_operand:HI 0 "register_operand" "=r,r")
4558 (match_operand:QI 1 "move_src_operand" "r,RQ")))]
4559 "GET_CODE (operands[1]) != CONST_INT"
4561 {extru|extrw,u} %1,31,8,%0
4563 [(set_attr "type" "shift,load")
4564 (set_attr "length" "4,4")])
4566 (define_expand "zero_extendqisi2"
4567 [(set (match_operand:SI 0 "register_operand" "")
4569 (match_operand:QI 1 "register_operand" "")))]
4574 [(set (match_operand:SI 0 "register_operand" "=r,r")
4576 (match_operand:QI 1 "move_src_operand" "r,RQ")))]
4577 "GET_CODE (operands[1]) != CONST_INT"
4579 {extru|extrw,u} %1,31,8,%0
4581 [(set_attr "type" "shift,load")
4582 (set_attr "length" "4,4")])
4584 (define_expand "zero_extendhisi2"
4585 [(set (match_operand:SI 0 "register_operand" "")
4587 (match_operand:HI 1 "register_operand" "")))]
4592 [(set (match_operand:SI 0 "register_operand" "=r,r")
4594 (match_operand:HI 1 "move_src_operand" "r,RQ")))]
4595 "GET_CODE (operands[1]) != CONST_INT"
4597 {extru|extrw,u} %1,31,16,%0
4599 [(set_attr "type" "shift,load")
4600 (set_attr "length" "4,4")])
4602 (define_expand "zero_extendqidi2"
4603 [(set (match_operand:DI 0 "register_operand" "")
4605 (match_operand:QI 1 "register_operand" "")))]
4610 [(set (match_operand:DI 0 "register_operand" "=r,r")
4612 (match_operand:QI 1 "move_src_operand" "r,RQ")))]
4613 "TARGET_64BIT && GET_CODE (operands[1]) != CONST_INT"
4617 [(set_attr "type" "shift,load")
4618 (set_attr "length" "4,4")])
4620 (define_expand "zero_extendhidi2"
4621 [(set (match_operand:DI 0 "register_operand" "")
4623 (match_operand:HI 1 "register_operand" "")))]
4628 [(set (match_operand:DI 0 "register_operand" "=r,r")
4630 (match_operand:HI 1 "move_src_operand" "r,RQ")))]
4631 "TARGET_64BIT && GET_CODE (operands[1]) != CONST_INT"
4635 [(set_attr "type" "shift,load")
4636 (set_attr "length" "4,4")])
4638 (define_expand "zero_extendsidi2"
4639 [(set (match_operand:DI 0 "register_operand" "")
4641 (match_operand:SI 1 "register_operand" "")))]
4646 [(set (match_operand:DI 0 "register_operand" "=r,r")
4648 (match_operand:SI 1 "move_src_operand" "r,RQ")))]
4649 "TARGET_64BIT && GET_CODE (operands[1]) != CONST_INT"
4653 [(set_attr "type" "shift,load")
4654 (set_attr "length" "4,4")])
4656 ;;- sign extension instructions
4658 (define_insn "extendhisi2"
4659 [(set (match_operand:SI 0 "register_operand" "=r")
4660 (sign_extend:SI (match_operand:HI 1 "register_operand" "r")))]
4662 "{extrs|extrw,s} %1,31,16,%0"
4663 [(set_attr "type" "shift")
4664 (set_attr "length" "4")])
4666 (define_insn "extendqihi2"
4667 [(set (match_operand:HI 0 "register_operand" "=r")
4668 (sign_extend:HI (match_operand:QI 1 "register_operand" "r")))]
4670 "{extrs|extrw,s} %1,31,8,%0"
4671 [(set_attr "type" "shift")
4672 (set_attr "length" "4")])
4674 (define_insn "extendqisi2"
4675 [(set (match_operand:SI 0 "register_operand" "=r")
4676 (sign_extend:SI (match_operand:QI 1 "register_operand" "r")))]
4678 "{extrs|extrw,s} %1,31,8,%0"
4679 [(set_attr "type" "shift")
4680 (set_attr "length" "4")])
4682 (define_insn "extendqidi2"
4683 [(set (match_operand:DI 0 "register_operand" "=r")
4684 (sign_extend:DI (match_operand:QI 1 "register_operand" "r")))]
4686 "extrd,s %1,63,8,%0"
4687 [(set_attr "type" "shift")
4688 (set_attr "length" "4")])
4690 (define_insn "extendhidi2"
4691 [(set (match_operand:DI 0 "register_operand" "=r")
4692 (sign_extend:DI (match_operand:HI 1 "register_operand" "r")))]
4694 "extrd,s %1,63,16,%0"
4695 [(set_attr "type" "shift")
4696 (set_attr "length" "4")])
4698 (define_insn "extendsidi2"
4699 [(set (match_operand:DI 0 "register_operand" "=r")
4700 (sign_extend:DI (match_operand:SI 1 "register_operand" "r")))]
4702 "extrd,s %1,63,32,%0"
4703 [(set_attr "type" "shift")
4704 (set_attr "length" "4")])
4707 ;; Conversions between float and double.
4709 (define_insn "extendsfdf2"
4710 [(set (match_operand:DF 0 "register_operand" "=f")
4712 (match_operand:SF 1 "register_operand" "f")))]
4713 "! TARGET_SOFT_FLOAT"
4714 "{fcnvff|fcnv},sgl,dbl %1,%0"
4715 [(set_attr "type" "fpalu")
4716 (set_attr "length" "4")])
4718 (define_insn "truncdfsf2"
4719 [(set (match_operand:SF 0 "register_operand" "=f")
4721 (match_operand:DF 1 "register_operand" "f")))]
4722 "! TARGET_SOFT_FLOAT"
4723 "{fcnvff|fcnv},dbl,sgl %1,%0"
4724 [(set_attr "type" "fpalu")
4725 (set_attr "length" "4")])
4727 ;; Conversion between fixed point and floating point.
4728 ;; Note that among the fix-to-float insns
4729 ;; the ones that start with SImode come first.
4730 ;; That is so that an operand that is a CONST_INT
4731 ;; (and therefore lacks a specific machine mode).
4732 ;; will be recognized as SImode (which is always valid)
4733 ;; rather than as QImode or HImode.
4735 ;; This pattern forces (set (reg:SF ...) (float:SF (const_int ...)))
4736 ;; to be reloaded by putting the constant into memory.
4737 ;; It must come before the more general floatsisf2 pattern.
4739 [(set (match_operand:SF 0 "register_operand" "=f")
4740 (float:SF (match_operand:SI 1 "const_int_operand" "m")))]
4741 "! TARGET_SOFT_FLOAT"
4742 "fldw%F1 %1,%0\;{fcnvxf,sgl,sgl|fcnv,w,sgl} %0,%0"
4743 [(set_attr "type" "fpalu")
4744 (set_attr "length" "8")])
4746 (define_insn "floatsisf2"
4747 [(set (match_operand:SF 0 "register_operand" "=f")
4748 (float:SF (match_operand:SI 1 "register_operand" "f")))]
4749 "! TARGET_SOFT_FLOAT"
4750 "{fcnvxf,sgl,sgl|fcnv,w,sgl} %1,%0"
4751 [(set_attr "type" "fpalu")
4752 (set_attr "length" "4")])
4754 ;; This pattern forces (set (reg:DF ...) (float:DF (const_int ...)))
4755 ;; to be reloaded by putting the constant into memory.
4756 ;; It must come before the more general floatsidf2 pattern.
4758 [(set (match_operand:DF 0 "register_operand" "=f")
4759 (float:DF (match_operand:SI 1 "const_int_operand" "m")))]
4760 "! TARGET_SOFT_FLOAT"
4761 "fldw%F1 %1,%0\;{fcnvxf,sgl,dbl|fcnv,w,dbl} %0,%0"
4762 [(set_attr "type" "fpalu")
4763 (set_attr "length" "8")])
4765 (define_insn "floatsidf2"
4766 [(set (match_operand:DF 0 "register_operand" "=f")
4767 (float:DF (match_operand:SI 1 "register_operand" "f")))]
4768 "! TARGET_SOFT_FLOAT"
4769 "{fcnvxf,sgl,dbl|fcnv,w,dbl} %1,%0"
4770 [(set_attr "type" "fpalu")
4771 (set_attr "length" "4")])
4773 (define_expand "floatunssisf2"
4774 [(set (subreg:SI (match_dup 2) 4)
4775 (match_operand:SI 1 "register_operand" ""))
4776 (set (subreg:SI (match_dup 2) 0)
4778 (set (match_operand:SF 0 "register_operand" "")
4779 (float:SF (match_dup 2)))]
4780 "TARGET_PA_11 && ! TARGET_SOFT_FLOAT"
4785 emit_insn (gen_floatunssisf2_pa20 (operands[0], operands[1]));
4788 operands[2] = gen_reg_rtx (DImode);
4791 (define_expand "floatunssidf2"
4792 [(set (subreg:SI (match_dup 2) 4)
4793 (match_operand:SI 1 "register_operand" ""))
4794 (set (subreg:SI (match_dup 2) 0)
4796 (set (match_operand:DF 0 "register_operand" "")
4797 (float:DF (match_dup 2)))]
4798 "TARGET_PA_11 && ! TARGET_SOFT_FLOAT"
4803 emit_insn (gen_floatunssidf2_pa20 (operands[0], operands[1]));
4806 operands[2] = gen_reg_rtx (DImode);
4809 (define_insn "floatdisf2"
4810 [(set (match_operand:SF 0 "register_operand" "=f")
4811 (float:SF (match_operand:DI 1 "register_operand" "f")))]
4812 "TARGET_PA_11 && ! TARGET_SOFT_FLOAT"
4813 "{fcnvxf,dbl,sgl|fcnv,dw,sgl} %1,%0"
4814 [(set_attr "type" "fpalu")
4815 (set_attr "length" "4")])
4817 (define_insn "floatdidf2"
4818 [(set (match_operand:DF 0 "register_operand" "=f")
4819 (float:DF (match_operand:DI 1 "register_operand" "f")))]
4820 "TARGET_PA_11 && ! TARGET_SOFT_FLOAT"
4821 "{fcnvxf,dbl,dbl|fcnv,dw,dbl} %1,%0"
4822 [(set_attr "type" "fpalu")
4823 (set_attr "length" "4")])
4825 ;; Convert a float to an actual integer.
4826 ;; Truncation is performed as part of the conversion.
4828 (define_insn "fix_truncsfsi2"
4829 [(set (match_operand:SI 0 "register_operand" "=f")
4830 (fix:SI (fix:SF (match_operand:SF 1 "register_operand" "f"))))]
4831 "! TARGET_SOFT_FLOAT"
4832 "{fcnvfxt,sgl,sgl|fcnv,t,sgl,w} %1,%0"
4833 [(set_attr "type" "fpalu")
4834 (set_attr "length" "4")])
4836 (define_insn "fix_truncdfsi2"
4837 [(set (match_operand:SI 0 "register_operand" "=f")
4838 (fix:SI (fix:DF (match_operand:DF 1 "register_operand" "f"))))]
4839 "! TARGET_SOFT_FLOAT"
4840 "{fcnvfxt,dbl,sgl|fcnv,t,dbl,w} %1,%0"
4841 [(set_attr "type" "fpalu")
4842 (set_attr "length" "4")])
4844 (define_insn "fix_truncsfdi2"
4845 [(set (match_operand:DI 0 "register_operand" "=f")
4846 (fix:DI (fix:SF (match_operand:SF 1 "register_operand" "f"))))]
4847 "TARGET_PA_11 && ! TARGET_SOFT_FLOAT"
4848 "{fcnvfxt,sgl,dbl|fcnv,t,sgl,dw} %1,%0"
4849 [(set_attr "type" "fpalu")
4850 (set_attr "length" "4")])
4852 (define_insn "fix_truncdfdi2"
4853 [(set (match_operand:DI 0 "register_operand" "=f")
4854 (fix:DI (fix:DF (match_operand:DF 1 "register_operand" "f"))))]
4855 "TARGET_PA_11 && ! TARGET_SOFT_FLOAT"
4856 "{fcnvfxt,dbl,dbl|fcnv,t,dbl,dw} %1,%0"
4857 [(set_attr "type" "fpalu")
4858 (set_attr "length" "4")])
4860 (define_insn "floatunssidf2_pa20"
4861 [(set (match_operand:DF 0 "register_operand" "=f")
4862 (unsigned_float:DF (match_operand:SI 1 "register_operand" "f")))]
4863 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
4865 [(set_attr "type" "fpalu")
4866 (set_attr "length" "4")])
4868 (define_insn "floatunssisf2_pa20"
4869 [(set (match_operand:SF 0 "register_operand" "=f")
4870 (unsigned_float:SF (match_operand:SI 1 "register_operand" "f")))]
4871 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
4873 [(set_attr "type" "fpalu")
4874 (set_attr "length" "4")])
4876 (define_insn "floatunsdisf2"
4877 [(set (match_operand:SF 0 "register_operand" "=f")
4878 (unsigned_float:SF (match_operand:DI 1 "register_operand" "f")))]
4879 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
4880 "fcnv,udw,sgl %1,%0"
4881 [(set_attr "type" "fpalu")
4882 (set_attr "length" "4")])
4884 (define_insn "floatunsdidf2"
4885 [(set (match_operand:DF 0 "register_operand" "=f")
4886 (unsigned_float:DF (match_operand:DI 1 "register_operand" "f")))]
4887 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
4888 "fcnv,udw,dbl %1,%0"
4889 [(set_attr "type" "fpalu")
4890 (set_attr "length" "4")])
4892 (define_insn "fixuns_truncsfsi2"
4893 [(set (match_operand:SI 0 "register_operand" "=f")
4894 (unsigned_fix:SI (fix:SF (match_operand:SF 1 "register_operand" "f"))))]
4895 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
4896 "fcnv,t,sgl,uw %1,%0"
4897 [(set_attr "type" "fpalu")
4898 (set_attr "length" "4")])
4900 (define_insn "fixuns_truncdfsi2"
4901 [(set (match_operand:SI 0 "register_operand" "=f")
4902 (unsigned_fix:SI (fix:DF (match_operand:DF 1 "register_operand" "f"))))]
4903 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
4904 "fcnv,t,dbl,uw %1,%0"
4905 [(set_attr "type" "fpalu")
4906 (set_attr "length" "4")])
4908 (define_insn "fixuns_truncsfdi2"
4909 [(set (match_operand:DI 0 "register_operand" "=f")
4910 (unsigned_fix:DI (fix:SF (match_operand:SF 1 "register_operand" "f"))))]
4911 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
4912 "fcnv,t,sgl,udw %1,%0"
4913 [(set_attr "type" "fpalu")
4914 (set_attr "length" "4")])
4916 (define_insn "fixuns_truncdfdi2"
4917 [(set (match_operand:DI 0 "register_operand" "=f")
4918 (unsigned_fix:DI (fix:DF (match_operand:DF 1 "register_operand" "f"))))]
4919 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
4920 "fcnv,t,dbl,udw %1,%0"
4921 [(set_attr "type" "fpalu")
4922 (set_attr "length" "4")])
4924 ;;- arithmetic instructions
4926 (define_expand "adddi3"
4927 [(set (match_operand:DI 0 "register_operand" "")
4928 (plus:DI (match_operand:DI 1 "register_operand" "")
4929 (match_operand:DI 2 "adddi3_operand" "")))]
4934 [(set (match_operand:DI 0 "register_operand" "=r")
4935 (plus:DI (match_operand:DI 1 "register_operand" "%r")
4936 (match_operand:DI 2 "arith11_operand" "rI")))]
4940 if (GET_CODE (operands[2]) == CONST_INT)
4942 if (INTVAL (operands[2]) >= 0)
4943 return \"addi %2,%R1,%R0\;{addc|add,c} %1,%%r0,%0\";
4945 return \"addi %2,%R1,%R0\;{subb|sub,b} %1,%%r0,%0\";
4948 return \"add %R2,%R1,%R0\;{addc|add,c} %2,%1,%0\";
4950 [(set_attr "type" "binary")
4951 (set_attr "length" "8")])
4954 [(set (match_operand:DI 0 "register_operand" "=r,r")
4955 (plus:DI (match_operand:DI 1 "register_operand" "%r,r")
4956 (match_operand:DI 2 "arith14_operand" "r,J")))]
4961 [(set_attr "type" "binary,binary")
4962 (set_attr "pa_combine_type" "addmove")
4963 (set_attr "length" "4,4")])
4966 [(set (match_operand:DI 0 "register_operand" "=r")
4967 (plus:DI (not:DI (match_operand:DI 1 "register_operand" "r"))
4968 (match_operand:DI 2 "register_operand" "r")))]
4971 [(set_attr "type" "binary")
4972 (set_attr "length" "4")])
4975 [(set (match_operand:SI 0 "register_operand" "=r")
4976 (plus:SI (not:SI (match_operand:SI 1 "register_operand" "r"))
4977 (match_operand:SI 2 "register_operand" "r")))]
4980 [(set_attr "type" "binary")
4981 (set_attr "length" "4")])
4983 (define_expand "addvdi3"
4984 [(parallel [(set (match_operand:DI 0 "register_operand" "")
4985 (plus:DI (match_operand:DI 1 "reg_or_0_operand" "")
4986 (match_operand:DI 2 "arith11_operand" "")))
4987 (trap_if (ne (plus:TI (sign_extend:TI (match_dup 1))
4988 (sign_extend:TI (match_dup 2)))
4989 (sign_extend:TI (plus:DI (match_dup 1)
4996 [(set (match_operand:DI 0 "register_operand" "=r,r")
4997 (plus:DI (match_operand:DI 1 "reg_or_0_operand" "%rM,rM")
4998 (match_operand:DI 2 "arith11_operand" "r,I")))
4999 (trap_if (ne (plus:TI (sign_extend:TI (match_dup 1))
5000 (sign_extend:TI (match_dup 2)))
5001 (sign_extend:TI (plus:DI (match_dup 1)
5007 addi,tsv,* %2,%1,%0"
5008 [(set_attr "type" "binary,binary")
5009 (set_attr "length" "4,4")])
5012 [(set (match_operand:DI 0 "register_operand" "=r")
5013 (plus:DI (match_operand:DI 1 "reg_or_0_operand" "%rM")
5014 (match_operand:DI 2 "arith11_operand" "rI")))
5015 (trap_if (ne (plus:TI (sign_extend:TI (match_dup 1))
5016 (sign_extend:TI (match_dup 2)))
5017 (sign_extend:TI (plus:DI (match_dup 1)
5023 if (GET_CODE (operands[2]) == CONST_INT)
5025 if (INTVAL (operands[2]) >= 0)
5026 return \"addi %2,%R1,%R0\;{addco|add,c,tsv} %1,%%r0,%0\";
5028 return \"addi %2,%R1,%R0\;{subbo|sub,b,tsv} %1,%%r0,%0\";
5031 return \"add %R2,%R1,%R0\;{addco|add,c,tsv} %2,%1,%0\";
5033 [(set_attr "type" "binary")
5034 (set_attr "length" "8")])
5036 ;; define_splits to optimize cases of adding a constant integer
5037 ;; to a register when the constant does not fit in 14 bits. */
5039 [(set (match_operand:SI 0 "register_operand" "")
5040 (plus:SI (match_operand:SI 1 "register_operand" "")
5041 (match_operand:SI 2 "const_int_operand" "")))
5042 (clobber (match_operand:SI 4 "register_operand" ""))]
5043 "! pa_cint_ok_for_move (UINTVAL (operands[2]))
5044 && VAL_14_BITS_P (INTVAL (operands[2]) >> 1)"
5045 [(set (match_dup 4) (plus:SI (match_dup 1) (match_dup 2)))
5046 (set (match_dup 0) (plus:SI (match_dup 4) (match_dup 3)))]
5049 int val = INTVAL (operands[2]);
5050 int low = (val < 0) ? -0x2000 : 0x1fff;
5051 int rest = val - low;
5053 operands[2] = GEN_INT (rest);
5054 operands[3] = GEN_INT (low);
5058 [(set (match_operand:SI 0 "register_operand" "")
5059 (plus:SI (match_operand:SI 1 "register_operand" "")
5060 (match_operand:SI 2 "const_int_operand" "")))
5061 (clobber (match_operand:SI 4 "register_operand" ""))]
5062 "! pa_cint_ok_for_move (UINTVAL (operands[2]))"
5063 [(set (match_dup 4) (match_dup 2))
5064 (set (match_dup 0) (plus:SI (ashift:SI (match_dup 4) (match_dup 3))
5068 unsigned HOST_WIDE_INT intval = UINTVAL (operands[2]);
5070 /* Try dividing the constant by 2, then 4, and finally 8 to see
5071 if we can get a constant which can be loaded into a register
5072 in a single instruction (pa_cint_ok_for_move).
5074 If that fails, try to negate the constant and subtract it
5075 from our input operand. */
5076 if (intval % 2 == 0 && pa_cint_ok_for_move (intval / 2))
5078 operands[2] = GEN_INT (intval / 2);
5079 operands[3] = const1_rtx;
5081 else if (intval % 4 == 0 && pa_cint_ok_for_move (intval / 4))
5083 operands[2] = GEN_INT (intval / 4);
5084 operands[3] = const2_rtx;
5086 else if (intval % 8 == 0 && pa_cint_ok_for_move (intval / 8))
5088 operands[2] = GEN_INT (intval / 8);
5089 operands[3] = GEN_INT (3);
5091 else if (pa_cint_ok_for_move (-intval))
5093 emit_insn (gen_rtx_SET (operands[4], GEN_INT (-intval)));
5094 emit_insn (gen_subsi3 (operands[0], operands[1], operands[4]));
5101 (define_insn "addsi3"
5102 [(set (match_operand:SI 0 "register_operand" "=r,r")
5103 (plus:SI (match_operand:SI 1 "register_operand" "%r,r")
5104 (match_operand:SI 2 "arith14_operand" "r,J")))]
5107 {addl|add,l} %1,%2,%0
5109 [(set_attr "type" "binary,binary")
5110 (set_attr "pa_combine_type" "addmove")
5111 (set_attr "length" "4,4")])
5113 (define_insn "addvsi3"
5114 [(set (match_operand:SI 0 "register_operand" "=r,r")
5115 (plus:SI (match_operand:SI 1 "reg_or_0_operand" "%rM,rM")
5116 (match_operand:SI 2 "arith11_operand" "r,I")))
5117 (trap_if (ne (plus:DI (sign_extend:DI (match_dup 1))
5118 (sign_extend:DI (match_dup 2)))
5119 (sign_extend:DI (plus:SI (match_dup 1)
5124 {addo|add,tsv} %2,%1,%0
5125 {addio|addi,tsv} %2,%1,%0"
5126 [(set_attr "type" "binary,binary")
5127 (set_attr "length" "4,4")])
5129 (define_expand "subdi3"
5130 [(set (match_operand:DI 0 "register_operand" "")
5131 (minus:DI (match_operand:DI 1 "arith11_operand" "")
5132 (match_operand:DI 2 "reg_or_0_operand" "")))]
5137 [(set (match_operand:DI 0 "register_operand" "=r,r,!q")
5138 (minus:DI (match_operand:DI 1 "arith11_operand" "r,I,!U")
5139 (match_operand:DI 2 "reg_or_0_operand" "rM,rM,!rM")))]
5145 [(set_attr "type" "binary,binary,move")
5146 (set_attr "length" "4,4,4")])
5149 [(set (match_operand:DI 0 "register_operand" "=r,&r")
5150 (minus:DI (match_operand:DI 1 "arith11_operand" "r,I")
5151 (match_operand:DI 2 "reg_or_0_operand" "rM,rM")))]
5155 if (GET_CODE (operands[1]) == CONST_INT)
5157 if (INTVAL (operands[1]) >= 0)
5158 return \"subi %1,%R2,%R0\;{subb|sub,b} %%r0,%2,%0\";
5160 return \"ldi -1,%0\;subi %1,%R2,%R0\;{subb|sub,b} %0,%2,%0\";
5163 return \"sub %R1,%R2,%R0\;{subb|sub,b} %1,%2,%0\";
5165 [(set_attr "type" "binary")
5166 (set (attr "length")
5167 (if_then_else (eq_attr "alternative" "0")
5169 (if_then_else (ge (symbol_ref "INTVAL (operands[1])")
5174 (define_expand "subvdi3"
5175 [(parallel [(set (match_operand:DI 0 "register_operand" "")
5176 (minus:DI (match_operand:DI 1 "arith11_operand" "")
5177 (match_operand:DI 2 "reg_or_0_operand" "")))
5178 (trap_if (ne (minus:TI (sign_extend:TI (match_dup 1))
5179 (sign_extend:TI (match_dup 2)))
5180 (sign_extend:TI (minus:DI (match_dup 1)
5187 [(set (match_operand:DI 0 "register_operand" "=r,r")
5188 (minus:DI (match_operand:DI 1 "arith11_operand" "r,I")
5189 (match_operand:DI 2 "reg_or_0_operand" "rM,rM")))
5190 (trap_if (ne (minus:TI (sign_extend:TI (match_dup 1))
5191 (sign_extend:TI (match_dup 2)))
5192 (sign_extend:TI (minus:DI (match_dup 1)
5197 {subo|sub,tsv} %1,%2,%0
5198 {subio|subi,tsv} %1,%2,%0"
5199 [(set_attr "type" "binary,binary")
5200 (set_attr "length" "4,4")])
5203 [(set (match_operand:DI 0 "register_operand" "=r,&r")
5204 (minus:DI (match_operand:DI 1 "arith11_operand" "r,I")
5205 (match_operand:DI 2 "reg_or_0_operand" "rM,rM")))
5206 (trap_if (ne (minus:TI (sign_extend:TI (match_dup 1))
5207 (sign_extend:TI (match_dup 2)))
5208 (sign_extend:TI (minus:DI (match_dup 1)
5214 if (GET_CODE (operands[1]) == CONST_INT)
5216 if (INTVAL (operands[1]) >= 0)
5217 return \"subi %1,%R2,%R0\;{subbo|sub,b,tsv} %%r0,%2,%0\";
5219 return \"ldi -1,%0\;subi %1,%R2,%R0\;{subbo|sub,b,tsv} %0,%2,%0\";
5222 return \"sub %R1,%R2,%R0\;{subbo|sub,b,tsv} %1,%2,%0\";
5224 [(set_attr "type" "binary,binary")
5225 (set (attr "length")
5226 (if_then_else (eq_attr "alternative" "0")
5228 (if_then_else (ge (symbol_ref "INTVAL (operands[1])")
5233 (define_expand "subsi3"
5234 [(set (match_operand:SI 0 "register_operand" "")
5235 (minus:SI (match_operand:SI 1 "arith11_operand" "")
5236 (match_operand:SI 2 "register_operand" "")))]
5241 [(set (match_operand:SI 0 "register_operand" "=r,r")
5242 (minus:SI (match_operand:SI 1 "arith11_operand" "r,I")
5243 (match_operand:SI 2 "register_operand" "r,r")))]
5248 [(set_attr "type" "binary,binary")
5249 (set_attr "length" "4,4")])
5252 [(set (match_operand:SI 0 "register_operand" "=r,r,!q")
5253 (minus:SI (match_operand:SI 1 "arith11_operand" "r,I,!S")
5254 (match_operand:SI 2 "register_operand" "r,r,!r")))]
5260 [(set_attr "type" "binary,binary,move")
5261 (set_attr "length" "4,4,4")])
5263 (define_insn "subvsi3"
5264 [(set (match_operand:SI 0 "register_operand" "=r,r")
5265 (minus:SI (match_operand:SI 1 "arith11_operand" "rM,I")
5266 (match_operand:SI 2 "reg_or_0_operand" "rM,rM")))
5267 (trap_if (ne (minus:DI (sign_extend:DI (match_dup 1))
5268 (sign_extend:DI (match_dup 2)))
5269 (sign_extend:DI (minus:SI (match_dup 1)
5274 {subo|sub,tsv} %1,%2,%0
5275 {subio|subi,tsv} %1,%2,%0"
5276 [(set_attr "type" "binary,binary")
5277 (set_attr "length" "4,4")])
5279 ;; Trap instructions.
5282 [(trap_if (const_int 1) (const_int 0))]
5284 "{addit|addi,tc},<> 1,%%r0,%%r0"
5285 [(set_attr "type" "trap")
5286 (set_attr "length" "4")])
5288 ;; Clobbering a "register_operand" instead of a match_scratch
5289 ;; in operand3 of millicode calls avoids spilling %r1 and
5290 ;; produces better code.
5292 ;; The mulsi3 insns set up registers for the millicode call.
5293 (define_expand "mulsi3"
5294 [(set (reg:SI 26) (match_operand:SI 1 "move_src_operand" ""))
5295 (set (reg:SI 25) (match_operand:SI 2 "move_src_operand" ""))
5296 (parallel [(set (reg:SI 29) (mult:SI (reg:SI 26) (reg:SI 25)))
5297 (clobber (match_dup 3))
5298 (clobber (reg:SI 26))
5299 (clobber (reg:SI 25))
5300 (clobber (match_dup 4))])
5301 (set (match_operand:SI 0 "move_dest_operand" "") (reg:SI 29))]
5305 operands[4] = gen_rtx_REG (SImode, TARGET_64BIT ? 2 : 31);
5306 if (TARGET_PA_11 && !TARGET_DISABLE_FPREGS && !TARGET_SOFT_FLOAT)
5308 rtx scratch = gen_reg_rtx (DImode);
5309 operands[1] = force_reg (SImode, operands[1]);
5310 operands[2] = force_reg (SImode, operands[2]);
5311 emit_insn (gen_umulsidi3 (scratch, operands[1], operands[2]));
5312 emit_insn (gen_movsi (operands[0],
5313 gen_rtx_SUBREG (SImode, scratch,
5314 GET_MODE_SIZE (SImode))));
5317 operands[3] = gen_reg_rtx (SImode);
5320 (define_insn "umulsidi3"
5321 [(set (match_operand:DI 0 "register_operand" "=f")
5322 (mult:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "f"))
5323 (zero_extend:DI (match_operand:SI 2 "register_operand" "f"))))]
5324 "TARGET_PA_11 && ! TARGET_DISABLE_FPREGS && ! TARGET_SOFT_FLOAT"
5326 [(set_attr "type" "fpmuldbl")
5327 (set_attr "length" "4")])
5330 [(set (match_operand:DI 0 "register_operand" "=f")
5331 (mult:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "f"))
5332 (match_operand:DI 2 "uint32_operand" "f")))]
5333 "TARGET_PA_11 && ! TARGET_DISABLE_FPREGS && ! TARGET_SOFT_FLOAT && !TARGET_64BIT"
5335 [(set_attr "type" "fpmuldbl")
5336 (set_attr "length" "4")])
5339 [(set (match_operand:DI 0 "register_operand" "=f")
5340 (mult:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "f"))
5341 (match_operand:DI 2 "uint32_operand" "f")))]
5342 "TARGET_PA_11 && ! TARGET_DISABLE_FPREGS && ! TARGET_SOFT_FLOAT && TARGET_64BIT"
5344 [(set_attr "type" "fpmuldbl")
5345 (set_attr "length" "4")])
5348 [(set (reg:SI 29) (mult:SI (reg:SI 26) (reg:SI 25)))
5349 (clobber (match_operand:SI 0 "register_operand" "=a"))
5350 (clobber (reg:SI 26))
5351 (clobber (reg:SI 25))
5352 (clobber (reg:SI 31))]
5354 "* return pa_output_mul_insn (0, insn);"
5355 [(set_attr "type" "milli")
5356 (set (attr "length")
5357 (cond [(and (const_int 0) (eq (const_int 0) (pc))) (const_int 8)]
5358 (symbol_ref "pa_attr_length_millicode_call (insn)")))])
5361 [(set (reg:SI 29) (mult:SI (reg:SI 26) (reg:SI 25)))
5362 (clobber (match_operand:SI 0 "register_operand" "=a"))
5363 (clobber (reg:SI 26))
5364 (clobber (reg:SI 25))
5365 (clobber (reg:SI 2))]
5367 "* return pa_output_mul_insn (0, insn);"
5368 [(set_attr "type" "milli")
5369 (set (attr "length")
5370 (cond [(and (const_int 0) (eq (const_int 0) (pc))) (const_int 8)]
5371 (symbol_ref "pa_attr_length_millicode_call (insn)")))])
5373 (define_expand "muldi3"
5374 [(set (match_operand:DI 0 "register_operand" "")
5375 (mult:DI (match_operand:DI 1 "register_operand" "")
5376 (match_operand:DI 2 "register_operand" "")))]
5377 "TARGET_64BIT && ! TARGET_DISABLE_FPREGS && ! TARGET_SOFT_FLOAT"
5380 rtx low_product = gen_reg_rtx (DImode);
5381 rtx cross_product1 = gen_reg_rtx (DImode);
5382 rtx cross_product2 = gen_reg_rtx (DImode);
5383 rtx cross_scratch = gen_reg_rtx (DImode);
5384 rtx cross_product = gen_reg_rtx (DImode);
5385 rtx op1l, op1r, op2l, op2r;
5386 rtx op1shifted, op2shifted;
5388 op1shifted = gen_reg_rtx (DImode);
5389 op2shifted = gen_reg_rtx (DImode);
5390 op1l = gen_reg_rtx (SImode);
5391 op1r = gen_reg_rtx (SImode);
5392 op2l = gen_reg_rtx (SImode);
5393 op2r = gen_reg_rtx (SImode);
5395 emit_move_insn (op1shifted, gen_rtx_LSHIFTRT (DImode, operands[1],
5397 emit_move_insn (op2shifted, gen_rtx_LSHIFTRT (DImode, operands[2],
5399 op1r = force_reg (SImode, gen_rtx_SUBREG (SImode, operands[1], 4));
5400 op2r = force_reg (SImode, gen_rtx_SUBREG (SImode, operands[2], 4));
5401 op1l = force_reg (SImode, gen_rtx_SUBREG (SImode, op1shifted, 4));
5402 op2l = force_reg (SImode, gen_rtx_SUBREG (SImode, op2shifted, 4));
5404 /* Emit multiplies for the cross products. */
5405 emit_insn (gen_umulsidi3 (cross_product1, op2r, op1l));
5406 emit_insn (gen_umulsidi3 (cross_product2, op2l, op1r));
5408 /* Emit a multiply for the low sub-word. */
5409 emit_insn (gen_umulsidi3 (low_product, copy_rtx (op2r), copy_rtx (op1r)));
5411 /* Sum the cross products and shift them into proper position. */
5412 emit_insn (gen_adddi3 (cross_scratch, cross_product1, cross_product2));
5413 emit_insn (gen_ashldi3 (cross_product, cross_scratch, GEN_INT (32)));
5415 /* Add the cross product to the low product and store the result
5416 into the output operand . */
5417 emit_insn (gen_adddi3 (operands[0], cross_product, low_product));
5421 ;;; Division and mod.
5422 (define_expand "divsi3"
5423 [(set (reg:SI 26) (match_operand:SI 1 "move_src_operand" ""))
5424 (set (reg:SI 25) (match_operand:SI 2 "move_src_operand" ""))
5425 (parallel [(set (reg:SI 29) (div:SI (reg:SI 26) (reg:SI 25)))
5426 (clobber (match_dup 3))
5427 (clobber (match_dup 4))
5428 (clobber (reg:SI 26))
5429 (clobber (reg:SI 25))
5430 (clobber (match_dup 5))])
5431 (set (match_operand:SI 0 "move_dest_operand" "") (reg:SI 29))]
5435 operands[3] = gen_reg_rtx (SImode);
5438 operands[5] = gen_rtx_REG (SImode, 2);
5439 operands[4] = operands[5];
5443 operands[5] = gen_rtx_REG (SImode, 31);
5444 operands[4] = gen_reg_rtx (SImode);
5446 if (GET_CODE (operands[2]) == CONST_INT && pa_emit_hpdiv_const (operands, 0))
5452 (div:SI (reg:SI 26) (match_operand:SI 0 "div_operand" "")))
5453 (clobber (match_operand:SI 1 "register_operand" "=a"))
5454 (clobber (match_operand:SI 2 "register_operand" "=&r"))
5455 (clobber (reg:SI 26))
5456 (clobber (reg:SI 25))
5457 (clobber (reg:SI 31))]
5460 return pa_output_div_insn (operands, 0, insn);"
5461 [(set_attr "type" "milli")
5462 (set (attr "length")
5463 (cond [(and (const_int 0) (eq (const_int 0) (pc))) (const_int 8)]
5464 (symbol_ref "pa_attr_length_millicode_call (insn)")))])
5468 (div:SI (reg:SI 26) (match_operand:SI 0 "div_operand" "")))
5469 (clobber (match_operand:SI 1 "register_operand" "=a"))
5470 (clobber (match_operand:SI 2 "register_operand" "=&r"))
5471 (clobber (reg:SI 26))
5472 (clobber (reg:SI 25))
5473 (clobber (reg:SI 2))]
5476 return pa_output_div_insn (operands, 0, insn);"
5477 [(set_attr "type" "milli")
5478 (set (attr "length")
5479 (cond [(and (const_int 0) (eq (const_int 0) (pc))) (const_int 8)]
5480 (symbol_ref "pa_attr_length_millicode_call (insn)")))])
5482 (define_expand "udivsi3"
5483 [(set (reg:SI 26) (match_operand:SI 1 "move_src_operand" ""))
5484 (set (reg:SI 25) (match_operand:SI 2 "move_src_operand" ""))
5485 (parallel [(set (reg:SI 29) (udiv:SI (reg:SI 26) (reg:SI 25)))
5486 (clobber (match_dup 3))
5487 (clobber (match_dup 4))
5488 (clobber (reg:SI 26))
5489 (clobber (reg:SI 25))
5490 (clobber (match_dup 5))])
5491 (set (match_operand:SI 0 "move_dest_operand" "") (reg:SI 29))]
5495 operands[3] = gen_reg_rtx (SImode);
5499 operands[5] = gen_rtx_REG (SImode, 2);
5500 operands[4] = operands[5];
5504 operands[5] = gen_rtx_REG (SImode, 31);
5505 operands[4] = gen_reg_rtx (SImode);
5507 if (GET_CODE (operands[2]) == CONST_INT && pa_emit_hpdiv_const (operands, 1))
5513 (udiv:SI (reg:SI 26) (match_operand:SI 0 "div_operand" "")))
5514 (clobber (match_operand:SI 1 "register_operand" "=a"))
5515 (clobber (match_operand:SI 2 "register_operand" "=&r"))
5516 (clobber (reg:SI 26))
5517 (clobber (reg:SI 25))
5518 (clobber (reg:SI 31))]
5521 return pa_output_div_insn (operands, 1, insn);"
5522 [(set_attr "type" "milli")
5523 (set (attr "length")
5524 (cond [(and (const_int 0) (eq (const_int 0) (pc))) (const_int 8)]
5525 (symbol_ref "pa_attr_length_millicode_call (insn)")))])
5529 (udiv:SI (reg:SI 26) (match_operand:SI 0 "div_operand" "")))
5530 (clobber (match_operand:SI 1 "register_operand" "=a"))
5531 (clobber (match_operand:SI 2 "register_operand" "=&r"))
5532 (clobber (reg:SI 26))
5533 (clobber (reg:SI 25))
5534 (clobber (reg:SI 2))]
5537 return pa_output_div_insn (operands, 1, insn);"
5538 [(set_attr "type" "milli")
5539 (set (attr "length")
5540 (cond [(and (const_int 0) (eq (const_int 0) (pc))) (const_int 8)]
5541 (symbol_ref "pa_attr_length_millicode_call (insn)")))])
5543 (define_expand "modsi3"
5544 [(set (reg:SI 26) (match_operand:SI 1 "move_src_operand" ""))
5545 (set (reg:SI 25) (match_operand:SI 2 "move_src_operand" ""))
5546 (parallel [(set (reg:SI 29) (mod:SI (reg:SI 26) (reg:SI 25)))
5547 (clobber (match_dup 3))
5548 (clobber (match_dup 4))
5549 (clobber (reg:SI 26))
5550 (clobber (reg:SI 25))
5551 (clobber (match_dup 5))])
5552 (set (match_operand:SI 0 "move_dest_operand" "") (reg:SI 29))]
5558 operands[5] = gen_rtx_REG (SImode, 2);
5559 operands[4] = operands[5];
5563 operands[5] = gen_rtx_REG (SImode, 31);
5564 operands[4] = gen_reg_rtx (SImode);
5566 operands[3] = gen_reg_rtx (SImode);
5570 [(set (reg:SI 29) (mod:SI (reg:SI 26) (reg:SI 25)))
5571 (clobber (match_operand:SI 0 "register_operand" "=a"))
5572 (clobber (match_operand:SI 1 "register_operand" "=&r"))
5573 (clobber (reg:SI 26))
5574 (clobber (reg:SI 25))
5575 (clobber (reg:SI 31))]
5578 return pa_output_mod_insn (0, insn);"
5579 [(set_attr "type" "milli")
5580 (set (attr "length")
5581 (cond [(and (const_int 0) (eq (const_int 0) (pc))) (const_int 8)]
5582 (symbol_ref "pa_attr_length_millicode_call (insn)")))])
5585 [(set (reg:SI 29) (mod:SI (reg:SI 26) (reg:SI 25)))
5586 (clobber (match_operand:SI 0 "register_operand" "=a"))
5587 (clobber (match_operand:SI 1 "register_operand" "=&r"))
5588 (clobber (reg:SI 26))
5589 (clobber (reg:SI 25))
5590 (clobber (reg:SI 2))]
5593 return pa_output_mod_insn (0, insn);"
5594 [(set_attr "type" "milli")
5595 (set (attr "length")
5596 (cond [(and (const_int 0) (eq (const_int 0) (pc))) (const_int 8)]
5597 (symbol_ref "pa_attr_length_millicode_call (insn)")))])
5599 (define_expand "umodsi3"
5600 [(set (reg:SI 26) (match_operand:SI 1 "move_src_operand" ""))
5601 (set (reg:SI 25) (match_operand:SI 2 "move_src_operand" ""))
5602 (parallel [(set (reg:SI 29) (umod:SI (reg:SI 26) (reg:SI 25)))
5603 (clobber (match_dup 3))
5604 (clobber (match_dup 4))
5605 (clobber (reg:SI 26))
5606 (clobber (reg:SI 25))
5607 (clobber (match_dup 5))])
5608 (set (match_operand:SI 0 "move_dest_operand" "") (reg:SI 29))]
5614 operands[5] = gen_rtx_REG (SImode, 2);
5615 operands[4] = operands[5];
5619 operands[5] = gen_rtx_REG (SImode, 31);
5620 operands[4] = gen_reg_rtx (SImode);
5622 operands[3] = gen_reg_rtx (SImode);
5626 [(set (reg:SI 29) (umod:SI (reg:SI 26) (reg:SI 25)))
5627 (clobber (match_operand:SI 0 "register_operand" "=a"))
5628 (clobber (match_operand:SI 1 "register_operand" "=&r"))
5629 (clobber (reg:SI 26))
5630 (clobber (reg:SI 25))
5631 (clobber (reg:SI 31))]
5634 return pa_output_mod_insn (1, insn);"
5635 [(set_attr "type" "milli")
5636 (set (attr "length")
5637 (cond [(and (const_int 0) (eq (const_int 0) (pc))) (const_int 8)]
5638 (symbol_ref "pa_attr_length_millicode_call (insn)")))])
5641 [(set (reg:SI 29) (umod:SI (reg:SI 26) (reg:SI 25)))
5642 (clobber (match_operand:SI 0 "register_operand" "=a"))
5643 (clobber (match_operand:SI 1 "register_operand" "=&r"))
5644 (clobber (reg:SI 26))
5645 (clobber (reg:SI 25))
5646 (clobber (reg:SI 2))]
5649 return pa_output_mod_insn (1, insn);"
5650 [(set_attr "type" "milli")
5651 (set (attr "length")
5652 (cond [(and (const_int 0) (eq (const_int 0) (pc))) (const_int 8)]
5653 (symbol_ref "pa_attr_length_millicode_call (insn)")))])
5655 ;;- and instructions
5656 ;; We define DImode `and` so with DImode `not` we can get
5657 ;; DImode `andn`. Other combinations are possible.
5659 (define_expand "anddi3"
5660 [(set (match_operand:DI 0 "register_operand" "")
5661 (and:DI (match_operand:DI 1 "register_operand" "")
5662 (match_operand:DI 2 "and_operand" "")))]
5667 [(set (match_operand:DI 0 "register_operand" "=r,r")
5668 (and:DI (match_operand:DI 1 "register_operand" "%?r,0")
5669 (match_operand:DI 2 "and_operand" "rO,P")))]
5671 "* return pa_output_64bit_and (operands); "
5672 [(set_attr "type" "binary")
5673 (set_attr "length" "4")])
5675 ; The ? for op1 makes reload prefer zdepi instead of loading a huge
5676 ; constant with ldil;ldo.
5677 (define_insn "andsi3"
5678 [(set (match_operand:SI 0 "register_operand" "=r,r")
5679 (and:SI (match_operand:SI 1 "register_operand" "%?r,0")
5680 (match_operand:SI 2 "and_operand" "rO,P")))]
5682 "* return pa_output_and (operands); "
5683 [(set_attr "type" "binary,shift")
5684 (set_attr "length" "4,4")])
5687 [(set (match_operand:DI 0 "register_operand" "=r")
5688 (and:DI (not:DI (match_operand:DI 1 "register_operand" "r"))
5689 (match_operand:DI 2 "register_operand" "r")))]
5692 [(set_attr "type" "binary")
5693 (set_attr "length" "4")])
5696 [(set (match_operand:SI 0 "register_operand" "=r")
5697 (and:SI (not:SI (match_operand:SI 1 "register_operand" "r"))
5698 (match_operand:SI 2 "register_operand" "r")))]
5701 [(set_attr "type" "binary")
5702 (set_attr "length" "4")])
5704 (define_expand "iordi3"
5705 [(set (match_operand:DI 0 "register_operand" "")
5706 (ior:DI (match_operand:DI 1 "register_operand" "")
5707 (match_operand:DI 2 "reg_or_cint_ior_operand" "")))]
5712 [(set (match_operand:DI 0 "register_operand" "=r,r")
5713 (ior:DI (match_operand:DI 1 "register_operand" "0,0")
5714 (match_operand:DI 2 "cint_ior_operand" "M,i")))]
5716 "* return pa_output_64bit_ior (operands); "
5717 [(set_attr "type" "binary,shift")
5718 (set_attr "length" "4,4")])
5721 [(set (match_operand:DI 0 "register_operand" "=r")
5722 (ior:DI (match_operand:DI 1 "register_operand" "%r")
5723 (match_operand:DI 2 "register_operand" "r")))]
5726 [(set_attr "type" "binary")
5727 (set_attr "length" "4")])
5729 ;; Need a define_expand because we've run out of CONST_OK... characters.
5730 (define_expand "iorsi3"
5731 [(set (match_operand:SI 0 "register_operand" "")
5732 (ior:SI (match_operand:SI 1 "register_operand" "")
5733 (match_operand:SI 2 "reg_or_cint_ior_operand" "")))]
5738 [(set (match_operand:SI 0 "register_operand" "=r,r")
5739 (ior:SI (match_operand:SI 1 "register_operand" "0,0")
5740 (match_operand:SI 2 "cint_ior_operand" "M,i")))]
5742 "* return pa_output_ior (operands); "
5743 [(set_attr "type" "binary,shift")
5744 (set_attr "length" "4,4")])
5747 [(set (match_operand:SI 0 "register_operand" "=r")
5748 (ior:SI (match_operand:SI 1 "register_operand" "%r")
5749 (match_operand:SI 2 "register_operand" "r")))]
5752 [(set_attr "type" "binary")
5753 (set_attr "length" "4")])
5755 (define_expand "xordi3"
5756 [(set (match_operand:DI 0 "register_operand" "")
5757 (xor:DI (match_operand:DI 1 "register_operand" "")
5758 (match_operand:DI 2 "register_operand" "")))]
5763 [(set (match_operand:DI 0 "register_operand" "=r")
5764 (xor:DI (match_operand:DI 1 "register_operand" "%r")
5765 (match_operand:DI 2 "register_operand" "r")))]
5768 [(set_attr "type" "binary")
5769 (set_attr "length" "4")])
5771 (define_insn "xorsi3"
5772 [(set (match_operand:SI 0 "register_operand" "=r")
5773 (xor:SI (match_operand:SI 1 "register_operand" "%r")
5774 (match_operand:SI 2 "register_operand" "r")))]
5777 [(set_attr "type" "binary")
5778 (set_attr "length" "4")])
5780 (define_expand "negdi2"
5781 [(set (match_operand:DI 0 "register_operand" "")
5782 (neg:DI (match_operand:DI 1 "register_operand" "")))]
5787 [(set (match_operand:DI 0 "register_operand" "=r")
5788 (neg:DI (match_operand:DI 1 "register_operand" "r")))]
5790 "sub %%r0,%R1,%R0\;{subb|sub,b} %%r0,%1,%0"
5791 [(set_attr "type" "unary")
5792 (set_attr "length" "8")])
5795 [(set (match_operand:DI 0 "register_operand" "=r")
5796 (neg:DI (match_operand:DI 1 "register_operand" "r")))]
5799 [(set_attr "type" "unary")
5800 (set_attr "length" "4")])
5802 (define_expand "negvdi2"
5803 [(parallel [(set (match_operand:DI 0 "register_operand" "")
5804 (neg:DI (match_operand:DI 1 "register_operand" "")))
5805 (trap_if (ne (neg:TI (sign_extend:TI (match_dup 1)))
5806 (sign_extend:TI (neg:DI (match_dup 1))))
5812 [(set (match_operand:DI 0 "register_operand" "=r")
5813 (neg:DI (match_operand:DI 1 "register_operand" "r")))
5814 (trap_if (ne (neg:TI (sign_extend:TI (match_dup 1)))
5815 (sign_extend:TI (neg:DI (match_dup 1))))
5818 "sub %%r0,%R1,%R0\;{subbo|sub,b,tsv} %%r0,%1,%0"
5819 [(set_attr "type" "unary")
5820 (set_attr "length" "8")])
5823 [(set (match_operand:DI 0 "register_operand" "=r")
5824 (neg:DI (match_operand:DI 1 "register_operand" "r")))
5825 (trap_if (ne (neg:TI (sign_extend:TI (match_dup 1)))
5826 (sign_extend:TI (neg:DI (match_dup 1))))
5829 "sub,tsv %%r0,%1,%0"
5830 [(set_attr "type" "unary")
5831 (set_attr "length" "4")])
5833 (define_insn "negsi2"
5834 [(set (match_operand:SI 0 "register_operand" "=r")
5835 (neg:SI (match_operand:SI 1 "register_operand" "r")))]
5838 [(set_attr "type" "unary")
5839 (set_attr "length" "4")])
5841 (define_insn "negvsi2"
5842 [(set (match_operand:SI 0 "register_operand" "=r")
5843 (neg:SI (match_operand:SI 1 "register_operand" "r")))
5844 (trap_if (ne (neg:DI (sign_extend:DI (match_dup 1)))
5845 (sign_extend:DI (neg:SI (match_dup 1))))
5848 "{subo|sub,tsv} %%r0,%1,%0"
5849 [(set_attr "type" "unary")
5850 (set_attr "length" "4")])
5852 (define_expand "one_cmpldi2"
5853 [(set (match_operand:DI 0 "register_operand" "")
5854 (not:DI (match_operand:DI 1 "register_operand" "")))]
5861 [(set (match_operand:DI 0 "register_operand" "=r")
5862 (not:DI (match_operand:DI 1 "register_operand" "r")))]
5864 "uaddcm %%r0,%1,%0\;uaddcm %%r0,%R1,%R0"
5865 [(set_attr "type" "unary")
5866 (set_attr "length" "8")])
5869 [(set (match_operand:DI 0 "register_operand" "=r")
5870 (not:DI (match_operand:DI 1 "register_operand" "r")))]
5873 [(set_attr "type" "unary")
5874 (set_attr "length" "4")])
5876 (define_insn "one_cmplsi2"
5877 [(set (match_operand:SI 0 "register_operand" "=r")
5878 (not:SI (match_operand:SI 1 "register_operand" "r")))]
5881 [(set_attr "type" "unary")
5882 (set_attr "length" "4")])
5884 ;; Floating point arithmetic instructions.
5886 (define_insn "adddf3"
5887 [(set (match_operand:DF 0 "register_operand" "=f")
5888 (plus:DF (match_operand:DF 1 "register_operand" "f")
5889 (match_operand:DF 2 "register_operand" "f")))]
5890 "! TARGET_SOFT_FLOAT"
5892 [(set_attr "type" "fpalu")
5893 (set_attr "pa_combine_type" "faddsub")
5894 (set_attr "length" "4")])
5896 (define_insn "addsf3"
5897 [(set (match_operand:SF 0 "register_operand" "=f")
5898 (plus:SF (match_operand:SF 1 "register_operand" "f")
5899 (match_operand:SF 2 "register_operand" "f")))]
5900 "! TARGET_SOFT_FLOAT"
5902 [(set_attr "type" "fpalu")
5903 (set_attr "pa_combine_type" "faddsub")
5904 (set_attr "length" "4")])
5906 (define_insn "subdf3"
5907 [(set (match_operand:DF 0 "register_operand" "=f")
5908 (minus:DF (match_operand:DF 1 "register_operand" "f")
5909 (match_operand:DF 2 "register_operand" "f")))]
5910 "! TARGET_SOFT_FLOAT"
5912 [(set_attr "type" "fpalu")
5913 (set_attr "pa_combine_type" "faddsub")
5914 (set_attr "length" "4")])
5916 (define_insn "subsf3"
5917 [(set (match_operand:SF 0 "register_operand" "=f")
5918 (minus:SF (match_operand:SF 1 "register_operand" "f")
5919 (match_operand:SF 2 "register_operand" "f")))]
5920 "! TARGET_SOFT_FLOAT"
5922 [(set_attr "type" "fpalu")
5923 (set_attr "pa_combine_type" "faddsub")
5924 (set_attr "length" "4")])
5926 (define_insn "muldf3"
5927 [(set (match_operand:DF 0 "register_operand" "=f")
5928 (mult:DF (match_operand:DF 1 "register_operand" "f")
5929 (match_operand:DF 2 "register_operand" "f")))]
5930 "! TARGET_SOFT_FLOAT"
5932 [(set_attr "type" "fpmuldbl")
5933 (set_attr "pa_combine_type" "fmpy")
5934 (set_attr "length" "4")])
5936 (define_insn "mulsf3"
5937 [(set (match_operand:SF 0 "register_operand" "=f")
5938 (mult:SF (match_operand:SF 1 "register_operand" "f")
5939 (match_operand:SF 2 "register_operand" "f")))]
5940 "! TARGET_SOFT_FLOAT"
5942 [(set_attr "type" "fpmulsgl")
5943 (set_attr "pa_combine_type" "fmpy")
5944 (set_attr "length" "4")])
5946 (define_insn "divdf3"
5947 [(set (match_operand:DF 0 "register_operand" "=f")
5948 (div:DF (match_operand:DF 1 "register_operand" "f")
5949 (match_operand:DF 2 "register_operand" "f")))]
5950 "! TARGET_SOFT_FLOAT"
5952 [(set_attr "type" "fpdivdbl")
5953 (set_attr "length" "4")])
5955 (define_insn "divsf3"
5956 [(set (match_operand:SF 0 "register_operand" "=f")
5957 (div:SF (match_operand:SF 1 "register_operand" "f")
5958 (match_operand:SF 2 "register_operand" "f")))]
5959 "! TARGET_SOFT_FLOAT"
5961 [(set_attr "type" "fpdivsgl")
5962 (set_attr "length" "4")])
5964 ;; Processors prior to PA 2.0 don't have a fneg instruction. Fast
5965 ;; negation can be done by subtracting from plus zero. However, this
5966 ;; violates the IEEE standard when negating plus and minus zero.
5967 ;; The slow path toggles the sign bit in the general registers.
5968 (define_expand "negdf2"
5969 [(set (match_operand:DF 0 "register_operand" "")
5970 (neg:DF (match_operand:DF 1 "register_operand" "")))]
5971 "!TARGET_SOFT_FLOAT"
5973 if (TARGET_PA_20 || !flag_signed_zeros)
5974 emit_insn (gen_negdf2_fast (operands[0], operands[1]));
5976 emit_insn (gen_negdf2_slow (operands[0], operands[1]));
5980 (define_insn "negdf2_slow"
5981 [(set (match_operand:DF 0 "register_operand" "=r")
5982 (neg:DF (match_operand:DF 1 "register_operand" "r")))]
5983 "!TARGET_SOFT_FLOAT && !TARGET_PA_20"
5986 if (rtx_equal_p (operands[0], operands[1]))
5987 return \"and,< %1,%1,%0\;depi,tr 1,0,1,%0\;depi 0,0,1,%0\";
5989 return \"and,< %1,%1,%0\;depi,tr 1,0,1,%0\;depi 0,0,1,%0\;copy %R1,%R0\";
5991 [(set_attr "type" "multi")
5992 (set (attr "length")
5993 (if_then_else (match_test "rtx_equal_p (operands[0], operands[1])")
5997 (define_insn "negdf2_fast"
5998 [(set (match_operand:DF 0 "register_operand" "=f")
5999 (neg:DF (match_operand:DF 1 "register_operand" "f")))]
6000 "!TARGET_SOFT_FLOAT"
6004 return \"fneg,dbl %1,%0\";
6006 return \"fsub,dbl %%fr0,%1,%0\";
6008 [(set_attr "type" "fpalu")
6009 (set_attr "length" "4")])
6011 (define_expand "negsf2"
6012 [(set (match_operand:SF 0 "register_operand" "")
6013 (neg:SF (match_operand:SF 1 "register_operand" "")))]
6014 "!TARGET_SOFT_FLOAT"
6016 if (TARGET_PA_20 || !flag_signed_zeros)
6017 emit_insn (gen_negsf2_fast (operands[0], operands[1]));
6019 emit_insn (gen_negsf2_slow (operands[0], operands[1]));
6023 (define_insn "negsf2_slow"
6024 [(set (match_operand:SF 0 "register_operand" "=r")
6025 (neg:SF (match_operand:SF 1 "register_operand" "r")))]
6026 "!TARGET_SOFT_FLOAT && !TARGET_PA_20"
6027 "and,< %1,%1,%0\;depi,tr 1,0,1,%0\;depi 0,0,1,%0"
6028 [(set_attr "type" "multi")
6029 (set_attr "length" "12")])
6031 (define_insn "negsf2_fast"
6032 [(set (match_operand:SF 0 "register_operand" "=f")
6033 (neg:SF (match_operand:SF 1 "register_operand" "f")))]
6034 "!TARGET_SOFT_FLOAT"
6038 return \"fneg,sgl %1,%0\";
6040 return \"fsub,sgl %%fr0,%1,%0\";
6042 [(set_attr "type" "fpalu")
6043 (set_attr "length" "4")])
6045 (define_insn "absdf2"
6046 [(set (match_operand:DF 0 "register_operand" "=f")
6047 (abs:DF (match_operand:DF 1 "register_operand" "f")))]
6048 "! TARGET_SOFT_FLOAT"
6050 [(set_attr "type" "fpalu")
6051 (set_attr "length" "4")])
6053 (define_insn "abssf2"
6054 [(set (match_operand:SF 0 "register_operand" "=f")
6055 (abs:SF (match_operand:SF 1 "register_operand" "f")))]
6056 "! TARGET_SOFT_FLOAT"
6058 [(set_attr "type" "fpalu")
6059 (set_attr "length" "4")])
6061 (define_insn "sqrtdf2"
6062 [(set (match_operand:DF 0 "register_operand" "=f")
6063 (sqrt:DF (match_operand:DF 1 "register_operand" "f")))]
6064 "! TARGET_SOFT_FLOAT"
6066 [(set_attr "type" "fpsqrtdbl")
6067 (set_attr "length" "4")])
6069 (define_insn "sqrtsf2"
6070 [(set (match_operand:SF 0 "register_operand" "=f")
6071 (sqrt:SF (match_operand:SF 1 "register_operand" "f")))]
6072 "! TARGET_SOFT_FLOAT"
6074 [(set_attr "type" "fpsqrtsgl")
6075 (set_attr "length" "4")])
6077 ;; PA 2.0 floating point instructions
6080 (define_insn "fmadf4"
6081 [(set (match_operand:DF 0 "register_operand" "=f")
6082 (fma:DF (match_operand:DF 1 "register_operand" "f")
6083 (match_operand:DF 2 "register_operand" "f")
6084 (match_operand:DF 3 "register_operand" "f")))]
6085 "TARGET_PA_20 && ! TARGET_SOFT_FLOAT"
6086 "fmpyfadd,dbl %1,%2,%3,%0"
6087 [(set_attr "type" "fpmuldbl")
6088 (set_attr "length" "4")])
6090 (define_insn "fmasf4"
6091 [(set (match_operand:SF 0 "register_operand" "=f")
6092 (fma:SF (match_operand:SF 1 "register_operand" "f")
6093 (match_operand:SF 2 "register_operand" "f")
6094 (match_operand:SF 3 "register_operand" "f")))]
6095 "TARGET_PA_20 && ! TARGET_SOFT_FLOAT"
6096 "fmpyfadd,sgl %1,%2,%3,%0"
6097 [(set_attr "type" "fpmulsgl")
6098 (set_attr "length" "4")])
6100 ; fmpynfadd patterns
6101 (define_insn "fnmadf4"
6102 [(set (match_operand:DF 0 "register_operand" "=f")
6103 (fma:DF (neg:DF (match_operand:DF 1 "register_operand" "f"))
6104 (match_operand:DF 2 "register_operand" "f")
6105 (match_operand:DF 3 "register_operand" "f")))]
6106 "TARGET_PA_20 && ! TARGET_SOFT_FLOAT"
6107 "fmpynfadd,dbl %1,%2,%3,%0"
6108 [(set_attr "type" "fpmuldbl")
6109 (set_attr "length" "4")])
6111 (define_insn "fnmasf4"
6112 [(set (match_operand:SF 0 "register_operand" "=f")
6113 (fma:SF (neg:SF (match_operand:SF 1 "register_operand" "f"))
6114 (match_operand:SF 2 "register_operand" "f")
6115 (match_operand:SF 3 "register_operand" "f")))]
6116 "TARGET_PA_20 && ! TARGET_SOFT_FLOAT"
6117 "fmpynfadd,sgl %1,%2,%3,%0"
6118 [(set_attr "type" "fpmulsgl")
6119 (set_attr "length" "4")])
6123 [(set (match_operand:DF 0 "register_operand" "=f")
6124 (neg:DF (abs:DF (match_operand:DF 1 "register_operand" "f"))))]
6125 "TARGET_PA_20 && ! TARGET_SOFT_FLOAT"
6127 [(set_attr "type" "fpalu")
6128 (set_attr "length" "4")])
6131 [(set (match_operand:SF 0 "register_operand" "=f")
6132 (neg:SF (abs:SF (match_operand:SF 1 "register_operand" "f"))))]
6133 "TARGET_PA_20 && ! TARGET_SOFT_FLOAT"
6135 [(set_attr "type" "fpalu")
6136 (set_attr "length" "4")])
6139 [(set (match_operand:DF 0 "register_operand" "=f")
6140 (neg:DF (abs:DF (match_operand:DF 1 "register_operand" "f"))))
6141 (set (match_operand:DF 2 "register_operand" "=&f") (abs:DF (match_dup 1)))]
6142 "(! TARGET_SOFT_FLOAT && TARGET_PA_20
6143 && ! reg_overlap_mentioned_p (operands[2], operands[1]))"
6145 [(set_attr "type" "fpalu")
6146 (set_attr "length" "8")])
6149 [(set (match_operand:DF 0 "register_operand" "")
6150 (neg:DF (abs:DF (match_operand:DF 1 "register_operand" ""))))
6151 (set (match_operand:DF 2 "register_operand" "") (abs:DF (match_dup 1)))]
6152 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
6153 [(set (match_dup 2) (abs:DF (match_dup 1)))
6154 (set (match_dup 0) (neg:DF (abs:DF (match_dup 1))))]
6158 [(set (match_operand:SF 0 "register_operand" "=f")
6159 (neg:SF (abs:SF (match_operand:SF 1 "register_operand" "f"))))
6160 (set (match_operand:SF 2 "register_operand" "=&f") (abs:SF (match_dup 1)))]
6161 "(! TARGET_SOFT_FLOAT && TARGET_PA_20
6162 && ! reg_overlap_mentioned_p (operands[2], operands[1]))"
6164 [(set_attr "type" "fpalu")
6165 (set_attr "length" "8")])
6168 [(set (match_operand:SF 0 "register_operand" "")
6169 (neg:SF (abs:SF (match_operand:SF 1 "register_operand" ""))))
6170 (set (match_operand:SF 2 "register_operand" "") (abs:SF (match_dup 1)))]
6171 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
6172 [(set (match_dup 2) (abs:SF (match_dup 1)))
6173 (set (match_dup 0) (neg:SF (abs:SF (match_dup 1))))]
6176 ;; Negating a multiply can be faked by adding zero in a fused multiply-add
6177 ;; instruction if we can ignore the sign of zero.
6179 [(set (match_operand:DF 0 "register_operand" "=f")
6180 (neg:DF (mult:DF (match_operand:DF 1 "register_operand" "f")
6181 (match_operand:DF 2 "register_operand" "f"))))]
6182 "!TARGET_SOFT_FLOAT && TARGET_PA_20 && !flag_signed_zeros"
6183 "fmpynfadd,dbl %1,%2,%%fr0,%0"
6184 [(set_attr "type" "fpmuldbl")
6185 (set_attr "length" "4")])
6188 [(set (match_operand:SF 0 "register_operand" "=f")
6189 (neg:SF (mult:SF (match_operand:SF 1 "register_operand" "f")
6190 (match_operand:SF 2 "register_operand" "f"))))]
6191 "!TARGET_SOFT_FLOAT && TARGET_PA_20 && !flag_signed_zeros"
6192 "fmpynfadd,sgl %1,%2,%%fr0,%0"
6193 [(set_attr "type" "fpmuldbl")
6194 (set_attr "length" "4")])
6197 [(set (match_operand:DF 0 "register_operand" "=f")
6198 (neg:DF (mult:DF (match_operand:DF 1 "register_operand" "f")
6199 (match_operand:DF 2 "register_operand" "f"))))
6200 (set (match_operand:DF 3 "register_operand" "=&f")
6201 (mult:DF (match_dup 1) (match_dup 2)))]
6202 "(!TARGET_SOFT_FLOAT && TARGET_PA_20 && !flag_signed_zeros
6203 && ! (reg_overlap_mentioned_p (operands[3], operands[1])
6204 || reg_overlap_mentioned_p (operands[3], operands[2])))"
6206 [(set_attr "type" "fpmuldbl")
6207 (set_attr "length" "8")])
6210 [(set (match_operand:DF 0 "register_operand" "")
6211 (neg:DF (mult:DF (match_operand:DF 1 "register_operand" "")
6212 (match_operand:DF 2 "register_operand" ""))))
6213 (set (match_operand:DF 3 "register_operand" "")
6214 (mult:DF (match_dup 1) (match_dup 2)))]
6215 "!TARGET_SOFT_FLOAT && TARGET_PA_20 && !flag_signed_zeros"
6216 [(set (match_dup 3) (mult:DF (match_dup 1) (match_dup 2)))
6217 (set (match_dup 0) (neg:DF (mult:DF (match_dup 1) (match_dup 2))))]
6221 [(set (match_operand:SF 0 "register_operand" "=f")
6222 (neg:SF (mult:SF (match_operand:SF 1 "register_operand" "f")
6223 (match_operand:SF 2 "register_operand" "f"))))
6224 (set (match_operand:SF 3 "register_operand" "=&f")
6225 (mult:SF (match_dup 1) (match_dup 2)))]
6226 "(!TARGET_SOFT_FLOAT && TARGET_PA_20 && !flag_signed_zeros
6227 && ! (reg_overlap_mentioned_p (operands[3], operands[1])
6228 || reg_overlap_mentioned_p (operands[3], operands[2])))"
6230 [(set_attr "type" "fpmuldbl")
6231 (set_attr "length" "8")])
6234 [(set (match_operand:SF 0 "register_operand" "")
6235 (neg:SF (mult:SF (match_operand:SF 1 "register_operand" "")
6236 (match_operand:SF 2 "register_operand" ""))))
6237 (set (match_operand:SF 3 "register_operand" "")
6238 (mult:SF (match_dup 1) (match_dup 2)))]
6239 "!TARGET_SOFT_FLOAT && TARGET_PA_20&& !flag_signed_zeros"
6240 [(set (match_dup 3) (mult:SF (match_dup 1) (match_dup 2)))
6241 (set (match_dup 0) (neg:SF (mult:SF (match_dup 1) (match_dup 2))))]
6244 ;;- Shift instructions
6246 ;; Optimized special case of shifting.
6249 [(set (match_operand:SI 0 "register_operand" "=r")
6250 (lshiftrt:SI (match_operand:SI 1 "memory_operand" "m")
6254 [(set_attr "type" "load")
6255 (set_attr "length" "4")])
6258 [(set (match_operand:SI 0 "register_operand" "=r")
6259 (lshiftrt:SI (match_operand:SI 1 "memory_operand" "m")
6263 [(set_attr "type" "load")
6264 (set_attr "length" "4")])
6267 [(set (match_operand:SI 0 "register_operand" "=r")
6268 (plus:SI (ashift:SI (match_operand:SI 2 "register_operand" "r")
6269 (match_operand:SI 3 "shadd_operand" ""))
6270 (match_operand:SI 1 "register_operand" "r")))]
6272 "{sh%o3addl %2,%1,%0|shladd,l %2,%o3,%1,%0} "
6273 [(set_attr "type" "binary")
6274 (set_attr "length" "4")])
6277 [(set (match_operand:SI 0 "register_operand" "=r")
6278 (plus:SI (mult:SI (match_operand:SI 2 "register_operand" "r")
6279 (match_operand:SI 3 "mem_shadd_operand" ""))
6280 (match_operand:SI 1 "register_operand" "r")))]
6284 int shift_val = exact_log2 (INTVAL (operands[3]));
6285 operands[3] = GEN_INT (shift_val);
6286 return \"{sh%o3addl %2,%1,%0|shladd,l %2,%o3,%1,%0}\";
6288 [(set_attr "type" "binary")
6289 (set_attr "length" "4")])
6292 [(set (match_operand:DI 0 "register_operand" "=r")
6293 (plus:DI (ashift:DI (match_operand:DI 2 "register_operand" "r")
6294 (match_operand:DI 3 "shadd_operand" ""))
6295 (match_operand:DI 1 "register_operand" "r")))]
6297 "shladd,l %2,%o3,%1,%0"
6298 [(set_attr "type" "binary")
6299 (set_attr "length" "4")])
6302 [(set (match_operand:DI 0 "register_operand" "=r")
6303 (plus:DI (mult:DI (match_operand:DI 2 "register_operand" "r")
6304 (match_operand:DI 3 "mem_shadd_operand" ""))
6305 (match_operand:DI 1 "register_operand" "r")))]
6309 int shift_val = exact_log2 (INTVAL (operands[3]));
6310 operands[3] = GEN_INT (shift_val);
6311 return \"shladd,l %2,%o3,%1,%0\";
6313 [(set_attr "type" "binary")
6314 (set_attr "length" "4")])
6316 (define_expand "ashlsi3"
6317 [(set (match_operand:SI 0 "register_operand" "")
6318 (ashift:SI (match_operand:SI 1 "lhs_lshift_operand" "")
6319 (match_operand:SI 2 "arith32_operand" "")))]
6323 if (GET_CODE (operands[2]) != CONST_INT)
6325 rtx temp = gen_reg_rtx (SImode);
6326 emit_insn (gen_subsi3 (temp, GEN_INT (31), operands[2]));
6327 if (GET_CODE (operands[1]) == CONST_INT)
6328 emit_insn (gen_zvdep_imm32 (operands[0], operands[1], temp));
6330 emit_insn (gen_zvdep32 (operands[0], operands[1], temp));
6333 /* Make sure both inputs are not constants,
6334 there are no patterns for that. */
6335 operands[1] = force_reg (SImode, operands[1]);
6339 [(set (match_operand:SI 0 "register_operand" "=r")
6340 (ashift:SI (match_operand:SI 1 "register_operand" "r")
6341 (match_operand:SI 2 "const_int_operand" "n")))]
6343 "{zdep|depw,z} %1,%P2,%L2,%0"
6344 [(set_attr "type" "shift")
6345 (set_attr "length" "4")])
6347 ; Match cases of op1 a CONST_INT here that zvdep_imm32 doesn't handle.
6348 ; Doing it like this makes slightly better code since reload can
6349 ; replace a register with a known value in range -16..15 with a
6350 ; constant. Ideally, we would like to merge zvdep32 and zvdep_imm32,
6351 ; but since we have no more CONST_OK... characters, that is not
6353 (define_insn "zvdep32"
6354 [(set (match_operand:SI 0 "register_operand" "=r,r")
6355 (ashift:SI (match_operand:SI 1 "arith5_operand" "r,L")
6356 (minus:SI (const_int 31)
6357 (match_operand:SI 2 "register_operand" "q,q"))))]
6360 {zvdep %1,32,%0|depw,z %1,%%sar,32,%0}
6361 {zvdepi %1,32,%0|depwi,z %1,%%sar,32,%0}"
6362 [(set_attr "type" "shift,shift")
6363 (set_attr "length" "4,4")])
6365 (define_insn "zvdep_imm32"
6366 [(set (match_operand:SI 0 "register_operand" "=r")
6367 (ashift:SI (match_operand:SI 1 "lhs_lshift_cint_operand" "")
6368 (minus:SI (const_int 31)
6369 (match_operand:SI 2 "register_operand" "q"))))]
6373 unsigned HOST_WIDE_INT x = UINTVAL (operands[1]);
6374 operands[2] = GEN_INT (4 + exact_log2 ((x >> 4) + 1));
6375 operands[1] = GEN_INT ((x & 0xf) - 0x10);
6376 return \"{zvdepi %1,%2,%0|depwi,z %1,%%sar,%2,%0}\";
6378 [(set_attr "type" "shift")
6379 (set_attr "length" "4")])
6381 (define_insn "vdepi_ior"
6382 [(set (match_operand:SI 0 "register_operand" "=r")
6383 (ior:SI (ashift:SI (match_operand:SI 1 "const_int_operand" "")
6384 (minus:SI (const_int 31)
6385 (match_operand:SI 2 "register_operand" "q")))
6386 (match_operand:SI 3 "register_operand" "0")))]
6387 ; accept ...0001...1, can this be generalized?
6388 "exact_log2 (INTVAL (operands[1]) + 1) > 0"
6391 HOST_WIDE_INT x = INTVAL (operands[1]);
6392 operands[2] = GEN_INT (exact_log2 (x + 1));
6393 return \"{vdepi -1,%2,%0|depwi -1,%%sar,%2,%0}\";
6395 [(set_attr "type" "shift")
6396 (set_attr "length" "4")])
6398 (define_insn "vdepi_and"
6399 [(set (match_operand:SI 0 "register_operand" "=r")
6400 (and:SI (rotate:SI (match_operand:SI 1 "const_int_operand" "")
6401 (minus:SI (const_int 31)
6402 (match_operand:SI 2 "register_operand" "q")))
6403 (match_operand:SI 3 "register_operand" "0")))]
6404 ; this can be generalized...!
6405 "INTVAL (operands[1]) == -2"
6408 HOST_WIDE_INT x = INTVAL (operands[1]);
6409 operands[2] = GEN_INT (exact_log2 ((~x) + 1));
6410 return \"{vdepi 0,%2,%0|depwi 0,%%sar,%2,%0}\";
6412 [(set_attr "type" "shift")
6413 (set_attr "length" "4")])
6415 (define_expand "ashldi3"
6416 [(set (match_operand:DI 0 "register_operand" "")
6417 (ashift:DI (match_operand:DI 1 "lhs_lshift_operand" "")
6418 (match_operand:DI 2 "arith32_operand" "")))]
6424 if (REG_P (operands[0]) && GET_CODE (operands[2]) == CONST_INT)
6426 unsigned HOST_WIDE_INT shift = UINTVAL (operands[2]);
6427 if (shift >= 1 && shift <= 31)
6429 rtx dst = operands[0];
6430 rtx src = force_reg (DImode, operands[1]);
6431 emit_insn (gen_shd_internal (gen_highpart (SImode, dst),
6432 gen_lowpart (SImode, src),
6434 gen_highpart (SImode, src),
6436 emit_insn (gen_ashlsi3 (gen_lowpart (SImode, dst),
6437 gen_lowpart (SImode, src),
6442 /* Fallback to using optabs.c's expand_doubleword_shift. */
6445 if (GET_CODE (operands[2]) != CONST_INT)
6447 rtx temp = gen_reg_rtx (DImode);
6448 emit_insn (gen_subdi3 (temp, GEN_INT (63), operands[2]));
6449 if (GET_CODE (operands[1]) == CONST_INT)
6450 emit_insn (gen_zvdep_imm64 (operands[0], operands[1], temp));
6452 emit_insn (gen_zvdep64 (operands[0], operands[1], temp));
6455 /* Make sure both inputs are not constants,
6456 there are no patterns for that. */
6457 operands[1] = force_reg (DImode, operands[1]);
6461 [(set (match_operand:DI 0 "register_operand" "=r")
6462 (ashift:DI (match_operand:DI 1 "register_operand" "r")
6463 (match_operand:DI 2 "const_int_operand" "n")))]
6465 "depd,z %1,%p2,%Q2,%0"
6466 [(set_attr "type" "shift")
6467 (set_attr "length" "4")])
6469 ; Match cases of op1 a CONST_INT here that zvdep_imm64 doesn't handle.
6470 ; Doing it like this makes slightly better code since reload can
6471 ; replace a register with a known value in range -16..15 with a
6472 ; constant. Ideally, we would like to merge zvdep64 and zvdep_imm64,
6473 ; but since we have no more CONST_OK... characters, that is not
6475 (define_insn "zvdep64"
6476 [(set (match_operand:DI 0 "register_operand" "=r,r")
6477 (ashift:DI (match_operand:DI 1 "arith5_operand" "r,L")
6478 (minus:DI (const_int 63)
6479 (match_operand:DI 2 "register_operand" "q,q"))))]
6482 depd,z %1,%%sar,64,%0
6483 depdi,z %1,%%sar,64,%0"
6484 [(set_attr "type" "shift,shift")
6485 (set_attr "length" "4,4")])
6487 (define_insn "zvdep_imm64"
6488 [(set (match_operand:DI 0 "register_operand" "=r")
6489 (ashift:DI (match_operand:DI 1 "lhs_lshift_cint_operand" "")
6490 (minus:DI (const_int 63)
6491 (match_operand:DI 2 "register_operand" "q"))))]
6495 unsigned HOST_WIDE_INT x = UINTVAL (operands[1]);
6496 operands[2] = GEN_INT (4 + exact_log2 ((x >> 4) + 1));
6497 operands[1] = GEN_INT ((x & 0x1f) - 0x20);
6498 return \"depdi,z %1,%%sar,%2,%0\";
6500 [(set_attr "type" "shift")
6501 (set_attr "length" "4")])
6504 [(set (match_operand:DI 0 "register_operand" "=r")
6505 (ior:DI (ashift:DI (match_operand:DI 1 "const_int_operand" "")
6506 (minus:DI (const_int 63)
6507 (match_operand:DI 2 "register_operand" "q")))
6508 (match_operand:DI 3 "register_operand" "0")))]
6509 ; accept ...0001...1, can this be generalized?
6510 "TARGET_64BIT && exact_log2 (INTVAL (operands[1]) + 1) > 0"
6513 HOST_WIDE_INT x = INTVAL (operands[1]);
6514 operands[2] = GEN_INT (exact_log2 (x + 1));
6515 return \"depdi -1,%%sar,%2,%0\";
6517 [(set_attr "type" "shift")
6518 (set_attr "length" "4")])
6521 [(set (match_operand:DI 0 "register_operand" "=r")
6522 (and:DI (rotate:DI (match_operand:DI 1 "const_int_operand" "")
6523 (minus:DI (const_int 63)
6524 (match_operand:DI 2 "register_operand" "q")))
6525 (match_operand:DI 3 "register_operand" "0")))]
6526 ; this can be generalized...!
6527 "TARGET_64BIT && INTVAL (operands[1]) == -2"
6530 HOST_WIDE_INT x = INTVAL (operands[1]);
6531 operands[2] = GEN_INT (exact_log2 ((~x) + 1));
6532 return \"depdi 0,%%sar,%2,%0\";
6534 [(set_attr "type" "shift")
6535 (set_attr "length" "4")])
6537 (define_expand "ashrsi3"
6538 [(set (match_operand:SI 0 "register_operand" "")
6539 (ashiftrt:SI (match_operand:SI 1 "register_operand" "")
6540 (match_operand:SI 2 "arith32_operand" "")))]
6544 if (GET_CODE (operands[2]) != CONST_INT)
6546 rtx temp = gen_reg_rtx (SImode);
6547 emit_insn (gen_subsi3 (temp, GEN_INT (31), operands[2]));
6548 emit_insn (gen_vextrs32 (operands[0], operands[1], temp));
6554 [(set (match_operand:SI 0 "register_operand" "=r")
6555 (ashiftrt:SI (match_operand:SI 1 "register_operand" "r")
6556 (match_operand:SI 2 "const_int_operand" "n")))]
6558 "{extrs|extrw,s} %1,%P2,%L2,%0"
6559 [(set_attr "type" "shift")
6560 (set_attr "length" "4")])
6562 (define_insn "vextrs32"
6563 [(set (match_operand:SI 0 "register_operand" "=r")
6564 (ashiftrt:SI (match_operand:SI 1 "register_operand" "r")
6565 (minus:SI (const_int 31)
6566 (match_operand:SI 2 "register_operand" "q"))))]
6568 "{vextrs %1,32,%0|extrw,s %1,%%sar,32,%0}"
6569 [(set_attr "type" "shift")
6570 (set_attr "length" "4")])
6572 (define_expand "ashrdi3"
6573 [(set (match_operand:DI 0 "register_operand" "")
6574 (ashiftrt:DI (match_operand:DI 1 "register_operand" "")
6575 (match_operand:DI 2 "arith32_operand" "")))]
6579 if (GET_CODE (operands[2]) != CONST_INT)
6581 rtx temp = gen_reg_rtx (DImode);
6582 emit_insn (gen_subdi3 (temp, GEN_INT (63), operands[2]));
6583 emit_insn (gen_vextrs64 (operands[0], operands[1], temp));
6589 [(set (match_operand:DI 0 "register_operand" "=r")
6590 (ashiftrt:DI (match_operand:DI 1 "register_operand" "r")
6591 (match_operand:DI 2 "const_int_operand" "n")))]
6593 "extrd,s %1,%p2,%Q2,%0"
6594 [(set_attr "type" "shift")
6595 (set_attr "length" "4")])
6597 (define_insn "vextrs64"
6598 [(set (match_operand:DI 0 "register_operand" "=r")
6599 (ashiftrt:DI (match_operand:DI 1 "register_operand" "r")
6600 (minus:DI (const_int 63)
6601 (match_operand:DI 2 "register_operand" "q"))))]
6603 "extrd,s %1,%%sar,64,%0"
6604 [(set_attr "type" "shift")
6605 (set_attr "length" "4")])
6607 (define_insn "lshrsi3"
6608 [(set (match_operand:SI 0 "register_operand" "=r,r")
6609 (lshiftrt:SI (match_operand:SI 1 "register_operand" "r,r")
6610 (match_operand:SI 2 "shift5_operand" "q,n")))]
6613 {vshd %%r0,%1,%0|shrpw %%r0,%1,%%sar,%0}
6614 {extru|extrw,u} %1,%P2,%L2,%0"
6615 [(set_attr "type" "shift")
6616 (set_attr "length" "4")])
6618 (define_insn "lshrdi3"
6619 [(set (match_operand:DI 0 "register_operand" "=r,r")
6620 (lshiftrt:DI (match_operand:DI 1 "register_operand" "r,r")
6621 (match_operand:DI 2 "shift6_operand" "q,n")))]
6624 shrpd %%r0,%1,%%sar,%0
6625 extrd,u %1,%p2,%Q2,%0"
6626 [(set_attr "type" "shift")
6627 (set_attr "length" "4")])
6629 ; Shift right pair word 0 to 31 bits.
6630 (define_insn "*shrpsi4_1"
6631 [(set (match_operand:SI 0 "register_operand" "=r")
6632 (match_operator:SI 4 "plus_xor_ior_operator"
6633 [(ashift:SI (match_operand:SI 1 "register_operand" "r")
6634 (minus:SI (const_int 32)
6635 (match_operand:SI 3 "register_operand" "q")))
6636 (lshiftrt:SI (match_operand:SI 2 "register_operand" "r")
6639 "{vshd %1,%2,%0|shrpw %1,%2,%%sar,%0}"
6640 [(set_attr "type" "shift")
6641 (set_attr "length" "4")])
6643 (define_insn "*shrpsi4_2"
6644 [(set (match_operand:SI 0 "register_operand" "=r")
6645 (match_operator:SI 4 "plus_xor_ior_operator"
6646 [(lshiftrt:SI (match_operand:SI 2 "register_operand" "r")
6647 (match_operand:SI 3 "register_operand" "q"))
6648 (ashift:SI (match_operand:SI 1 "register_operand" "r")
6649 (minus:SI (const_int 32)
6652 "{vshd %1,%2,%0|shrpw %1,%2,%%sar,%0}"
6653 [(set_attr "type" "shift")
6654 (set_attr "length" "4")])
6656 ; Shift right pair doubleword 0 to 63 bits.
6657 (define_insn "*shrpdi4_1"
6658 [(set (match_operand:DI 0 "register_operand" "=r")
6659 (match_operator:DI 4 "plus_xor_ior_operator"
6660 [(ashift:DI (match_operand:DI 1 "register_operand" "r")
6661 (minus:DI (const_int 64)
6662 (match_operand:DI 3 "register_operand" "q")))
6663 (lshiftrt:DI (match_operand:DI 2 "register_operand" "r")
6666 "shrpd %1,%2,%%sar,%0"
6667 [(set_attr "type" "shift")
6668 (set_attr "length" "4")])
6670 (define_insn "*shrpdi4_2"
6671 [(set (match_operand:DI 0 "register_operand" "=r")
6672 (match_operator:DI 4 "plus_xor_ior_operator"
6673 [(lshiftrt:DI (match_operand:DI 2 "register_operand" "r")
6674 (match_operand:DI 3 "shift6_operand" "q"))
6675 (ashift:DI (match_operand:SI 1 "register_operand" "r")
6676 (minus:DI (const_int 64)
6679 "shrpd %1,%2,%%sar,%0"
6680 [(set_attr "type" "shift")
6681 (set_attr "length" "4")])
6683 (define_insn "*shrpdi4_3"
6684 [(set (match_operand:DI 0 "register_operand" "=r")
6685 (match_operator:DI 5 "plus_xor_ior_operator"
6686 [(ashift:DI (match_operand:DI 1 "register_operand" "r")
6687 (match_operand:DI 3 "const_int_operand" "n"))
6688 (lshiftrt:DI (match_operand:DI 2 "register_operand" "r")
6689 (match_operand:DI 4 "const_int_operand" "n"))]))]
6691 && INTVAL (operands[3]) + INTVAL (operands[4]) == 64"
6693 [(set_attr "type" "shift")
6694 (set_attr "length" "4")])
6696 (define_insn "*shrpdi4_4"
6697 [(set (match_operand:DI 0 "register_operand" "=r")
6698 (match_operator:DI 5 "plus_xor_ior_operator"
6699 [(lshiftrt:DI (match_operand:DI 2 "register_operand" "r")
6700 (match_operand:DI 4 "const_int_operand" "n"))
6701 (ashift:DI (match_operand:DI 1 "register_operand" "r")
6702 (match_operand:DI 3 "const_int_operand" "n"))]))]
6704 && INTVAL (operands[3]) + INTVAL (operands[4]) == 64"
6706 [(set_attr "type" "shift")
6707 (set_attr "length" "4")])
6709 (define_insn "rotrsi3"
6710 [(set (match_operand:SI 0 "register_operand" "=r,r")
6711 (rotatert:SI (match_operand:SI 1 "register_operand" "r,r")
6712 (match_operand:SI 2 "shift5_operand" "q,n")))]
6716 if (GET_CODE (operands[2]) == CONST_INT)
6718 operands[2] = GEN_INT (INTVAL (operands[2]) & 31);
6719 return \"{shd|shrpw} %1,%1,%2,%0\";
6722 return \"{vshd %1,%1,%0|shrpw %1,%1,%%sar,%0}\";
6724 [(set_attr "type" "shift")
6725 (set_attr "length" "4")])
6727 (define_expand "rotlsi3"
6728 [(set (match_operand:SI 0 "register_operand" "")
6729 (rotate:SI (match_operand:SI 1 "register_operand" "")
6730 (match_operand:SI 2 "arith32_operand" "")))]
6734 if (GET_CODE (operands[2]) != CONST_INT)
6736 rtx temp = gen_reg_rtx (SImode);
6737 emit_insn (gen_subsi3 (temp, GEN_INT (32), operands[2]));
6738 emit_insn (gen_rotrsi3 (operands[0], operands[1], temp));
6741 /* Else expand normally. */
6744 (define_insn "*rotlsi3_internal"
6745 [(set (match_operand:SI 0 "register_operand" "=r")
6746 (rotate:SI (match_operand:SI 1 "register_operand" "r")
6747 (match_operand:SI 2 "const_int_operand" "n")))]
6751 operands[2] = GEN_INT ((32 - INTVAL (operands[2])) & 31);
6752 return \"{shd|shrpw} %1,%1,%2,%0\";
6754 [(set_attr "type" "shift")
6755 (set_attr "length" "4")])
6757 (define_insn "rotrdi3"
6758 [(set (match_operand:DI 0 "register_operand" "=r,r")
6759 (rotatert:DI (match_operand:DI 1 "register_operand" "r,r")
6760 (match_operand:DI 2 "shift6_operand" "q,n")))]
6764 if (GET_CODE (operands[2]) == CONST_INT)
6766 operands[2] = GEN_INT (INTVAL (operands[2]) & 63);
6767 return \"shrpd %1,%1,%2,%0\";
6770 return \"shrpd %1,%1,%%sar,%0\";
6772 [(set_attr "type" "shift")
6773 (set_attr "length" "4")])
6775 (define_expand "rotldi3"
6776 [(set (match_operand:DI 0 "register_operand" "")
6777 (rotate:DI (match_operand:DI 1 "register_operand" "")
6778 (match_operand:DI 2 "arith32_operand" "")))]
6782 if (GET_CODE (operands[2]) != CONST_INT)
6784 rtx temp = gen_reg_rtx (DImode);
6785 emit_insn (gen_subdi3 (temp, GEN_INT (64), operands[2]));
6786 emit_insn (gen_rotrdi3 (operands[0], operands[1], temp));
6789 /* Else expand normally. */
6792 (define_insn "*rotldi3_internal"
6793 [(set (match_operand:DI 0 "register_operand" "=r")
6794 (rotate:DI (match_operand:DI 1 "register_operand" "r")
6795 (match_operand:DI 2 "const_int_operand" "n")))]
6799 operands[2] = GEN_INT ((64 - INTVAL (operands[2])) & 63);
6800 return \"shrpd %1,%1,%2,%0\";
6802 [(set_attr "type" "shift")
6803 (set_attr "length" "4")])
6806 [(set (match_operand:SI 0 "register_operand" "=r")
6807 (match_operator:SI 5 "plus_xor_ior_operator"
6808 [(ashift:SI (match_operand:SI 1 "register_operand" "r")
6809 (match_operand:SI 3 "const_int_operand" "n"))
6810 (lshiftrt:SI (match_operand:SI 2 "register_operand" "r")
6811 (match_operand:SI 4 "const_int_operand" "n"))]))]
6812 "INTVAL (operands[3]) + INTVAL (operands[4]) == 32"
6813 "{shd|shrpw} %1,%2,%4,%0"
6814 [(set_attr "type" "shift")
6815 (set_attr "length" "4")])
6818 [(set (match_operand:SI 0 "register_operand" "=r")
6819 (match_operator:SI 5 "plus_xor_ior_operator"
6820 [(lshiftrt:SI (match_operand:SI 2 "register_operand" "r")
6821 (match_operand:SI 4 "const_int_operand" "n"))
6822 (ashift:SI (match_operand:SI 1 "register_operand" "r")
6823 (match_operand:SI 3 "const_int_operand" "n"))]))]
6824 "INTVAL (operands[3]) + INTVAL (operands[4]) == 32"
6825 "{shd|shrpw} %1,%2,%4,%0"
6826 [(set_attr "type" "shift")
6827 (set_attr "length" "4")])
6829 (define_expand "shd_internal"
6830 [(set (match_operand:SI 0 "register_operand")
6832 (lshiftrt:SI (match_operand:SI 1 "register_operand")
6833 (match_operand:SI 2 "const_int_operand"))
6834 (ashift:SI (match_operand:SI 3 "register_operand")
6835 (match_operand:SI 4 "const_int_operand"))))]
6839 [(set (match_operand:SI 0 "register_operand" "=r")
6840 (and:SI (ashift:SI (match_operand:SI 1 "register_operand" "r")
6841 (match_operand:SI 2 "const_int_operand" ""))
6842 (match_operand:SI 3 "const_int_operand" "")))]
6843 "exact_log2 (1 + (INTVAL (operands[3]) >> (INTVAL (operands[2]) & 31))) > 0"
6846 int cnt = INTVAL (operands[2]) & 31;
6847 operands[3] = GEN_INT (exact_log2 (1 + (INTVAL (operands[3]) >> cnt)));
6848 operands[2] = GEN_INT (31 - cnt);
6849 return \"{zdep|depw,z} %1,%2,%3,%0\";
6851 [(set_attr "type" "shift")
6852 (set_attr "length" "4")])
6854 ;; Unconditional and other jump instructions.
6856 ;; Trivial return used when no epilogue is needed.
6857 (define_insn "return"
6860 "pa_can_use_return_insn ()"
6864 return \"bve%* (%%r2)\";
6865 return \"bv%* %%r0(%%r2)\";
6867 [(set_attr "type" "branch")
6868 (set_attr "length" "4")])
6870 ;; This is used for most returns.
6871 (define_insn "return_internal"
6878 return \"bve%* (%%r2)\";
6879 return \"bv%* %%r0(%%r2)\";
6881 [(set_attr "type" "branch")
6882 (set_attr "length" "4")])
6884 ;; This is used for eh returns which bypass the return stub.
6885 (define_insn "return_external_pic"
6887 (clobber (reg:SI 1))
6889 "!TARGET_NO_SPACE_REGS
6891 && flag_pic && crtl->calls_eh_return"
6892 "ldsid (%%sr0,%%r2),%%r1\;mtsp %%r1,%%sr0\;be%* 0(%%sr0,%%r2)"
6893 [(set_attr "type" "branch")
6894 (set_attr "length" "12")])
6896 (define_expand "prologue"
6899 "pa_expand_prologue ();DONE;")
6901 (define_expand "sibcall_epilogue"
6906 pa_expand_epilogue ();
6910 (define_expand "epilogue"
6917 /* Try to use the trivial return first. Else use the full epilogue. */
6918 if (pa_can_use_return_insn ())
6922 pa_expand_epilogue ();
6924 /* EH returns bypass the normal return stub. Thus, we must do an
6925 interspace branch to return from functions that call eh_return.
6926 This is only a problem for returns from shared code on ports
6927 using space registers. */
6928 if (!TARGET_NO_SPACE_REGS
6930 && flag_pic && crtl->calls_eh_return)
6931 x = gen_return_external_pic ();
6933 x = gen_return_internal ();
6939 ; Used by hppa_profile_hook to load the starting address of the current
6940 ; function; operand 1 contains the address of the label in operand 3
6941 (define_insn "load_offset_label_address"
6942 [(set (match_operand:SI 0 "register_operand" "=r")
6943 (plus:SI (match_operand:SI 1 "register_operand" "r")
6944 (minus:SI (match_operand:SI 2 "" "")
6945 (label_ref:SI (match_operand 3 "" "")))))]
6948 [(set_attr "type" "multi")
6949 (set_attr "length" "4")])
6951 ; Output a code label and load its address.
6952 (define_insn "lcla1"
6953 [(set (match_operand:SI 0 "register_operand" "=r")
6954 (label_ref:SI (match_operand 1 "" "")))
6959 output_asm_insn (\"bl .+8,%0\;depi 0,31,2,%0\", operands);
6960 (*targetm.asm_out.internal_label) (asm_out_file, \"L\",
6961 CODE_LABEL_NUMBER (operands[1]));
6964 [(set_attr "type" "multi")
6965 (set_attr "length" "8")])
6967 (define_insn "lcla2"
6968 [(set (match_operand:SI 0 "register_operand" "=r")
6969 (label_ref:SI (match_operand 1 "" "")))
6974 (*targetm.asm_out.internal_label) (asm_out_file, \"L\",
6975 CODE_LABEL_NUMBER (operands[1]));
6978 [(set_attr "type" "move")
6979 (set_attr "length" "4")])
6981 (define_insn "blockage"
6982 [(unspec_volatile [(const_int 2)] UNSPECV_BLOCKAGE)]
6985 [(set_attr "length" "0")])
6988 [(set (pc) (label_ref (match_operand 0 "" "")))]
6992 /* An unconditional branch which can reach its target. */
6993 if (get_attr_length (insn) < 16)
6996 return pa_output_lbranch (operands[0], insn, 1);
6998 [(set_attr "type" "uncond_branch")
6999 (set_attr "pa_combine_type" "uncond_branch")
7000 (set (attr "length")
7001 (cond [(lt (abs (minus (match_dup 0) (plus (pc) (const_int 8))))
7002 (const_int MAX_17BIT_OFFSET))
7004 (match_test "TARGET_PORTABLE_RUNTIME")
7006 (not (match_test "flag_pic"))
7010 ;;; Hope this is only within a function...
7011 (define_insn "indirect_jump"
7012 [(set (pc) (match_operand 0 "pmode_register_operand" "r"))]
7015 [(set_attr "type" "branch")
7016 (set_attr "length" "4")])
7018 ;;; An indirect jump can be optimized to a direct jump. GAS for the
7019 ;;; SOM target doesn't allow branching to a label inside a function.
7020 ;;; We also don't correctly compute branch distances for labels
7021 ;;; outside the current function. Thus, we use an indirect jump can't
7022 ;;; be optimized to a direct jump for all targets. We assume that
7023 ;;; the branch target is in the same space (i.e., nested function
7024 ;;; jumping to a label in an outer function in the same translation
7026 (define_expand "nonlocal_goto"
7027 [(use (match_operand 0 "general_operand" ""))
7028 (use (match_operand 1 "general_operand" ""))
7029 (use (match_operand 2 "general_operand" ""))
7030 (use (match_operand 3 "general_operand" ""))]
7033 rtx lab = operands[1];
7034 rtx stack = operands[2];
7035 rtx fp = operands[3];
7037 emit_clobber (gen_rtx_MEM (BLKmode, gen_rtx_SCRATCH (VOIDmode)));
7038 emit_clobber (gen_rtx_MEM (BLKmode, hard_frame_pointer_rtx));
7040 lab = copy_to_reg (lab);
7042 /* Restore the stack and frame pointers. */
7043 fp = copy_to_reg (fp);
7044 emit_stack_restore (SAVE_NONLOCAL, stack);
7046 /* Ensure the frame pointer move is not optimized. */
7047 emit_insn (gen_blockage ());
7048 emit_clobber (hard_frame_pointer_rtx);
7049 emit_clobber (frame_pointer_rtx);
7050 emit_move_insn (hard_frame_pointer_rtx, fp);
7052 emit_use (hard_frame_pointer_rtx);
7053 emit_use (stack_pointer_rtx);
7055 /* Nonlocal goto jumps are only used between functions in the same
7056 translation unit. Thus, we can avoid the extra overhead of an
7058 emit_jump_insn (gen_indirect_goto (lab));
7063 (define_insn "indirect_goto"
7064 [(unspec [(match_operand 0 "register_operand" "=r")] UNSPEC_GOTO)]
7065 "GET_MODE (operands[0]) == word_mode"
7067 [(set_attr "type" "branch")
7068 (set_attr "length" "4")])
7070 ;; Subroutines of "casesi".
7071 ;; operand 0 is index
7072 ;; operand 1 is the minimum bound
7073 ;; operand 2 is the maximum bound - minimum bound + 1
7074 ;; operand 3 is CODE_LABEL for the table;
7075 ;; operand 4 is the CODE_LABEL to go to if index out of range.
7077 (define_expand "casesi"
7078 [(match_operand:SI 0 "general_operand" "")
7079 (match_operand:SI 1 "const_int_operand" "")
7080 (match_operand:SI 2 "const_int_operand" "")
7081 (match_operand 3 "" "")
7082 (match_operand 4 "" "")]
7086 if (GET_CODE (operands[0]) != REG)
7087 operands[0] = force_reg (SImode, operands[0]);
7089 if (operands[1] != const0_rtx)
7091 rtx index = gen_reg_rtx (SImode);
7093 operands[1] = gen_int_mode (-INTVAL (operands[1]), SImode);
7094 if (!INT_14_BITS (operands[1]))
7095 operands[1] = force_reg (SImode, operands[1]);
7096 emit_insn (gen_addsi3 (index, operands[0], operands[1]));
7097 operands[0] = index;
7100 if (!INT_5_BITS (operands[2]))
7101 operands[2] = force_reg (SImode, operands[2]);
7103 /* This branch prevents us finding an insn for the delay slot of the
7104 following vectored branch. It might be possible to use the delay
7105 slot if an index value of -1 was used to transfer to the out-of-range
7106 label. In order to do this, we would have to output the -1 vector
7107 element after the delay insn. The casesi output code would have to
7108 check if the casesi insn is in a delay branch sequence and output
7109 the delay insn if one is found. If this was done, then it might
7110 then be worthwhile to split the casesi patterns to improve scheduling.
7111 However, it's not clear that all this extra complexity is worth
7114 rtx test = gen_rtx_GTU (VOIDmode, operands[0], operands[2]);
7115 emit_jump_insn (gen_cbranchsi4 (test, operands[0], operands[2], operands[4]));
7118 /* In 64bit mode we must make sure to wipe the upper bits of the register
7119 just in case the addition overflowed or we had random bits in the
7120 high part of the register. */
7123 rtx index = gen_reg_rtx (DImode);
7125 emit_insn (gen_extendsidi2 (index, operands[0]));
7126 operands[0] = index;
7130 emit_jump_insn (gen_casesi64p (operands[0], operands[3]));
7132 emit_jump_insn (gen_casesi32p (operands[0], operands[3]));
7134 emit_jump_insn (gen_casesi32 (operands[0], operands[3]));
7138 ;;; 32-bit code, absolute branch table.
7139 (define_insn "casesi32"
7140 [(set (pc) (mem:SI (plus:SI
7141 (mult:SI (match_operand:SI 0 "register_operand" "r")
7143 (label_ref (match_operand 1 "" "")))))
7144 (clobber (match_scratch:SI 2 "=&r"))]
7146 "ldil L'%l1,%2\;ldo R'%l1(%2),%2\;{ldwx|ldw},s %0(%2),%2\;bv,n %%r0(%2)"
7147 [(set_attr "type" "multi")
7148 (set_attr "length" "16")])
7150 ;;; 32-bit code, relative branch table.
7151 (define_insn "casesi32p"
7152 [(set (pc) (mem:SI (plus:SI
7153 (mult:SI (match_operand:SI 0 "register_operand" "r")
7155 (label_ref (match_operand 1 "" "")))))
7156 (clobber (match_scratch:SI 2 "=&r"))
7157 (clobber (match_scratch:SI 3 "=&r"))]
7159 "{bl .+8,%2\;depi 0,31,2,%2|mfia %2}\;ldo {%l1-.|%l1+4-.}(%2),%2\;\
7160 {ldwx|ldw},s %0(%2),%3\;{addl|add,l} %2,%3,%3\;bv,n %%r0(%3)"
7161 [(set_attr "type" "multi")
7162 (set (attr "length")
7163 (if_then_else (match_test "TARGET_PA_20")
7167 ;;; 64-bit code, 32-bit relative branch table.
7168 (define_insn "casesi64p"
7169 [(set (pc) (mem:DI (plus:DI
7170 (mult:DI (match_operand:DI 0 "register_operand" "r")
7172 (label_ref (match_operand 1 "" "")))))
7173 (clobber (match_scratch:DI 2 "=&r"))
7174 (clobber (match_scratch:DI 3 "=&r"))]
7176 "mfia %2\;ldo %l1+4-.(%2),%2\;ldw,s %0(%2),%3\;extrd,s %3,63,32,%3\;\
7177 add,l %2,%3,%3\;bv,n %%r0(%3)"
7178 [(set_attr "type" "multi")
7179 (set_attr "length" "24")])
7183 ;;- jump to subroutine
7185 (define_expand "call"
7186 [(parallel [(call (match_operand:SI 0 "" "")
7187 (match_operand 1 "" ""))
7188 (clobber (reg:SI 2))])]
7193 rtx nb = operands[1];
7195 if (TARGET_PORTABLE_RUNTIME)
7196 op = force_reg (SImode, XEXP (operands[0], 0));
7199 op = XEXP (operands[0], 0);
7201 /* Generate indirect long calls to non-local functions. */
7202 if (TARGET_LONG_CALLS && GET_CODE (op) == SYMBOL_REF)
7204 tree call_decl = SYMBOL_REF_DECL (op);
7205 if (!(call_decl && targetm.binds_local_p (call_decl)))
7206 op = force_reg (word_mode, op);
7212 if (!virtuals_instantiated)
7213 emit_move_insn (arg_pointer_rtx,
7214 gen_rtx_PLUS (word_mode, virtual_outgoing_args_rtx,
7218 /* The loop pass can generate new libcalls after the virtual
7219 registers are instantiated when fpregs are disabled because
7220 the only method that we have for doing DImode multiplication
7221 is with a libcall. This could be trouble if we haven't
7222 allocated enough space for the outgoing arguments. */
7223 gcc_assert (INTVAL (nb) <= crtl->outgoing_args_size);
7225 emit_move_insn (arg_pointer_rtx,
7226 gen_rtx_PLUS (word_mode, stack_pointer_rtx,
7227 GEN_INT (STACK_POINTER_OFFSET + 64)));
7231 /* Use two different patterns for calls to explicitly named functions
7232 and calls through function pointers. This is necessary as these two
7233 types of calls use different calling conventions, and CSE might try
7234 to change the named call into an indirect call in some cases (using
7235 two patterns keeps CSE from performing this optimization).
7237 We now use even more call patterns as there was a subtle bug in
7238 attempting to restore the pic register after a call using a simple
7239 move insn. During reload, a instruction involving a pseudo register
7240 with no explicit dependence on the PIC register can be converted
7241 to an equivalent load from memory using the PIC register. If we
7242 emit a simple move to restore the PIC register in the initial rtl
7243 generation, then it can potentially be repositioned during scheduling.
7244 and an instruction that eventually uses the PIC register may end up
7245 between the call and the PIC register restore.
7247 This only worked because there is a post call group of instructions
7248 that are scheduled with the call. These instructions are included
7249 in the same basic block as the call. However, calls can throw in
7250 C++ code and a basic block has to terminate at the call if the call
7251 can throw. This results in the PIC register restore being scheduled
7252 independently from the call. So, we now hide the save and restore
7253 of the PIC register in the call pattern until after reload. Then,
7254 we split the moves out. A small side benefit is that we now don't
7255 need to have a use of the PIC register in the return pattern and
7256 the final save/restore operation is not needed.
7258 I elected to just use register %r4 in the PIC patterns instead
7259 of trying to force hppa_pic_save_rtx () to a callee saved register.
7260 This might have required a new register class and constraint. It
7261 was also simpler to just handle the restore from a register than a
7265 rtx r4 = gen_rtx_REG (word_mode, 4);
7266 if (GET_CODE (op) == SYMBOL_REF)
7267 emit_call_insn (gen_call_symref_64bit (op, nb, r4));
7270 op = force_reg (word_mode, op);
7271 emit_call_insn (gen_call_reg_64bit (op, nb, r4));
7276 if (GET_CODE (op) == SYMBOL_REF)
7280 rtx r4 = gen_rtx_REG (word_mode, 4);
7281 emit_call_insn (gen_call_symref_pic (op, nb, r4));
7284 emit_call_insn (gen_call_symref (op, nb));
7288 rtx tmpreg = gen_rtx_REG (word_mode, 22);
7289 emit_move_insn (tmpreg, force_reg (word_mode, op));
7292 rtx r4 = gen_rtx_REG (word_mode, 4);
7293 emit_call_insn (gen_call_reg_pic (nb, r4));
7296 emit_call_insn (gen_call_reg (nb));
7303 ;; We use function calls to set the attribute length of calls and millicode
7304 ;; calls. This is necessary because of the large variety of call sequences.
7305 ;; Implementing the calculation in rtl is difficult as well as ugly. As
7306 ;; we need the same calculation in several places, maintenance becomes a
7309 ;; However, this has a subtle impact on branch shortening. When the
7310 ;; expression used to set the length attribute of an instruction depends
7311 ;; on a relative address (e.g., pc or a branch address), genattrtab
7312 ;; notes that the insn's length is variable, and attempts to determine a
7313 ;; worst-case default length and code to compute an insn's current length.
7315 ;; The use of a function call hides the variable dependence of our calls
7316 ;; and millicode calls. The result is genattrtab doesn't treat the operation
7317 ;; as variable and it only generates code for the default case using our
7318 ;; function call. Because of this, calls and millicode calls have a fixed
7319 ;; length in the branch shortening pass, and some branches will use a longer
7320 ;; code sequence than necessary. However, the length of any given call
7321 ;; will still reflect its final code location and it may be shorter than
7322 ;; the initial length estimate.
7324 ;; It's possible to trick genattrtab by adding an expression involving `pc'
7325 ;; in the set. However, when genattrtab hits a function call in its attempt
7326 ;; to compute the default length, it marks the result as unknown and sets
7327 ;; the default result to MAX_INT ;-( One possible fix that would allow
7328 ;; calls to participate in branch shortening would be to make the call to
7329 ;; insn_default_length a target option. Then, we could massage unknown
7330 ;; results. Another fix might be to change genattrtab so that it just does
7331 ;; the call in the variable case as it already does for the fixed case.
7333 (define_insn "call_symref"
7334 [(call (mem:SI (match_operand 0 "call_operand_address" ""))
7335 (match_operand 1 "" "i"))
7336 (clobber (reg:SI 1))
7337 (clobber (reg:SI 2))
7338 (use (const_int 0))]
7339 "!TARGET_PORTABLE_RUNTIME && !TARGET_64BIT"
7342 pa_output_arg_descriptor (insn);
7343 return pa_output_call (insn, operands[0], 0);
7345 [(set_attr "type" "call")
7346 (set (attr "length")
7347 (cond [(and (const_int 0) (eq (const_int 0) (pc))) (const_int 8)]
7348 (symbol_ref "pa_attr_length_call (insn, 0)")))])
7350 (define_insn "call_symref_pic"
7351 [(call (mem:SI (match_operand 0 "call_operand_address" ""))
7352 (match_operand 1 "" "i"))
7353 (clobber (reg:SI 1))
7354 (clobber (reg:SI 2))
7355 (clobber (match_operand 2))
7357 (use (const_int 0))]
7358 "!TARGET_PORTABLE_RUNTIME && !TARGET_64BIT"
7361 ;; Split out the PIC register save and restore after reload. As the
7362 ;; split is done after reload, there are some situations in which we
7363 ;; unnecessarily save and restore %r4. This happens when there is a
7364 ;; single call and the PIC register is not used after the call.
7366 ;; The split has to be done since call_from_call_insn () can't handle
7367 ;; the pattern as is. Noreturn calls are special because they have to
7368 ;; terminate the basic block. The split has to contain more than one
7371 [(parallel [(call (mem:SI (match_operand 0 "call_operand_address" ""))
7372 (match_operand 1 "" ""))
7373 (clobber (reg:SI 1))
7374 (clobber (reg:SI 2))
7375 (clobber (match_operand 2))
7377 (use (const_int 0))])]
7378 "!TARGET_PORTABLE_RUNTIME && !TARGET_64BIT && reload_completed
7379 && find_reg_note (insn, REG_NORETURN, NULL_RTX)"
7380 [(set (match_dup 2) (reg:SI 19))
7381 (parallel [(call (mem:SI (match_dup 0))
7383 (clobber (reg:SI 1))
7384 (clobber (reg:SI 2))
7386 (use (const_int 0))])]
7390 [(parallel [(call (mem:SI (match_operand 0 "call_operand_address" ""))
7391 (match_operand 1 "" ""))
7392 (clobber (reg:SI 1))
7393 (clobber (reg:SI 2))
7394 (clobber (match_operand 2))
7396 (use (const_int 0))])]
7397 "!TARGET_PORTABLE_RUNTIME && !TARGET_64BIT && reload_completed"
7398 [(set (match_dup 2) (reg:SI 19))
7399 (parallel [(call (mem:SI (match_dup 0))
7401 (clobber (reg:SI 1))
7402 (clobber (reg:SI 2))
7404 (use (const_int 0))])
7405 (set (reg:SI 19) (match_dup 2))]
7408 (define_insn "*call_symref_pic_post_reload"
7409 [(call (mem:SI (match_operand 0 "call_operand_address" ""))
7410 (match_operand 1 "" "i"))
7411 (clobber (reg:SI 1))
7412 (clobber (reg:SI 2))
7414 (use (const_int 0))]
7415 "!TARGET_PORTABLE_RUNTIME && !TARGET_64BIT"
7418 pa_output_arg_descriptor (insn);
7419 return pa_output_call (insn, operands[0], 0);
7421 [(set_attr "type" "call")
7422 (set (attr "length")
7423 (cond [(and (const_int 0) (eq (const_int 0) (pc))) (const_int 8)]
7424 (symbol_ref "pa_attr_length_call (insn, 0)")))])
7426 ;; This pattern is split if it is necessary to save and restore the
7428 (define_insn "call_symref_64bit"
7429 [(call (mem:SI (match_operand 0 "call_operand_address" ""))
7430 (match_operand 1 "" "i"))
7431 (clobber (reg:DI 1))
7432 (clobber (reg:DI 2))
7433 (clobber (match_operand 2))
7436 (use (const_int 0))]
7440 ;; Split out the PIC register save and restore after reload. As the
7441 ;; split is done after reload, there are some situations in which we
7442 ;; unnecessarily save and restore %r4. This happens when there is a
7443 ;; single call and the PIC register is not used after the call.
7445 ;; The split has to be done since call_from_call_insn () can't handle
7446 ;; the pattern as is. Noreturn calls are special because they have to
7447 ;; terminate the basic block. The split has to contain more than one
7450 [(parallel [(call (mem:SI (match_operand 0 "call_operand_address" ""))
7451 (match_operand 1 "" ""))
7452 (clobber (reg:DI 1))
7453 (clobber (reg:DI 2))
7454 (clobber (match_operand 2))
7457 (use (const_int 0))])]
7458 "TARGET_64BIT && reload_completed
7459 && find_reg_note (insn, REG_NORETURN, NULL_RTX)"
7460 [(set (match_dup 2) (reg:DI 27))
7461 (parallel [(call (mem:SI (match_dup 0))
7463 (clobber (reg:DI 1))
7464 (clobber (reg:DI 2))
7467 (use (const_int 0))])]
7471 [(parallel [(call (mem:SI (match_operand 0 "call_operand_address" ""))
7472 (match_operand 1 "" ""))
7473 (clobber (reg:DI 1))
7474 (clobber (reg:DI 2))
7475 (clobber (match_operand 2))
7478 (use (const_int 0))])]
7479 "TARGET_64BIT && reload_completed"
7480 [(set (match_dup 2) (reg:DI 27))
7481 (parallel [(call (mem:SI (match_dup 0))
7483 (clobber (reg:DI 1))
7484 (clobber (reg:DI 2))
7487 (use (const_int 0))])
7488 (set (reg:DI 27) (match_dup 2))]
7491 (define_insn "*call_symref_64bit_post_reload"
7492 [(call (mem:SI (match_operand 0 "call_operand_address" ""))
7493 (match_operand 1 "" "i"))
7494 (clobber (reg:DI 1))
7495 (clobber (reg:DI 2))
7498 (use (const_int 0))]
7502 return pa_output_call (insn, operands[0], 0);
7504 [(set_attr "type" "call")
7505 (set (attr "length")
7506 (cond [(and (const_int 0) (eq (const_int 0) (pc))) (const_int 8)]
7507 (symbol_ref "pa_attr_length_call (insn, 0)")))])
7509 (define_insn "call_reg"
7510 [(call (mem:SI (reg:SI 22))
7511 (match_operand 0 "" "i"))
7512 (clobber (reg:SI 1))
7513 (clobber (reg:SI 2))
7514 (use (const_int 1))]
7518 return pa_output_indirect_call (insn, gen_rtx_REG (word_mode, 22));
7520 [(set_attr "type" "dyncall")
7521 (set (attr "length")
7522 (cond [(and (const_int 0) (eq (const_int 0) (pc))) (const_int 8)]
7523 (symbol_ref "pa_attr_length_indirect_call (insn)")))])
7525 ;; This pattern is split if it is necessary to save and restore the
7527 (define_insn "call_reg_pic"
7528 [(call (mem:SI (reg:SI 22))
7529 (match_operand 0 "" "i"))
7530 (clobber (reg:SI 1))
7531 (clobber (reg:SI 2))
7532 (clobber (match_operand 1))
7534 (use (const_int 1))]
7538 ;; Split out the PIC register save and restore after reload. As the
7539 ;; split is done after reload, there are some situations in which we
7540 ;; unnecessarily save and restore %r4. This happens when there is a
7541 ;; single call and the PIC register is not used after the call.
7543 ;; The split has to be done since call_from_call_insn () can't handle
7544 ;; the pattern as is. Noreturn calls are special because they have to
7545 ;; terminate the basic block. The split has to contain more than one
7548 [(parallel [(call (mem:SI (reg:SI 22))
7549 (match_operand 0 "" ""))
7550 (clobber (reg:SI 1))
7551 (clobber (reg:SI 2))
7552 (clobber (match_operand 1))
7554 (use (const_int 1))])]
7555 "!TARGET_64BIT && reload_completed
7556 && find_reg_note (insn, REG_NORETURN, NULL_RTX)"
7557 [(set (match_dup 1) (reg:SI 19))
7558 (parallel [(call (mem:SI (reg:SI 22))
7560 (clobber (reg:SI 1))
7561 (clobber (reg:SI 2))
7563 (use (const_int 1))])]
7567 [(parallel [(call (mem:SI (reg:SI 22))
7568 (match_operand 0 "" ""))
7569 (clobber (reg:SI 1))
7570 (clobber (reg:SI 2))
7571 (clobber (match_operand 1))
7573 (use (const_int 1))])]
7574 "!TARGET_64BIT && reload_completed"
7575 [(set (match_dup 1) (reg:SI 19))
7576 (parallel [(call (mem:SI (reg:SI 22))
7578 (clobber (reg:SI 1))
7579 (clobber (reg:SI 2))
7581 (use (const_int 1))])
7582 (set (reg:SI 19) (match_dup 1))]
7585 (define_insn "*call_reg_pic_post_reload"
7586 [(call (mem:SI (reg:SI 22))
7587 (match_operand 0 "" "i"))
7588 (clobber (reg:SI 1))
7589 (clobber (reg:SI 2))
7591 (use (const_int 1))]
7595 return pa_output_indirect_call (insn, gen_rtx_REG (word_mode, 22));
7597 [(set_attr "type" "dyncall")
7598 (set (attr "length")
7599 (cond [(and (const_int 0) (eq (const_int 0) (pc))) (const_int 8)]
7600 (symbol_ref "pa_attr_length_indirect_call (insn)")))])
7602 ;; This pattern is split if it is necessary to save and restore the
7604 (define_insn "call_reg_64bit"
7605 [(call (mem:SI (match_operand:DI 0 "register_operand" "r"))
7606 (match_operand 1 "" "i"))
7607 (clobber (reg:DI 2))
7608 (clobber (match_operand 2))
7611 (use (const_int 1))]
7615 ;; Split out the PIC register save and restore after reload. As the
7616 ;; split is done after reload, there are some situations in which we
7617 ;; unnecessarily save and restore %r4. This happens when there is a
7618 ;; single call and the PIC register is not used after the call.
7620 ;; The split has to be done since call_from_call_insn () can't handle
7621 ;; the pattern as is. Noreturn calls are special because they have to
7622 ;; terminate the basic block. The split has to contain more than one
7625 [(parallel [(call (mem:SI (match_operand 0 "register_operand" ""))
7626 (match_operand 1 "" ""))
7627 (clobber (reg:DI 2))
7628 (clobber (match_operand 2))
7631 (use (const_int 1))])]
7632 "TARGET_64BIT && reload_completed
7633 && find_reg_note (insn, REG_NORETURN, NULL_RTX)"
7634 [(set (match_dup 2) (reg:DI 27))
7635 (parallel [(call (mem:SI (match_dup 0))
7637 (clobber (reg:DI 2))
7640 (use (const_int 1))])]
7644 [(parallel [(call (mem:SI (match_operand 0 "register_operand" ""))
7645 (match_operand 1 "" ""))
7646 (clobber (reg:DI 2))
7647 (clobber (match_operand 2))
7650 (use (const_int 1))])]
7651 "TARGET_64BIT && reload_completed"
7652 [(set (match_dup 2) (reg:DI 27))
7653 (parallel [(call (mem:SI (match_dup 0))
7655 (clobber (reg:DI 2))
7658 (use (const_int 1))])
7659 (set (reg:DI 27) (match_dup 2))]
7662 (define_insn "*call_reg_64bit_post_reload"
7663 [(call (mem:SI (match_operand:DI 0 "register_operand" "r"))
7664 (match_operand 1 "" "i"))
7665 (clobber (reg:DI 2))
7668 (use (const_int 1))]
7672 return pa_output_indirect_call (insn, operands[0]);
7674 [(set_attr "type" "dyncall")
7675 (set (attr "length")
7676 (cond [(and (const_int 0) (eq (const_int 0) (pc))) (const_int 12)]
7677 (symbol_ref "pa_attr_length_indirect_call (insn)")))])
7679 (define_expand "call_value"
7680 [(parallel [(set (match_operand 0 "" "")
7681 (call (match_operand:SI 1 "" "")
7682 (match_operand 2 "" "")))
7683 (clobber (reg:SI 2))])]
7687 rtx dst = operands[0];
7688 rtx nb = operands[2];
7689 bool call_powf = false;
7691 if (TARGET_PORTABLE_RUNTIME)
7692 op = force_reg (SImode, XEXP (operands[1], 0));
7695 op = XEXP (operands[1], 0);
7696 if (GET_CODE (op) == SYMBOL_REF)
7698 /* Handle special call to buggy powf function. */
7699 if (TARGET_HPUX && !TARGET_DISABLE_FPREGS && !TARGET_SOFT_FLOAT
7700 && !strcmp (targetm.strip_name_encoding (XSTR (op, 0)), "powf"))
7703 /* Generate indirect long calls to non-local functions. */
7704 else if (TARGET_LONG_CALLS)
7706 tree call_decl = SYMBOL_REF_DECL (op);
7707 if (!(call_decl && targetm.binds_local_p (call_decl)))
7708 op = force_reg (word_mode, op);
7715 if (!virtuals_instantiated)
7716 emit_move_insn (arg_pointer_rtx,
7717 gen_rtx_PLUS (word_mode, virtual_outgoing_args_rtx,
7721 /* The loop pass can generate new libcalls after the virtual
7722 registers are instantiated when fpregs are disabled because
7723 the only method that we have for doing DImode multiplication
7724 is with a libcall. This could be trouble if we haven't
7725 allocated enough space for the outgoing arguments. */
7726 gcc_assert (INTVAL (nb) <= crtl->outgoing_args_size);
7728 emit_move_insn (arg_pointer_rtx,
7729 gen_rtx_PLUS (word_mode, stack_pointer_rtx,
7730 GEN_INT (STACK_POINTER_OFFSET + 64)));
7734 /* Use two different patterns for calls to explicitly named functions
7735 and calls through function pointers. This is necessary as these two
7736 types of calls use different calling conventions, and CSE might try
7737 to change the named call into an indirect call in some cases (using
7738 two patterns keeps CSE from performing this optimization).
7740 We now use even more call patterns as there was a subtle bug in
7741 attempting to restore the pic register after a call using a simple
7742 move insn. During reload, a instruction involving a pseudo register
7743 with no explicit dependence on the PIC register can be converted
7744 to an equivalent load from memory using the PIC register. If we
7745 emit a simple move to restore the PIC register in the initial rtl
7746 generation, then it can potentially be repositioned during scheduling.
7747 and an instruction that eventually uses the PIC register may end up
7748 between the call and the PIC register restore.
7750 This only worked because there is a post call group of instructions
7751 that are scheduled with the call. These instructions are included
7752 in the same basic block as the call. However, calls can throw in
7753 C++ code and a basic block has to terminate at the call if the call
7754 can throw. This results in the PIC register restore being scheduled
7755 independently from the call. So, we now hide the save and restore
7756 of the PIC register in the call pattern until after reload. Then,
7757 we split the moves out. A small side benefit is that we now don't
7758 need to have a use of the PIC register in the return pattern and
7759 the final save/restore operation is not needed.
7761 I elected to just use register %r4 in the PIC patterns instead
7762 of trying to force hppa_pic_save_rtx () to a callee saved register.
7763 This might have required a new register class and constraint. It
7764 was also simpler to just handle the restore from a register than a
7768 rtx r4 = gen_rtx_REG (word_mode, 4);
7769 if (GET_CODE (op) == SYMBOL_REF)
7772 emit_call_insn (gen_call_val_powf_64bit (dst, op, nb, r4));
7774 emit_call_insn (gen_call_val_symref_64bit (dst, op, nb, r4));
7778 op = force_reg (word_mode, op);
7779 emit_call_insn (gen_call_val_reg_64bit (dst, op, nb, r4));
7784 if (GET_CODE (op) == SYMBOL_REF)
7788 rtx r4 = gen_rtx_REG (word_mode, 4);
7791 emit_call_insn (gen_call_val_powf_pic (dst, op, nb, r4));
7793 emit_call_insn (gen_call_val_symref_pic (dst, op, nb, r4));
7798 emit_call_insn (gen_call_val_powf (dst, op, nb));
7800 emit_call_insn (gen_call_val_symref (dst, op, nb));
7805 rtx tmpreg = gen_rtx_REG (word_mode, 22);
7806 emit_move_insn (tmpreg, force_reg (word_mode, op));
7809 rtx r4 = gen_rtx_REG (word_mode, 4);
7810 emit_call_insn (gen_call_val_reg_pic (dst, nb, r4));
7813 emit_call_insn (gen_call_val_reg (dst, nb));
7820 (define_insn "call_val_symref"
7821 [(set (match_operand 0 "" "")
7822 (call (mem:SI (match_operand 1 "call_operand_address" ""))
7823 (match_operand 2 "" "i")))
7824 (clobber (reg:SI 1))
7825 (clobber (reg:SI 2))
7826 (use (const_int 0))]
7827 "!TARGET_PORTABLE_RUNTIME && !TARGET_64BIT"
7830 pa_output_arg_descriptor (insn);
7831 return pa_output_call (insn, operands[1], 0);
7833 [(set_attr "type" "call")
7834 (set (attr "length")
7835 (cond [(and (const_int 0) (eq (const_int 0) (pc))) (const_int 8)]
7836 (symbol_ref "pa_attr_length_call (insn, 0)")))])
7838 ;; powf function clobbers %fr12
7839 (define_insn "call_val_powf"
7840 [(set (match_operand 0 "" "")
7841 (call (mem:SI (match_operand 1 "call_operand_address" ""))
7842 (match_operand 2 "" "i")))
7843 (clobber (reg:SI 1))
7844 (clobber (reg:SI 2))
7845 (clobber (reg:DF 48))
7846 (use (const_int 1))]
7847 "TARGET_HPUX && !TARGET_PORTABLE_RUNTIME && !TARGET_64BIT"
7850 pa_output_arg_descriptor (insn);
7851 return pa_output_call (insn, operands[1], 0);
7853 [(set_attr "type" "call")
7854 (set (attr "length")
7855 (cond [(and (const_int 0) (eq (const_int 0) (pc))) (const_int 8)]
7856 (symbol_ref "pa_attr_length_call (insn, 0)")))])
7858 (define_insn "call_val_symref_pic"
7859 [(set (match_operand 0 "" "")
7860 (call (mem:SI (match_operand 1 "call_operand_address" ""))
7861 (match_operand 2 "" "i")))
7862 (clobber (reg:SI 1))
7863 (clobber (reg:SI 2))
7864 (clobber (match_operand 3))
7866 (use (const_int 0))]
7867 "!TARGET_PORTABLE_RUNTIME && !TARGET_64BIT"
7870 ;; Split out the PIC register save and restore after reload. As the
7871 ;; split is done after reload, there are some situations in which we
7872 ;; unnecessarily save and restore %r4. This happens when there is a
7873 ;; single call and the PIC register is not used after the call.
7875 ;; The split has to be done since call_from_call_insn () can't handle
7876 ;; the pattern as is. Noreturn calls are special because they have to
7877 ;; terminate the basic block. The split has to contain more than one
7880 [(parallel [(set (match_operand 0 "" "")
7881 (call (mem:SI (match_operand 1 "call_operand_address" ""))
7882 (match_operand 2 "" "")))
7883 (clobber (reg:SI 1))
7884 (clobber (reg:SI 2))
7885 (clobber (match_operand 3))
7887 (use (const_int 0))])]
7888 "!TARGET_PORTABLE_RUNTIME && !TARGET_64BIT && reload_completed
7889 && find_reg_note (insn, REG_NORETURN, NULL_RTX)"
7890 [(set (match_dup 3) (reg:SI 19))
7891 (parallel [(set (match_dup 0)
7892 (call (mem:SI (match_dup 1))
7894 (clobber (reg:SI 1))
7895 (clobber (reg:SI 2))
7897 (use (const_int 0))])]
7901 [(parallel [(set (match_operand 0 "" "")
7902 (call (mem:SI (match_operand 1 "call_operand_address" ""))
7903 (match_operand 2 "" "")))
7904 (clobber (reg:SI 1))
7905 (clobber (reg:SI 2))
7906 (clobber (match_operand 3))
7908 (use (const_int 0))])]
7909 "!TARGET_PORTABLE_RUNTIME && !TARGET_64BIT && reload_completed"
7910 [(set (match_dup 3) (reg:SI 19))
7911 (parallel [(set (match_dup 0)
7912 (call (mem:SI (match_dup 1))
7914 (clobber (reg:SI 1))
7915 (clobber (reg:SI 2))
7917 (use (const_int 0))])
7918 (set (reg:SI 19) (match_dup 3))]
7921 (define_insn "*call_val_symref_pic_post_reload"
7922 [(set (match_operand 0 "" "")
7923 (call (mem:SI (match_operand 1 "call_operand_address" ""))
7924 (match_operand 2 "" "i")))
7925 (clobber (reg:SI 1))
7926 (clobber (reg:SI 2))
7928 (use (const_int 0))]
7929 "!TARGET_PORTABLE_RUNTIME && !TARGET_64BIT"
7932 pa_output_arg_descriptor (insn);
7933 return pa_output_call (insn, operands[1], 0);
7935 [(set_attr "type" "call")
7936 (set (attr "length")
7937 (cond [(and (const_int 0) (eq (const_int 0) (pc))) (const_int 8)]
7938 (symbol_ref "pa_attr_length_call (insn, 0)")))])
7940 ;; powf function clobbers %fr12
7941 (define_insn "call_val_powf_pic"
7942 [(set (match_operand 0 "" "")
7943 (call (mem:SI (match_operand 1 "call_operand_address" ""))
7944 (match_operand 2 "" "i")))
7945 (clobber (reg:SI 1))
7946 (clobber (reg:SI 2))
7947 (clobber (reg:DF 48))
7948 (clobber (match_operand 3))
7950 (use (const_int 1))]
7951 "TARGET_HPUX && !TARGET_PORTABLE_RUNTIME && !TARGET_64BIT"
7954 ;; Split out the PIC register save and restore after reload. As the
7955 ;; split is done after reload, there are some situations in which we
7956 ;; unnecessarily save and restore %r4. This happens when there is a
7957 ;; single call and the PIC register is not used after the call.
7959 ;; The split has to be done since call_from_call_insn () can't handle
7960 ;; the pattern as is. Noreturn calls are special because they have to
7961 ;; terminate the basic block. The split has to contain more than one
7964 [(parallel [(set (match_operand 0 "" "")
7965 (call (mem:SI (match_operand 1 "call_operand_address" ""))
7966 (match_operand 2 "" "")))
7967 (clobber (reg:SI 1))
7968 (clobber (reg:SI 2))
7969 (clobber (reg:DF 48))
7970 (clobber (match_operand 3))
7972 (use (const_int 1))])]
7973 "TARGET_HPUX && !TARGET_PORTABLE_RUNTIME && !TARGET_64BIT && reload_completed
7974 && find_reg_note (insn, REG_NORETURN, NULL_RTX)"
7975 [(set (match_dup 3) (reg:SI 19))
7976 (parallel [(set (match_dup 0)
7977 (call (mem:SI (match_dup 1))
7979 (clobber (reg:SI 1))
7980 (clobber (reg:SI 2))
7981 (clobber (reg:DF 48))
7983 (use (const_int 1))])]
7987 [(parallel [(set (match_operand 0 "" "")
7988 (call (mem:SI (match_operand 1 "call_operand_address" ""))
7989 (match_operand 2 "" "")))
7990 (clobber (reg:SI 1))
7991 (clobber (reg:SI 2))
7992 (clobber (reg:DF 48))
7993 (clobber (match_operand 3))
7995 (use (const_int 1))])]
7996 "TARGET_HPUX && !TARGET_PORTABLE_RUNTIME && !TARGET_64BIT && reload_completed"
7997 [(set (match_dup 3) (reg:SI 19))
7998 (parallel [(set (match_dup 0)
7999 (call (mem:SI (match_dup 1))
8001 (clobber (reg:SI 1))
8002 (clobber (reg:SI 2))
8003 (clobber (reg:DF 48))
8005 (use (const_int 1))])
8006 (set (reg:SI 19) (match_dup 3))]
8009 (define_insn "*call_val_powf_pic_post_reload"
8010 [(set (match_operand 0 "" "")
8011 (call (mem:SI (match_operand 1 "call_operand_address" ""))
8012 (match_operand 2 "" "i")))
8013 (clobber (reg:SI 1))
8014 (clobber (reg:SI 2))
8015 (clobber (reg:DF 48))
8017 (use (const_int 1))]
8018 "TARGET_HPUX && !TARGET_PORTABLE_RUNTIME && !TARGET_64BIT"
8021 pa_output_arg_descriptor (insn);
8022 return pa_output_call (insn, operands[1], 0);
8024 [(set_attr "type" "call")
8025 (set (attr "length")
8026 (cond [(and (const_int 0) (eq (const_int 0) (pc))) (const_int 8)]
8027 (symbol_ref "pa_attr_length_call (insn, 0)")))])
8029 ;; This pattern is split if it is necessary to save and restore the
8031 (define_insn "call_val_symref_64bit"
8032 [(set (match_operand 0 "" "")
8033 (call (mem:SI (match_operand 1 "call_operand_address" ""))
8034 (match_operand 2 "" "i")))
8035 (clobber (reg:DI 1))
8036 (clobber (reg:DI 2))
8037 (clobber (match_operand 3))
8040 (use (const_int 0))]
8044 ;; Split out the PIC register save and restore after reload. As the
8045 ;; split is done after reload, there are some situations in which we
8046 ;; unnecessarily save and restore %r4. This happens when there is a
8047 ;; single call and the PIC register is not used after the call.
8049 ;; The split has to be done since call_from_call_insn () can't handle
8050 ;; the pattern as is. Noreturn calls are special because they have to
8051 ;; terminate the basic block. The split has to contain more than one
8054 [(parallel [(set (match_operand 0 "" "")
8055 (call (mem:SI (match_operand 1 "call_operand_address" ""))
8056 (match_operand 2 "" "")))
8057 (clobber (reg:DI 1))
8058 (clobber (reg:DI 2))
8059 (clobber (match_operand 3))
8062 (use (const_int 0))])]
8063 "TARGET_64BIT && reload_completed
8064 && find_reg_note (insn, REG_NORETURN, NULL_RTX)"
8065 [(set (match_dup 3) (reg:DI 27))
8066 (parallel [(set (match_dup 0)
8067 (call (mem:SI (match_dup 1))
8069 (clobber (reg:DI 1))
8070 (clobber (reg:DI 2))
8073 (use (const_int 0))])]
8077 [(parallel [(set (match_operand 0 "" "")
8078 (call (mem:SI (match_operand 1 "call_operand_address" ""))
8079 (match_operand 2 "" "")))
8080 (clobber (reg:DI 1))
8081 (clobber (reg:DI 2))
8082 (clobber (match_operand 3))
8085 (use (const_int 0))])]
8086 "TARGET_64BIT && reload_completed"
8087 [(set (match_dup 3) (reg:DI 27))
8088 (parallel [(set (match_dup 0)
8089 (call (mem:SI (match_dup 1))
8091 (clobber (reg:DI 1))
8092 (clobber (reg:DI 2))
8095 (use (const_int 0))])
8096 (set (reg:DI 27) (match_dup 3))]
8099 (define_insn "*call_val_symref_64bit_post_reload"
8100 [(set (match_operand 0 "" "")
8101 (call (mem:SI (match_operand 1 "call_operand_address" ""))
8102 (match_operand 2 "" "i")))
8103 (clobber (reg:DI 1))
8104 (clobber (reg:DI 2))
8107 (use (const_int 0))]
8111 return pa_output_call (insn, operands[1], 0);
8113 [(set_attr "type" "call")
8114 (set (attr "length")
8115 (cond [(and (const_int 0) (eq (const_int 0) (pc))) (const_int 8)]
8116 (symbol_ref "pa_attr_length_call (insn, 0)")))])
8118 ;; powf function clobbers %fr12
8119 (define_insn "call_val_powf_64bit"
8120 [(set (match_operand 0 "" "")
8121 (call (mem:SI (match_operand 1 "call_operand_address" ""))
8122 (match_operand 2 "" "i")))
8123 (clobber (reg:DI 1))
8124 (clobber (reg:DI 2))
8125 (clobber (reg:DF 40))
8126 (clobber (match_operand 3))
8129 (use (const_int 1))]
8130 "TARGET_64BIT && TARGET_HPUX"
8133 ;; Split out the PIC register save and restore after reload. As the
8134 ;; split is done after reload, there are some situations in which we
8135 ;; unnecessarily save and restore %r4. This happens when there is a
8136 ;; single call and the PIC register is not used after the call.
8138 ;; The split has to be done since call_from_call_insn () can't handle
8139 ;; the pattern as is. Noreturn calls are special because they have to
8140 ;; terminate the basic block. The split has to contain more than one
8143 [(parallel [(set (match_operand 0 "" "")
8144 (call (mem:SI (match_operand 1 "call_operand_address" ""))
8145 (match_operand 2 "" "")))
8146 (clobber (reg:DI 1))
8147 (clobber (reg:DI 2))
8148 (clobber (reg:DF 40))
8149 (clobber (match_operand 3))
8152 (use (const_int 1))])]
8153 "TARGET_64BIT && TARGET_HPUX && reload_completed
8154 && find_reg_note (insn, REG_NORETURN, NULL_RTX)"
8155 [(set (match_dup 3) (reg:DI 27))
8156 (parallel [(set (match_dup 0)
8157 (call (mem:SI (match_dup 1))
8159 (clobber (reg:DI 1))
8160 (clobber (reg:DI 2))
8161 (clobber (reg:DF 40))
8164 (use (const_int 1))])]
8168 [(parallel [(set (match_operand 0 "" "")
8169 (call (mem:SI (match_operand 1 "call_operand_address" ""))
8170 (match_operand 2 "" "")))
8171 (clobber (reg:DI 1))
8172 (clobber (reg:DI 2))
8173 (clobber (reg:DF 40))
8174 (clobber (match_operand 3))
8177 (use (const_int 1))])]
8178 "TARGET_64BIT && TARGET_HPUX && reload_completed"
8179 [(set (match_dup 3) (reg:DI 27))
8180 (parallel [(set (match_dup 0)
8181 (call (mem:SI (match_dup 1))
8183 (clobber (reg:DI 1))
8184 (clobber (reg:DI 2))
8185 (clobber (reg:DF 40))
8188 (use (const_int 1))])
8189 (set (reg:DI 27) (match_dup 3))]
8192 (define_insn "*call_val_powf_64bit_post_reload"
8193 [(set (match_operand 0 "" "")
8194 (call (mem:SI (match_operand 1 "call_operand_address" ""))
8195 (match_operand 2 "" "i")))
8196 (clobber (reg:DI 1))
8197 (clobber (reg:DI 2))
8198 (clobber (reg:DF 40))
8201 (use (const_int 1))]
8202 "TARGET_64BIT && TARGET_HPUX"
8205 return pa_output_call (insn, operands[1], 0);
8207 [(set_attr "type" "call")
8208 (set (attr "length")
8209 (cond [(and (const_int 0) (eq (const_int 0) (pc))) (const_int 8)]
8210 (symbol_ref "pa_attr_length_call (insn, 0)")))])
8212 (define_insn "call_val_reg"
8213 [(set (match_operand 0 "" "")
8214 (call (mem:SI (reg:SI 22))
8215 (match_operand 1 "" "i")))
8216 (clobber (reg:SI 1))
8217 (clobber (reg:SI 2))
8218 (use (const_int 1))]
8222 return pa_output_indirect_call (insn, gen_rtx_REG (word_mode, 22));
8224 [(set_attr "type" "dyncall")
8225 (set (attr "length")
8226 (cond [(and (const_int 0) (eq (const_int 0) (pc))) (const_int 8)]
8227 (symbol_ref "pa_attr_length_indirect_call (insn)")))])
8229 ;; This pattern is split if it is necessary to save and restore the
8231 (define_insn "call_val_reg_pic"
8232 [(set (match_operand 0 "" "")
8233 (call (mem:SI (reg:SI 22))
8234 (match_operand 1 "" "i")))
8235 (clobber (reg:SI 1))
8236 (clobber (reg:SI 2))
8237 (clobber (match_operand 2))
8239 (use (const_int 1))]
8243 ;; Split out the PIC register save and restore after reload. As the
8244 ;; split is done after reload, there are some situations in which we
8245 ;; unnecessarily save and restore %r4. This happens when there is a
8246 ;; single call and the PIC register is not used after the call.
8248 ;; The split has to be done since call_from_call_insn () can't handle
8249 ;; the pattern as is. Noreturn calls are special because they have to
8250 ;; terminate the basic block. The split has to contain more than one
8253 [(parallel [(set (match_operand 0 "" "")
8254 (call (mem:SI (reg:SI 22))
8255 (match_operand 1 "" "")))
8256 (clobber (reg:SI 1))
8257 (clobber (reg:SI 2))
8258 (clobber (match_operand 2))
8260 (use (const_int 1))])]
8261 "!TARGET_64BIT && reload_completed
8262 && find_reg_note (insn, REG_NORETURN, NULL_RTX)"
8263 [(set (match_dup 2) (reg:SI 19))
8264 (parallel [(set (match_dup 0)
8265 (call (mem:SI (reg:SI 22))
8267 (clobber (reg:SI 1))
8268 (clobber (reg:SI 2))
8270 (use (const_int 1))])]
8274 [(parallel [(set (match_operand 0 "" "")
8275 (call (mem:SI (reg:SI 22))
8276 (match_operand 1 "" "")))
8277 (clobber (reg:SI 1))
8278 (clobber (reg:SI 2))
8279 (clobber (match_operand 2))
8281 (use (const_int 1))])]
8282 "!TARGET_64BIT && reload_completed"
8283 [(set (match_dup 2) (reg:SI 19))
8284 (parallel [(set (match_dup 0)
8285 (call (mem:SI (reg:SI 22))
8287 (clobber (reg:SI 1))
8288 (clobber (reg:SI 2))
8290 (use (const_int 1))])
8291 (set (reg:SI 19) (match_dup 2))]
8294 (define_insn "*call_val_reg_pic_post_reload"
8295 [(set (match_operand 0 "" "")
8296 (call (mem:SI (reg:SI 22))
8297 (match_operand 1 "" "i")))
8298 (clobber (reg:SI 1))
8299 (clobber (reg:SI 2))
8301 (use (const_int 1))]
8305 return pa_output_indirect_call (insn, gen_rtx_REG (word_mode, 22));
8307 [(set_attr "type" "dyncall")
8308 (set (attr "length")
8309 (cond [(and (const_int 0) (eq (const_int 0) (pc))) (const_int 8)]
8310 (symbol_ref "pa_attr_length_indirect_call (insn)")))])
8312 ;; This pattern is split if it is necessary to save and restore the
8314 (define_insn "call_val_reg_64bit"
8315 [(set (match_operand 0 "" "")
8316 (call (mem:SI (match_operand:DI 1 "register_operand" "r"))
8317 (match_operand 2 "" "i")))
8318 (clobber (reg:DI 2))
8319 (clobber (match_operand 3))
8322 (use (const_int 1))]
8326 ;; Split out the PIC register save and restore after reload. As the
8327 ;; split is done after reload, there are some situations in which we
8328 ;; unnecessarily save and restore %r4. This happens when there is a
8329 ;; single call and the PIC register is not used after the call.
8331 ;; The split has to be done since call_from_call_insn () can't handle
8332 ;; the pattern as is. Noreturn calls are special because they have to
8333 ;; terminate the basic block. The split has to contain more than one
8336 [(parallel [(set (match_operand 0 "" "")
8337 (call (mem:SI (match_operand:DI 1 "register_operand" ""))
8338 (match_operand 2 "" "")))
8339 (clobber (reg:DI 2))
8340 (clobber (match_operand 3))
8343 (use (const_int 1))])]
8344 "TARGET_64BIT && reload_completed
8345 && find_reg_note (insn, REG_NORETURN, NULL_RTX)"
8346 [(set (match_dup 3) (reg:DI 27))
8347 (parallel [(set (match_dup 0)
8348 (call (mem:SI (match_dup 1))
8350 (clobber (reg:DI 2))
8353 (use (const_int 1))])]
8357 [(parallel [(set (match_operand 0 "" "")
8358 (call (mem:SI (match_operand:DI 1 "register_operand" ""))
8359 (match_operand 2 "" "")))
8360 (clobber (reg:DI 2))
8361 (clobber (match_operand 3))
8364 (use (const_int 1))])]
8365 "TARGET_64BIT && reload_completed"
8366 [(set (match_dup 3) (reg:DI 27))
8367 (parallel [(set (match_dup 0)
8368 (call (mem:SI (match_dup 1))
8370 (clobber (reg:DI 2))
8373 (use (const_int 1))])
8374 (set (reg:DI 27) (match_dup 3))]
8377 (define_insn "*call_val_reg_64bit_post_reload"
8378 [(set (match_operand 0 "" "")
8379 (call (mem:SI (match_operand:DI 1 "register_operand" "r"))
8380 (match_operand 2 "" "i")))
8381 (clobber (reg:DI 2))
8384 (use (const_int 1))]
8388 return pa_output_indirect_call (insn, operands[1]);
8390 [(set_attr "type" "dyncall")
8391 (set (attr "length")
8392 (cond [(and (const_int 0) (eq (const_int 0) (pc))) (const_int 12)]
8393 (symbol_ref "pa_attr_length_indirect_call (insn)")))])
8395 /* Expand special pc-relative call to _mcount. */
8397 (define_expand "call_mcount"
8398 [(parallel [(call (match_operand:SI 0 "" "")
8399 (match_operand 1 "" ""))
8402 (minus:SI (match_operand 2 "" "")
8403 (plus:SI (pc) (const_int 4)))))
8404 (clobber (reg:SI 2))])]
8405 "!TARGET_PORTABLE_RUNTIME"
8408 rtx op = XEXP (operands[0], 0);
8409 rtx nb = operands[1];
8410 rtx lab = operands[2];
8414 rtx r4 = gen_rtx_REG (word_mode, 4);
8415 emit_move_insn (arg_pointer_rtx,
8416 gen_rtx_PLUS (word_mode, virtual_outgoing_args_rtx,
8418 emit_call_insn (gen_call_mcount_64bit (op, nb, lab, r4));
8424 rtx r4 = gen_rtx_REG (word_mode, 4);
8425 emit_call_insn (gen_call_mcount_pic (op, nb, lab, r4));
8428 emit_call_insn (gen_call_mcount_nonpic (op, nb, lab));
8434 (define_insn "call_mcount_nonpic"
8435 [(call (mem:SI (match_operand 0 "call_operand_address" ""))
8436 (match_operand 1 "" "i"))
8439 (minus:SI (match_operand 2 "" "")
8440 (plus:SI (pc) (const_int 4)))))
8441 (clobber (reg:SI 2))]
8442 "!TARGET_PORTABLE_RUNTIME && !TARGET_64BIT"
8445 pa_output_arg_descriptor (insn);
8446 return \"{bl|b,l} %0,%%r2\;ldo %2-.-4(%%r2),%%r25\";
8448 [(set_attr "type" "multi")
8449 (set_attr "length" "8")])
8451 (define_insn "call_mcount_pic"
8452 [(call (mem:SI (match_operand 0 "call_operand_address" ""))
8453 (match_operand 1 "" "i"))
8456 (minus:SI (match_operand 2 "" "")
8457 (plus:SI (pc) (const_int 4)))))
8458 (clobber (reg:SI 2))
8459 (clobber (match_operand 3))
8461 "!TARGET_PORTABLE_RUNTIME && !TARGET_64BIT"
8465 [(parallel [(call (mem:SI (match_operand 0 "call_operand_address" ""))
8466 (match_operand 1 "" ""))
8469 (minus:SI (match_operand 2 "" "")
8470 (plus:SI (pc) (const_int 4)))))
8471 (clobber (reg:SI 2))
8472 (clobber (match_operand 3))
8473 (use (reg:SI 19))])]
8474 "!TARGET_PORTABLE_RUNTIME && !TARGET_64BIT && reload_completed"
8475 [(set (match_dup 3) (reg:SI 19))
8476 (parallel [(call (mem:SI (match_dup 0))
8480 (minus:SI (match_dup 2)
8481 (plus:SI (pc) (const_int 4)))))
8482 (clobber (reg:SI 2))
8484 (set (reg:SI 19) (match_dup 3))]
8487 (define_insn "*call_mcount_pic_post_reload"
8488 [(call (mem:SI (match_operand 0 "call_operand_address" ""))
8489 (match_operand 1 "" "i"))
8492 (minus:SI (match_operand 2 "" "")
8493 (plus:SI (pc) (const_int 4)))))
8494 (clobber (reg:SI 2))
8496 "!TARGET_PORTABLE_RUNTIME && !TARGET_64BIT"
8499 pa_output_arg_descriptor (insn);
8500 return \"{bl|b,l} %0,%%r2\;ldo %2-.-4(%%r2),%%r25\";
8502 [(set_attr "type" "multi")
8503 (set_attr "length" "8")])
8505 (define_insn "call_mcount_64bit"
8506 [(call (mem:SI (match_operand 0 "call_operand_address" ""))
8507 (match_operand 1 "" "i"))
8510 (minus:SI (match_operand 2 "" "")
8511 (plus:SI (pc) (const_int 4)))))
8512 (clobber (reg:DI 2))
8513 (clobber (match_operand 3))
8520 [(parallel [(call (mem:SI (match_operand 0 "call_operand_address" ""))
8521 (match_operand 1 "" ""))
8524 (minus:SI (match_operand 2 "" "")
8525 (plus:SI (pc) (const_int 4)))))
8526 (clobber (reg:DI 2))
8527 (clobber (match_operand 3))
8529 (use (reg:DI 29))])]
8530 "TARGET_64BIT && reload_completed"
8531 [(set (match_dup 3) (reg:DI 27))
8532 (parallel [(call (mem:SI (match_dup 0))
8536 (minus:SI (match_dup 2)
8537 (plus:SI (pc) (const_int 4)))))
8538 (clobber (reg:DI 2))
8541 (set (reg:DI 27) (match_dup 3))]
8544 (define_insn "*call_mcount_64bit_post_reload"
8545 [(call (mem:SI (match_operand 0 "call_operand_address" ""))
8546 (match_operand 1 "" "i"))
8549 (minus:SI (match_operand 2 "" "")
8550 (plus:SI (pc) (const_int 4)))))
8551 (clobber (reg:DI 2))
8555 "{bl|b,l} %0,%%r2\;ldo %2-.-4(%%r2),%%r25"
8556 [(set_attr "type" "multi")
8557 (set_attr "length" "8")])
8559 ;; Call subroutine returning any type.
8561 (define_expand "untyped_call"
8562 [(parallel [(call (match_operand 0 "" "")
8564 (match_operand 1 "" "")
8565 (match_operand 2 "" "")])]
8571 emit_call_insn (gen_call (operands[0], const0_rtx));
8573 for (i = 0; i < XVECLEN (operands[2], 0); i++)
8575 rtx set = XVECEXP (operands[2], 0, i);
8576 emit_move_insn (SET_DEST (set), SET_SRC (set));
8579 /* The optimizer does not know that the call sets the function value
8580 registers we stored in the result block. We avoid problems by
8581 claiming that all hard registers are used and clobbered at this
8583 emit_insn (gen_blockage ());
8588 (define_expand "sibcall"
8589 [(call (match_operand:SI 0 "" "")
8590 (match_operand 1 "" ""))]
8591 "!TARGET_PORTABLE_RUNTIME"
8595 rtx nb = operands[1];
8597 op = XEXP (operands[0], 0);
8601 if (!virtuals_instantiated)
8602 emit_move_insn (arg_pointer_rtx,
8603 gen_rtx_PLUS (word_mode, virtual_outgoing_args_rtx,
8607 /* The loop pass can generate new libcalls after the virtual
8608 registers are instantiated when fpregs are disabled because
8609 the only method that we have for doing DImode multiplication
8610 is with a libcall. This could be trouble if we haven't
8611 allocated enough space for the outgoing arguments. */
8612 gcc_assert (INTVAL (nb) <= crtl->outgoing_args_size);
8614 emit_move_insn (arg_pointer_rtx,
8615 gen_rtx_PLUS (word_mode, stack_pointer_rtx,
8616 GEN_INT (STACK_POINTER_OFFSET + 64)));
8620 /* Indirect sibling calls are not allowed. */
8622 call_insn = gen_sibcall_internal_symref_64bit (op, operands[1]);
8624 call_insn = gen_sibcall_internal_symref (op, operands[1]);
8626 call_insn = emit_call_insn (call_insn);
8629 use_reg (&CALL_INSN_FUNCTION_USAGE (call_insn), arg_pointer_rtx);
8631 /* We don't have to restore the PIC register. */
8633 use_reg (&CALL_INSN_FUNCTION_USAGE (call_insn), pic_offset_table_rtx);
8638 (define_insn "sibcall_internal_symref"
8639 [(call (mem:SI (match_operand 0 "call_operand_address" ""))
8640 (match_operand 1 "" "i"))
8641 (clobber (reg:SI 1))
8643 (use (const_int 0))]
8644 "!TARGET_PORTABLE_RUNTIME && !TARGET_64BIT"
8647 pa_output_arg_descriptor (insn);
8648 return pa_output_call (insn, operands[0], 1);
8650 [(set_attr "type" "sibcall")
8651 (set (attr "length")
8652 (cond [(and (const_int 0) (eq (const_int 0) (pc))) (const_int 8)]
8653 (symbol_ref "pa_attr_length_call (insn, 1)")))])
8655 (define_insn "sibcall_internal_symref_64bit"
8656 [(call (mem:SI (match_operand 0 "call_operand_address" ""))
8657 (match_operand 1 "" "i"))
8658 (clobber (reg:DI 1))
8660 (use (const_int 0))]
8664 return pa_output_call (insn, operands[0], 1);
8666 [(set_attr "type" "sibcall")
8667 (set (attr "length")
8668 (cond [(and (const_int 0) (eq (const_int 0) (pc))) (const_int 8)]
8669 (symbol_ref "pa_attr_length_call (insn, 1)")))])
8671 (define_expand "sibcall_value"
8672 [(set (match_operand 0 "" "")
8673 (call (match_operand:SI 1 "" "")
8674 (match_operand 2 "" "")))]
8675 "!TARGET_PORTABLE_RUNTIME"
8679 rtx nb = operands[1];
8681 op = XEXP (operands[1], 0);
8685 if (!virtuals_instantiated)
8686 emit_move_insn (arg_pointer_rtx,
8687 gen_rtx_PLUS (word_mode, virtual_outgoing_args_rtx,
8691 /* The loop pass can generate new libcalls after the virtual
8692 registers are instantiated when fpregs are disabled because
8693 the only method that we have for doing DImode multiplication
8694 is with a libcall. This could be trouble if we haven't
8695 allocated enough space for the outgoing arguments. */
8696 gcc_assert (INTVAL (nb) <= crtl->outgoing_args_size);
8698 emit_move_insn (arg_pointer_rtx,
8699 gen_rtx_PLUS (word_mode, stack_pointer_rtx,
8700 GEN_INT (STACK_POINTER_OFFSET + 64)));
8704 /* Indirect sibling calls are not allowed. */
8707 = gen_sibcall_value_internal_symref_64bit (operands[0], op, operands[2]);
8710 = gen_sibcall_value_internal_symref (operands[0], op, operands[2]);
8712 call_insn = emit_call_insn (call_insn);
8715 use_reg (&CALL_INSN_FUNCTION_USAGE (call_insn), arg_pointer_rtx);
8717 /* We don't have to restore the PIC register. */
8719 use_reg (&CALL_INSN_FUNCTION_USAGE (call_insn), pic_offset_table_rtx);
8724 (define_insn "sibcall_value_internal_symref"
8725 [(set (match_operand 0 "" "")
8726 (call (mem:SI (match_operand 1 "call_operand_address" ""))
8727 (match_operand 2 "" "i")))
8728 (clobber (reg:SI 1))
8730 (use (const_int 0))]
8731 "!TARGET_PORTABLE_RUNTIME && !TARGET_64BIT"
8734 pa_output_arg_descriptor (insn);
8735 return pa_output_call (insn, operands[1], 1);
8737 [(set_attr "type" "sibcall")
8738 (set (attr "length")
8739 (cond [(and (const_int 0) (eq (const_int 0) (pc))) (const_int 8)]
8740 (symbol_ref "pa_attr_length_call (insn, 1)")))])
8742 (define_insn "sibcall_value_internal_symref_64bit"
8743 [(set (match_operand 0 "" "")
8744 (call (mem:SI (match_operand 1 "call_operand_address" ""))
8745 (match_operand 2 "" "i")))
8746 (clobber (reg:DI 1))
8748 (use (const_int 0))]
8752 return pa_output_call (insn, operands[1], 1);
8754 [(set_attr "type" "sibcall")
8755 (set (attr "length")
8756 (cond [(and (const_int 0) (eq (const_int 0) (pc))) (const_int 8)]
8757 (symbol_ref "pa_attr_length_call (insn, 1)")))])
8763 [(set_attr "type" "move")
8764 (set_attr "length" "4")])
8766 ;;; EH does longjmp's from and within the data section. Thus,
8767 ;;; an interspace branch is required for the longjmp implementation.
8768 ;;; Registers r1 and r2 are used as scratch registers for the jump
8770 (define_expand "interspace_jump"
8772 [(set (pc) (match_operand 0 "pmode_register_operand" "a"))
8773 (clobber (match_dup 1))])]
8777 operands[1] = gen_rtx_REG (word_mode, 2);
8781 [(set (pc) (match_operand 0 "pmode_register_operand" "a"))
8782 (clobber (reg:SI 2))]
8783 "TARGET_PA_20 && !TARGET_64BIT"
8785 [(set_attr "type" "branch")
8786 (set_attr "length" "4")])
8789 [(set (pc) (match_operand 0 "pmode_register_operand" "a"))
8790 (clobber (reg:SI 2))]
8791 "TARGET_NO_SPACE_REGS && !TARGET_64BIT"
8793 [(set_attr "type" "branch")
8794 (set_attr "length" "4")])
8797 [(set (pc) (match_operand 0 "pmode_register_operand" "a"))
8798 (clobber (reg:SI 2))]
8800 "ldsid (%%sr0,%0),%%r2\;mtsp %%r2,%%sr0\;be%* 0(%%sr0,%0)"
8801 [(set_attr "type" "branch")
8802 (set_attr "length" "12")])
8805 [(set (pc) (match_operand 0 "pmode_register_operand" "a"))
8806 (clobber (reg:DI 2))]
8809 [(set_attr "type" "branch")
8810 (set_attr "length" "4")])
8812 (define_expand "builtin_longjmp"
8813 [(unspec_volatile [(match_operand 0 "register_operand" "r")] UNSPECV_LONGJMP)]
8817 /* The elements of the buffer are, in order: */
8818 rtx fp = gen_rtx_MEM (Pmode, operands[0]);
8819 rtx lab = gen_rtx_MEM (Pmode, plus_constant (Pmode, operands[0],
8820 POINTER_SIZE / BITS_PER_UNIT));
8821 rtx stack = gen_rtx_MEM (Pmode, plus_constant (Pmode, operands[0],
8822 (POINTER_SIZE * 2) / BITS_PER_UNIT));
8823 rtx pv = gen_rtx_REG (Pmode, 1);
8825 emit_clobber (gen_rtx_MEM (BLKmode, gen_rtx_SCRATCH (VOIDmode)));
8826 emit_clobber (gen_rtx_MEM (BLKmode, hard_frame_pointer_rtx));
8828 /* Load the label we are jumping through into r1 so that we know
8829 where to look for it when we get back to setjmp's function for
8830 restoring the gp. */
8831 emit_move_insn (pv, lab);
8833 /* Restore the stack and frame pointers. */
8834 fp = copy_to_reg (fp);
8835 emit_stack_restore (SAVE_NONLOCAL, stack);
8837 /* Ensure the frame pointer move is not optimized. */
8838 emit_insn (gen_blockage ());
8839 emit_clobber (hard_frame_pointer_rtx);
8840 emit_clobber (frame_pointer_rtx);
8841 emit_move_insn (hard_frame_pointer_rtx, fp);
8843 emit_use (hard_frame_pointer_rtx);
8844 emit_use (stack_pointer_rtx);
8846 /* Prevent the insns above from being scheduled into the delay slot
8847 of the interspace jump because the space register could change. */
8848 emit_insn (gen_blockage ());
8850 emit_jump_insn (gen_interspace_jump (pv));
8855 ;;; Operands 2 and 3 are assumed to be CONST_INTs.
8856 (define_expand "extzvsi"
8857 [(set (match_operand:SI 0 "register_operand" "")
8858 (zero_extract:SI (match_operand:SI 1 "register_operand" "")
8859 (match_operand:SI 2 "uint5_operand" "")
8860 (match_operand:SI 3 "uint5_operand" "")))]
8864 unsigned HOST_WIDE_INT len = UINTVAL (operands[2]);
8865 unsigned HOST_WIDE_INT pos = UINTVAL (operands[3]);
8867 /* PA extraction insns don't support zero length bitfields or fields
8868 extending beyond the left or right-most bits. Also, the predicate
8869 rejects lengths equal to a word as they are better handled by
8870 the move patterns. */
8871 if (len == 0 || pos + len > 32)
8874 /* From mips.md: extract_bit_field doesn't verify that our source
8875 matches the predicate, so check it again here. */
8876 if (!register_operand (operands[1], VOIDmode))
8879 emit_insn (gen_extzv_32 (operands[0], operands[1],
8880 operands[2], operands[3]));
8884 (define_insn "extzv_32"
8885 [(set (match_operand:SI 0 "register_operand" "=r")
8886 (zero_extract:SI (match_operand:SI 1 "register_operand" "r")
8887 (match_operand:SI 2 "uint5_operand" "")
8888 (match_operand:SI 3 "uint5_operand" "")))]
8889 "UINTVAL (operands[2]) > 0
8890 && UINTVAL (operands[2]) + UINTVAL (operands[3]) <= 32"
8891 "{extru|extrw,u} %1,%3+%2-1,%2,%0"
8892 [(set_attr "type" "shift")
8893 (set_attr "length" "4")])
8896 [(set (match_operand:SI 0 "register_operand" "=r")
8897 (zero_extract:SI (match_operand:SI 1 "register_operand" "r")
8899 (match_operand:SI 2 "register_operand" "q")))]
8901 "{vextru %1,1,%0|extrw,u %1,%%sar,1,%0}"
8902 [(set_attr "type" "shift")
8903 (set_attr "length" "4")])
8905 (define_expand "extzvdi"
8906 [(set (match_operand:DI 0 "register_operand" "")
8907 (zero_extract:DI (match_operand:DI 1 "register_operand" "")
8908 (match_operand:DI 2 "uint6_operand" "")
8909 (match_operand:DI 3 "uint6_operand" "")))]
8913 unsigned HOST_WIDE_INT len = UINTVAL (operands[2]);
8914 unsigned HOST_WIDE_INT pos = UINTVAL (operands[3]);
8916 /* PA extraction insns don't support zero length bitfields or fields
8917 extending beyond the left or right-most bits. Also, the predicate
8918 rejects lengths equal to a doubleword as they are better handled by
8919 the move patterns. */
8920 if (len == 0 || pos + len > 64)
8923 /* From mips.md: extract_bit_field doesn't verify that our source
8924 matches the predicate, so check it again here. */
8925 if (!register_operand (operands[1], VOIDmode))
8928 emit_insn (gen_extzv_64 (operands[0], operands[1],
8929 operands[2], operands[3]));
8933 (define_insn "extzv_64"
8934 [(set (match_operand:DI 0 "register_operand" "=r")
8935 (zero_extract:DI (match_operand:DI 1 "register_operand" "r")
8936 (match_operand:DI 2 "uint6_operand" "")
8937 (match_operand:DI 3 "uint6_operand" "")))]
8939 && UINTVAL (operands[2]) > 0
8940 && UINTVAL (operands[2]) + UINTVAL (operands[3]) <= 64"
8941 "extrd,u %1,%3+%2-1,%2,%0"
8942 [(set_attr "type" "shift")
8943 (set_attr "length" "4")])
8946 [(set (match_operand:DI 0 "register_operand" "=r")
8947 (zero_extract:DI (match_operand:DI 1 "register_operand" "r")
8949 (match_operand:DI 2 "register_operand" "q")))]
8951 "extrd,u %1,%%sar,1,%0"
8952 [(set_attr "type" "shift")
8953 (set_attr "length" "4")])
8955 ;;; Operands 2 and 3 are assumed to be CONST_INTs.
8956 (define_expand "extvsi"
8957 [(set (match_operand:SI 0 "register_operand" "")
8958 (sign_extract:SI (match_operand:SI 1 "register_operand" "")
8959 (match_operand:SI 2 "uint5_operand" "")
8960 (match_operand:SI 3 "uint5_operand" "")))]
8964 unsigned HOST_WIDE_INT len = UINTVAL (operands[2]);
8965 unsigned HOST_WIDE_INT pos = UINTVAL (operands[3]);
8967 /* PA extraction insns don't support zero length bitfields or fields
8968 extending beyond the left or right-most bits. Also, the predicate
8969 rejects lengths equal to a word as they are better handled by
8970 the move patterns. */
8971 if (len == 0 || pos + len > 32)
8974 /* From mips.md: extract_bit_field doesn't verify that our source
8975 matches the predicate, so check it again here. */
8976 if (!register_operand (operands[1], VOIDmode))
8979 emit_insn (gen_extv_32 (operands[0], operands[1],
8980 operands[2], operands[3]));
8984 (define_insn "extv_32"
8985 [(set (match_operand:SI 0 "register_operand" "=r")
8986 (sign_extract:SI (match_operand:SI 1 "register_operand" "r")
8987 (match_operand:SI 2 "uint5_operand" "")
8988 (match_operand:SI 3 "uint5_operand" "")))]
8989 "UINTVAL (operands[2]) > 0
8990 && UINTVAL (operands[2]) + UINTVAL (operands[3]) <= 32"
8991 "{extrs|extrw,s} %1,%3+%2-1,%2,%0"
8992 [(set_attr "type" "shift")
8993 (set_attr "length" "4")])
8996 [(set (match_operand:SI 0 "register_operand" "=r")
8997 (sign_extract:SI (match_operand:SI 1 "register_operand" "r")
8999 (match_operand:SI 2 "register_operand" "q")))]
9001 "{vextrs %1,1,%0|extrw,s %1,%%sar,1,%0}"
9002 [(set_attr "type" "shift")
9003 (set_attr "length" "4")])
9005 (define_expand "extvdi"
9006 [(set (match_operand:DI 0 "register_operand" "")
9007 (sign_extract:DI (match_operand:DI 1 "register_operand" "")
9008 (match_operand:DI 2 "uint6_operand" "")
9009 (match_operand:DI 3 "uint6_operand" "")))]
9013 unsigned HOST_WIDE_INT len = UINTVAL (operands[2]);
9014 unsigned HOST_WIDE_INT pos = UINTVAL (operands[3]);
9016 /* PA extraction insns don't support zero length bitfields or fields
9017 extending beyond the left or right-most bits. Also, the predicate
9018 rejects lengths equal to a doubleword as they are better handled by
9019 the move patterns. */
9020 if (len == 0 || pos + len > 64)
9023 /* From mips.md: extract_bit_field doesn't verify that our source
9024 matches the predicate, so check it again here. */
9025 if (!register_operand (operands[1], VOIDmode))
9028 emit_insn (gen_extv_64 (operands[0], operands[1],
9029 operands[2], operands[3]));
9033 (define_insn "extv_64"
9034 [(set (match_operand:DI 0 "register_operand" "=r")
9035 (sign_extract:DI (match_operand:DI 1 "register_operand" "r")
9036 (match_operand:DI 2 "uint6_operand" "")
9037 (match_operand:DI 3 "uint6_operand" "")))]
9039 && UINTVAL (operands[2]) > 0
9040 && UINTVAL (operands[2]) + UINTVAL (operands[3]) <= 64"
9041 "extrd,s %1,%3+%2-1,%2,%0"
9042 [(set_attr "type" "shift")
9043 (set_attr "length" "4")])
9046 [(set (match_operand:DI 0 "register_operand" "=r")
9047 (sign_extract:DI (match_operand:DI 1 "register_operand" "r")
9049 (match_operand:DI 2 "register_operand" "q")))]
9051 "extrd,s %1,%%sar,1,%0"
9052 [(set_attr "type" "shift")
9053 (set_attr "length" "4")])
9055 ;;; Operands 1 and 2 are assumed to be CONST_INTs.
9056 (define_expand "insvsi"
9057 [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "")
9058 (match_operand:SI 1 "uint5_operand" "")
9059 (match_operand:SI 2 "uint5_operand" ""))
9060 (match_operand:SI 3 "arith5_operand" ""))]
9064 unsigned HOST_WIDE_INT len = UINTVAL (operands[1]);
9065 unsigned HOST_WIDE_INT pos = UINTVAL (operands[2]);
9067 /* PA insertion insns don't support zero length bitfields or fields
9068 extending beyond the left or right-most bits. Also, the predicate
9069 rejects lengths equal to a word as they are better handled by
9070 the move patterns. */
9071 if (len <= 0 || pos + len > 32)
9074 /* From mips.md: insert_bit_field doesn't verify that our destination
9075 matches the predicate, so check it again here. */
9076 if (!register_operand (operands[0], VOIDmode))
9079 emit_insn (gen_insv_32 (operands[0], operands[1],
9080 operands[2], operands[3]));
9084 (define_insn "insv_32"
9085 [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "+r,r")
9086 (match_operand:SI 1 "uint5_operand" "")
9087 (match_operand:SI 2 "uint5_operand" ""))
9088 (match_operand:SI 3 "arith5_operand" "r,L"))]
9089 "UINTVAL (operands[1]) > 0
9090 && UINTVAL (operands[1]) + UINTVAL (operands[2]) <= 32"
9092 {dep|depw} %3,%2+%1-1,%1,%0
9093 {depi|depwi} %3,%2+%1-1,%1,%0"
9094 [(set_attr "type" "shift,shift")
9095 (set_attr "length" "4,4")])
9097 ;; Optimize insertion of const_int values of type 1...1xxxx.
9099 [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "+r")
9100 (match_operand:SI 1 "uint5_operand" "")
9101 (match_operand:SI 2 "uint5_operand" ""))
9102 (match_operand:SI 3 "const_int_operand" ""))]
9103 "(INTVAL (operands[3]) & 0x10) != 0 &&
9104 (~INTVAL (operands[3]) & ((1L << INTVAL (operands[1])) - 1) & ~0xf) == 0"
9107 operands[3] = GEN_INT ((INTVAL (operands[3]) & 0xf) - 0x10);
9108 return \"{depi|depwi} %3,%2+%1-1,%1,%0\";
9110 [(set_attr "type" "shift")
9111 (set_attr "length" "4")])
9113 (define_expand "insvdi"
9114 [(set (zero_extract:DI (match_operand:DI 0 "register_operand" "")
9115 (match_operand:DI 1 "uint6_operand" "")
9116 (match_operand:DI 2 "uint6_operand" ""))
9117 (match_operand:DI 3 "arith5_operand" ""))]
9121 unsigned HOST_WIDE_INT len = UINTVAL (operands[1]);
9122 unsigned HOST_WIDE_INT pos = UINTVAL (operands[2]);
9124 /* PA insertion insns don't support zero length bitfields or fields
9125 extending beyond the left or right-most bits. Also, the predicate
9126 rejects lengths equal to a doubleword as they are better handled by
9127 the move patterns. */
9128 if (len <= 0 || pos + len > 64)
9131 /* From mips.md: insert_bit_field doesn't verify that our destination
9132 matches the predicate, so check it again here. */
9133 if (!register_operand (operands[0], VOIDmode))
9136 emit_insn (gen_insv_64 (operands[0], operands[1],
9137 operands[2], operands[3]));
9141 (define_insn "insv_64"
9142 [(set (zero_extract:DI (match_operand:DI 0 "register_operand" "+r,r")
9143 (match_operand:DI 1 "uint6_operand" "")
9144 (match_operand:DI 2 "uint6_operand" ""))
9145 (match_operand:DI 3 "arith5_operand" "r,L"))]
9147 && UINTVAL (operands[1]) > 0
9148 && UINTVAL (operands[1]) + UINTVAL (operands[2]) <= 64"
9150 depd %3,%2+%1-1,%1,%0
9151 depdi %3,%2+%1-1,%1,%0"
9152 [(set_attr "type" "shift,shift")
9153 (set_attr "length" "4,4")])
9155 ;; Optimize insertion of const_int values of type 1...1xxxx.
9157 [(set (zero_extract:DI (match_operand:DI 0 "register_operand" "+r")
9158 (match_operand:DI 1 "uint6_operand" "")
9159 (match_operand:DI 2 "uint6_operand" ""))
9160 (match_operand:DI 3 "const_int_operand" ""))]
9161 "(INTVAL (operands[3]) & 0x10) != 0
9163 && (~INTVAL (operands[3]) & ((1L << INTVAL (operands[1])) - 1) & ~0xf) == 0"
9166 operands[3] = GEN_INT ((INTVAL (operands[3]) & 0xf) - 0x10);
9167 return \"depdi %3,%2+%1-1,%1,%0\";
9169 [(set_attr "type" "shift")
9170 (set_attr "length" "4")])
9173 [(set (match_operand:DI 0 "register_operand" "=r")
9174 (ashift:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "r"))
9177 "depd,z %1,31,32,%0"
9178 [(set_attr "type" "shift")
9179 (set_attr "length" "4")])
9181 ;; This insn is used for some loop tests, typically loops reversed when
9182 ;; strength reduction is used. It is actually created when the instruction
9183 ;; combination phase combines the special loop test. Since this insn
9184 ;; is both a jump insn and has an output, it must deal with its own
9185 ;; reloads, hence the `Q' constraints. The `!' constraints direct reload
9186 ;; to not choose the register alternatives in the event a reload is needed.
9187 (define_insn "decrement_and_branch_until_zero"
9190 (match_operator 2 "ordered_comparison_operator"
9192 (match_operand:SI 0 "reg_before_reload_operand" "+!r,!*f,*Q")
9193 (match_operand:SI 1 "int5_operand" "L,L,L"))
9195 (label_ref (match_operand 3 "" ""))
9198 (plus:SI (match_dup 0) (match_dup 1)))
9199 (clobber (match_scratch:SI 4 "=X,r,r"))]
9201 "* return pa_output_dbra (operands, insn, which_alternative); "
9202 ;; Do not expect to understand this the first time through.
9203 [(set_attr "type" "cbranch,multi,multi")
9204 (set (attr "length")
9205 (if_then_else (eq_attr "alternative" "0")
9206 ;; Loop counter in register case
9207 ;; Short branch has length of 4
9208 ;; Long branch has length of 8, 20, 24 or 28
9209 (cond [(lt (abs (minus (match_dup 3) (plus (pc) (const_int 8))))
9210 (const_int MAX_12BIT_OFFSET))
9212 (lt (abs (minus (match_dup 3) (plus (pc) (const_int 8))))
9213 (const_int MAX_17BIT_OFFSET))
9215 (match_test "TARGET_PORTABLE_RUNTIME")
9217 (not (match_test "flag_pic"))
9221 ;; Loop counter in FP reg case.
9222 ;; Extra goo to deal with additional reload insns.
9223 (if_then_else (eq_attr "alternative" "1")
9224 (if_then_else (lt (match_dup 3) (pc))
9225 (cond [(lt (abs (minus (match_dup 3) (plus (pc) (const_int 24))))
9226 (const_int MAX_12BIT_OFFSET))
9228 (lt (abs (minus (match_dup 3) (plus (pc) (const_int 24))))
9229 (const_int MAX_17BIT_OFFSET))
9231 (match_test "TARGET_PORTABLE_RUNTIME")
9233 (not (match_test "flag_pic"))
9236 (cond [(lt (abs (minus (match_dup 3) (plus (pc) (const_int 8))))
9237 (const_int MAX_12BIT_OFFSET))
9239 (lt (abs (minus (match_dup 3) (plus (pc) (const_int 8))))
9240 (const_int MAX_17BIT_OFFSET))
9242 (match_test "TARGET_PORTABLE_RUNTIME")
9244 (not (match_test "flag_pic"))
9248 ;; Loop counter in memory case.
9249 ;; Extra goo to deal with additional reload insns.
9250 (if_then_else (lt (match_dup 3) (pc))
9251 (cond [(lt (abs (minus (match_dup 3) (plus (pc) (const_int 12))))
9252 (const_int MAX_12BIT_OFFSET))
9254 (lt (abs (minus (match_dup 3) (plus (pc) (const_int 12))))
9255 (const_int MAX_17BIT_OFFSET))
9257 (match_test "TARGET_PORTABLE_RUNTIME")
9259 (not (match_test "flag_pic"))
9262 (cond [(lt (abs (minus (match_dup 3) (plus (pc) (const_int 8))))
9263 (const_int MAX_12BIT_OFFSET))
9265 (lt (abs (minus (match_dup 3) (plus (pc) (const_int 8))))
9266 (const_int MAX_17BIT_OFFSET))
9268 (match_test "TARGET_PORTABLE_RUNTIME")
9270 (not (match_test "flag_pic"))
9272 (const_int 36))))))])
9277 (match_operator 2 "movb_comparison_operator"
9278 [(match_operand:SI 1 "register_operand" "r,r,r,r") (const_int 0)])
9279 (label_ref (match_operand 3 "" ""))
9281 (set (match_operand:SI 0 "reg_before_reload_operand" "=!r,!*f,*Q,!*q")
9284 "* return pa_output_movb (operands, insn, which_alternative, 0); "
9285 ;; Do not expect to understand this the first time through.
9286 [(set_attr "type" "cbranch,multi,multi,multi")
9287 (set (attr "length")
9288 (if_then_else (eq_attr "alternative" "0")
9289 ;; Loop counter in register case
9290 ;; Short branch has length of 4
9291 ;; Long branch has length of 8, 20, 24 or 28
9292 (cond [(lt (abs (minus (match_dup 3) (plus (pc) (const_int 8))))
9293 (const_int MAX_12BIT_OFFSET))
9295 (lt (abs (minus (match_dup 3) (plus (pc) (const_int 8))))
9296 (const_int MAX_17BIT_OFFSET))
9298 (match_test "TARGET_PORTABLE_RUNTIME")
9300 (not (match_test "flag_pic"))
9304 ;; Loop counter in FP reg case.
9305 ;; Extra goo to deal with additional reload insns.
9306 (if_then_else (eq_attr "alternative" "1")
9307 (if_then_else (lt (match_dup 3) (pc))
9308 (cond [(lt (abs (minus (match_dup 3) (plus (pc) (const_int 12))))
9309 (const_int MAX_12BIT_OFFSET))
9311 (lt (abs (minus (match_dup 3) (plus (pc) (const_int 12))))
9312 (const_int MAX_17BIT_OFFSET))
9314 (match_test "TARGET_PORTABLE_RUNTIME")
9316 (not (match_test "flag_pic"))
9319 (cond [(lt (abs (minus (match_dup 3) (plus (pc) (const_int 8))))
9320 (const_int MAX_12BIT_OFFSET))
9322 (lt (abs (minus (match_dup 3) (plus (pc) (const_int 8))))
9323 (const_int MAX_17BIT_OFFSET))
9325 (match_test "TARGET_PORTABLE_RUNTIME")
9327 (not (match_test "flag_pic"))
9331 ;; Loop counter in memory or sar case.
9332 ;; Extra goo to deal with additional reload insns.
9333 (cond [(lt (abs (minus (match_dup 3) (plus (pc) (const_int 8))))
9334 (const_int MAX_12BIT_OFFSET))
9336 (lt (abs (minus (match_dup 3) (plus (pc) (const_int 8))))
9337 (const_int MAX_17BIT_OFFSET))
9339 (match_test "TARGET_PORTABLE_RUNTIME")
9341 (not (match_test "flag_pic"))
9343 (const_int 32)))))])
9345 ;; Handle negated branch.
9349 (match_operator 2 "movb_comparison_operator"
9350 [(match_operand:SI 1 "register_operand" "r,r,r,r") (const_int 0)])
9352 (label_ref (match_operand 3 "" ""))))
9353 (set (match_operand:SI 0 "reg_before_reload_operand" "=!r,!*f,*Q,!*q")
9356 "* return pa_output_movb (operands, insn, which_alternative, 1); "
9357 ;; Do not expect to understand this the first time through.
9358 [(set_attr "type" "cbranch,multi,multi,multi")
9359 (set (attr "length")
9360 (if_then_else (eq_attr "alternative" "0")
9361 ;; Loop counter in register case
9362 ;; Short branch has length of 4
9363 ;; Long branch has length of 8
9364 (cond [(lt (abs (minus (match_dup 3) (plus (pc) (const_int 8))))
9365 (const_int MAX_12BIT_OFFSET))
9367 (lt (abs (minus (match_dup 3) (plus (pc) (const_int 8))))
9368 (const_int MAX_17BIT_OFFSET))
9370 (match_test "TARGET_PORTABLE_RUNTIME")
9372 (not (match_test "flag_pic"))
9376 ;; Loop counter in FP reg case.
9377 ;; Extra goo to deal with additional reload insns.
9378 (if_then_else (eq_attr "alternative" "1")
9379 (if_then_else (lt (match_dup 3) (pc))
9380 (cond [(lt (abs (minus (match_dup 3) (plus (pc) (const_int 12))))
9381 (const_int MAX_12BIT_OFFSET))
9383 (lt (abs (minus (match_dup 3) (plus (pc) (const_int 12))))
9384 (const_int MAX_17BIT_OFFSET))
9386 (match_test "TARGET_PORTABLE_RUNTIME")
9388 (not (match_test "flag_pic"))
9391 (cond [(lt (abs (minus (match_dup 3) (plus (pc) (const_int 8))))
9392 (const_int MAX_12BIT_OFFSET))
9394 (lt (abs (minus (match_dup 3) (plus (pc) (const_int 8))))
9395 (const_int MAX_17BIT_OFFSET))
9397 (match_test "TARGET_PORTABLE_RUNTIME")
9399 (not (match_test "flag_pic"))
9403 ;; Loop counter in memory or SAR case.
9404 ;; Extra goo to deal with additional reload insns.
9405 (cond [(lt (abs (minus (match_dup 3) (plus (pc) (const_int 8))))
9406 (const_int MAX_12BIT_OFFSET))
9408 (lt (abs (minus (match_dup 3) (plus (pc) (const_int 8))))
9409 (const_int MAX_17BIT_OFFSET))
9411 (match_test "TARGET_PORTABLE_RUNTIME")
9413 (not (match_test "flag_pic"))
9415 (const_int 32)))))])
9418 [(set (pc) (label_ref (match_operand 3 "" "" )))
9419 (set (match_operand:SI 0 "ireg_operand" "=r")
9420 (plus:SI (match_operand:SI 1 "ireg_operand" "r")
9421 (match_operand:SI 2 "ireg_or_int5_operand" "rL")))]
9422 "(reload_completed && operands[0] == operands[1]) || operands[0] == operands[2]"
9425 return pa_output_parallel_addb (operands, insn);
9427 [(set_attr "type" "parallel_branch")
9428 (set (attr "length")
9429 (cond [(lt (abs (minus (match_dup 3) (plus (pc) (const_int 8))))
9430 (const_int MAX_12BIT_OFFSET))
9432 (lt (abs (minus (match_dup 3) (plus (pc) (const_int 8))))
9433 (const_int MAX_17BIT_OFFSET))
9435 (match_test "TARGET_PORTABLE_RUNTIME")
9437 (not (match_test "flag_pic"))
9442 [(set (pc) (label_ref (match_operand 2 "" "" )))
9443 (set (match_operand:SF 0 "ireg_operand" "=r")
9444 (match_operand:SF 1 "ireg_or_int5_operand" "rL"))]
9448 return pa_output_parallel_movb (operands, insn);
9450 [(set_attr "type" "parallel_branch")
9451 (set (attr "length")
9452 (cond [(lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
9453 (const_int MAX_12BIT_OFFSET))
9455 (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
9456 (const_int MAX_17BIT_OFFSET))
9458 (match_test "TARGET_PORTABLE_RUNTIME")
9460 (not (match_test "flag_pic"))
9465 [(set (pc) (label_ref (match_operand 2 "" "" )))
9466 (set (match_operand:SI 0 "ireg_operand" "=r")
9467 (match_operand:SI 1 "ireg_or_int5_operand" "rL"))]
9471 return pa_output_parallel_movb (operands, insn);
9473 [(set_attr "type" "parallel_branch")
9474 (set (attr "length")
9475 (cond [(lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
9476 (const_int MAX_12BIT_OFFSET))
9478 (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
9479 (const_int MAX_17BIT_OFFSET))
9481 (match_test "TARGET_PORTABLE_RUNTIME")
9483 (not (match_test "flag_pic"))
9488 [(set (pc) (label_ref (match_operand 2 "" "" )))
9489 (set (match_operand:HI 0 "ireg_operand" "=r")
9490 (match_operand:HI 1 "ireg_or_int5_operand" "rL"))]
9494 return pa_output_parallel_movb (operands, insn);
9496 [(set_attr "type" "parallel_branch")
9497 (set (attr "length")
9498 (cond [(lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
9499 (const_int MAX_12BIT_OFFSET))
9501 (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
9502 (const_int MAX_17BIT_OFFSET))
9504 (match_test "TARGET_PORTABLE_RUNTIME")
9506 (not (match_test "flag_pic"))
9511 [(set (pc) (label_ref (match_operand 2 "" "" )))
9512 (set (match_operand:QI 0 "ireg_operand" "=r")
9513 (match_operand:QI 1 "ireg_or_int5_operand" "rL"))]
9517 return pa_output_parallel_movb (operands, insn);
9519 [(set_attr "type" "parallel_branch")
9520 (set (attr "length")
9521 (cond [(lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
9522 (const_int MAX_12BIT_OFFSET))
9524 (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
9525 (const_int MAX_17BIT_OFFSET))
9527 (match_test "TARGET_PORTABLE_RUNTIME")
9529 (not (match_test "flag_pic"))
9534 [(set (match_operand 0 "register_operand" "=f")
9535 (mult (match_operand 1 "register_operand" "f")
9536 (match_operand 2 "register_operand" "f")))
9537 (set (match_operand 3 "register_operand" "+f")
9538 (plus (match_operand 4 "register_operand" "f")
9539 (match_operand 5 "register_operand" "f")))]
9540 "TARGET_PA_11 && ! TARGET_SOFT_FLOAT
9541 && reload_completed && pa_fmpyaddoperands (operands)"
9544 if (GET_MODE (operands[0]) == DFmode)
9546 if (rtx_equal_p (operands[3], operands[5]))
9547 return \"fmpyadd,dbl %1,%2,%0,%4,%3\";
9549 return \"fmpyadd,dbl %1,%2,%0,%5,%3\";
9553 if (rtx_equal_p (operands[3], operands[5]))
9554 return \"fmpyadd,sgl %1,%2,%0,%4,%3\";
9556 return \"fmpyadd,sgl %1,%2,%0,%5,%3\";
9559 [(set_attr "type" "fpalu")
9560 (set_attr "length" "4")])
9563 [(set (match_operand 3 "register_operand" "+f")
9564 (plus (match_operand 4 "register_operand" "f")
9565 (match_operand 5 "register_operand" "f")))
9566 (set (match_operand 0 "register_operand" "=f")
9567 (mult (match_operand 1 "register_operand" "f")
9568 (match_operand 2 "register_operand" "f")))]
9569 "TARGET_PA_11 && ! TARGET_SOFT_FLOAT
9570 && reload_completed && pa_fmpyaddoperands (operands)"
9573 if (GET_MODE (operands[0]) == DFmode)
9575 if (rtx_equal_p (operands[3], operands[5]))
9576 return \"fmpyadd,dbl %1,%2,%0,%4,%3\";
9578 return \"fmpyadd,dbl %1,%2,%0,%5,%3\";
9582 if (rtx_equal_p (operands[3], operands[5]))
9583 return \"fmpyadd,sgl %1,%2,%0,%4,%3\";
9585 return \"fmpyadd,sgl %1,%2,%0,%5,%3\";
9588 [(set_attr "type" "fpalu")
9589 (set_attr "length" "4")])
9592 [(set (match_operand 0 "register_operand" "=f")
9593 (mult (match_operand 1 "register_operand" "f")
9594 (match_operand 2 "register_operand" "f")))
9595 (set (match_operand 3 "register_operand" "+f")
9596 (minus (match_operand 4 "register_operand" "f")
9597 (match_operand 5 "register_operand" "f")))]
9598 "TARGET_PA_11 && ! TARGET_SOFT_FLOAT
9599 && reload_completed && pa_fmpysuboperands (operands)"
9602 if (GET_MODE (operands[0]) == DFmode)
9603 return \"fmpysub,dbl %1,%2,%0,%5,%3\";
9605 return \"fmpysub,sgl %1,%2,%0,%5,%3\";
9607 [(set_attr "type" "fpalu")
9608 (set_attr "length" "4")])
9611 [(set (match_operand 3 "register_operand" "+f")
9612 (minus (match_operand 4 "register_operand" "f")
9613 (match_operand 5 "register_operand" "f")))
9614 (set (match_operand 0 "register_operand" "=f")
9615 (mult (match_operand 1 "register_operand" "f")
9616 (match_operand 2 "register_operand" "f")))]
9617 "TARGET_PA_11 && ! TARGET_SOFT_FLOAT
9618 && reload_completed && pa_fmpysuboperands (operands)"
9621 if (GET_MODE (operands[0]) == DFmode)
9622 return \"fmpysub,dbl %1,%2,%0,%5,%3\";
9624 return \"fmpysub,sgl %1,%2,%0,%5,%3\";
9626 [(set_attr "type" "fpalu")
9627 (set_attr "length" "4")])
9629 ;; The following two patterns are used by the trampoline code for nested
9630 ;; functions. They flush the I and D cache lines from the start address
9631 ;; (operand0) to the end address (operand1). No lines are flushed if the
9632 ;; end address is less than the start address (unsigned).
9634 ;; Because the range of memory flushed is variable and the size of a MEM
9635 ;; can only be a CONST_INT, the patterns specify that they perform an
9636 ;; unspecified volatile operation on all memory.
9638 ;; The address range for an icache flush must lie within a single
9639 ;; space on targets with non-equivalent space registers.
9641 ;; Operand 0 contains the start address.
9642 ;; Operand 1 contains the end address.
9643 ;; Operand 2 contains the line length to use.
9644 (define_insn "dcacheflush<P:mode>"
9646 (unspec_volatile [(mem:BLK (scratch))] UNSPECV_DCACHE)
9647 (use (match_operand 0 "pmode_register_operand" "r"))
9648 (use (match_operand 1 "pmode_register_operand" "r"))
9649 (use (match_operand 2 "pmode_register_operand" "r"))
9650 (clobber (match_scratch:P 3 "=&0"))]
9652 "cmpb,<dwc><<=,n %3,%1,.\;fdc,m %2(%3)\;sync"
9653 [(set_attr "type" "multi")
9654 (set_attr "length" "12")])
9656 (define_insn "icacheflush<P:mode>"
9658 (unspec_volatile [(mem:BLK (scratch))] UNSPECV_ICACHE)
9659 (use (match_operand 0 "pmode_register_operand" "r"))
9660 (use (match_operand 1 "pmode_register_operand" "r"))
9661 (use (match_operand 2 "pmode_register_operand" "r"))
9662 (clobber (match_operand 3 "pmode_register_operand" "=&r"))
9663 (clobber (match_operand 4 "pmode_register_operand" "=&r"))
9664 (clobber (match_scratch:P 5 "=&0"))]
9666 "mfsp %%sr0,%4\;ldsid (%5),%3\;mtsp %3,%%sr0\;cmpb,<dwc><<=,n %5,%1,.\;fic,m %2(%%sr0,%5)\;sync\;mtsp %4,%%sr0\;nop\;nop\;nop\;nop\;nop\;nop"
9667 [(set_attr "type" "multi")
9668 (set_attr "length" "52")])
9670 ;; An out-of-line prologue.
9671 (define_insn "outline_prologue_call"
9672 [(unspec_volatile [(const_int 0)] UNSPECV_OPC)
9673 (clobber (reg:SI 31))
9674 (clobber (reg:SI 22))
9675 (clobber (reg:SI 21))
9676 (clobber (reg:SI 20))
9677 (clobber (reg:SI 19))
9678 (clobber (reg:SI 1))]
9683 /* We need two different versions depending on whether or not we
9684 need a frame pointer. Also note that we return to the instruction
9685 immediately after the branch rather than two instructions after the
9686 break as normally is the case. */
9687 if (frame_pointer_needed)
9689 /* Must import the magic millicode routine(s). */
9690 output_asm_insn (\".IMPORT __outline_prologue_fp,MILLICODE\", NULL);
9692 if (TARGET_PORTABLE_RUNTIME)
9694 output_asm_insn (\"ldil L'__outline_prologue_fp,%%r31\", NULL);
9695 output_asm_insn (\"ble,n R'__outline_prologue_fp(%%sr0,%%r31)\",
9699 output_asm_insn (\"{bl|b,l},n __outline_prologue_fp,%%r31\", NULL);
9703 /* Must import the magic millicode routine(s). */
9704 output_asm_insn (\".IMPORT __outline_prologue,MILLICODE\", NULL);
9706 if (TARGET_PORTABLE_RUNTIME)
9708 output_asm_insn (\"ldil L'__outline_prologue,%%r31\", NULL);
9709 output_asm_insn (\"ble,n R'__outline_prologue(%%sr0,%%r31)\", NULL);
9712 output_asm_insn (\"{bl|b,l},n __outline_prologue,%%r31\", NULL);
9716 [(set_attr "type" "multi")
9717 (set_attr "length" "8")])
9719 ;; An out-of-line epilogue.
9720 (define_insn "outline_epilogue_call"
9721 [(unspec_volatile [(const_int 1)] UNSPECV_OEC)
9724 (clobber (reg:SI 31))
9725 (clobber (reg:SI 22))
9726 (clobber (reg:SI 21))
9727 (clobber (reg:SI 20))
9728 (clobber (reg:SI 19))
9729 (clobber (reg:SI 2))
9730 (clobber (reg:SI 1))]
9735 /* We need two different versions depending on whether or not we
9736 need a frame pointer. Also note that we return to the instruction
9737 immediately after the branch rather than two instructions after the
9738 break as normally is the case. */
9739 if (frame_pointer_needed)
9741 /* Must import the magic millicode routine. */
9742 output_asm_insn (\".IMPORT __outline_epilogue_fp,MILLICODE\", NULL);
9744 /* The out-of-line prologue will make sure we return to the right
9746 if (TARGET_PORTABLE_RUNTIME)
9748 output_asm_insn (\"ldil L'__outline_epilogue_fp,%%r31\", NULL);
9749 output_asm_insn (\"ble,n R'__outline_epilogue_fp(%%sr0,%%r31)\",
9753 output_asm_insn (\"{bl|b,l},n __outline_epilogue_fp,%%r31\", NULL);
9757 /* Must import the magic millicode routine. */
9758 output_asm_insn (\".IMPORT __outline_epilogue,MILLICODE\", NULL);
9760 /* The out-of-line prologue will make sure we return to the right
9762 if (TARGET_PORTABLE_RUNTIME)
9764 output_asm_insn (\"ldil L'__outline_epilogue,%%r31\", NULL);
9765 output_asm_insn (\"ble,n R'__outline_epilogue(%%sr0,%%r31)\", NULL);
9768 output_asm_insn (\"{bl|b,l},n __outline_epilogue,%%r31\", NULL);
9772 [(set_attr "type" "multi")
9773 (set_attr "length" "8")])
9775 ;; Given a function pointer, canonicalize it so it can be
9776 ;; reliably compared to another function pointer. */
9777 (define_expand "canonicalize_funcptr_for_compare"
9778 [(set (reg:SI 26) (match_operand:SI 1 "register_operand" ""))
9779 (parallel [(set (reg:SI 29) (unspec:SI [(reg:SI 26)] UNSPEC_CFFC))
9780 (clobber (match_dup 2))
9781 (clobber (reg:SI 26))
9782 (clobber (reg:SI 22))
9783 (clobber (reg:SI 31))])
9784 (set (match_operand:SI 0 "register_operand" "")
9786 "!TARGET_PORTABLE_RUNTIME && !TARGET_64BIT"
9791 rtx canonicalize_funcptr_for_compare_libfunc
9792 = init_one_libfunc (CANONICALIZE_FUNCPTR_FOR_COMPARE_LIBCALL);
9794 emit_library_call_value (canonicalize_funcptr_for_compare_libfunc,
9795 operands[0], LCT_NORMAL, Pmode,
9796 operands[1], Pmode);
9800 operands[2] = gen_reg_rtx (SImode);
9801 if (GET_CODE (operands[1]) != REG)
9803 rtx tmp = gen_reg_rtx (Pmode);
9804 emit_move_insn (tmp, operands[1]);
9809 (define_insn "*$$sh_func_adrs"
9810 [(set (reg:SI 29) (unspec:SI [(reg:SI 26)] UNSPEC_CFFC))
9811 (clobber (match_operand:SI 0 "register_operand" "=a"))
9812 (clobber (reg:SI 26))
9813 (clobber (reg:SI 22))
9814 (clobber (reg:SI 31))]
9818 int length = get_attr_length (insn);
9821 xoperands[0] = GEN_INT (length - 8);
9822 xoperands[1] = GEN_INT (length - 16);
9824 /* Must import the magic millicode routine. */
9825 output_asm_insn (\".IMPORT $$sh_func_adrs,MILLICODE\", NULL);
9827 /* This is absolutely amazing.
9829 First, copy our input parameter into %r29 just in case we don't
9830 need to call $$sh_func_adrs. */
9831 output_asm_insn (\"copy %%r26,%%r29\", NULL);
9832 output_asm_insn (\"{extru|extrw,u} %%r26,31,2,%%r31\", NULL);
9834 /* Next, examine the low two bits in %r26, if they aren't 0x2, then
9835 we use %r26 unchanged. */
9836 output_asm_insn (\"{comib|cmpib},<>,n 2,%%r31,.+%0\", xoperands);
9837 output_asm_insn (\"ldi 4096,%%r31\", NULL);
9839 /* Next, compare %r26 with 4096, if %r26 is less than or equal to
9840 4096, then again we use %r26 unchanged. */
9841 output_asm_insn (\"{comb|cmpb},<<,n %%r26,%%r31,.+%1\", xoperands);
9843 /* Finally, call $$sh_func_adrs to extract the function's real add24. */
9844 return pa_output_millicode_call (insn,
9845 gen_rtx_SYMBOL_REF (SImode,
9846 \"$$sh_func_adrs\"));
9848 [(set_attr "type" "sh_func_adrs")
9849 (set (attr "length")
9850 (cond [(and (const_int 0) (eq (const_int 0) (pc))) (const_int 28)]
9851 (plus (symbol_ref "pa_attr_length_millicode_call (insn)")
9854 ;; On the PA, the PIC register is call clobbered, so it must
9855 ;; be saved & restored around calls by the caller. If the call
9856 ;; doesn't return normally (nonlocal goto, or an exception is
9857 ;; thrown), then the code at the exception handler label must
9858 ;; restore the PIC register.
9859 (define_expand "exception_receiver"
9864 /* On the 64-bit port, we need a blockage because there is
9865 confusion regarding the dependence of the restore on the
9866 frame pointer. As a result, the frame pointer and pic
9867 register restores sometimes are interchanged erroneously. */
9869 emit_insn (gen_blockage ());
9870 /* Restore the PIC register using hppa_pic_save_rtx (). The
9871 PIC register is not saved in the frame in 64-bit ABI. */
9872 emit_move_insn (pic_offset_table_rtx, hppa_pic_save_rtx ());
9873 emit_insn (gen_blockage ());
9877 (define_expand "builtin_setjmp_receiver"
9878 [(label_ref (match_operand 0 "" ""))]
9883 emit_insn (gen_blockage ());
9884 /* Restore the PIC register. Hopefully, this will always be from
9885 a stack slot. The only registers that are valid after a
9886 builtin_longjmp are the stack and frame pointers. */
9887 emit_move_insn (pic_offset_table_rtx, hppa_pic_save_rtx ());
9888 emit_insn (gen_blockage ());
9892 ;; Allocate new stack space and update the saved stack pointer in the
9893 ;; frame marker. The HP C compilers also copy additional words in the
9894 ;; frame marker. The 64-bit compiler copies words at -48, -32 and -24.
9895 ;; The 32-bit compiler copies the word at -16 (Static Link). We
9896 ;; currently don't copy these values.
9898 ;; Since the copy of the frame marker can't be done atomically, I
9899 ;; suspect that using it for unwind purposes may be somewhat unreliable.
9900 ;; The HP compilers appear to raise the stack and copy the frame
9901 ;; marker in a strict instruction sequence. This suggests that the
9902 ;; unwind library may check for an alloca sequence when ALLOCA_FRAME
9903 ;; is set in the callinfo data. We currently don't set ALLOCA_FRAME
9904 ;; as GAS doesn't support it, or try to keep the instructions emitted
9905 ;; here in strict sequence.
9906 (define_expand "allocate_stack"
9907 [(match_operand 0 "" "")
9908 (match_operand 1 "" "")]
9914 /* Since the stack grows upward, we need to store virtual_stack_dynamic_rtx
9915 in operand 0 before adjusting the stack. */
9916 emit_move_insn (operands[0], virtual_stack_dynamic_rtx);
9917 anti_adjust_stack (operands[1]);
9918 if (TARGET_HPUX_UNWIND_LIBRARY)
9920 addr = gen_rtx_PLUS (word_mode, stack_pointer_rtx,
9921 GEN_INT (TARGET_64BIT ? -8 : -4));
9922 emit_move_insn (gen_rtx_MEM (word_mode, addr), hard_frame_pointer_rtx);
9924 if (!TARGET_64BIT && flag_pic)
9926 rtx addr = gen_rtx_PLUS (word_mode, stack_pointer_rtx, GEN_INT (-32));
9927 emit_move_insn (gen_rtx_MEM (word_mode, addr), pic_offset_table_rtx);
9932 (define_expand "prefetch"
9933 [(match_operand 0 "address_operand" "")
9934 (match_operand 1 "const_int_operand" "")
9935 (match_operand 2 "const_int_operand" "")]
9938 operands[0] = copy_addr_to_reg (operands[0]);
9939 emit_insn (gen_prefetch_20 (operands[0], operands[1], operands[2]));
9943 (define_insn "prefetch_20"
9944 [(prefetch (match_operand 0 "pmode_register_operand" "r")
9945 (match_operand:SI 1 "const_int_operand" "n")
9946 (match_operand:SI 2 "const_int_operand" "n"))]
9949 /* The SL cache-control completer indicates good spatial locality but
9950 poor temporal locality. The ldw instruction with a target of general
9951 register 0 prefetches a cache line for a read. The ldd instruction
9952 prefetches a cache line for a write. */
9953 static const char * const instr[2][2] = {
9955 "ldw,sl 0(%0),%%r0",
9963 int read_or_write = INTVAL (operands[1]) == 0 ? 0 : 1;
9964 int locality = INTVAL (operands[2]) == 0 ? 0 : 1;
9966 return instr [locality][read_or_write];
9968 [(set_attr "type" "load")
9969 (set_attr "length" "4")])
9972 (define_insn "tgd_load"
9973 [(set (match_operand:SI 0 "register_operand" "=r")
9974 (unspec:SI [(match_operand 1 "tgd_symbolic_operand" "")] UNSPEC_TLSGD))
9975 (clobber (reg:SI 1))
9980 return \"addil LR'%1-$tls_gdidx$,%%r27\;ldo RR'%1-$tls_gdidx$(%%r1),%0\";
9982 [(set_attr "type" "multi")
9983 (set_attr "length" "8")])
9985 (define_insn "tgd_load_pic"
9986 [(set (match_operand:SI 0 "register_operand" "=r")
9987 (unspec:SI [(match_operand 1 "tgd_symbolic_operand" "")] UNSPEC_TLSGD_PIC))
9988 (clobber (reg:SI 1))
9993 return \"addil LT'%1-$tls_gdidx$,%%r19\;ldo RT'%1-$tls_gdidx$(%%r1),%0\";
9995 [(set_attr "type" "multi")
9996 (set_attr "length" "8")])
9998 (define_insn "tld_load"
9999 [(set (match_operand:SI 0 "register_operand" "=r")
10000 (unspec:SI [(match_operand 1 "tld_symbolic_operand" "")] UNSPEC_TLSLDM))
10001 (clobber (reg:SI 1))
10006 return \"addil LR'%1-$tls_ldidx$,%%r27\;ldo RR'%1-$tls_ldidx$(%%r1),%0\";
10008 [(set_attr "type" "multi")
10009 (set_attr "length" "8")])
10011 (define_insn "tld_load_pic"
10012 [(set (match_operand:SI 0 "register_operand" "=r")
10013 (unspec:SI [(match_operand 1 "tld_symbolic_operand" "")] UNSPEC_TLSLDM_PIC))
10014 (clobber (reg:SI 1))
10019 return \"addil LT'%1-$tls_ldidx$,%%r19\;ldo RT'%1-$tls_ldidx$(%%r1),%0\";
10021 [(set_attr "type" "multi")
10022 (set_attr "length" "8")])
10024 (define_insn "tld_offset_load"
10025 [(set (match_operand:SI 0 "register_operand" "=r")
10026 (plus:SI (unspec:SI [(match_operand 1 "tld_symbolic_operand" "")]
10028 (match_operand:SI 2 "register_operand" "r")))
10029 (clobber (reg:SI 1))]
10033 return \"addil LR'%1-$tls_dtpoff$,%2\;ldo RR'%1-$tls_dtpoff$(%%r1),%0\";
10035 [(set_attr "type" "multi")
10036 (set_attr "length" "8")])
10038 (define_insn "tp_load"
10039 [(set (match_operand:SI 0 "register_operand" "=r")
10040 (unspec:SI [(const_int 0)] UNSPEC_TP))]
10043 [(set_attr "type" "multi")
10044 (set_attr "length" "4")])
10046 (define_insn "tie_load"
10047 [(set (match_operand:SI 0 "register_operand" "=r")
10048 (unspec:SI [(match_operand 1 "tie_symbolic_operand" "")] UNSPEC_TLSIE))
10049 (clobber (reg:SI 1))
10054 return \"addil LR'%1-$tls_ieoff$,%%r27\;ldw RR'%1-$tls_ieoff$(%%r1),%0\";
10056 [(set_attr "type" "multi")
10057 (set_attr "length" "8")])
10059 (define_insn "tie_load_pic"
10060 [(set (match_operand:SI 0 "register_operand" "=r")
10061 (unspec:SI [(match_operand 1 "tie_symbolic_operand" "")] UNSPEC_TLSIE_PIC))
10062 (clobber (reg:SI 1))
10067 return \"addil LT'%1-$tls_ieoff$,%%r19\;ldw RT'%1-$tls_ieoff$(%%r1),%0\";
10069 [(set_attr "type" "multi")
10070 (set_attr "length" "8")])
10072 (define_insn "tle_load"
10073 [(set (match_operand:SI 0 "register_operand" "=r")
10074 (plus:SI (unspec:SI [(match_operand 1 "tle_symbolic_operand" "")]
10076 (match_operand:SI 2 "register_operand" "r")))
10077 (clobber (reg:SI 1))]
10079 "addil LR'%1-$tls_leoff$,%2\;ldo RR'%1-$tls_leoff$(%%r1),%0"
10080 [(set_attr "type" "multi")
10081 (set_attr "length" "8")])
10083 ;; Atomic instructions
10085 ;; All memory loads and stores access storage atomically except
10086 ;; for one exception. The STORE BYTES, STORE DOUBLE BYTES, and
10087 ;; doubleword loads and stores are not guaranteed to be atomic
10088 ;; when referencing the I/O address space.
10090 ;; These patterns are at the bottom so the non atomic versions are preferred.
10092 (define_expand "atomic_storeqi"
10093 [(match_operand:QI 0 "memory_operand") ;; memory
10094 (match_operand:QI 1 "register_operand") ;; val out
10095 (match_operand:SI 2 "const_int_operand")] ;; model
10098 if (TARGET_SYNC_LIBCALL)
10100 rtx mem = operands[0];
10101 rtx val = operands[1];
10102 if (pa_maybe_emit_compare_and_swap_exchange_loop (NULL_RTX, mem, val))
10108 ;; Implement atomic HImode stores using exchange.
10110 (define_expand "atomic_storehi"
10111 [(match_operand:HI 0 "memory_operand") ;; memory
10112 (match_operand:HI 1 "register_operand") ;; val out
10113 (match_operand:SI 2 "const_int_operand")] ;; model
10116 if (TARGET_SYNC_LIBCALL)
10118 rtx mem = operands[0];
10119 rtx val = operands[1];
10120 if (pa_maybe_emit_compare_and_swap_exchange_loop (NULL_RTX, mem, val))
10126 ;; Implement atomic SImode store using exchange.
10128 (define_expand "atomic_storesi"
10129 [(match_operand:SI 0 "memory_operand") ;; memory
10130 (match_operand:SI 1 "register_operand") ;; val out
10131 (match_operand:SI 2 "const_int_operand")] ;; model
10134 if (TARGET_SYNC_LIBCALL)
10136 rtx mem = operands[0];
10137 rtx val = operands[1];
10138 if (pa_maybe_emit_compare_and_swap_exchange_loop (NULL_RTX, mem, val))
10144 ;; Implement atomic DImode load.
10146 (define_expand "atomic_loaddi"
10147 [(match_operand:DI 0 "register_operand") ;; val out
10148 (match_operand:DI 1 "memory_operand") ;; memory
10149 (match_operand:SI 2 "const_int_operand")] ;; model
10152 enum memmodel model;
10154 if (TARGET_64BIT || TARGET_DISABLE_FPREGS || TARGET_SOFT_FLOAT)
10157 model = memmodel_from_int (INTVAL (operands[2]));
10158 operands[1] = force_reg (SImode, XEXP (operands[1], 0));
10159 if (is_mm_seq_cst (model))
10160 expand_mem_thread_fence (model);
10161 emit_insn (gen_atomic_loaddi_1 (operands[0], operands[1]));
10162 expand_mem_thread_fence (model);
10166 (define_insn "atomic_loaddi_1"
10167 [(set (match_operand:DI 0 "register_operand" "=r")
10168 (mem:DI (match_operand:SI 1 "register_operand" "r")))
10169 (clobber (match_scratch:DI 2 "=f"))]
10170 "!TARGET_64BIT && !TARGET_DISABLE_FPREGS && !TARGET_SOFT_FLOAT"
10171 "{fldds|fldd} 0(%1),%2\n\t{fstds|fstd} %2,-16(%%sp)\n\t{ldws|ldw} -16(%%sp),%0\n\t{ldws|ldw} -12(%%sp),%R0"
10172 [(set_attr "type" "move")
10173 (set_attr "length" "16")])
10175 ;; Implement atomic DImode store.
10177 (define_expand "atomic_storedi"
10178 [(match_operand:DI 0 "memory_operand") ;; memory
10179 (match_operand:DI 1 "reg_or_cint_move_operand") ;; val out
10180 (match_operand:SI 2 "const_int_operand")] ;; model
10183 enum memmodel model;
10185 if (TARGET_SYNC_LIBCALL)
10187 rtx mem = operands[0];
10188 rtx val = operands[1];
10189 if (pa_maybe_emit_compare_and_swap_exchange_loop (NULL_RTX, mem, val))
10193 if (TARGET_64BIT || TARGET_DISABLE_FPREGS || TARGET_SOFT_FLOAT)
10196 model = memmodel_from_int (INTVAL (operands[2]));
10197 operands[0] = force_reg (SImode, XEXP (operands[0], 0));
10198 if (operands[1] != CONST0_RTX (DImode))
10199 operands[1] = force_reg (DImode, operands[1]);
10200 expand_mem_thread_fence (model);
10201 emit_insn (gen_atomic_storedi_1 (operands[0], operands[1]));
10202 if (is_mm_seq_cst (model))
10203 expand_mem_thread_fence (model);
10207 (define_insn "atomic_storedi_1"
10208 [(set (mem:DI (match_operand:SI 0 "register_operand" "r,r"))
10209 (match_operand:DI 1 "reg_or_0_operand" "M,r"))
10210 (clobber (match_scratch:DI 2 "=X,f"))]
10211 "!TARGET_64BIT && !TARGET_DISABLE_FPREGS && !TARGET_SOFT_FLOAT"
10213 {fstds|fstd} %%fr0,0(%0)
10214 {stws|stw} %1,-16(%%sp)\n\t{stws|stw} %R1,-12(%%sp)\n\t{fldds|fldd} -16(%%sp),%2\n\t{fstds|fstd} %2,0(%0)"
10215 [(set_attr "type" "move,move")
10216 (set_attr "length" "4,16")])
10218 ;; PA 2.0 hardware supports out-of-order execution of loads and stores, so
10219 ;; we need memory barriers to enforce program order for memory references
10220 ;; when the TLB and PSW O bits are not set. We assume all PA 2.0 systems
10221 ;; are weakly ordered since neither HP-UX or Linux set the PSW O bit. Since
10222 ;; we want PA 1.x code to be PA 2.0 compatible, we also need barriers when
10223 ;; generating PA 1.x code even though all PA 1.x systems are strongly ordered.
10225 ;; When barriers are needed, we use a strongly ordered ldcw instruction as
10226 ;; the barrier. Most PA 2.0 targets are cache coherent. In that case, we
10227 ;; can use the coherent cache control hint and avoid aligning the ldcw
10228 ;; address. In spite of its description, it is not clear that the sync
10229 ;; instruction works as a barrier.
10231 (define_expand "memory_barrier"
10233 [(set (match_dup 0) (unspec:BLK [(match_dup 0)] UNSPEC_MEMORY_BARRIER))
10234 (clobber (match_dup 1))])]
10237 /* We don't need a barrier if the target uses ordered memory references. */
10238 if (TARGET_ORDERED)
10240 operands[1] = gen_reg_rtx (Pmode);
10241 operands[0] = gen_rtx_MEM (BLKmode, operands[1]);
10242 MEM_VOLATILE_P (operands[0]) = 1;
10245 (define_insn "*memory_barrier_coherent"
10246 [(set (match_operand:BLK 0 "" "")
10247 (unspec:BLK [(match_dup 0)] UNSPEC_MEMORY_BARRIER))
10248 (clobber (match_operand 1 "pmode_register_operand" "=r"))]
10249 "TARGET_PA_20 && TARGET_COHERENT_LDCW"
10250 "ldcw,co 0(%%sp),%1"
10251 [(set_attr "type" "binary")
10252 (set_attr "length" "4")])
10254 (define_insn "*memory_barrier_64"
10255 [(set (match_operand:BLK 0 "" "")
10256 (unspec:BLK [(match_dup 0)] UNSPEC_MEMORY_BARRIER))
10257 (clobber (match_operand 1 "pmode_register_operand" "=&r"))]
10259 "ldo 15(%%sp),%1\n\tdepd %%r0,63,3,%1\n\tldcw 0(%1),%1"
10260 [(set_attr "type" "binary")
10261 (set_attr "length" "12")])
10263 (define_insn "*memory_barrier_32"
10264 [(set (match_operand:BLK 0 "" "")
10265 (unspec:BLK [(match_dup 0)] UNSPEC_MEMORY_BARRIER))
10266 (clobber (match_operand 1 "pmode_register_operand" "=&r"))]
10268 "ldo 15(%%sp),%1\n\t{dep|depw} %%r0,31,3,%1\n\tldcw 0(%1),%1"
10269 [(set_attr "type" "binary")
10270 (set_attr "length" "12")])