1 ;; Predicate definitions for POWER and PowerPC.
2 ;; Copyright (C) 2005-2021 Free Software Foundation, Inc.
4 ;; This file is part of GCC.
6 ;; GCC is free software; you can redistribute it and/or modify
7 ;; it under the terms of the GNU General Public License as published by
8 ;; the Free Software Foundation; either version 3, or (at your option)
11 ;; GCC is distributed in the hope that it will be useful,
12 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
13 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 ;; GNU General Public License for more details.
16 ;; You should have received a copy of the GNU General Public License
17 ;; along with GCC; see the file COPYING3. If not see
18 ;; <http://www.gnu.org/licenses/>.
20 ;; Return 1 for anything except PARALLEL.
21 (define_predicate "any_operand"
22 (match_code "const_int,const_double,const_wide_int,const,symbol_ref,label_ref,subreg,reg,mem"))
24 ;; Return 1 for any PARALLEL.
25 (define_predicate "any_parallel_operand"
26 (match_code "parallel"))
28 ;; Return 1 if op is COUNT register.
29 (define_predicate "count_register_operand"
30 (and (match_code "reg")
31 (match_test "REGNO (op) == CTR_REGNO
32 || REGNO (op) > LAST_VIRTUAL_REGISTER")))
34 ;; Return 1 if op is a SUBREG that is used to look at a SFmode value as
35 ;; and integer or vice versa.
37 ;; In the normal case where SFmode is in a floating point/vector register, it
38 ;; is stored as a DFmode and has a different format. If we don't transform the
39 ;; value, things that use logical operations on the values will get the wrong
42 ;; If we don't have 64-bit and direct move, this conversion will be done by
43 ;; store and load, instead of by fiddling with the bits within the register.
44 (define_predicate "sf_subreg_operand"
47 rtx inner_reg = SUBREG_REG (op);
48 machine_mode inner_mode = GET_MODE (inner_reg);
50 if (TARGET_ALLOW_SF_SUBREG || !REG_P (inner_reg))
53 if ((mode == SFmode && GET_MODE_CLASS (inner_mode) == MODE_INT)
54 || (GET_MODE_CLASS (mode) == MODE_INT && inner_mode == SFmode))
56 if (INT_REGNO_P (REGNO (inner_reg)))
64 ;; Return 1 if op is an Altivec register.
65 (define_predicate "altivec_register_operand"
66 (match_operand 0 "register_operand")
70 if (TARGET_NO_SF_SUBREG && sf_subreg_operand (op, mode))
79 if (!HARD_REGISTER_P (op))
82 return ALTIVEC_REGNO_P (REGNO (op));
85 ;; Return 1 if op is a VSX register.
86 (define_predicate "vsx_register_operand"
87 (match_operand 0 "register_operand")
91 if (TARGET_NO_SF_SUBREG && sf_subreg_operand (op, mode))
100 if (!HARD_REGISTER_P (op))
103 return VSX_REGNO_P (REGNO (op));
106 ;; Like vsx_register_operand, but allow SF SUBREGS
107 (define_predicate "vsx_reg_sfsubreg_ok"
108 (match_operand 0 "register_operand")
111 op = SUBREG_REG (op);
116 if (!HARD_REGISTER_P (op))
119 return VSX_REGNO_P (REGNO (op));
122 ;; Return 1 if op is a vector register that operates on floating point vectors
123 ;; (either altivec or VSX).
124 (define_predicate "vfloat_operand"
125 (match_operand 0 "register_operand")
129 if (TARGET_NO_SF_SUBREG && sf_subreg_operand (op, mode))
132 op = SUBREG_REG (op);
138 if (!HARD_REGISTER_P (op))
141 return VFLOAT_REGNO_P (REGNO (op));
144 ;; Return 1 if op is a vector register that operates on integer vectors
145 ;; (only altivec, VSX doesn't support integer vectors)
146 (define_predicate "vint_operand"
147 (match_operand 0 "register_operand")
151 if (TARGET_NO_SF_SUBREG && sf_subreg_operand (op, mode))
154 op = SUBREG_REG (op);
160 if (!HARD_REGISTER_P (op))
163 return VINT_REGNO_P (REGNO (op));
166 ;; Return 1 if op is a vector register to do logical operations on (and, or,
168 (define_predicate "vlogical_operand"
169 (match_operand 0 "register_operand")
173 if (TARGET_NO_SF_SUBREG && sf_subreg_operand (op, mode))
176 op = SUBREG_REG (op);
183 if (!HARD_REGISTER_P (op))
186 return VLOGICAL_REGNO_P (REGNO (op));
189 ;; Return 1 if op is the carry register.
190 (define_predicate "ca_operand"
191 (match_operand 0 "register_operand")
194 op = SUBREG_REG (op);
199 return CA_REGNO_P (REGNO (op));
202 ;; Return 1 if operand is constant zero (scalars and vectors).
203 (define_predicate "zero_constant"
204 (and (match_code "const_int,const_double,const_wide_int,const_vector")
205 (match_test "op == CONST0_RTX (mode)")))
207 ;; Return 1 if operand is constant -1 (scalars and vectors).
208 (define_predicate "all_ones_constant"
209 (and (match_code "const_int,const_double,const_wide_int,const_vector")
210 (match_test "op == CONSTM1_RTX (mode) && !FLOAT_MODE_P (mode)")))
212 ;; Return 1 if op is a signed 5-bit constant integer.
213 (define_predicate "s5bit_cint_operand"
214 (and (match_code "const_int")
215 (match_test "INTVAL (op) >= -16 && INTVAL (op) <= 15")))
217 ;; Return 1 if op is an unsigned 1-bit constant integer.
218 (define_predicate "u1bit_cint_operand"
219 (and (match_code "const_int")
220 (match_test "INTVAL (op) >= 0 && INTVAL (op) <= 1")))
222 ;; Return 1 if op is a unsigned 3-bit constant integer.
223 (define_predicate "u3bit_cint_operand"
224 (and (match_code "const_int")
225 (match_test "INTVAL (op) >= 0 && INTVAL (op) <= 7")))
227 ;; Return 1 if op is a unsigned 5-bit constant integer.
228 (define_predicate "u5bit_cint_operand"
229 (and (match_code "const_int")
230 (match_test "INTVAL (op) >= 0 && INTVAL (op) <= 31")))
232 ;; Return 1 if op is a unsigned 6-bit constant integer.
233 (define_predicate "u6bit_cint_operand"
234 (and (match_code "const_int")
235 (match_test "INTVAL (op) >= 0 && INTVAL (op) <= 63")))
237 ;; Return 1 if op is an unsigned 7-bit constant integer.
238 (define_predicate "u7bit_cint_operand"
239 (and (match_code "const_int")
240 (match_test "IN_RANGE (INTVAL (op), 0, 127)")))
242 ;; Return 1 if op is a unsigned 8-bit constant integer.
243 (define_predicate "u8bit_cint_operand"
244 (and (match_code "const_int")
245 (match_test "IN_RANGE (INTVAL (op), 0, 255)")))
247 ;; Return 1 if op is a signed 8-bit constant integer.
248 ;; Integer multiplication complete more quickly
249 (define_predicate "s8bit_cint_operand"
250 (and (match_code "const_int")
251 (match_test "INTVAL (op) >= -128 && INTVAL (op) <= 127")))
253 ;; Return 1 if op is a unsigned 10-bit constant integer.
254 (define_predicate "u10bit_cint_operand"
255 (and (match_code "const_int")
256 (match_test "INTVAL (op) >= 0 && INTVAL (op) <= 1023")))
258 ;; Return 1 if op is a constant integer that can fit in a D field.
259 (define_predicate "short_cint_operand"
260 (and (match_code "const_int")
261 (match_test "satisfies_constraint_I (op)")))
263 ;; Return 1 if op is a constant integer that can fit in an unsigned D field.
264 (define_predicate "u_short_cint_operand"
265 (and (match_code "const_int")
266 (match_test "satisfies_constraint_K (op)")))
268 ;; Return 1 if op is a constant integer that is a signed 16-bit constant
269 ;; shifted left 16 bits
270 (define_predicate "upper16_cint_operand"
271 (and (match_code "const_int")
272 (match_test "satisfies_constraint_L (op)")))
274 ;; Return 1 if op is a constant integer that cannot fit in a signed D field.
275 (define_predicate "non_short_cint_operand"
276 (and (match_code "const_int")
277 (match_test "(unsigned HOST_WIDE_INT)
278 (INTVAL (op) + 0x8000) >= 0x10000")))
280 ;; Return 1 if op is a 32-bit constant signed integer
281 (define_predicate "s32bit_cint_operand"
282 (and (match_code "const_int")
283 (match_test "(0x80000000 + UINTVAL (op)) >> 32 == 0")))
285 ;; Return 1 if op is a constant 32-bit unsigned
286 (define_predicate "c32bit_cint_operand"
287 (and (match_code "const_int")
288 (match_test "((UINTVAL (op) >> 32) == 0)")))
290 ;; Return 1 if op is a positive constant integer that is an exact power of 2.
291 (define_predicate "exact_log2_cint_operand"
292 (and (match_code "const_int")
293 (match_test "INTVAL (op) > 0 && exact_log2 (INTVAL (op)) >= 0")))
295 ;; Match op = 0 or op = 1.
296 (define_predicate "const_0_to_1_operand"
297 (and (match_code "const_int")
298 (match_test "IN_RANGE (INTVAL (op), 0, 1)")))
301 (define_predicate "const_0_to_3_operand"
302 (and (match_code "const_int")
303 (match_test "IN_RANGE (INTVAL (op), 0, 3)")))
305 ;; Match op = 2 or op = 3.
306 (define_predicate "const_2_to_3_operand"
307 (and (match_code "const_int")
308 (match_test "IN_RANGE (INTVAL (op), 2, 3)")))
311 (define_predicate "const_0_to_7_operand"
312 (and (match_code "const_int")
313 (match_test "IN_RANGE (INTVAL (op), 0, 7)")))
316 (define_predicate "const_0_to_12_operand"
317 (and (match_code "const_int")
318 (match_test "IN_RANGE (INTVAL (op), 0, 12)")))
321 (define_predicate "const_0_to_15_operand"
322 (and (match_code "const_int")
323 (match_test "IN_RANGE (INTVAL (op), 0, 15)")))
325 ;; Return 1 if op is a 34-bit constant integer.
326 (define_predicate "cint34_operand"
327 (match_code "const_int")
329 if (!TARGET_PREFIXED)
332 return SIGNED_INTEGER_34BIT_P (INTVAL (op));
335 ;; Return 1 if op is a register that is not special.
336 ;; Disallow (SUBREG:SF (REG:SI)) and (SUBREG:SI (REG:SF)) on VSX systems where
337 ;; you need to be careful in moving a SFmode to SImode and vice versa due to
338 ;; the fact that SFmode is represented as DFmode in the VSX registers.
339 (define_predicate "gpc_reg_operand"
340 (match_operand 0 "register_operand")
344 if (TARGET_NO_SF_SUBREG && sf_subreg_operand (op, mode))
347 op = SUBREG_REG (op);
353 if (!HARD_REGISTER_P (op))
356 if (TARGET_ALTIVEC && ALTIVEC_REGNO_P (REGNO (op)))
359 if (TARGET_VSX && VSX_REGNO_P (REGNO (op)))
362 return INT_REGNO_P (REGNO (op)) || FP_REGNO_P (REGNO (op));
365 ;; Return 1 if op is a general purpose register. Unlike gpc_reg_operand, don't
366 ;; allow floating point or vector registers. Since vector registers are not
367 ;; allowed, we don't have to reject SFmode/SImode subregs.
368 (define_predicate "int_reg_operand"
369 (match_operand 0 "register_operand")
373 if (TARGET_NO_SF_SUBREG && sf_subreg_operand (op, mode))
376 op = SUBREG_REG (op);
382 if (!HARD_REGISTER_P (op))
385 return INT_REGNO_P (REGNO (op));
388 ;; Like int_reg_operand, but don't return true for pseudo registers
389 ;; We don't have to check for SF SUBREGS because pseudo registers
390 ;; are not allowed, and SF SUBREGs are ok within GPR registers.
391 (define_predicate "int_reg_operand_not_pseudo"
392 (match_operand 0 "register_operand")
395 op = SUBREG_REG (op);
400 if (!HARD_REGISTER_P (op))
403 return INT_REGNO_P (REGNO (op));
406 ;; Like int_reg_operand, but only return true for base registers
407 (define_predicate "base_reg_operand"
408 (match_operand 0 "int_reg_operand")
411 op = SUBREG_REG (op);
416 return (REGNO (op) != FIRST_GPR_REGNO);
420 ;; Return true if this is a traditional floating point register
421 (define_predicate "fpr_reg_operand"
422 (match_code "reg,subreg")
427 op = SUBREG_REG (op);
433 if (!HARD_REGISTER_NUM_P (r))
436 return FP_REGNO_P (r);
439 ;; Return 1 if op is a general purpose register that is an even register
440 ;; which suitable for a load/store quad operation
441 ;; Subregs are not allowed here because when they are combine can
442 ;; create (subreg:PTI (reg:TI pseudo)) which will cause reload to
443 ;; think the innermost reg needs reloading, in TImode instead of
444 ;; PTImode. So reload will choose a reg in TImode which has no
445 ;; requirement that the reg be even.
446 (define_predicate "quad_int_reg_operand"
451 if (!TARGET_QUAD_MEMORY && !TARGET_QUAD_MEMORY_ATOMIC)
455 if (!HARD_REGISTER_NUM_P (r))
458 return (INT_REGNO_P (r) && ((r & 1) == 0));
461 ;; Return 1 if op is a register that is a condition register field.
462 (define_predicate "cc_reg_operand"
463 (match_operand 0 "register_operand")
466 op = SUBREG_REG (op);
471 if (REGNO (op) > LAST_VIRTUAL_REGISTER)
474 return CR_REGNO_P (REGNO (op));
477 ;; Return 1 if op is a register that is a condition register field not cr0.
478 (define_predicate "cc_reg_not_cr0_operand"
479 (match_operand 0 "register_operand")
482 op = SUBREG_REG (op);
487 if (REGNO (op) > LAST_VIRTUAL_REGISTER)
490 return CR_REGNO_NOT_CR0_P (REGNO (op));
493 ;; Return 1 if op is a constant integer valid for D field
494 ;; or non-special register register.
495 (define_predicate "reg_or_short_operand"
496 (if_then_else (match_code "const_int")
497 (match_operand 0 "short_cint_operand")
498 (match_operand 0 "gpc_reg_operand")))
500 ;; Return 1 if op is a constant integer valid for DS field
501 ;; or non-special register.
502 (define_predicate "reg_or_aligned_short_operand"
503 (if_then_else (match_code "const_int")
504 (and (match_operand 0 "short_cint_operand")
505 (match_test "!(INTVAL (op) & 3)"))
506 (match_operand 0 "gpc_reg_operand")))
508 ;; Return 1 if op is a constant integer whose high-order 16 bits are zero
509 ;; or non-special register.
510 (define_predicate "reg_or_u_short_operand"
511 (if_then_else (match_code "const_int")
512 (match_operand 0 "u_short_cint_operand")
513 (match_operand 0 "gpc_reg_operand")))
515 ;; Return 1 if op is any constant integer or a non-special register.
516 (define_predicate "reg_or_cint_operand"
517 (ior (match_code "const_int")
518 (match_operand 0 "gpc_reg_operand")))
520 ;; Return 1 if op is constant zero or a non-special register.
521 (define_predicate "reg_or_zero_operand"
522 (ior (match_operand 0 "zero_constant")
523 (match_operand 0 "gpc_reg_operand")))
525 ;; Return 1 if op is a constant integer valid for addition with addis, addi.
526 (define_predicate "add_cint_operand"
527 (and (match_code "const_int")
528 (match_test "((unsigned HOST_WIDE_INT) INTVAL (op)
529 + (mode == SImode ? 0x80000000 : 0x80008000))
530 < (unsigned HOST_WIDE_INT) 0x100000000ll")))
532 ;; Return 1 if op is a constant integer valid for addition
533 ;; or non-special register.
534 (define_predicate "reg_or_add_cint_operand"
535 (if_then_else (match_code "const_int")
536 (match_operand 0 "add_cint_operand")
537 (match_operand 0 "gpc_reg_operand")))
539 ;; Return 1 if op is a constant integer valid for subtraction
540 ;; or non-special register.
541 (define_predicate "reg_or_sub_cint_operand"
542 (if_then_else (match_code "const_int")
543 (match_test "(unsigned HOST_WIDE_INT)
544 (- UINTVAL (op) + (mode == SImode ? 0x80000000 : 0x80008000))
545 < (unsigned HOST_WIDE_INT) 0x100000000ll")
546 (match_operand 0 "gpc_reg_operand")))
548 ;; Return 1 if op is any 32-bit unsigned constant integer
549 ;; or non-special register.
550 (define_predicate "reg_or_logical_cint_operand"
551 (if_then_else (match_code "const_int")
552 (match_test "(GET_MODE_BITSIZE (mode) > HOST_BITS_PER_WIDE_INT
554 || ((INTVAL (op) & GET_MODE_MASK (mode)
555 & (~ (unsigned HOST_WIDE_INT) 0xffffffff)) == 0)")
556 (match_operand 0 "gpc_reg_operand")))
558 ;; Like reg_or_logical_cint_operand, but allow vsx registers
559 (define_predicate "vsx_reg_or_cint_operand"
560 (ior (match_operand 0 "vsx_register_operand")
561 (match_operand 0 "reg_or_logical_cint_operand")))
563 ;; Return 1 if operand is a CONST_DOUBLE that can be set in a register
564 ;; with no more than one instruction per word.
565 (define_predicate "easy_fp_constant"
566 (match_code "const_double")
568 gcc_assert (GET_MODE (op) == mode && SCALAR_FLOAT_MODE_P (mode));
570 /* Consider all constants with -msoft-float to be easy when regs are
571 32-bit and thus can be loaded with a maximum of 2 insns. For
572 64-bit avoid long dependent insn sequences. */
573 if (TARGET_SOFT_FLOAT)
575 if (!TARGET_POWERPC64)
578 int size = GET_MODE_SIZE (mode);
582 int load_from_mem_insns = 2;
584 load_from_mem_insns++;
585 if (TARGET_CMODEL != CMODEL_SMALL)
586 load_from_mem_insns++;
587 if (num_insns_constant (op, mode) <= load_from_mem_insns)
591 /* 0.0D is not all zero bits. */
592 if (DECIMAL_FLOAT_MODE_P (mode))
595 /* The constant 0.0 is easy under VSX. */
596 if (TARGET_VSX && op == CONST0_RTX (mode))
599 /* Otherwise consider floating point constants hard, so that the
600 constant gets pushed to memory during the early RTL phases. This
601 has the advantage that double precision constants that can be
602 represented in single precision without a loss of precision will
603 use single precision loads. */
607 ;; Return 1 if the operand is a constant that can loaded with a XXSPLTIB
608 ;; instruction and then a VUPKHSB, VECSB2W or VECSB2D instruction.
610 (define_predicate "xxspltib_constant_split"
611 (match_code "const_vector,vec_duplicate,const_int")
616 if (!xxspltib_constant_p (op, mode, &num_insns, &value))
619 return num_insns > 1;
623 ;; Return 1 if the operand is constant that can loaded directly with a XXSPLTIB
626 (define_predicate "xxspltib_constant_nosplit"
627 (match_code "const_vector,vec_duplicate,const_int")
632 if (!xxspltib_constant_p (op, mode, &num_insns, &value))
635 return num_insns == 1;
638 ;; Return 1 if the operand is a CONST_VECTOR and can be loaded into a
639 ;; vector register without using memory.
640 (define_predicate "easy_vector_constant"
641 (match_code "const_vector")
643 if (VECTOR_MEM_ALTIVEC_OR_VSX_P (mode))
648 if (zero_constant (op, mode) || all_ones_constant (op, mode))
652 && xxspltib_constant_p (op, mode, &num_insns, &value))
655 return easy_altivec_constant (op, mode);
661 ;; Same as easy_vector_constant but only for EASY_VECTOR_15_ADD_SELF.
662 (define_predicate "easy_vector_constant_add_self"
663 (and (match_code "const_vector")
664 (and (match_test "TARGET_ALTIVEC")
665 (match_test "easy_altivec_constant (op, mode)")))
669 if (mode == V2DImode || mode == V2DFmode)
671 elt = BYTES_BIG_ENDIAN ? GET_MODE_NUNITS (mode) - 1 : 0;
672 val = const_vector_elt_as_int (op, elt);
673 val = ((val & 0xff) ^ 0x80) - 0x80;
674 return EASY_VECTOR_15_ADD_SELF (val);
677 ;; Same as easy_vector_constant but only for EASY_VECTOR_MSB.
678 (define_predicate "easy_vector_constant_msb"
679 (and (match_code "const_vector")
680 (and (match_test "TARGET_ALTIVEC")
681 (match_test "easy_altivec_constant (op, mode)")))
685 if (mode == V2DImode || mode == V2DFmode)
687 elt = BYTES_BIG_ENDIAN ? GET_MODE_NUNITS (mode) - 1 : 0;
688 val = const_vector_elt_as_int (op, elt);
689 return EASY_VECTOR_MSB (val, GET_MODE_INNER (mode));
692 ;; Return true if this is an easy altivec constant that we form
694 (define_predicate "easy_vector_constant_vsldoi"
695 (and (match_code "const_vector")
696 (and (match_test "TARGET_ALTIVEC")
697 (and (match_test "easy_altivec_constant (op, mode)")
698 (match_test "vspltis_shifted (op) != 0")))))
700 ;; Return 1 if operand is a vector int register or is either a vector constant
701 ;; of all 0 bits of a vector constant of all 1 bits.
702 (define_predicate "vector_int_reg_or_same_bit"
703 (match_code "reg,subreg,const_vector")
705 if (GET_MODE_CLASS (mode) != MODE_VECTOR_INT)
708 else if (REG_P (op) || SUBREG_P (op))
709 return vint_operand (op, mode);
712 return op == CONST0_RTX (mode) || op == CONSTM1_RTX (mode);
715 ;; Return 1 if operand is 0.0.
716 (define_predicate "zero_fp_constant"
717 (and (match_code "const_double")
718 (match_test "SCALAR_FLOAT_MODE_P (mode)
719 && op == CONST0_RTX (mode)")))
721 ;; Return 1 if the operand is in volatile memory. Note that during the
722 ;; RTL generation phase, memory_operand does not return TRUE for volatile
723 ;; memory references. So this function allows us to recognize volatile
724 ;; references where it's safe.
725 (define_predicate "volatile_mem_operand"
726 (and (match_code "mem")
727 (match_test "MEM_VOLATILE_P (op)")
728 (if_then_else (match_test "reload_completed")
729 (match_operand 0 "memory_operand")
730 (match_test "memory_address_p (mode, XEXP (op, 0))"))))
732 ;; Return 1 if the operand is a volatile or non-volatile memory operand.
733 (define_predicate "any_memory_operand"
734 (ior (match_operand 0 "memory_operand")
735 (match_operand 0 "volatile_mem_operand")))
737 ;; Return 1 if the operand is an offsettable memory operand.
738 (define_predicate "offsettable_mem_operand"
739 (and (match_operand 0 "any_memory_operand")
740 (match_test "offsettable_nonstrict_memref_p (op)")))
742 ;; Return 1 if the operand is a simple offsettable memory operand
743 ;; that does not include pre-increment, post-increment, etc.
744 (define_predicate "simple_offsettable_mem_operand"
745 (match_operand 0 "offsettable_mem_operand")
747 rtx addr = XEXP (op, 0);
749 if (GET_CODE (addr) != PLUS && GET_CODE (addr) != LO_SUM)
752 if (!CONSTANT_P (XEXP (addr, 1)))
755 return base_reg_operand (XEXP (addr, 0), Pmode);
758 ;; Return 1 if the operand is suitable for load/store quad memory.
759 ;; This predicate only checks for non-atomic loads/stores (not lqarx/stqcx).
760 (define_predicate "quad_memory_operand"
763 if (!TARGET_QUAD_MEMORY && !TARGET_SYNC_TI)
766 if (GET_MODE_SIZE (mode) != 16 || !MEM_P (op) || MEM_ALIGN (op) < 128)
769 return quad_address_p (XEXP (op, 0), mode, false);
772 ;; Return 1 if the operand is suitable for load/store to vector registers with
773 ;; d-form addressing (register+offset), which was added in ISA 3.0.
774 ;; Unlike quad_memory_operand, we do not have to check for alignment.
775 (define_predicate "vsx_quad_dform_memory_operand"
778 if (!TARGET_P9_VECTOR || !MEM_P (op) || GET_MODE_SIZE (mode) != 16)
781 return quad_address_p (XEXP (op, 0), mode, false);
784 ;; Return 1 if the operand is an indexed or indirect memory operand.
785 (define_predicate "indexed_or_indirect_operand"
789 if (VECTOR_MEM_ALTIVEC_P (mode)
790 && GET_CODE (op) == AND
791 && CONST_INT_P (XEXP (op, 1))
792 && INTVAL (XEXP (op, 1)) == -16)
795 return indexed_or_indirect_address (op, mode);
798 ;; Like indexed_or_indirect_operand, but also allow a GPR register if direct
799 ;; moves are supported.
800 (define_predicate "reg_or_indexed_operand"
801 (match_code "mem,reg,subreg")
804 return indexed_or_indirect_operand (op, mode);
805 else if (TARGET_DIRECT_MOVE)
806 return register_operand (op, mode);
811 ;; Return 1 if the operand is an indexed or indirect memory operand with an
812 ;; AND -16 in it, used to recognize when we need to switch to Altivec loads
813 ;; to realign loops instead of VSX (altivec silently ignores the bottom bits,
814 ;; while VSX uses the full address and traps)
815 (define_predicate "altivec_indexed_or_indirect_operand"
819 if (VECTOR_MEM_ALTIVEC_OR_VSX_P (mode)
820 && GET_CODE (op) == AND
821 && CONST_INT_P (XEXP (op, 1))
822 && INTVAL (XEXP (op, 1)) == -16)
823 return indexed_or_indirect_address (XEXP (op, 0), mode);
828 ;; Return 1 if the operand is an indexed or indirect address.
829 (define_special_predicate "indexed_or_indirect_address"
830 (and (match_test "REG_P (op)
831 || (GET_CODE (op) == PLUS
832 /* Omit testing REG_P (XEXP (op, 0)). */
833 && REG_P (XEXP (op, 1)))")
834 (match_operand 0 "address_operand")))
836 ;; Return 1 if the operand is an index-form address.
837 (define_special_predicate "indexed_address"
838 (match_test "(GET_CODE (op) == PLUS
839 && REG_P (XEXP (op, 0))
840 && REG_P (XEXP (op, 1)))"))
842 ;; Return 1 if the operand is a MEM with an update-form address. This may
843 ;; also include update-indexed form.
844 (define_special_predicate "update_address_mem"
845 (match_test "(MEM_P (op)
846 && (GET_CODE (XEXP (op, 0)) == PRE_INC
847 || GET_CODE (XEXP (op, 0)) == PRE_DEC
848 || GET_CODE (XEXP (op, 0)) == PRE_MODIFY))"))
850 ;; Return 1 if the operand is a MEM with an indexed-form address.
851 (define_special_predicate "indexed_address_mem"
852 (match_test "(MEM_P (op)
853 && (indexed_address (XEXP (op, 0), mode)
854 || (GET_CODE (XEXP (op, 0)) == PRE_MODIFY
855 && indexed_address (XEXP (XEXP (op, 0), 1), mode))))"))
857 ;; Return 1 if the operand is either a non-special register or can be used
858 ;; as the operand of a `mode' add insn.
859 (define_predicate "add_operand"
860 (if_then_else (match_code "const_int")
861 (match_test "satisfies_constraint_I (op)
862 || satisfies_constraint_L (op)
863 || satisfies_constraint_eI (op)")
864 (match_operand 0 "gpc_reg_operand")))
866 ;; Return 1 if the operand is either a non-special register, or 0, or -1.
867 (define_predicate "adde_operand"
868 (if_then_else (match_code "const_int")
869 (match_test "INTVAL (op) == 0 || INTVAL (op) == -1")
870 (match_operand 0 "gpc_reg_operand")))
872 ;; Return 1 if OP is a constant but not a valid add_operand.
873 (define_predicate "non_add_cint_operand"
874 (and (match_code "const_int")
875 (not (match_operand 0 "add_operand"))))
877 ;; Return 1 if the operand is a constant that can be used as the operand
878 ;; of an AND, OR or XOR.
879 (define_predicate "logical_const_operand"
880 (match_code "const_int")
884 opl = INTVAL (op) & GET_MODE_MASK (mode);
886 return ((opl & ~ (unsigned HOST_WIDE_INT) 0xffff) == 0
887 || (opl & ~ (unsigned HOST_WIDE_INT) 0xffff0000) == 0);
890 ;; Return 1 if the operand is a non-special register or a constant that
891 ;; can be used as the operand of an AND, OR or XOR.
892 (define_predicate "logical_operand"
893 (ior (match_operand 0 "gpc_reg_operand")
894 (match_operand 0 "logical_const_operand")))
896 ;; Return 1 if op is a constant that is not a logical operand, but could
897 ;; be split into one.
898 (define_predicate "non_logical_cint_operand"
899 (and (match_code "const_int,const_wide_int")
900 (and (not (match_operand 0 "logical_operand"))
901 (match_operand 0 "reg_or_logical_cint_operand"))))
903 ;; Return 1 if the operand is either a non-special register or a
904 ;; constant that can be used as the operand of a logical AND.
905 (define_predicate "and_operand"
906 (ior (and (match_code "const_int")
907 (match_test "rs6000_is_valid_and_mask (op, mode)"))
908 (if_then_else (match_test "fixed_regs[CR0_REGNO]")
909 (match_operand 0 "gpc_reg_operand")
910 (match_operand 0 "logical_operand"))))
912 ;; Return 1 if the operand is either a logical operand or a short cint operand.
913 (define_predicate "scc_eq_operand"
914 (ior (match_operand 0 "logical_operand")
915 (match_operand 0 "short_cint_operand")))
917 ;; Return 1 if the operand is a general non-special register or memory operand.
918 (define_predicate "reg_or_mem_operand"
919 (ior (match_operand 0 "gpc_reg_operand")
920 (match_operand 0 "any_memory_operand")
921 (and (match_code "mem")
922 (match_test "macho_lo_sum_memory_operand (op, mode)"))))
924 ;; Return 1 if the operand is CONST_DOUBLE 0, register or memory operand.
925 (define_predicate "zero_reg_mem_operand"
926 (ior (and (match_test "TARGET_VSX")
927 (match_operand 0 "zero_fp_constant"))
928 (match_operand 0 "reg_or_mem_operand")))
930 ;; Return 1 if the operand is a CONST_INT and it is the element for 64-bit
931 ;; data types inside of a vector that scalar instructions operate on
932 (define_predicate "vsx_scalar_64bit"
933 (match_code "const_int")
935 return (INTVAL (op) == VECTOR_ELEMENT_SCALAR_64BIT);
938 ;; Return 1 if the operand is a general register or memory operand without
939 ;; pre_inc or pre_dec or pre_modify, which produces invalid form of PowerPC
941 (define_predicate "lwa_operand"
942 (match_code "reg,subreg,mem")
944 rtx inner, addr, offset;
947 if (reload_completed && SUBREG_P (inner))
948 inner = SUBREG_REG (inner);
950 if (gpc_reg_operand (inner, mode))
952 if (!any_memory_operand (inner, mode))
955 addr = XEXP (inner, 0);
957 /* The LWA instruction uses the DS-form instruction format which requires
958 that the bottom two bits of the offset must be 0. The prefixed PLWA does
959 not have this restriction. While the actual load from memory is 32-bits,
960 we pass in DImode here to test for using a DS instruction. */
961 if (address_is_prefixed (addr, DImode, NON_PREFIXED_DS))
964 if (GET_CODE (addr) == PRE_INC
965 || GET_CODE (addr) == PRE_DEC
966 || (GET_CODE (addr) == PRE_MODIFY
967 && !legitimate_indexed_address_p (XEXP (addr, 1), 0)))
969 if (GET_CODE (addr) == LO_SUM
970 && REG_P (XEXP (addr, 0))
971 && GET_CODE (XEXP (addr, 1)) == CONST)
972 addr = XEXP (XEXP (addr, 1), 0);
973 if (GET_CODE (addr) != PLUS)
975 offset = XEXP (addr, 1);
976 if (!CONST_INT_P (offset))
978 return INTVAL (offset) % 4 == 0;
981 ;; Return 1 if the operand, used inside a MEM, is a SYMBOL_REF.
982 (define_predicate "symbol_ref_operand"
983 (and (match_code "symbol_ref")
984 (match_test "(mode == VOIDmode || GET_MODE (op) == mode)
985 && (DEFAULT_ABI != ABI_AIX || SYMBOL_REF_FUNCTION_P (op))")))
987 ;; Return 1 if op is an operand that can be loaded via the GOT.
988 ;; or non-special register register field no cr0
989 (define_predicate "got_operand"
990 (match_code "symbol_ref,const,label_ref"))
992 ;; Return 1 if op is a simple reference that can be loaded via the GOT,
993 ;; excluding labels involving addition.
994 (define_predicate "got_no_const_operand"
995 (match_code "symbol_ref,label_ref"))
997 ;; Return 1 if op is a SYMBOL_REF for a TLS symbol.
998 (define_predicate "rs6000_tls_symbol_ref"
999 (and (match_code "symbol_ref")
1000 (match_test "RS6000_SYMBOL_REF_TLS_P (op)")))
1002 ;; Return 1 for the CONST_INT or UNSPEC second CALL operand.
1003 ;; Prevents unwanted substitution of the unspec got_reg arg.
1004 (define_predicate "unspec_tls"
1005 (match_code "const_int,unspec")
1007 if (CONST_INT_P (op))
1009 if (XINT (op, 1) == UNSPEC_TLSGD)
1010 return REG_P (XVECEXP (op, 0, 1)) || XVECEXP (op, 0, 1) == const0_rtx;
1011 if (XINT (op, 1) == UNSPEC_TLSLD)
1012 return REG_P (XVECEXP (op, 0, 0)) || XVECEXP (op, 0, 0) == const0_rtx;
1016 ;; Return 1 if the operand, used inside a MEM, is a valid first argument
1017 ;; to CALL. This is a SYMBOL_REF, a pseudo-register, LR or CTR.
1018 (define_predicate "call_operand"
1019 (if_then_else (match_code "reg")
1020 (match_test "REGNO (op) == LR_REGNO
1021 || REGNO (op) == CTR_REGNO
1022 || !HARD_REGISTER_P (op)")
1023 (match_code "symbol_ref")))
1025 ;; Return 1 if the operand, used inside a MEM, is a valid first argument
1026 ;; to an indirect CALL. This is LR, CTR, or a PLTSEQ unspec using CTR.
1027 (define_predicate "indirect_call_operand"
1028 (match_code "reg,unspec")
1031 return (REGNO (op) == LR_REGNO
1032 || REGNO (op) == CTR_REGNO);
1033 if (GET_CODE (op) == UNSPEC)
1035 if (XINT (op, 1) != UNSPEC_PLTSEQ)
1037 op = XVECEXP (op, 0, 0);
1038 return REG_P (op) && REGNO (op) == CTR_REGNO;
1043 ;; Return 1 if the operand is a SYMBOL_REF for a function known to be in
1045 (define_predicate "current_file_function_operand"
1046 (and (match_code "symbol_ref")
1047 (match_test "(DEFAULT_ABI != ABI_AIX || SYMBOL_REF_FUNCTION_P (op))
1048 && (SYMBOL_REF_LOCAL_P (op)
1049 || (op == XEXP (DECL_RTL (current_function_decl), 0)
1050 && !decl_replaceable_p (current_function_decl)))
1051 && !((DEFAULT_ABI == ABI_AIX
1052 || DEFAULT_ABI == ABI_ELFv2)
1053 && (SYMBOL_REF_EXTERNAL_P (op)
1054 || SYMBOL_REF_WEAK (op)))
1055 && !(DEFAULT_ABI == ABI_ELFv2
1056 && SYMBOL_REF_DECL (op) != NULL
1057 && TREE_CODE (SYMBOL_REF_DECL (op)) == FUNCTION_DECL
1058 && (rs6000_fndecl_pcrel_p (SYMBOL_REF_DECL (op))
1059 != rs6000_pcrel_p ()))")))
1061 ;; Return 1 if this operand is a valid input for a move insn.
1062 (define_predicate "input_operand"
1063 (match_code "symbol_ref,const,reg,subreg,mem,
1064 const_double,const_wide_int,const_vector,const_int")
1066 /* Memory is always valid. */
1067 if (any_memory_operand (op, mode))
1070 /* For floating-point, easy constants are valid. */
1071 if (SCALAR_FLOAT_MODE_P (mode)
1072 && easy_fp_constant (op, mode))
1075 /* Allow any integer constant. */
1076 if (SCALAR_INT_MODE_P (mode) && CONST_SCALAR_INT_P (op))
1079 /* Allow easy vector constants. */
1080 if (GET_CODE (op) == CONST_VECTOR
1081 && easy_vector_constant (op, mode))
1084 /* For floating-point or multi-word mode, the only remaining valid type
1086 if (SCALAR_FLOAT_MODE_P (mode)
1087 || GET_MODE_SIZE (mode) > UNITS_PER_WORD)
1088 return register_operand (op, mode);
1090 /* We don't allow moving the carry bit around. */
1091 if (ca_operand (op, mode))
1094 /* The only cases left are integral modes one word or smaller (we
1095 do not get called for MODE_CC values). These can be in any
1097 if (register_operand (op, mode))
1100 /* V.4 allows SYMBOL_REFs and CONSTs that are in the small data region
1102 if (DEFAULT_ABI == ABI_V4
1103 && (SYMBOL_REF_P (op) || GET_CODE (op) == CONST)
1104 && small_data_operand (op, Pmode))
1110 ;; Return 1 if this operand is a valid input for a vsx_splat insn.
1111 (define_predicate "splat_input_operand"
1112 (match_code "reg,subreg,mem")
1118 else if (mode == DImode)
1120 else if (mode == SImode && TARGET_P9_VECTOR)
1122 else if (mode == SFmode && TARGET_P9_VECTOR)
1129 rtx addr = XEXP (op, 0);
1131 if (! volatile_ok && MEM_VOLATILE_P (op))
1134 if (lra_in_progress || reload_completed)
1135 return indexed_or_indirect_address (addr, vmode);
1137 return memory_address_addr_space_p (vmode, addr, MEM_ADDR_SPACE (op));
1139 return gpc_reg_operand (op, mode);
1142 ;; Return 1 if this operand is valid for a MMA assemble accumulator insn.
1143 (define_special_predicate "mma_assemble_input_operand"
1144 (match_test "(mode == V16QImode
1145 && (vsx_register_operand (op, mode) || MEM_P (op)))"))
1147 ;; Return 1 if this operand is valid for an MMA disassemble insn.
1148 (define_predicate "mma_disassemble_output_operand"
1149 (match_code "reg,subreg,mem")
1152 op = SUBREG_REG (op);
1156 return vsx_register_operand (op, mode);
1159 ;; Return true if operand is an operator used in rotate-and-mask instructions.
1160 (define_predicate "rotate_mask_operator"
1161 (match_code "rotate,ashift,lshiftrt"))
1163 ;; Return true if operand is boolean operator.
1164 (define_predicate "boolean_operator"
1165 (match_code "and,ior,xor"))
1167 ;; Return true if operand is OR-form of boolean operator.
1168 (define_predicate "boolean_or_operator"
1169 (match_code "ior,xor"))
1171 ;; Return true if operand is an equality operator.
1172 (define_special_predicate "equality_operator"
1173 (match_code "eq,ne"))
1175 ;; Return 1 if OP is a comparison operation that is valid for a branch
1176 ;; instruction. We check the opcode against the mode of the CC value.
1177 ;; validate_condition_mode is an assertion.
1178 (define_predicate "branch_comparison_operator"
1179 (and (match_operand 0 "comparison_operator")
1180 (match_test "GET_MODE_CLASS (GET_MODE (XEXP (op, 0))) == MODE_CC")
1181 (if_then_else (match_test "GET_MODE (XEXP (op, 0)) == CCFPmode
1182 && !flag_finite_math_only")
1183 (match_code "lt,gt,eq,unordered,unge,unle,ne,ordered")
1184 (match_code "lt,ltu,le,leu,gt,gtu,ge,geu,eq,ne"))
1185 (match_test "validate_condition_mode (GET_CODE (op),
1186 GET_MODE (XEXP (op, 0))),
1189 ;; Return 1 if OP is a comparison that needs an extra instruction to do (a
1190 ;; crlogical or an extra branch).
1191 (define_predicate "extra_insn_branch_comparison_operator"
1192 (and (match_operand 0 "comparison_operator")
1193 (match_test "GET_MODE (XEXP (op, 0)) == CCFPmode")
1194 (match_code "ltgt,le,ge,unlt,ungt,uneq")
1195 (match_test "validate_condition_mode (GET_CODE (op),
1196 GET_MODE (XEXP (op, 0))),
1199 ;; Return 1 if OP is an unsigned comparison operator.
1200 (define_predicate "unsigned_comparison_operator"
1201 (match_code "ltu,gtu,leu,geu"))
1203 ;; Return 1 if OP is a signed comparison operator.
1204 (define_predicate "signed_comparison_operator"
1205 (match_code "lt,gt,le,ge"))
1207 ;; Return 1 if OP is a signed comparison or an equality operator.
1208 (define_predicate "signed_or_equality_comparison_operator"
1209 (ior (match_operand 0 "equality_operator")
1210 (match_operand 0 "signed_comparison_operator")))
1212 ;; Return 1 if OP is an unsigned comparison or an equality operator.
1213 (define_predicate "unsigned_or_equality_comparison_operator"
1214 (ior (match_operand 0 "equality_operator")
1215 (match_operand 0 "unsigned_comparison_operator")))
1217 ;; Return 1 if OP is a comparison operation that is valid for an SCC insn --
1218 ;; it must be a positive comparison.
1219 (define_predicate "scc_comparison_operator"
1220 (and (match_operand 0 "branch_comparison_operator")
1221 (match_code "eq,lt,gt,ltu,gtu,unordered")))
1223 ;; Return 1 if OP is a comparison operation whose inverse would be valid for
1225 (define_predicate "scc_rev_comparison_operator"
1226 (and (match_operand 0 "branch_comparison_operator")
1227 (match_code "ne,le,ge,leu,geu,ordered")))
1229 ;; Return 1 if OP is a comparison operator suitable for floating point
1230 ;; vector/scalar comparisons that generate a -1/0 mask.
1231 (define_predicate "fpmask_comparison_operator"
1232 (match_code "eq,gt,ge"))
1234 ;; Return 1 if OP is a comparison operator suitable for vector/scalar
1235 ;; comparisons that generate a 0/-1 mask (i.e. the inverse of
1236 ;; fpmask_comparison_operator).
1237 (define_predicate "invert_fpmask_comparison_operator"
1238 (match_code "ne,unlt,unle"))
1240 ;; Return 1 if OP is a comparison operation suitable for integer vector/scalar
1241 ;; comparisons that generate a -1/0 mask.
1242 (define_predicate "vecint_comparison_operator"
1243 (match_code "eq,gt,gtu"))
1245 ;; Return 1 if OP is a comparison operation that is valid for a branch
1246 ;; insn, which is true if the corresponding bit in the CC register is set.
1247 (define_predicate "branch_positive_comparison_operator"
1248 (and (match_operand 0 "branch_comparison_operator")
1249 (match_code "eq,lt,gt,ltu,gtu,unordered")))
1251 ;; Return 1 if OP is valid for a save_world call in prologue, known to be
1253 (define_predicate "save_world_operation"
1254 (match_code "parallel")
1259 int count = XVECLEN (op, 0);
1265 if (GET_CODE (XVECEXP (op, 0, index++)) != CLOBBER
1266 || GET_CODE (XVECEXP (op, 0, index++)) != USE)
1269 for (i=1; i <= 18; i++)
1271 elt = XVECEXP (op, 0, index++);
1272 if (GET_CODE (elt) != SET
1273 || !MEM_P (SET_DEST (elt))
1274 || !memory_operand (SET_DEST (elt), DFmode)
1275 || !REG_P (SET_SRC (elt))
1276 || GET_MODE (SET_SRC (elt)) != DFmode)
1280 for (i=1; i <= 12; i++)
1282 elt = XVECEXP (op, 0, index++);
1283 if (GET_CODE (elt) != SET
1284 || !MEM_P (SET_DEST (elt))
1285 || !REG_P (SET_SRC (elt))
1286 || GET_MODE (SET_SRC (elt)) != V4SImode)
1290 for (i=1; i <= 19; i++)
1292 elt = XVECEXP (op, 0, index++);
1293 if (GET_CODE (elt) != SET
1294 || !MEM_P (SET_DEST (elt))
1295 || !memory_operand (SET_DEST (elt), Pmode)
1296 || !REG_P (SET_SRC (elt))
1297 || GET_MODE (SET_SRC (elt)) != Pmode)
1301 elt = XVECEXP (op, 0, index++);
1302 if (GET_CODE (elt) != SET
1303 || !MEM_P (SET_DEST (elt))
1304 || !memory_operand (SET_DEST (elt), Pmode)
1305 || !REG_P (SET_SRC (elt))
1306 || REGNO (SET_SRC (elt)) != CR2_REGNO
1307 || GET_MODE (SET_SRC (elt)) != Pmode)
1310 if (GET_CODE (XVECEXP (op, 0, index++)) != SET
1311 || GET_CODE (XVECEXP (op, 0, index++)) != SET)
1316 ;; Return 1 if OP is valid for a restore_world call in epilogue, known to be
1318 (define_predicate "restore_world_operation"
1319 (match_code "parallel")
1324 int count = XVECLEN (op, 0);
1330 if (GET_CODE (XVECEXP (op, 0, index++)) != RETURN
1331 || GET_CODE (XVECEXP (op, 0, index++)) != USE
1332 || GET_CODE (XVECEXP (op, 0, index++)) != CLOBBER)
1335 elt = XVECEXP (op, 0, index++);
1336 if (GET_CODE (elt) != SET
1337 || !MEM_P (SET_SRC (elt))
1338 || !memory_operand (SET_SRC (elt), Pmode)
1339 || !REG_P (SET_DEST (elt))
1340 || REGNO (SET_DEST (elt)) != CR2_REGNO
1341 || GET_MODE (SET_DEST (elt)) != Pmode)
1344 for (i=1; i <= 19; i++)
1346 elt = XVECEXP (op, 0, index++);
1347 if (GET_CODE (elt) != SET
1348 || !MEM_P (SET_SRC (elt))
1349 || !memory_operand (SET_SRC (elt), Pmode)
1350 || !REG_P (SET_DEST (elt))
1351 || GET_MODE (SET_DEST (elt)) != Pmode)
1355 for (i=1; i <= 12; i++)
1357 elt = XVECEXP (op, 0, index++);
1358 if (GET_CODE (elt) != SET
1359 || !MEM_P (SET_SRC (elt))
1360 || !REG_P (SET_DEST (elt))
1361 || GET_MODE (SET_DEST (elt)) != V4SImode)
1365 for (i=1; i <= 18; i++)
1367 elt = XVECEXP (op, 0, index++);
1368 if (GET_CODE (elt) != SET
1369 || !MEM_P (SET_SRC (elt))
1370 || !memory_operand (SET_SRC (elt), DFmode)
1371 || !REG_P (SET_DEST (elt))
1372 || GET_MODE (SET_DEST (elt)) != DFmode)
1376 if (GET_CODE (XVECEXP (op, 0, index++)) != CLOBBER
1377 || GET_CODE (XVECEXP (op, 0, index++)) != CLOBBER
1378 || GET_CODE (XVECEXP (op, 0, index++)) != CLOBBER
1379 || GET_CODE (XVECEXP (op, 0, index++)) != CLOBBER
1380 || GET_CODE (XVECEXP (op, 0, index++)) != USE)
1385 ;; Return 1 if OP is valid for a vrsave call, known to be a PARALLEL.
1386 (define_predicate "vrsave_operation"
1387 (match_code "parallel")
1389 int count = XVECLEN (op, 0);
1390 unsigned int dest_regno, src_regno;
1394 || GET_CODE (XVECEXP (op, 0, 0)) != SET
1395 || !REG_P (SET_DEST (XVECEXP (op, 0, 0)))
1396 || GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != UNSPEC_VOLATILE
1397 || XINT (SET_SRC (XVECEXP (op, 0, 0)), 1) != UNSPECV_SET_VRSAVE)
1400 dest_regno = REGNO (SET_DEST (XVECEXP (op, 0, 0)));
1401 src_regno = REGNO (XVECEXP (SET_SRC (XVECEXP (op, 0, 0)), 0, 1));
1403 if (dest_regno != VRSAVE_REGNO || src_regno != VRSAVE_REGNO)
1406 for (i = 1; i < count; i++)
1408 rtx elt = XVECEXP (op, 0, i);
1410 if (GET_CODE (elt) != CLOBBER
1411 && GET_CODE (elt) != SET)
1418 ;; Return 1 if OP is valid for mfcr insn, known to be a PARALLEL.
1419 (define_predicate "mfcr_operation"
1420 (match_code "parallel")
1422 int count = XVECLEN (op, 0);
1425 /* Perform a quick check so we don't blow up below. */
1427 || GET_CODE (XVECEXP (op, 0, 0)) != SET
1428 || GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != UNSPEC
1429 || XVECLEN (SET_SRC (XVECEXP (op, 0, 0)), 0) != 2)
1432 for (i = 0; i < count; i++)
1434 rtx exp = XVECEXP (op, 0, i);
1439 src_reg = XVECEXP (SET_SRC (exp), 0, 0);
1441 if (!REG_P (src_reg)
1442 || GET_MODE (src_reg) != CCmode
1443 || ! CR_REGNO_P (REGNO (src_reg)))
1446 if (GET_CODE (exp) != SET
1447 || !REG_P (SET_DEST (exp))
1448 || GET_MODE (SET_DEST (exp)) != SImode
1449 || ! INT_REGNO_P (REGNO (SET_DEST (exp))))
1451 unspec = SET_SRC (exp);
1452 maskval = 1 << (MAX_CR_REGNO - REGNO (src_reg));
1454 if (GET_CODE (unspec) != UNSPEC
1455 || XINT (unspec, 1) != UNSPEC_MOVESI_FROM_CR
1456 || XVECLEN (unspec, 0) != 2
1457 || XVECEXP (unspec, 0, 0) != src_reg
1458 || !CONST_INT_P (XVECEXP (unspec, 0, 1))
1459 || INTVAL (XVECEXP (unspec, 0, 1)) != maskval)
1465 ;; Return 1 if OP is valid for mtcrf insn, known to be a PARALLEL.
1466 (define_predicate "mtcrf_operation"
1467 (match_code "parallel")
1469 int count = XVECLEN (op, 0);
1473 /* Perform a quick check so we don't blow up below. */
1475 || GET_CODE (XVECEXP (op, 0, 0)) != SET
1476 || GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != UNSPEC
1477 || XVECLEN (SET_SRC (XVECEXP (op, 0, 0)), 0) != 2)
1479 src_reg = XVECEXP (SET_SRC (XVECEXP (op, 0, 0)), 0, 0);
1481 if (!REG_P (src_reg)
1482 || GET_MODE (src_reg) != SImode
1483 || ! INT_REGNO_P (REGNO (src_reg)))
1486 for (i = 0; i < count; i++)
1488 rtx exp = XVECEXP (op, 0, i);
1492 if (GET_CODE (exp) != SET
1493 || !REG_P (SET_DEST (exp))
1494 || GET_MODE (SET_DEST (exp)) != CCmode
1495 || ! CR_REGNO_P (REGNO (SET_DEST (exp))))
1497 unspec = SET_SRC (exp);
1498 maskval = 1 << (MAX_CR_REGNO - REGNO (SET_DEST (exp)));
1500 if (GET_CODE (unspec) != UNSPEC
1501 || XINT (unspec, 1) != UNSPEC_MOVESI_TO_CR
1502 || XVECLEN (unspec, 0) != 2
1503 || XVECEXP (unspec, 0, 0) != src_reg
1504 || !CONST_INT_P (XVECEXP (unspec, 0, 1))
1505 || INTVAL (XVECEXP (unspec, 0, 1)) != maskval)
1511 ;; Return 1 if OP is valid for crsave insn, known to be a PARALLEL.
1512 (define_predicate "crsave_operation"
1513 (match_code "parallel")
1515 int count = XVECLEN (op, 0);
1518 for (i = 1; i < count; i++)
1520 rtx exp = XVECEXP (op, 0, i);
1522 if (GET_CODE (exp) != USE
1523 || !REG_P (XEXP (exp, 0))
1524 || GET_MODE (XEXP (exp, 0)) != CCmode
1525 || ! CR_REGNO_P (REGNO (XEXP (exp, 0))))
1531 ;; Return 1 if OP is valid for lmw insn, known to be a PARALLEL.
1532 (define_predicate "lmw_operation"
1533 (match_code "parallel")
1535 int count = XVECLEN (op, 0);
1536 unsigned int dest_regno;
1538 unsigned int base_regno;
1539 HOST_WIDE_INT offset;
1542 /* Perform a quick check so we don't blow up below. */
1544 || GET_CODE (XVECEXP (op, 0, 0)) != SET
1545 || !REG_P (SET_DEST (XVECEXP (op, 0, 0)))
1546 || !MEM_P (SET_SRC (XVECEXP (op, 0, 0))))
1549 dest_regno = REGNO (SET_DEST (XVECEXP (op, 0, 0)));
1550 src_addr = XEXP (SET_SRC (XVECEXP (op, 0, 0)), 0);
1553 || count != 32 - (int) dest_regno)
1556 if (legitimate_indirect_address_p (src_addr, 0))
1559 base_regno = REGNO (src_addr);
1560 if (base_regno == 0)
1563 else if (rs6000_legitimate_offset_address_p (SImode, src_addr, false, false))
1565 offset = INTVAL (XEXP (src_addr, 1));
1566 base_regno = REGNO (XEXP (src_addr, 0));
1571 for (i = 0; i < count; i++)
1573 rtx elt = XVECEXP (op, 0, i);
1576 HOST_WIDE_INT newoffset;
1578 if (GET_CODE (elt) != SET
1579 || !REG_P (SET_DEST (elt))
1580 || GET_MODE (SET_DEST (elt)) != SImode
1581 || REGNO (SET_DEST (elt)) != dest_regno + i
1582 || !MEM_P (SET_SRC (elt))
1583 || GET_MODE (SET_SRC (elt)) != SImode)
1585 newaddr = XEXP (SET_SRC (elt), 0);
1586 if (legitimate_indirect_address_p (newaddr, 0))
1591 else if (rs6000_legitimate_offset_address_p (SImode, newaddr, false, false))
1593 addr_reg = XEXP (newaddr, 0);
1594 newoffset = INTVAL (XEXP (newaddr, 1));
1598 if (REGNO (addr_reg) != base_regno
1599 || newoffset != offset + 4 * i)
1606 ;; Return 1 if OP is valid for stmw insn, known to be a PARALLEL.
1607 (define_predicate "stmw_operation"
1608 (match_code "parallel")
1610 int count = XVECLEN (op, 0);
1611 unsigned int src_regno;
1613 unsigned int base_regno;
1614 HOST_WIDE_INT offset;
1617 /* Perform a quick check so we don't blow up below. */
1619 || GET_CODE (XVECEXP (op, 0, 0)) != SET
1620 || !MEM_P (SET_DEST (XVECEXP (op, 0, 0)))
1621 || !REG_P (SET_SRC (XVECEXP (op, 0, 0))))
1624 src_regno = REGNO (SET_SRC (XVECEXP (op, 0, 0)));
1625 dest_addr = XEXP (SET_DEST (XVECEXP (op, 0, 0)), 0);
1628 || count != 32 - (int) src_regno)
1631 if (legitimate_indirect_address_p (dest_addr, 0))
1634 base_regno = REGNO (dest_addr);
1635 if (base_regno == 0)
1638 else if (rs6000_legitimate_offset_address_p (SImode, dest_addr, false, false))
1640 offset = INTVAL (XEXP (dest_addr, 1));
1641 base_regno = REGNO (XEXP (dest_addr, 0));
1646 for (i = 0; i < count; i++)
1648 rtx elt = XVECEXP (op, 0, i);
1651 HOST_WIDE_INT newoffset;
1653 if (GET_CODE (elt) != SET
1654 || !REG_P (SET_SRC (elt))
1655 || GET_MODE (SET_SRC (elt)) != SImode
1656 || REGNO (SET_SRC (elt)) != src_regno + i
1657 || !MEM_P (SET_DEST (elt))
1658 || GET_MODE (SET_DEST (elt)) != SImode)
1660 newaddr = XEXP (SET_DEST (elt), 0);
1661 if (legitimate_indirect_address_p (newaddr, 0))
1666 else if (rs6000_legitimate_offset_address_p (SImode, newaddr, false, false))
1668 addr_reg = XEXP (newaddr, 0);
1669 newoffset = INTVAL (XEXP (newaddr, 1));
1673 if (REGNO (addr_reg) != base_regno
1674 || newoffset != offset + 4 * i)
1681 ;; Return 1 if OP is a stack tie operand.
1682 (define_predicate "tie_operand"
1683 (match_code "parallel")
1685 return (GET_CODE (XVECEXP (op, 0, 0)) == SET
1686 && MEM_P (XEXP (XVECEXP (op, 0, 0), 0))
1687 && GET_MODE (XEXP (XVECEXP (op, 0, 0), 0)) == BLKmode
1688 && XEXP (XVECEXP (op, 0, 0), 1) == const0_rtx);
1691 ;; Match a small code model toc reference (or medium and large
1692 ;; model toc references before reload).
1693 (define_predicate "small_toc_ref"
1694 (match_code "unspec,plus")
1696 if (GET_CODE (op) == PLUS && add_cint_operand (XEXP (op, 1), mode))
1699 return GET_CODE (op) == UNSPEC && XINT (op, 1) == UNSPEC_TOCREL;
1703 ;; Match the first insn (addis) in fusing the combination of addis and loads to
1704 ;; GPR registers on power8.
1705 (define_predicate "fusion_gpr_addis"
1706 (match_code "const_int,high,plus")
1708 HOST_WIDE_INT value;
1711 if (GET_CODE (op) == HIGH)
1714 if (CONST_INT_P (op))
1717 else if (GET_CODE (op) == PLUS
1718 && base_reg_operand (XEXP (op, 0), Pmode)
1719 && CONST_INT_P (XEXP (op, 1)))
1720 int_const = XEXP (op, 1);
1725 value = INTVAL (int_const);
1726 if ((value & (HOST_WIDE_INT)0xffff) != 0)
1729 if ((value & (HOST_WIDE_INT)0xffff0000) == 0)
1732 /* Power8 only does the fusion if the top 12 bits of the addis value are all
1734 return (IN_RANGE (value >> 16, -16, 15));
1737 ;; Match the second insn (lbz, lhz, lwz, ld) in fusing the combination of addis
1738 ;; and loads to GPR registers on power8.
1739 (define_predicate "fusion_gpr_mem_load"
1740 (match_code "mem,sign_extend,zero_extend")
1742 rtx addr, base, offset;
1744 /* Handle sign/zero extend. */
1745 if (GET_CODE (op) == ZERO_EXTEND
1746 || (TARGET_P8_FUSION_SIGN && GET_CODE (op) == SIGN_EXTEND))
1749 mode = GET_MODE (op);
1763 if (!TARGET_POWERPC64)
1767 /* Do not allow SF/DFmode in GPR fusion. While the loads do occur, they
1773 addr = XEXP (op, 0);
1774 if (GET_CODE (addr) != PLUS && GET_CODE (addr) != LO_SUM)
1777 base = XEXP (addr, 0);
1778 if (!base_reg_operand (base, GET_MODE (base)))
1781 offset = XEXP (addr, 1);
1783 if (GET_CODE (addr) == PLUS)
1784 return satisfies_constraint_I (offset);
1786 else if (GET_CODE (addr) == LO_SUM)
1788 if (TARGET_XCOFF || (TARGET_ELF && TARGET_POWERPC64))
1789 return small_toc_ref (offset, GET_MODE (offset));
1791 else if (TARGET_ELF && !TARGET_POWERPC64)
1792 return CONSTANT_P (offset);
1798 ;; Match a GPR load (lbz, lhz, lwz, ld) that uses a combined address in the
1799 ;; memory field with both the addis and the memory offset. Sign extension
1800 ;; is not handled here, since lha and lwa are not fused.
1801 (define_predicate "fusion_addis_mem_combo_load"
1802 (match_code "mem,zero_extend")
1804 rtx addr, base, offset;
1806 /* Handle zero extend. */
1807 if (GET_CODE (op) == ZERO_EXTEND)
1810 mode = GET_MODE (op);
1823 /* Do not fuse 64-bit DImode in 32-bit since it splits into two
1824 separate instructions. */
1826 if (!TARGET_POWERPC64)
1830 /* Do not allow SF/DFmode in GPR fusion. While the loads do occur, they
1836 addr = XEXP (op, 0);
1837 if (GET_CODE (addr) != PLUS && GET_CODE (addr) != LO_SUM)
1840 base = XEXP (addr, 0);
1841 if (!fusion_gpr_addis (base, GET_MODE (base)))
1844 offset = XEXP (addr, 1);
1845 if (GET_CODE (addr) == PLUS)
1846 return satisfies_constraint_I (offset);
1848 else if (GET_CODE (addr) == LO_SUM)
1850 if (TARGET_XCOFF || (TARGET_ELF && TARGET_POWERPC64))
1851 return small_toc_ref (offset, GET_MODE (offset));
1853 else if (TARGET_ELF && !TARGET_POWERPC64)
1854 return CONSTANT_P (offset);
1861 ;; Return true if the operand is a PC-relative address of a local symbol or a
1862 ;; label that can be used directly in a memory operation.
1863 (define_predicate "pcrel_local_address"
1864 (match_code "label_ref,symbol_ref,const")
1866 enum insn_form iform = address_to_insn_form (op, mode, NON_PREFIXED_DEFAULT);
1867 return iform == INSN_FORM_PCREL_LOCAL;
1870 ;; Return true if the operand is a PC-relative external symbol whose address
1871 ;; can be loaded into a register.
1872 (define_predicate "pcrel_external_address"
1873 (match_code "symbol_ref,const")
1875 enum insn_form iform = address_to_insn_form (op, mode, NON_PREFIXED_DEFAULT);
1876 return iform == INSN_FORM_PCREL_EXTERNAL;
1879 ;; Return true if the address is PC-relative and the symbol is either local or
1881 (define_predicate "pcrel_local_or_external_address"
1882 (ior (match_operand 0 "pcrel_local_address")
1883 (match_operand 0 "pcrel_external_address")))
1885 ;; Return true if the operand is a memory address that uses a prefixed address.
1886 (define_predicate "prefixed_memory"
1889 return address_is_prefixed (XEXP (op, 0), mode, NON_PREFIXED_DEFAULT);