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5b8c8b93 GKH |
1 | From 5f563c31ff0c40ce395d0bae7daa94c7950dac97 Mon Sep 17 00:00:00 2001 |
2 | From: =?UTF-8?q?Ar=C4=B1n=C3=A7=20=C3=9CNAL?= <arinc.unal@arinc9.com> | |
3 | Date: Wed, 20 Mar 2024 23:45:30 +0300 | |
4 | Subject: net: dsa: mt7530: fix improper frames on all 25MHz and 40MHz XTAL MT7530 | |
5 | MIME-Version: 1.0 | |
6 | Content-Type: text/plain; charset=UTF-8 | |
7 | Content-Transfer-Encoding: 8bit | |
8 | ||
9 | From: Arınç ÜNAL <arinc.unal@arinc9.com> | |
10 | ||
11 | commit 5f563c31ff0c40ce395d0bae7daa94c7950dac97 upstream. | |
12 | ||
13 | The MT7530 switch after reset initialises with a core clock frequency that | |
14 | works with a 25MHz XTAL connected to it. For 40MHz XTAL, the core clock | |
15 | frequency must be set to 500MHz. | |
16 | ||
17 | The mt7530_pll_setup() function is responsible of setting the core clock | |
18 | frequency. Currently, it runs on MT7530 with 25MHz and 40MHz XTAL. This | |
19 | causes MT7530 switch with 25MHz XTAL to egress and ingress frames | |
20 | improperly. | |
21 | ||
22 | Introduce a check to run it only on MT7530 with 40MHz XTAL. | |
23 | ||
24 | The core clock frequency is set by writing to a switch PHY's register. | |
25 | Access to the PHY's register is done via the MDIO bus the switch is also | |
26 | on. Therefore, it works only when the switch makes switch PHYs listen on | |
27 | the MDIO bus the switch is on. This is controlled either by the state of | |
28 | the ESW_P1_LED_1 pin after reset deassertion or modifying bit 5 of the | |
29 | modifiable trap register. | |
30 | ||
31 | When ESW_P1_LED_1 is pulled high, PHY indirect access is used. That means | |
32 | accessing PHY registers via the PHY indirect access control register of the | |
33 | switch. | |
34 | ||
35 | When ESW_P1_LED_1 is pulled low, PHY direct access is used. That means | |
36 | accessing PHY registers via the MDIO bus the switch is on. | |
37 | ||
38 | For MT7530 switch with 40MHz XTAL on a board with ESW_P1_LED_1 pulled high, | |
39 | the core clock frequency won't be set to 500MHz, causing the switch to | |
40 | egress and ingress frames improperly. | |
41 | ||
42 | Run mt7530_pll_setup() after PHY direct access is set on the modifiable | |
43 | trap register. | |
44 | ||
45 | With these two changes, all MT7530 switches with 25MHz and 40MHz, and | |
46 | P1_LED_1 pulled high or low, will egress and ingress frames properly. | |
47 | ||
48 | Link: https://github.com/BPI-SINOVOIP/BPI-R2-bsp/blob/4a5dd143f2172ec97a2872fa29c7c4cd520f45b5/linux-mt/drivers/net/ethernet/mediatek/gsw_mt7623.c#L1039 | |
49 | Fixes: b8f126a8d543 ("net-next: dsa: add dsa support for Mediatek MT7530 switch") | |
50 | Signed-off-by: Arınç ÜNAL <arinc.unal@arinc9.com> | |
51 | Link: https://lore.kernel.org/r/20240320-for-net-mt7530-fix-25mhz-xtal-with-direct-phy-access-v1-1-d92f605f1160@arinc9.com | |
52 | Signed-off-by: Paolo Abeni <pabeni@redhat.com> | |
53 | Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> | |
54 | --- | |
55 | drivers/net/dsa/mt7530.c | 5 +++-- | |
56 | 1 file changed, 3 insertions(+), 2 deletions(-) | |
57 | ||
58 | --- a/drivers/net/dsa/mt7530.c | |
59 | +++ b/drivers/net/dsa/mt7530.c | |
60 | @@ -2410,8 +2410,6 @@ mt7530_setup(struct dsa_switch *ds) | |
61 | SYS_CTRL_PHY_RST | SYS_CTRL_SW_RST | | |
62 | SYS_CTRL_REG_RST); | |
63 | ||
64 | - mt7530_pll_setup(priv); | |
65 | - | |
66 | /* Lower Tx driving for TRGMII path */ | |
67 | for (i = 0; i < NUM_TRGMII_CTRL; i++) | |
68 | mt7530_write(priv, MT7530_TRGMII_TD_ODT(i), | |
69 | @@ -2429,6 +2427,9 @@ mt7530_setup(struct dsa_switch *ds) | |
70 | ||
71 | priv->p6_interface = PHY_INTERFACE_MODE_NA; | |
72 | ||
73 | + if ((val & HWTRAP_XTAL_MASK) == HWTRAP_XTAL_40MHZ) | |
74 | + mt7530_pll_setup(priv); | |
75 | + | |
76 | mt753x_trap_frames(priv); | |
77 | ||
78 | /* Enable and reset MIB counters */ |