releases/6.8.6/arm64-dts-qcom-qcs6490-rb3gen2-declare-gcc-clocks-pr.patch

   1 From 7eda2e758e812ad24b266b552ef6caf363b93835 Mon Sep 17 00:00:00 2001
   2 From: Sasha Levin <sashal@kernel.org>
   3 Date: Fri, 9 Feb 2024 15:21:48 -0800
   4 Subject: arm64: dts: qcom: qcs6490-rb3gen2: Declare GCC clocks protected
   5
   6 From: Bjorn Andersson <quic_bjorande@quicinc.com>
   7
   8 [ Upstream commit 7c6bef576a8891abce08d448165b53328032aa5f ]
   9
  10 The SC7280 GCC binding describes clocks which, due to the difference in
  11 security model, are not accessible on the RB3gen2 - in the same way seen
  12 on QCM6490.
  13
  14 Mark these clocks as protected, to allow the board to boot. In contrast
  15 to the present QCM6490 boards GCC_EDP_CLKREF_EN is left out, as this
  16 does not need to be "protected" and is used on the RB3Gen2 board.
  17
  18 Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
  19 Reviewed-by: Luca Weiss <luca.weiss@fairphone.com>
  20 Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
  21 Signed-off-by: Bjorn Andersson <quic_bjorande@quicinc.com>
  22 Link: https://lore.kernel.org/r/20240209-qcm6490-gcc-protected-clocks-v2-1-11cd5fc13bd0@quicinc.com
  23 Signed-off-by: Bjorn Andersson <andersson@kernel.org>
  24 Signed-off-by: Sasha Levin <sashal@kernel.org>
  25 ---
  26  arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts | 17 +++++++++++++++++
  27  1 file changed, 17 insertions(+)
  28
  29 diff --git a/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts b/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts
  30 index ae1632182d7c1..ac4579119d3ba 100644
  31 --- a/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts
  32 +++ b/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts
  33 @@ -413,6 +413,23 @@ vreg_bob_3p296: bob {
  34         };
  35  };
  36
  37 +&gcc {
  38 +       protected-clocks = <GCC_CFG_NOC_LPASS_CLK>,
  39 +                          <GCC_MSS_CFG_AHB_CLK>,
  40 +                          <GCC_MSS_GPLL0_MAIN_DIV_CLK_SRC>,
  41 +                          <GCC_MSS_OFFLINE_AXI_CLK>,
  42 +                          <GCC_MSS_Q6SS_BOOT_CLK_SRC>,
  43 +                          <GCC_MSS_Q6_MEMNOC_AXI_CLK>,
  44 +                          <GCC_MSS_SNOC_AXI_CLK>,
  45 +                          <GCC_QSPI_CNOC_PERIPH_AHB_CLK>,
  46 +                          <GCC_QSPI_CORE_CLK>,
  47 +                          <GCC_QSPI_CORE_CLK_SRC>,
  48 +                          <GCC_SEC_CTRL_CLK_SRC>,
  49 +                          <GCC_WPSS_AHB_BDG_MST_CLK>,
  50 +                          <GCC_WPSS_AHB_CLK>,
  51 +                          <GCC_WPSS_RSCP_CLK>;
  52 +};
  53 +
  54  &qupv3_id_0 {
  55         status = "okay";
  56  };
  57 --
  58 2.43.0
  59