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Commit | Line | Data |
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edf79e66 HC |
1 | /* |
2 | * VT82C686B south bridge support | |
3 | * | |
4 | * Copyright (c) 2008 yajin (yajin@vm-kernel.org) | |
5 | * Copyright (c) 2009 chenming (chenming@rdc.faw.com.cn) | |
6 | * Copyright (c) 2010 Huacai Chen (zltjiangshi@gmail.com) | |
7 | * This code is licensed under the GNU GPL v2. | |
6b620ca3 PB |
8 | * |
9 | * Contributions after 2012-01-13 are licensed under the terms of the | |
10 | * GNU GPL, version 2 or (at your option) any later version. | |
edf79e66 HC |
11 | */ |
12 | ||
0430891c | 13 | #include "qemu/osdep.h" |
83c9f4ca | 14 | #include "hw/hw.h" |
0d09e41a PB |
15 | #include "hw/isa/vt82c686.h" |
16 | #include "hw/i2c/i2c.h" | |
83c9f4ca | 17 | #include "hw/pci/pci.h" |
0d09e41a | 18 | #include "hw/isa/isa.h" |
98cf824b | 19 | #include "hw/isa/superio.h" |
83c9f4ca | 20 | #include "hw/sysbus.h" |
0d09e41a PB |
21 | #include "hw/mips/mips.h" |
22 | #include "hw/isa/apm.h" | |
23 | #include "hw/acpi/acpi.h" | |
24 | #include "hw/i2c/pm_smbus.h" | |
71e8a915 | 25 | #include "sysemu/reset.h" |
9c17d615 | 26 | #include "sysemu/sysemu.h" |
0b8fa32f | 27 | #include "qemu/module.h" |
1de7afc9 | 28 | #include "qemu/timer.h" |
022c62cb | 29 | #include "exec/address-spaces.h" |
edf79e66 | 30 | |
edf79e66 HC |
31 | //#define DEBUG_VT82C686B |
32 | ||
33 | #ifdef DEBUG_VT82C686B | |
a89f364a | 34 | #define DPRINTF(fmt, ...) fprintf(stderr, "%s: " fmt, __func__, ##__VA_ARGS__) |
edf79e66 HC |
35 | #else |
36 | #define DPRINTF(fmt, ...) | |
37 | #endif | |
38 | ||
39 | typedef struct SuperIOConfig | |
40 | { | |
9feb8ade | 41 | uint8_t config[0x100]; |
edf79e66 HC |
42 | uint8_t index; |
43 | uint8_t data; | |
44 | } SuperIOConfig; | |
45 | ||
46 | typedef struct VT82C686BState { | |
47 | PCIDevice dev; | |
bcc37e24 | 48 | MemoryRegion superio; |
edf79e66 HC |
49 | SuperIOConfig superio_conf; |
50 | } VT82C686BState; | |
51 | ||
417349e6 GA |
52 | #define TYPE_VT82C686B_DEVICE "VT82C686B" |
53 | #define VT82C686B_DEVICE(obj) \ | |
54 | OBJECT_CHECK(VT82C686BState, (obj), TYPE_VT82C686B_DEVICE) | |
55 | ||
bcc37e24 JK |
56 | static void superio_ioport_writeb(void *opaque, hwaddr addr, uint64_t data, |
57 | unsigned size) | |
edf79e66 | 58 | { |
edf79e66 HC |
59 | SuperIOConfig *superio_conf = opaque; |
60 | ||
b2bedb21 | 61 | DPRINTF("superio_ioport_writeb address 0x%x val 0x%x\n", addr, data); |
edf79e66 HC |
62 | if (addr == 0x3f0) { |
63 | superio_conf->index = data & 0xff; | |
64 | } else { | |
b196d969 | 65 | bool can_write = true; |
edf79e66 HC |
66 | /* 0x3f1 */ |
67 | switch (superio_conf->index) { | |
68 | case 0x00 ... 0xdf: | |
69 | case 0xe4: | |
70 | case 0xe5: | |
71 | case 0xe9 ... 0xed: | |
72 | case 0xf3: | |
73 | case 0xf5: | |
74 | case 0xf7: | |
75 | case 0xf9 ... 0xfb: | |
76 | case 0xfd ... 0xff: | |
b196d969 HZ |
77 | can_write = false; |
78 | break; | |
79 | case 0xe7: | |
80 | if ((data & 0xff) != 0xfe) { | |
81 | DPRINTF("change uart 1 base. unsupported yet\n"); | |
82 | can_write = false; | |
83 | } | |
84 | break; | |
85 | case 0xe8: | |
86 | if ((data & 0xff) != 0xbe) { | |
87 | DPRINTF("change uart 2 base. unsupported yet\n"); | |
88 | can_write = false; | |
89 | } | |
edf79e66 HC |
90 | break; |
91 | default: | |
b196d969 | 92 | break; |
edf79e66 | 93 | |
edf79e66 | 94 | } |
b196d969 HZ |
95 | if (can_write) { |
96 | superio_conf->config[superio_conf->index] = data & 0xff; | |
97 | } | |
edf79e66 HC |
98 | } |
99 | } | |
100 | ||
bcc37e24 | 101 | static uint64_t superio_ioport_readb(void *opaque, hwaddr addr, unsigned size) |
edf79e66 HC |
102 | { |
103 | SuperIOConfig *superio_conf = opaque; | |
104 | ||
b2bedb21 | 105 | DPRINTF("superio_ioport_readb address 0x%x\n", addr); |
edf79e66 HC |
106 | return (superio_conf->config[superio_conf->index]); |
107 | } | |
108 | ||
bcc37e24 JK |
109 | static const MemoryRegionOps superio_ops = { |
110 | .read = superio_ioport_readb, | |
111 | .write = superio_ioport_writeb, | |
112 | .endianness = DEVICE_NATIVE_ENDIAN, | |
113 | .impl = { | |
114 | .min_access_size = 1, | |
115 | .max_access_size = 1, | |
116 | }, | |
117 | }; | |
118 | ||
edf79e66 HC |
119 | static void vt82c686b_reset(void * opaque) |
120 | { | |
121 | PCIDevice *d = opaque; | |
122 | uint8_t *pci_conf = d->config; | |
417349e6 | 123 | VT82C686BState *vt82c = VT82C686B_DEVICE(d); |
edf79e66 HC |
124 | |
125 | pci_set_long(pci_conf + PCI_CAPABILITY_LIST, 0x000000c0); | |
126 | pci_set_word(pci_conf + PCI_COMMAND, PCI_COMMAND_IO | PCI_COMMAND_MEMORY | | |
127 | PCI_COMMAND_MASTER | PCI_COMMAND_SPECIAL); | |
128 | pci_set_word(pci_conf + PCI_STATUS, PCI_STATUS_DEVSEL_MEDIUM); | |
129 | ||
130 | pci_conf[0x48] = 0x01; /* Miscellaneous Control 3 */ | |
131 | pci_conf[0x4a] = 0x04; /* IDE interrupt Routing */ | |
132 | pci_conf[0x4f] = 0x03; /* DMA/Master Mem Access Control 3 */ | |
133 | pci_conf[0x50] = 0x2d; /* PnP DMA Request Control */ | |
134 | pci_conf[0x59] = 0x04; | |
135 | pci_conf[0x5a] = 0x04; /* KBC/RTC Control*/ | |
136 | pci_conf[0x5f] = 0x04; | |
137 | pci_conf[0x77] = 0x10; /* GPIO Control 1/2/3/4 */ | |
138 | ||
139 | vt82c->superio_conf.config[0xe0] = 0x3c; | |
140 | vt82c->superio_conf.config[0xe2] = 0x03; | |
141 | vt82c->superio_conf.config[0xe3] = 0xfc; | |
142 | vt82c->superio_conf.config[0xe6] = 0xde; | |
143 | vt82c->superio_conf.config[0xe7] = 0xfe; | |
144 | vt82c->superio_conf.config[0xe8] = 0xbe; | |
145 | } | |
146 | ||
147 | /* write config pci function0 registers. PCI-ISA bridge */ | |
148 | static void vt82c686b_write_config(PCIDevice * d, uint32_t address, | |
149 | uint32_t val, int len) | |
150 | { | |
417349e6 | 151 | VT82C686BState *vt686 = VT82C686B_DEVICE(d); |
edf79e66 | 152 | |
b2bedb21 | 153 | DPRINTF("vt82c686b_write_config address 0x%x val 0x%x len 0x%x\n", |
edf79e66 HC |
154 | address, val, len); |
155 | ||
156 | pci_default_write_config(d, address, val, len); | |
157 | if (address == 0x85) { /* enable or disable super IO configure */ | |
bcc37e24 | 158 | memory_region_set_enabled(&vt686->superio, val & 0x2); |
edf79e66 HC |
159 | } |
160 | } | |
161 | ||
162 | #define ACPI_DBG_IO_ADDR 0xb044 | |
163 | ||
164 | typedef struct VT686PMState { | |
165 | PCIDevice dev; | |
a2902821 | 166 | MemoryRegion io; |
355bf2e5 | 167 | ACPIREGS ar; |
edf79e66 | 168 | APMState apm; |
edf79e66 HC |
169 | PMSMBus smb; |
170 | uint32_t smb_io_base; | |
171 | } VT686PMState; | |
172 | ||
173 | typedef struct VT686AC97State { | |
174 | PCIDevice dev; | |
175 | } VT686AC97State; | |
176 | ||
177 | typedef struct VT686MC97State { | |
178 | PCIDevice dev; | |
179 | } VT686MC97State; | |
180 | ||
417349e6 GA |
181 | #define TYPE_VT82C686B_PM_DEVICE "VT82C686B_PM" |
182 | #define VT82C686B_PM_DEVICE(obj) \ | |
183 | OBJECT_CHECK(VT686PMState, (obj), TYPE_VT82C686B_PM_DEVICE) | |
184 | ||
185 | #define TYPE_VT82C686B_MC97_DEVICE "VT82C686B_MC97" | |
186 | #define VT82C686B_MC97_DEVICE(obj) \ | |
187 | OBJECT_CHECK(VT686MC97State, (obj), TYPE_VT82C686B_MC97_DEVICE) | |
188 | ||
189 | #define TYPE_VT82C686B_AC97_DEVICE "VT82C686B_AC97" | |
190 | #define VT82C686B_AC97_DEVICE(obj) \ | |
191 | OBJECT_CHECK(VT686AC97State, (obj), TYPE_VT82C686B_AC97_DEVICE) | |
192 | ||
edf79e66 HC |
193 | static void pm_update_sci(VT686PMState *s) |
194 | { | |
195 | int sci_level, pmsts; | |
edf79e66 | 196 | |
2886be1b | 197 | pmsts = acpi_pm1_evt_get_sts(&s->ar); |
355bf2e5 | 198 | sci_level = (((pmsts & s->ar.pm1.evt.en) & |
04dc308f IY |
199 | (ACPI_BITMASK_RT_CLOCK_ENABLE | |
200 | ACPI_BITMASK_POWER_BUTTON_ENABLE | | |
201 | ACPI_BITMASK_GLOBAL_LOCK_ENABLE | | |
202 | ACPI_BITMASK_TIMER_ENABLE)) != 0); | |
9e64f8a3 | 203 | pci_set_irq(&s->dev, sci_level); |
edf79e66 | 204 | /* schedule a timer interruption if needed */ |
355bf2e5 | 205 | acpi_pm_tmr_update(&s->ar, (s->ar.pm1.evt.en & ACPI_BITMASK_TIMER_ENABLE) && |
a54d41a8 | 206 | !(pmsts & ACPI_BITMASK_TIMER_STATUS)); |
edf79e66 HC |
207 | } |
208 | ||
355bf2e5 | 209 | static void pm_tmr_timer(ACPIREGS *ar) |
edf79e66 | 210 | { |
355bf2e5 | 211 | VT686PMState *s = container_of(ar, VT686PMState, ar); |
edf79e66 HC |
212 | pm_update_sci(s); |
213 | } | |
214 | ||
edf79e66 HC |
215 | static void pm_io_space_update(VT686PMState *s) |
216 | { | |
217 | uint32_t pm_io_base; | |
218 | ||
a2902821 GH |
219 | pm_io_base = pci_get_long(s->dev.config + 0x40); |
220 | pm_io_base &= 0xffc0; | |
edf79e66 | 221 | |
a2902821 GH |
222 | memory_region_transaction_begin(); |
223 | memory_region_set_enabled(&s->io, s->dev.config[0x80] & 1); | |
224 | memory_region_set_address(&s->io, pm_io_base); | |
225 | memory_region_transaction_commit(); | |
edf79e66 HC |
226 | } |
227 | ||
228 | static void pm_write_config(PCIDevice *d, | |
229 | uint32_t address, uint32_t val, int len) | |
230 | { | |
b2bedb21 | 231 | DPRINTF("pm_write_config address 0x%x val 0x%x len 0x%x\n", |
edf79e66 HC |
232 | address, val, len); |
233 | pci_default_write_config(d, address, val, len); | |
234 | } | |
235 | ||
236 | static int vmstate_acpi_post_load(void *opaque, int version_id) | |
237 | { | |
238 | VT686PMState *s = opaque; | |
239 | ||
240 | pm_io_space_update(s); | |
241 | return 0; | |
242 | } | |
243 | ||
244 | static const VMStateDescription vmstate_acpi = { | |
245 | .name = "vt82c686b_pm", | |
246 | .version_id = 1, | |
247 | .minimum_version_id = 1, | |
edf79e66 | 248 | .post_load = vmstate_acpi_post_load, |
d49805ae | 249 | .fields = (VMStateField[]) { |
edf79e66 | 250 | VMSTATE_PCI_DEVICE(dev, VT686PMState), |
355bf2e5 GH |
251 | VMSTATE_UINT16(ar.pm1.evt.sts, VT686PMState), |
252 | VMSTATE_UINT16(ar.pm1.evt.en, VT686PMState), | |
253 | VMSTATE_UINT16(ar.pm1.cnt.cnt, VT686PMState), | |
edf79e66 | 254 | VMSTATE_STRUCT(apm, VT686PMState, 0, vmstate_apm, APMState), |
e720677e | 255 | VMSTATE_TIMER_PTR(ar.tmr.timer, VT686PMState), |
355bf2e5 | 256 | VMSTATE_INT64(ar.tmr.overflow_time, VT686PMState), |
edf79e66 HC |
257 | VMSTATE_END_OF_LIST() |
258 | } | |
259 | }; | |
260 | ||
261 | /* | |
262 | * TODO: vt82c686b_ac97_init() and vt82c686b_mc97_init() | |
263 | * just register a PCI device now, functionalities will be implemented later. | |
264 | */ | |
265 | ||
9af21dbe | 266 | static void vt82c686b_ac97_realize(PCIDevice *dev, Error **errp) |
edf79e66 | 267 | { |
417349e6 | 268 | VT686AC97State *s = VT82C686B_AC97_DEVICE(dev); |
edf79e66 HC |
269 | uint8_t *pci_conf = s->dev.config; |
270 | ||
edf79e66 HC |
271 | pci_set_word(pci_conf + PCI_COMMAND, PCI_COMMAND_INVALIDATE | |
272 | PCI_COMMAND_PARITY); | |
273 | pci_set_word(pci_conf + PCI_STATUS, PCI_STATUS_CAP_LIST | | |
274 | PCI_STATUS_DEVSEL_MEDIUM); | |
275 | pci_set_long(pci_conf + PCI_INTERRUPT_PIN, 0x03); | |
edf79e66 HC |
276 | } |
277 | ||
278 | void vt82c686b_ac97_init(PCIBus *bus, int devfn) | |
279 | { | |
280 | PCIDevice *dev; | |
281 | ||
417349e6 | 282 | dev = pci_create(bus, devfn, TYPE_VT82C686B_AC97_DEVICE); |
edf79e66 HC |
283 | qdev_init_nofail(&dev->qdev); |
284 | } | |
285 | ||
40021f08 AL |
286 | static void via_ac97_class_init(ObjectClass *klass, void *data) |
287 | { | |
39bffca2 | 288 | DeviceClass *dc = DEVICE_CLASS(klass); |
40021f08 AL |
289 | PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); |
290 | ||
9af21dbe | 291 | k->realize = vt82c686b_ac97_realize; |
40021f08 AL |
292 | k->vendor_id = PCI_VENDOR_ID_VIA; |
293 | k->device_id = PCI_DEVICE_ID_VIA_AC97; | |
294 | k->revision = 0x50; | |
295 | k->class_id = PCI_CLASS_MULTIMEDIA_AUDIO; | |
125ee0ed | 296 | set_bit(DEVICE_CATEGORY_SOUND, dc->categories); |
39bffca2 | 297 | dc->desc = "AC97"; |
40021f08 AL |
298 | } |
299 | ||
8c43a6f0 | 300 | static const TypeInfo via_ac97_info = { |
417349e6 | 301 | .name = TYPE_VT82C686B_AC97_DEVICE, |
39bffca2 AL |
302 | .parent = TYPE_PCI_DEVICE, |
303 | .instance_size = sizeof(VT686AC97State), | |
304 | .class_init = via_ac97_class_init, | |
fd3b02c8 EH |
305 | .interfaces = (InterfaceInfo[]) { |
306 | { INTERFACE_CONVENTIONAL_PCI_DEVICE }, | |
307 | { }, | |
308 | }, | |
edf79e66 HC |
309 | }; |
310 | ||
9af21dbe | 311 | static void vt82c686b_mc97_realize(PCIDevice *dev, Error **errp) |
edf79e66 | 312 | { |
417349e6 | 313 | VT686MC97State *s = VT82C686B_MC97_DEVICE(dev); |
edf79e66 HC |
314 | uint8_t *pci_conf = s->dev.config; |
315 | ||
edf79e66 HC |
316 | pci_set_word(pci_conf + PCI_COMMAND, PCI_COMMAND_INVALIDATE | |
317 | PCI_COMMAND_VGA_PALETTE); | |
318 | pci_set_word(pci_conf + PCI_STATUS, PCI_STATUS_DEVSEL_MEDIUM); | |
319 | pci_set_long(pci_conf + PCI_INTERRUPT_PIN, 0x03); | |
edf79e66 HC |
320 | } |
321 | ||
322 | void vt82c686b_mc97_init(PCIBus *bus, int devfn) | |
323 | { | |
324 | PCIDevice *dev; | |
325 | ||
417349e6 | 326 | dev = pci_create(bus, devfn, TYPE_VT82C686B_MC97_DEVICE); |
edf79e66 HC |
327 | qdev_init_nofail(&dev->qdev); |
328 | } | |
329 | ||
40021f08 AL |
330 | static void via_mc97_class_init(ObjectClass *klass, void *data) |
331 | { | |
39bffca2 | 332 | DeviceClass *dc = DEVICE_CLASS(klass); |
40021f08 AL |
333 | PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); |
334 | ||
9af21dbe | 335 | k->realize = vt82c686b_mc97_realize; |
40021f08 AL |
336 | k->vendor_id = PCI_VENDOR_ID_VIA; |
337 | k->device_id = PCI_DEVICE_ID_VIA_MC97; | |
338 | k->class_id = PCI_CLASS_COMMUNICATION_OTHER; | |
339 | k->revision = 0x30; | |
125ee0ed | 340 | set_bit(DEVICE_CATEGORY_NETWORK, dc->categories); |
39bffca2 | 341 | dc->desc = "MC97"; |
40021f08 AL |
342 | } |
343 | ||
8c43a6f0 | 344 | static const TypeInfo via_mc97_info = { |
417349e6 | 345 | .name = TYPE_VT82C686B_MC97_DEVICE, |
39bffca2 AL |
346 | .parent = TYPE_PCI_DEVICE, |
347 | .instance_size = sizeof(VT686MC97State), | |
348 | .class_init = via_mc97_class_init, | |
fd3b02c8 EH |
349 | .interfaces = (InterfaceInfo[]) { |
350 | { INTERFACE_CONVENTIONAL_PCI_DEVICE }, | |
351 | { }, | |
352 | }, | |
edf79e66 HC |
353 | }; |
354 | ||
edf79e66 | 355 | /* vt82c686 pm init */ |
9af21dbe | 356 | static void vt82c686b_pm_realize(PCIDevice *dev, Error **errp) |
edf79e66 | 357 | { |
417349e6 | 358 | VT686PMState *s = VT82C686B_PM_DEVICE(dev); |
edf79e66 HC |
359 | uint8_t *pci_conf; |
360 | ||
361 | pci_conf = s->dev.config; | |
edf79e66 HC |
362 | pci_set_word(pci_conf + PCI_COMMAND, 0); |
363 | pci_set_word(pci_conf + PCI_STATUS, PCI_STATUS_FAST_BACK | | |
364 | PCI_STATUS_DEVSEL_MEDIUM); | |
365 | ||
366 | /* 0x48-0x4B is Power Management I/O Base */ | |
367 | pci_set_long(pci_conf + 0x48, 0x00000001); | |
368 | ||
369 | /* SMB ports:0xeee0~0xeeef */ | |
370 | s->smb_io_base =((s->smb_io_base & 0xfff0) + 0x0); | |
371 | pci_conf[0x90] = s->smb_io_base | 1; | |
372 | pci_conf[0x91] = s->smb_io_base >> 8; | |
373 | pci_conf[0xd2] = 0x90; | |
a30c34d2 | 374 | pm_smbus_init(DEVICE(s), &s->smb, false); |
798512e5 | 375 | memory_region_add_subregion(get_system_io(), s->smb_io_base, &s->smb.io); |
edf79e66 | 376 | |
42d8a3cf | 377 | apm_init(dev, &s->apm, NULL, s); |
edf79e66 | 378 | |
1437c94b | 379 | memory_region_init(&s->io, OBJECT(dev), "vt82c686-pm", 64); |
a2902821 GH |
380 | memory_region_set_enabled(&s->io, false); |
381 | memory_region_add_subregion(get_system_io(), 0, &s->io); | |
edf79e66 | 382 | |
77d58b1e | 383 | acpi_pm_tmr_init(&s->ar, pm_tmr_timer, &s->io); |
b5a7c024 | 384 | acpi_pm1_evt_init(&s->ar, pm_tmr_timer, &s->io); |
9a10bbb4 | 385 | acpi_pm1_cnt_init(&s->ar, &s->io, false, false, 2); |
edf79e66 HC |
386 | } |
387 | ||
a5c82852 AF |
388 | I2CBus *vt82c686b_pm_init(PCIBus *bus, int devfn, uint32_t smb_io_base, |
389 | qemu_irq sci_irq) | |
edf79e66 HC |
390 | { |
391 | PCIDevice *dev; | |
392 | VT686PMState *s; | |
393 | ||
417349e6 | 394 | dev = pci_create(bus, devfn, TYPE_VT82C686B_PM_DEVICE); |
edf79e66 HC |
395 | qdev_prop_set_uint32(&dev->qdev, "smb_io_base", smb_io_base); |
396 | ||
417349e6 | 397 | s = VT82C686B_PM_DEVICE(dev); |
edf79e66 HC |
398 | |
399 | qdev_init_nofail(&dev->qdev); | |
400 | ||
401 | return s->smb.smbus; | |
402 | } | |
403 | ||
40021f08 AL |
404 | static Property via_pm_properties[] = { |
405 | DEFINE_PROP_UINT32("smb_io_base", VT686PMState, smb_io_base, 0), | |
406 | DEFINE_PROP_END_OF_LIST(), | |
407 | }; | |
408 | ||
409 | static void via_pm_class_init(ObjectClass *klass, void *data) | |
410 | { | |
39bffca2 | 411 | DeviceClass *dc = DEVICE_CLASS(klass); |
40021f08 AL |
412 | PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); |
413 | ||
9af21dbe | 414 | k->realize = vt82c686b_pm_realize; |
40021f08 AL |
415 | k->config_write = pm_write_config; |
416 | k->vendor_id = PCI_VENDOR_ID_VIA; | |
417 | k->device_id = PCI_DEVICE_ID_VIA_ACPI; | |
418 | k->class_id = PCI_CLASS_BRIDGE_OTHER; | |
419 | k->revision = 0x40; | |
39bffca2 AL |
420 | dc->desc = "PM"; |
421 | dc->vmsd = &vmstate_acpi; | |
125ee0ed | 422 | set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories); |
39bffca2 | 423 | dc->props = via_pm_properties; |
40021f08 AL |
424 | } |
425 | ||
8c43a6f0 | 426 | static const TypeInfo via_pm_info = { |
417349e6 | 427 | .name = TYPE_VT82C686B_PM_DEVICE, |
39bffca2 AL |
428 | .parent = TYPE_PCI_DEVICE, |
429 | .instance_size = sizeof(VT686PMState), | |
430 | .class_init = via_pm_class_init, | |
fd3b02c8 EH |
431 | .interfaces = (InterfaceInfo[]) { |
432 | { INTERFACE_CONVENTIONAL_PCI_DEVICE }, | |
433 | { }, | |
434 | }, | |
edf79e66 HC |
435 | }; |
436 | ||
edf79e66 HC |
437 | static const VMStateDescription vmstate_via = { |
438 | .name = "vt82c686b", | |
439 | .version_id = 1, | |
440 | .minimum_version_id = 1, | |
d49805ae | 441 | .fields = (VMStateField[]) { |
edf79e66 HC |
442 | VMSTATE_PCI_DEVICE(dev, VT82C686BState), |
443 | VMSTATE_END_OF_LIST() | |
444 | } | |
445 | }; | |
446 | ||
447 | /* init the PCI-to-ISA bridge */ | |
9af21dbe | 448 | static void vt82c686b_realize(PCIDevice *d, Error **errp) |
edf79e66 | 449 | { |
417349e6 | 450 | VT82C686BState *vt82c = VT82C686B_DEVICE(d); |
edf79e66 | 451 | uint8_t *pci_conf; |
bcc37e24 | 452 | ISABus *isa_bus; |
edf79e66 HC |
453 | uint8_t *wmask; |
454 | int i; | |
455 | ||
bb2ed009 | 456 | isa_bus = isa_bus_new(DEVICE(d), get_system_memory(), |
d10e5432 MA |
457 | pci_address_space_io(d), errp); |
458 | if (!isa_bus) { | |
459 | return; | |
460 | } | |
edf79e66 HC |
461 | |
462 | pci_conf = d->config; | |
edf79e66 | 463 | pci_config_set_prog_interface(pci_conf, 0x0); |
edf79e66 HC |
464 | |
465 | wmask = d->wmask; | |
466 | for (i = 0x00; i < 0xff; i++) { | |
467 | if (i<=0x03 || (i>=0x08 && i<=0x3f)) { | |
468 | wmask[i] = 0x00; | |
469 | } | |
470 | } | |
471 | ||
db10ca90 | 472 | memory_region_init_io(&vt82c->superio, OBJECT(d), &superio_ops, |
2c9b15ca | 473 | &vt82c->superio_conf, "superio", 2); |
bcc37e24 JK |
474 | memory_region_set_enabled(&vt82c->superio, false); |
475 | /* The floppy also uses 0x3f0 and 0x3f1. | |
476 | * But we do not emulate a floppy, so just set it here. */ | |
477 | memory_region_add_subregion(isa_bus->address_space_io, 0x3f0, | |
478 | &vt82c->superio); | |
479 | ||
edf79e66 | 480 | qemu_register_reset(vt82c686b_reset, d); |
edf79e66 HC |
481 | } |
482 | ||
728d8910 | 483 | ISABus *vt82c686b_isa_init(PCIBus *bus, int devfn) |
edf79e66 HC |
484 | { |
485 | PCIDevice *d; | |
486 | ||
417349e6 GA |
487 | d = pci_create_simple_multifunction(bus, devfn, true, |
488 | TYPE_VT82C686B_DEVICE); | |
edf79e66 | 489 | |
2ae0e48d | 490 | return ISA_BUS(qdev_get_child_bus(DEVICE(d), "isa.0")); |
edf79e66 HC |
491 | } |
492 | ||
40021f08 AL |
493 | static void via_class_init(ObjectClass *klass, void *data) |
494 | { | |
39bffca2 | 495 | DeviceClass *dc = DEVICE_CLASS(klass); |
40021f08 AL |
496 | PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); |
497 | ||
9af21dbe | 498 | k->realize = vt82c686b_realize; |
40021f08 AL |
499 | k->config_write = vt82c686b_write_config; |
500 | k->vendor_id = PCI_VENDOR_ID_VIA; | |
501 | k->device_id = PCI_DEVICE_ID_VIA_ISA_BRIDGE; | |
502 | k->class_id = PCI_CLASS_BRIDGE_ISA; | |
503 | k->revision = 0x40; | |
39bffca2 | 504 | dc->desc = "ISA bridge"; |
39bffca2 | 505 | dc->vmsd = &vmstate_via; |
04916ee9 MA |
506 | /* |
507 | * Reason: part of VIA VT82C686 southbridge, needs to be wired up, | |
508 | * e.g. by mips_fulong2e_init() | |
509 | */ | |
e90f2a8c | 510 | dc->user_creatable = false; |
40021f08 AL |
511 | } |
512 | ||
8c43a6f0 | 513 | static const TypeInfo via_info = { |
417349e6 | 514 | .name = TYPE_VT82C686B_DEVICE, |
39bffca2 AL |
515 | .parent = TYPE_PCI_DEVICE, |
516 | .instance_size = sizeof(VT82C686BState), | |
517 | .class_init = via_class_init, | |
fd3b02c8 EH |
518 | .interfaces = (InterfaceInfo[]) { |
519 | { INTERFACE_CONVENTIONAL_PCI_DEVICE }, | |
520 | { }, | |
521 | }, | |
edf79e66 HC |
522 | }; |
523 | ||
98cf824b PMD |
524 | static void vt82c686b_superio_class_init(ObjectClass *klass, void *data) |
525 | { | |
526 | ISASuperIOClass *sc = ISA_SUPERIO_CLASS(klass); | |
527 | ||
528 | sc->serial.count = 2; | |
529 | sc->parallel.count = 1; | |
530 | sc->ide.count = 0; | |
531 | sc->floppy.count = 1; | |
532 | } | |
533 | ||
534 | static const TypeInfo via_superio_info = { | |
535 | .name = TYPE_VT82C686B_SUPERIO, | |
536 | .parent = TYPE_ISA_SUPERIO, | |
537 | .instance_size = sizeof(ISASuperIODevice), | |
538 | .class_size = sizeof(ISASuperIOClass), | |
539 | .class_init = vt82c686b_superio_class_init, | |
540 | }; | |
541 | ||
83f7d43a | 542 | static void vt82c686b_register_types(void) |
edf79e66 | 543 | { |
83f7d43a AF |
544 | type_register_static(&via_ac97_info); |
545 | type_register_static(&via_mc97_info); | |
546 | type_register_static(&via_pm_info); | |
98cf824b | 547 | type_register_static(&via_superio_info); |
39bffca2 | 548 | type_register_static(&via_info); |
edf79e66 | 549 | } |
83f7d43a AF |
550 | |
551 | type_init(vt82c686b_register_types) |