]> git.ipfire.org Git - thirdparty/qemu.git/blame - target-sparc/translate.c
projects / thirdparty / qemu.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
AMD NOR flash device support (initial patch by Jocelyn Mayer)
[thirdparty/qemu.git] / target-sparc / translate.c
CommitLineData
7a3f1944
FB		 1/*
2 SPARC translation
3
4 Copyright (C) 2003 Thomas M. Ogrisegg <tom@fnord.at>
3475187d 5 Copyright (C) 2003-2005 Fabrice Bellard
7a3f1944
FB		 6
7 This library is free software; you can redistribute it and/or
8 modify it under the terms of the GNU Lesser General Public
9 License as published by the Free Software Foundation; either
10 version 2 of the License, or (at your option) any later version.
11
12 This library is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 Lesser General Public License for more details.
16
17 You should have received a copy of the GNU Lesser General Public
18 License along with this library; if not, write to the Free Software
19 Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 */
21
22/*
7a3f1944
FB		 23 TODO-list:
24
3475187d 25 Rest of V9 instructions, VIS instructions
bd497938 26 NPC/PC static optimisations (use JUMP_TB when possible)
7a3f1944 27 Optimize synthetic instructions
3475187d
FB		 28 Optional alignment check
29 128-bit float
30 Tagged add/sub
bd497938 31*/
7a3f1944
FB		 32
33#include <stdarg.h>
34#include <stdlib.h>
35#include <stdio.h>
36#include <string.h>
37#include <inttypes.h>
38
39#include "cpu.h"
40#include "exec-all.h"
41#include "disas.h"
42
43#define DEBUG_DISAS
44
72cbca10
FB		 45#define DYNAMIC_PC 1 /* dynamic pc value */
46#define JUMP_PC 2 /* dynamic pc value which takes only two values
47 according to jump_pc[T2] */
48
7a3f1944 49typedef struct DisasContext {
72cbca10
FB		 50 target_ulong pc; /* current Program Counter: integer or DYNAMIC_PC */
51 target_ulong npc; /* next PC: integer or DYNAMIC_PC or JUMP_PC */
52 target_ulong jump_pc[2]; /* used when JUMP_PC pc value is used */
cf495bcf 53 int is_br;
e8af50a3 54 int mem_idx;
cf495bcf 55 struct TranslationBlock *tb;
7a3f1944
FB		 56} DisasContext;
57
58static uint16_t *gen_opc_ptr;
59static uint32_t *gen_opparam_ptr;
60extern FILE *logfile;
61extern int loglevel;
62
63enum {
64#define DEF(s,n,copy_size) INDEX_op_ ## s,
65#include "opc.h"
66#undef DEF
cf495bcf 67 NB_OPS
7a3f1944
FB		 68};
69
70#include "gen-op.h"
71
3475187d 72// This function uses non-native bit order
7a3f1944
FB		 73#define GET_FIELD(X, FROM, TO) \
74 ((X) >> (31 - (TO)) & ((1 << ((TO) - (FROM) + 1)) - 1))
75
3475187d
FB		 76// This function uses the order in the manuals, i.e. bit 0 is 2^0
77#define GET_FIELD_SP(X, FROM, TO) \
78 GET_FIELD(X, 31 - (TO), 31 - (FROM))
79
80#define GET_FIELDs(x,a,b) sign_extend (GET_FIELD(x,a,b), (b) - (a) + 1)
81#define GET_FIELD_SPs(x,a,b) sign_extend (GET_FIELD_SP(x,a,b), 32 - ((b) - (a) + 1))
82
83#ifdef TARGET_SPARC64
84#define DFPREG(r) (((r & 1) << 6) | (r & 0x1e))
85#else
86#define DFPREG(r) (r)
87#endif
88
83469015
FB		 89#ifdef USE_DIRECT_JUMP
90#define TBPARAM(x)
91#else
92#define TBPARAM(x) (long)(x)
93#endif
94
3475187d
FB		 95static int sign_extend(int x, int len)
96{
97 len = 32 - len;
98 return (x << len) >> len;
99}
100
7a3f1944
FB		 101#define IS_IMM (insn & (1<<13))
102
cf495bcf 103static void disas_sparc_insn(DisasContext * dc);
7a3f1944 104
7a3f1944 105static GenOpFunc *gen_op_movl_TN_reg[2][32] = {
cf495bcf
FB		 106 {
107 gen_op_movl_g0_T0,
108 gen_op_movl_g1_T0,
109 gen_op_movl_g2_T0,
110 gen_op_movl_g3_T0,
111 gen_op_movl_g4_T0,
112 gen_op_movl_g5_T0,
113 gen_op_movl_g6_T0,
114 gen_op_movl_g7_T0,
115 gen_op_movl_o0_T0,
116 gen_op_movl_o1_T0,
117 gen_op_movl_o2_T0,
118 gen_op_movl_o3_T0,
119 gen_op_movl_o4_T0,
120 gen_op_movl_o5_T0,
121 gen_op_movl_o6_T0,
122 gen_op_movl_o7_T0,
123 gen_op_movl_l0_T0,
124 gen_op_movl_l1_T0,
125 gen_op_movl_l2_T0,
126 gen_op_movl_l3_T0,
127 gen_op_movl_l4_T0,
128 gen_op_movl_l5_T0,
129 gen_op_movl_l6_T0,
130 gen_op_movl_l7_T0,
131 gen_op_movl_i0_T0,
132 gen_op_movl_i1_T0,
133 gen_op_movl_i2_T0,
134 gen_op_movl_i3_T0,
135 gen_op_movl_i4_T0,
136 gen_op_movl_i5_T0,
137 gen_op_movl_i6_T0,
138 gen_op_movl_i7_T0,
139 },
140 {
141 gen_op_movl_g0_T1,
142 gen_op_movl_g1_T1,
143 gen_op_movl_g2_T1,
144 gen_op_movl_g3_T1,
145 gen_op_movl_g4_T1,
146 gen_op_movl_g5_T1,
147 gen_op_movl_g6_T1,
148 gen_op_movl_g7_T1,
149 gen_op_movl_o0_T1,
150 gen_op_movl_o1_T1,
151 gen_op_movl_o2_T1,
152 gen_op_movl_o3_T1,
153 gen_op_movl_o4_T1,
154 gen_op_movl_o5_T1,
155 gen_op_movl_o6_T1,
156 gen_op_movl_o7_T1,
157 gen_op_movl_l0_T1,
158 gen_op_movl_l1_T1,
159 gen_op_movl_l2_T1,
160 gen_op_movl_l3_T1,
161 gen_op_movl_l4_T1,
162 gen_op_movl_l5_T1,
163 gen_op_movl_l6_T1,
164 gen_op_movl_l7_T1,
165 gen_op_movl_i0_T1,
166 gen_op_movl_i1_T1,
167 gen_op_movl_i2_T1,
168 gen_op_movl_i3_T1,
169 gen_op_movl_i4_T1,
170 gen_op_movl_i5_T1,
171 gen_op_movl_i6_T1,
172 gen_op_movl_i7_T1,
173 }
7a3f1944
FB		 174};
175
176static GenOpFunc *gen_op_movl_reg_TN[3][32] = {
cf495bcf
FB		 177 {
178 gen_op_movl_T0_g0,
179 gen_op_movl_T0_g1,
180 gen_op_movl_T0_g2,
181 gen_op_movl_T0_g3,
182 gen_op_movl_T0_g4,
183 gen_op_movl_T0_g5,
184 gen_op_movl_T0_g6,
185 gen_op_movl_T0_g7,
186 gen_op_movl_T0_o0,
187 gen_op_movl_T0_o1,
188 gen_op_movl_T0_o2,
189 gen_op_movl_T0_o3,
190 gen_op_movl_T0_o4,
191 gen_op_movl_T0_o5,
192 gen_op_movl_T0_o6,
193 gen_op_movl_T0_o7,
194 gen_op_movl_T0_l0,
195 gen_op_movl_T0_l1,
196 gen_op_movl_T0_l2,
197 gen_op_movl_T0_l3,
198 gen_op_movl_T0_l4,
199 gen_op_movl_T0_l5,
200 gen_op_movl_T0_l6,
201 gen_op_movl_T0_l7,
202 gen_op_movl_T0_i0,
203 gen_op_movl_T0_i1,
204 gen_op_movl_T0_i2,
205 gen_op_movl_T0_i3,
206 gen_op_movl_T0_i4,
207 gen_op_movl_T0_i5,
208 gen_op_movl_T0_i6,
209 gen_op_movl_T0_i7,
210 },
211 {
212 gen_op_movl_T1_g0,
213 gen_op_movl_T1_g1,
214 gen_op_movl_T1_g2,
215 gen_op_movl_T1_g3,
216 gen_op_movl_T1_g4,
217 gen_op_movl_T1_g5,
218 gen_op_movl_T1_g6,
219 gen_op_movl_T1_g7,
220 gen_op_movl_T1_o0,
221 gen_op_movl_T1_o1,
222 gen_op_movl_T1_o2,
223 gen_op_movl_T1_o3,
224 gen_op_movl_T1_o4,
225 gen_op_movl_T1_o5,
226 gen_op_movl_T1_o6,
227 gen_op_movl_T1_o7,
228 gen_op_movl_T1_l0,
229 gen_op_movl_T1_l1,
230 gen_op_movl_T1_l2,
231 gen_op_movl_T1_l3,
232 gen_op_movl_T1_l4,
233 gen_op_movl_T1_l5,
234 gen_op_movl_T1_l6,
235 gen_op_movl_T1_l7,
236 gen_op_movl_T1_i0,
237 gen_op_movl_T1_i1,
238 gen_op_movl_T1_i2,
239 gen_op_movl_T1_i3,
240 gen_op_movl_T1_i4,
241 gen_op_movl_T1_i5,
242 gen_op_movl_T1_i6,
243 gen_op_movl_T1_i7,
244 },
245 {
246 gen_op_movl_T2_g0,
247 gen_op_movl_T2_g1,
248 gen_op_movl_T2_g2,
249 gen_op_movl_T2_g3,
250 gen_op_movl_T2_g4,
251 gen_op_movl_T2_g5,
252 gen_op_movl_T2_g6,
253 gen_op_movl_T2_g7,
254 gen_op_movl_T2_o0,
255 gen_op_movl_T2_o1,
256 gen_op_movl_T2_o2,
257 gen_op_movl_T2_o3,
258 gen_op_movl_T2_o4,
259 gen_op_movl_T2_o5,
260 gen_op_movl_T2_o6,
261 gen_op_movl_T2_o7,
262 gen_op_movl_T2_l0,
263 gen_op_movl_T2_l1,
264 gen_op_movl_T2_l2,
265 gen_op_movl_T2_l3,
266 gen_op_movl_T2_l4,
267 gen_op_movl_T2_l5,
268 gen_op_movl_T2_l6,
269 gen_op_movl_T2_l7,
270 gen_op_movl_T2_i0,
271 gen_op_movl_T2_i1,
272 gen_op_movl_T2_i2,
273 gen_op_movl_T2_i3,
274 gen_op_movl_T2_i4,
275 gen_op_movl_T2_i5,
276 gen_op_movl_T2_i6,
277 gen_op_movl_T2_i7,
278 }
7a3f1944
FB		 279};
280
281static GenOpFunc1 *gen_op_movl_TN_im[3] = {
cf495bcf
FB		 282 gen_op_movl_T0_im,
283 gen_op_movl_T1_im,
284 gen_op_movl_T2_im
7a3f1944
FB		 285};
286
3475187d
FB		 287// Sign extending version
288static GenOpFunc1 * const gen_op_movl_TN_sim[3] = {
289 gen_op_movl_T0_sim,
290 gen_op_movl_T1_sim,
291 gen_op_movl_T2_sim
292};
293
294#ifdef TARGET_SPARC64
295#define GEN32(func, NAME) \
296static GenOpFunc *NAME ## _table [64] = { \
297NAME ## 0, NAME ## 1, NAME ## 2, NAME ## 3, \
298NAME ## 4, NAME ## 5, NAME ## 6, NAME ## 7, \
299NAME ## 8, NAME ## 9, NAME ## 10, NAME ## 11, \
300NAME ## 12, NAME ## 13, NAME ## 14, NAME ## 15, \
301NAME ## 16, NAME ## 17, NAME ## 18, NAME ## 19, \
302NAME ## 20, NAME ## 21, NAME ## 22, NAME ## 23, \
303NAME ## 24, NAME ## 25, NAME ## 26, NAME ## 27, \
304NAME ## 28, NAME ## 29, NAME ## 30, NAME ## 31, \
305NAME ## 32, 0, NAME ## 34, 0, NAME ## 36, 0, NAME ## 38, 0, \
306NAME ## 40, 0, NAME ## 42, 0, NAME ## 44, 0, NAME ## 46, 0, \
307NAME ## 48, 0, NAME ## 50, 0, NAME ## 52, 0, NAME ## 54, 0, \
308NAME ## 56, 0, NAME ## 58, 0, NAME ## 60, 0, NAME ## 62, 0, \
309}; \
310static inline void func(int n) \
311{ \
312 NAME ## _table[n](); \
313}
314#else
e8af50a3
FB		 315#define GEN32(func, NAME) \
316static GenOpFunc *NAME ## _table [32] = { \
317NAME ## 0, NAME ## 1, NAME ## 2, NAME ## 3, \
318NAME ## 4, NAME ## 5, NAME ## 6, NAME ## 7, \
319NAME ## 8, NAME ## 9, NAME ## 10, NAME ## 11, \
320NAME ## 12, NAME ## 13, NAME ## 14, NAME ## 15, \
321NAME ## 16, NAME ## 17, NAME ## 18, NAME ## 19, \
322NAME ## 20, NAME ## 21, NAME ## 22, NAME ## 23, \
323NAME ## 24, NAME ## 25, NAME ## 26, NAME ## 27, \
324NAME ## 28, NAME ## 29, NAME ## 30, NAME ## 31, \
325}; \
326static inline void func(int n) \
327{ \
328 NAME ## _table[n](); \
329}
3475187d 330#endif
e8af50a3
FB		 331
332/* floating point registers moves */
333GEN32(gen_op_load_fpr_FT0, gen_op_load_fpr_FT0_fprf);
334GEN32(gen_op_load_fpr_FT1, gen_op_load_fpr_FT1_fprf);
e8af50a3
FB		 335GEN32(gen_op_store_FT0_fpr, gen_op_store_FT0_fpr_fprf);
336GEN32(gen_op_store_FT1_fpr, gen_op_store_FT1_fpr_fprf);
e8af50a3
FB		 337
338GEN32(gen_op_load_fpr_DT0, gen_op_load_fpr_DT0_fprf);
339GEN32(gen_op_load_fpr_DT1, gen_op_load_fpr_DT1_fprf);
e8af50a3
FB		 340GEN32(gen_op_store_DT0_fpr, gen_op_store_DT0_fpr_fprf);
341GEN32(gen_op_store_DT1_fpr, gen_op_store_DT1_fpr_fprf);
e8af50a3 342
3475187d
FB		 343#ifdef TARGET_SPARC64
344// 'a' versions allowed to user depending on asi
345#if defined(CONFIG_USER_ONLY)
346#define supervisor(dc) 0
347#define gen_op_ldst(name) gen_op_##name##_raw()
348#define OP_LD_TABLE(width) \
349 static void gen_op_##width##a(int insn, int is_ld, int size, int sign) \
350 { \
351 int asi, offset; \
352 \
353 if (IS_IMM) { \
354 offset = GET_FIELD(insn, 25, 31); \
355 if (is_ld) \
356 gen_op_ld_asi_reg(offset, size, sign); \
357 else \
358 gen_op_st_asi_reg(offset, size, sign); \
359 return; \
360 } \
361 asi = GET_FIELD(insn, 19, 26); \
362 switch (asi) { \
363 case 0x80: /* Primary address space */ \
364 gen_op_##width##_raw(); \
365 break; \
366 default: \
367 break; \
368 } \
369 }
370
371#else
372#define gen_op_ldst(name) (*gen_op_##name[dc->mem_idx])()
373#define OP_LD_TABLE(width) \
374 static GenOpFunc *gen_op_##width[] = { \
375 &gen_op_##width##_user, \
376 &gen_op_##width##_kernel, \
377 }; \
378 \
379 static void gen_op_##width##a(int insn, int is_ld, int size, int sign) \
380 { \
381 int asi, offset; \
382 \
383 if (IS_IMM) { \
384 offset = GET_FIELD(insn, 25, 31); \
385 if (is_ld) \
386 gen_op_ld_asi_reg(offset, size, sign); \
387 else \
388 gen_op_st_asi_reg(offset, size, sign); \
389 return; \
390 } \
391 asi = GET_FIELD(insn, 19, 26); \
392 if (is_ld) \
393 gen_op_ld_asi(asi, size, sign); \
394 else \
395 gen_op_st_asi(asi, size, sign); \
396 }
397
398#define supervisor(dc) (dc->mem_idx == 1)
399#endif
400#else
e8af50a3
FB		 401#if defined(CONFIG_USER_ONLY)
402#define gen_op_ldst(name) gen_op_##name##_raw()
0fa85d43 403#define OP_LD_TABLE(width)
e8af50a3
FB		 404#define supervisor(dc) 0
405#else
406#define gen_op_ldst(name) (*gen_op_##name[dc->mem_idx])()
407#define OP_LD_TABLE(width) \
408static GenOpFunc *gen_op_##width[] = { \
409 &gen_op_##width##_user, \
410 &gen_op_##width##_kernel, \
411}; \
412 \
413static void gen_op_##width##a(int insn, int is_ld, int size, int sign) \
414{ \
415 int asi; \
416 \
417 asi = GET_FIELD(insn, 19, 26); \
418 switch (asi) { \
419 case 10: /* User data access */ \
420 gen_op_##width##_user(); \
421 break; \
422 case 11: /* Supervisor data access */ \
423 gen_op_##width##_kernel(); \
424 break; \
425 case 0x20 ... 0x2f: /* MMU passthrough */ \
426 if (is_ld) \
427 gen_op_ld_asi(asi, size, sign); \
428 else \
429 gen_op_st_asi(asi, size, sign); \
430 break; \
431 default: \
432 if (is_ld) \
433 gen_op_ld_asi(asi, size, sign); \
434 else \
435 gen_op_st_asi(asi, size, sign); \
436 break; \
437 } \
438}
439
440#define supervisor(dc) (dc->mem_idx == 1)
441#endif
3475187d 442#endif
e8af50a3
FB		 443
444OP_LD_TABLE(ld);
445OP_LD_TABLE(st);
446OP_LD_TABLE(ldub);
447OP_LD_TABLE(lduh);
448OP_LD_TABLE(ldsb);
449OP_LD_TABLE(ldsh);
450OP_LD_TABLE(stb);
451OP_LD_TABLE(sth);
452OP_LD_TABLE(std);
453OP_LD_TABLE(ldstub);
454OP_LD_TABLE(swap);
455OP_LD_TABLE(ldd);
456OP_LD_TABLE(stf);
457OP_LD_TABLE(stdf);
458OP_LD_TABLE(ldf);
459OP_LD_TABLE(lddf);
460
3475187d
FB		 461#ifdef TARGET_SPARC64
462OP_LD_TABLE(ldsw);
463OP_LD_TABLE(ldx);
464OP_LD_TABLE(stx);
465OP_LD_TABLE(cas);
466OP_LD_TABLE(casx);
467#endif
468
469static inline void gen_movl_imm_TN(int reg, uint32_t imm)
7a3f1944 470{
83469015 471 gen_op_movl_TN_im[reg](imm);
7a3f1944
FB		 472}
473
3475187d 474static inline void gen_movl_imm_T1(uint32_t val)
7a3f1944 475{
cf495bcf 476 gen_movl_imm_TN(1, val);
7a3f1944
FB		 477}
478
3475187d 479static inline void gen_movl_imm_T0(uint32_t val)
7a3f1944 480{
cf495bcf 481 gen_movl_imm_TN(0, val);
7a3f1944
FB		 482}
483
3475187d
FB		 484static inline void gen_movl_simm_TN(int reg, int32_t imm)
485{
486 gen_op_movl_TN_sim[reg](imm);
487}
488
489static inline void gen_movl_simm_T1(int32_t val)
490{
491 gen_movl_simm_TN(1, val);
492}
493
494static inline void gen_movl_simm_T0(int32_t val)
495{
496 gen_movl_simm_TN(0, val);
497}
498
cf495bcf 499static inline void gen_movl_reg_TN(int reg, int t)
7a3f1944 500{
cf495bcf
FB		 501 if (reg)
502 gen_op_movl_reg_TN[t][reg] ();
503 else
504 gen_movl_imm_TN(t, 0);
7a3f1944
FB		 505}
506
cf495bcf 507static inline void gen_movl_reg_T0(int reg)
7a3f1944 508{
cf495bcf 509 gen_movl_reg_TN(reg, 0);
7a3f1944
FB		 510}
511
cf495bcf 512static inline void gen_movl_reg_T1(int reg)
7a3f1944 513{
cf495bcf 514 gen_movl_reg_TN(reg, 1);
7a3f1944
FB		 515}
516
cf495bcf 517static inline void gen_movl_reg_T2(int reg)
7a3f1944 518{
cf495bcf 519 gen_movl_reg_TN(reg, 2);
7a3f1944
FB		 520}
521
cf495bcf 522static inline void gen_movl_TN_reg(int reg, int t)
7a3f1944 523{
cf495bcf
FB		 524 if (reg)
525 gen_op_movl_TN_reg[t][reg] ();
7a3f1944
FB		 526}
527
cf495bcf 528static inline void gen_movl_T0_reg(int reg)
7a3f1944 529{
cf495bcf 530 gen_movl_TN_reg(reg, 0);
7a3f1944
FB		 531}
532
cf495bcf 533static inline void gen_movl_T1_reg(int reg)
7a3f1944 534{
cf495bcf 535 gen_movl_TN_reg(reg, 1);
7a3f1944
FB		 536}
537
3475187d
FB		 538static inline void gen_jmp_im(target_ulong pc)
539{
540#ifdef TARGET_SPARC64
541 if (pc == (uint32_t)pc) {
542 gen_op_jmp_im(pc);
543 } else {
544 gen_op_jmp_im64(pc >> 32, pc);
545 }
546#else
547 gen_op_jmp_im(pc);
548#endif
549}
550
551static inline void gen_movl_npc_im(target_ulong npc)
552{
553#ifdef TARGET_SPARC64
554 if (npc == (uint32_t)npc) {
555 gen_op_movl_npc_im(npc);
556 } else {
557 gen_op_movq_npc_im64(npc >> 32, npc);
558 }
559#else
560 gen_op_movl_npc_im(npc);
561#endif
562}
563
6e256c93
FB		 564static inline void gen_goto_tb(DisasContext *s, int tb_num,
565 target_ulong pc, target_ulong npc)
566{
567 TranslationBlock *tb;
568
569 tb = s->tb;
570 if ((pc & TARGET_PAGE_MASK) == (tb->pc & TARGET_PAGE_MASK) &&
571 (npc & TARGET_PAGE_MASK) == (tb->pc & TARGET_PAGE_MASK)) {
572 /* jump to same page: we can use a direct jump */
573 if (tb_num == 0)
574 gen_op_goto_tb0(TBPARAM(tb));
575 else
576 gen_op_goto_tb1(TBPARAM(tb));
577 gen_jmp_im(pc);
578 gen_movl_npc_im(npc);
579 gen_op_movl_T0_im((long)tb + tb_num);
580 gen_op_exit_tb();
581 } else {
582 /* jump to another page: currently not optimized */
583 gen_jmp_im(pc);
584 gen_movl_npc_im(npc);
585 gen_op_movl_T0_0();
586 gen_op_exit_tb();
587 }
588}
589
83469015
FB		 590static inline void gen_branch2(DisasContext *dc, long tb, target_ulong pc1, target_ulong pc2)
591{
592 int l1;
593
594 l1 = gen_new_label();
595
596 gen_op_jz_T2_label(l1);
597
6e256c93 598 gen_goto_tb(dc, 0, pc1, pc1 + 4);
83469015
FB		 599
600 gen_set_label(l1);
6e256c93 601 gen_goto_tb(dc, 1, pc2, pc2 + 4);
83469015
FB		 602}
603
604static inline void gen_branch_a(DisasContext *dc, long tb, target_ulong pc1, target_ulong pc2)
605{
606 int l1;
607
608 l1 = gen_new_label();
609
610 gen_op_jz_T2_label(l1);
611
6e256c93 612 gen_goto_tb(dc, 0, pc2, pc1);
83469015
FB		 613
614 gen_set_label(l1);
6e256c93 615 gen_goto_tb(dc, 1, pc2 + 4, pc2 + 8);
83469015
FB		 616}
617
618static inline void gen_branch(DisasContext *dc, long tb, target_ulong pc, target_ulong npc)
619{
6e256c93 620 gen_goto_tb(dc, 0, pc, npc);
83469015
FB		 621}
622
623static inline void gen_generic_branch(DisasContext *dc, target_ulong npc1, target_ulong npc2)
624{
625 int l1, l2;
626
627 l1 = gen_new_label();
628 l2 = gen_new_label();
629 gen_op_jz_T2_label(l1);
630
631 gen_movl_npc_im(npc1);
632 gen_op_jmp_label(l2);
633
634 gen_set_label(l1);
635 gen_movl_npc_im(npc2);
636 gen_set_label(l2);
637}
638
639/* call this function before using T2 as it may have been set for a jump */
640static inline void flush_T2(DisasContext * dc)
641{
642 if (dc->npc == JUMP_PC) {
643 gen_generic_branch(dc, dc->jump_pc[0], dc->jump_pc[1]);
644 dc->npc = DYNAMIC_PC;
645 }
646}
647
72cbca10
FB		 648static inline void save_npc(DisasContext * dc)
649{
650 if (dc->npc == JUMP_PC) {
83469015 651 gen_generic_branch(dc, dc->jump_pc[0], dc->jump_pc[1]);
72cbca10
FB		 652 dc->npc = DYNAMIC_PC;
653 } else if (dc->npc != DYNAMIC_PC) {
3475187d 654 gen_movl_npc_im(dc->npc);
72cbca10
FB		 655 }
656}
657
658static inline void save_state(DisasContext * dc)
659{
3475187d 660 gen_jmp_im(dc->pc);
72cbca10
FB		 661 save_npc(dc);
662}
663
0bee699e
FB		 664static inline void gen_mov_pc_npc(DisasContext * dc)
665{
666 if (dc->npc == JUMP_PC) {
83469015 667 gen_generic_branch(dc, dc->jump_pc[0], dc->jump_pc[1]);
0bee699e
FB		 668 gen_op_mov_pc_npc();
669 dc->pc = DYNAMIC_PC;
670 } else if (dc->npc == DYNAMIC_PC) {
671 gen_op_mov_pc_npc();
672 dc->pc = DYNAMIC_PC;
673 } else {
674 dc->pc = dc->npc;
675 }
676}
677
3475187d
FB		 678static GenOpFunc * const gen_cond[2][16] = {
679 {
680 gen_op_eval_ba,
681 gen_op_eval_be,
682 gen_op_eval_ble,
683 gen_op_eval_bl,
684 gen_op_eval_bleu,
685 gen_op_eval_bcs,
686 gen_op_eval_bneg,
687 gen_op_eval_bvs,
688 gen_op_eval_bn,
689 gen_op_eval_bne,
690 gen_op_eval_bg,
691 gen_op_eval_bge,
692 gen_op_eval_bgu,
693 gen_op_eval_bcc,
694 gen_op_eval_bpos,
695 gen_op_eval_bvc,
696 },
697 {
698#ifdef TARGET_SPARC64
699 gen_op_eval_ba,
700 gen_op_eval_xbe,
701 gen_op_eval_xble,
702 gen_op_eval_xbl,
703 gen_op_eval_xbleu,
704 gen_op_eval_xbcs,
705 gen_op_eval_xbneg,
706 gen_op_eval_xbvs,
707 gen_op_eval_bn,
708 gen_op_eval_xbne,
709 gen_op_eval_xbg,
710 gen_op_eval_xbge,
711 gen_op_eval_xbgu,
712 gen_op_eval_xbcc,
713 gen_op_eval_xbpos,
714 gen_op_eval_xbvc,
715#endif
716 },
717};
718
719static GenOpFunc * const gen_fcond[4][16] = {
720 {
721 gen_op_eval_ba,
722 gen_op_eval_fbne,
723 gen_op_eval_fblg,
724 gen_op_eval_fbul,
725 gen_op_eval_fbl,
726 gen_op_eval_fbug,
727 gen_op_eval_fbg,
728 gen_op_eval_fbu,
729 gen_op_eval_bn,
730 gen_op_eval_fbe,
731 gen_op_eval_fbue,
732 gen_op_eval_fbge,
733 gen_op_eval_fbuge,
734 gen_op_eval_fble,
735 gen_op_eval_fbule,
736 gen_op_eval_fbo,
737 },
738#ifdef TARGET_SPARC64
739 {
740 gen_op_eval_ba,
741 gen_op_eval_fbne_fcc1,
742 gen_op_eval_fblg_fcc1,
743 gen_op_eval_fbul_fcc1,
744 gen_op_eval_fbl_fcc1,
745 gen_op_eval_fbug_fcc1,
746 gen_op_eval_fbg_fcc1,
747 gen_op_eval_fbu_fcc1,
748 gen_op_eval_bn,
749 gen_op_eval_fbe_fcc1,
750 gen_op_eval_fbue_fcc1,
751 gen_op_eval_fbge_fcc1,
752 gen_op_eval_fbuge_fcc1,
753 gen_op_eval_fble_fcc1,
754 gen_op_eval_fbule_fcc1,
755 gen_op_eval_fbo_fcc1,
756 },
757 {
758 gen_op_eval_ba,
759 gen_op_eval_fbne_fcc2,
760 gen_op_eval_fblg_fcc2,
761 gen_op_eval_fbul_fcc2,
762 gen_op_eval_fbl_fcc2,
763 gen_op_eval_fbug_fcc2,
764 gen_op_eval_fbg_fcc2,
765 gen_op_eval_fbu_fcc2,
766 gen_op_eval_bn,
767 gen_op_eval_fbe_fcc2,
768 gen_op_eval_fbue_fcc2,
769 gen_op_eval_fbge_fcc2,
770 gen_op_eval_fbuge_fcc2,
771 gen_op_eval_fble_fcc2,
772 gen_op_eval_fbule_fcc2,
773 gen_op_eval_fbo_fcc2,
774 },
775 {
776 gen_op_eval_ba,
777 gen_op_eval_fbne_fcc3,
778 gen_op_eval_fblg_fcc3,
779 gen_op_eval_fbul_fcc3,
780 gen_op_eval_fbl_fcc3,
781 gen_op_eval_fbug_fcc3,
782 gen_op_eval_fbg_fcc3,
783 gen_op_eval_fbu_fcc3,
784 gen_op_eval_bn,
785 gen_op_eval_fbe_fcc3,
786 gen_op_eval_fbue_fcc3,
787 gen_op_eval_fbge_fcc3,
788 gen_op_eval_fbuge_fcc3,
789 gen_op_eval_fble_fcc3,
790 gen_op_eval_fbule_fcc3,
791 gen_op_eval_fbo_fcc3,
792 },
793#else
794 {}, {}, {},
795#endif
796};
7a3f1944 797
3475187d
FB		 798#ifdef TARGET_SPARC64
799static void gen_cond_reg(int cond)
e8af50a3
FB		 800{
801 switch (cond) {
e8af50a3 802 case 0x1:
3475187d 803 gen_op_eval_brz();
e8af50a3
FB		 804 break;
805 case 0x2:
3475187d 806 gen_op_eval_brlez();
e8af50a3
FB		 807 break;
808 case 0x3:
3475187d 809 gen_op_eval_brlz();
e8af50a3
FB		 810 break;
811 case 0x5:
3475187d 812 gen_op_eval_brnz();
e8af50a3
FB		 813 break;
814 case 0x6:
3475187d 815 gen_op_eval_brgz();
e8af50a3
FB		 816 break;
817 default:
3475187d
FB		 818 case 0x7:
819 gen_op_eval_brgez();
e8af50a3
FB		 820 break;
821 }
822}
3475187d 823#endif
cf495bcf 824
0bee699e 825/* XXX: potentially incorrect if dynamic npc */
3475187d 826static void do_branch(DisasContext * dc, int32_t offset, uint32_t insn, int cc)
7a3f1944 827{
cf495bcf 828 unsigned int cond = GET_FIELD(insn, 3, 6), a = (insn & (1 << 29));
af7bf89b 829 target_ulong target = dc->pc + offset;
3475187d 830
cf495bcf
FB		 831 if (cond == 0x0) {
832 /* unconditional not taken */
833 if (a) {
0bee699e 834 dc->pc = dc->npc + 4;
cf495bcf
FB		 835 dc->npc = dc->pc + 4;
836 } else {
837 dc->pc = dc->npc;
838 dc->npc = dc->pc + 4;
839 }
840 } else if (cond == 0x8) {
841 /* unconditional taken */
842 if (a) {
72cbca10 843 dc->pc = target;
cf495bcf
FB		 844 dc->npc = dc->pc + 4;
845 } else {
846 dc->pc = dc->npc;
72cbca10 847 dc->npc = target;
cf495bcf
FB		 848 }
849 } else {
72cbca10 850 flush_T2(dc);
3475187d 851 gen_cond[cc][cond]();
cf495bcf 852 if (a) {
83469015 853 gen_branch_a(dc, (long)dc->tb, target, dc->npc);
cf495bcf 854 dc->is_br = 1;
cf495bcf
FB		 855 } else {
856 dc->pc = dc->npc;
72cbca10
FB		 857 dc->jump_pc[0] = target;
858 dc->jump_pc[1] = dc->npc + 4;
859 dc->npc = JUMP_PC;
cf495bcf
FB		 860 }
861 }
7a3f1944
FB		 862}
863
0bee699e 864/* XXX: potentially incorrect if dynamic npc */
3475187d 865static void do_fbranch(DisasContext * dc, int32_t offset, uint32_t insn, int cc)
e8af50a3
FB		 866{
867 unsigned int cond = GET_FIELD(insn, 3, 6), a = (insn & (1 << 29));
af7bf89b
FB		 868 target_ulong target = dc->pc + offset;
869
e8af50a3
FB		 870 if (cond == 0x0) {
871 /* unconditional not taken */
872 if (a) {
873 dc->pc = dc->npc + 4;
874 dc->npc = dc->pc + 4;
875 } else {
876 dc->pc = dc->npc;
877 dc->npc = dc->pc + 4;
878 }
879 } else if (cond == 0x8) {
880 /* unconditional taken */
881 if (a) {
882 dc->pc = target;
883 dc->npc = dc->pc + 4;
884 } else {
885 dc->pc = dc->npc;
886 dc->npc = target;
887 }
888 } else {
889 flush_T2(dc);
3475187d 890 gen_fcond[cc][cond]();
e8af50a3 891 if (a) {
83469015 892 gen_branch_a(dc, (long)dc->tb, target, dc->npc);
e8af50a3
FB		 893 dc->is_br = 1;
894 } else {
895 dc->pc = dc->npc;
896 dc->jump_pc[0] = target;
897 dc->jump_pc[1] = dc->npc + 4;
898 dc->npc = JUMP_PC;
899 }
900 }
901}
902
3475187d
FB		 903#ifdef TARGET_SPARC64
904/* XXX: potentially incorrect if dynamic npc */
905static void do_branch_reg(DisasContext * dc, int32_t offset, uint32_t insn)
7a3f1944 906{
3475187d
FB		 907 unsigned int cond = GET_FIELD_SP(insn, 25, 27), a = (insn & (1 << 29));
908 target_ulong target = dc->pc + offset;
909
910 flush_T2(dc);
911 gen_cond_reg(cond);
912 if (a) {
83469015 913 gen_branch_a(dc, (long)dc->tb, target, dc->npc);
3475187d
FB		 914 dc->is_br = 1;
915 } else {
916 dc->pc = dc->npc;
917 dc->jump_pc[0] = target;
918 dc->jump_pc[1] = dc->npc + 4;
919 dc->npc = JUMP_PC;
920 }
7a3f1944
FB		 921}
922
3475187d
FB		 923static GenOpFunc * const gen_fcmps[4] = {
924 gen_op_fcmps,
925 gen_op_fcmps_fcc1,
926 gen_op_fcmps_fcc2,
927 gen_op_fcmps_fcc3,
928};
929
930static GenOpFunc * const gen_fcmpd[4] = {
931 gen_op_fcmpd,
932 gen_op_fcmpd_fcc1,
933 gen_op_fcmpd_fcc2,
934 gen_op_fcmpd_fcc3,
935};
936#endif
937
0bee699e 938/* before an instruction, dc->pc must be static */
cf495bcf
FB		 939static void disas_sparc_insn(DisasContext * dc)
940{
941 unsigned int insn, opc, rs1, rs2, rd;
7a3f1944 942
0fa85d43 943 insn = ldl_code(dc->pc);
cf495bcf 944 opc = GET_FIELD(insn, 0, 1);
7a3f1944 945
cf495bcf
FB		 946 rd = GET_FIELD(insn, 2, 6);
947 switch (opc) {
948 case 0: /* branches/sethi */
949 {
950 unsigned int xop = GET_FIELD(insn, 7, 9);
af7bf89b 951 int32_t target;
cf495bcf 952 switch (xop) {
3475187d 953#ifdef TARGET_SPARC64
af7bf89b 954 case 0x1: /* V9 BPcc */
3475187d
FB		 955 {
956 int cc;
957
958 target = GET_FIELD_SP(insn, 0, 18);
3475187d 959 target = sign_extend(target, 18);
ee6c0b51 960 target <<= 2;
3475187d
FB		 961 cc = GET_FIELD_SP(insn, 20, 21);
962 if (cc == 0)
963 do_branch(dc, target, insn, 0);
964 else if (cc == 2)
965 do_branch(dc, target, insn, 1);
966 else
967 goto illegal_insn;
968 goto jmp_insn;
969 }
af7bf89b 970 case 0x3: /* V9 BPr */
3475187d
FB		 971 {
972 target = GET_FIELD_SP(insn, 0, 13) |
13846e70 973 (GET_FIELD_SP(insn, 20, 21) << 14);
3475187d 974 target = sign_extend(target, 16);
ee6c0b51 975 target <<= 2;
3475187d 976 rs1 = GET_FIELD(insn, 13, 17);
83469015 977 gen_movl_reg_T0(rs1);
3475187d
FB		 978 do_branch_reg(dc, target, insn);
979 goto jmp_insn;
980 }
af7bf89b 981 case 0x5: /* V9 FBPcc */
3475187d
FB		 982 {
983 int cc = GET_FIELD_SP(insn, 20, 21);
984#if !defined(CONFIG_USER_ONLY)
55e4f664 985 save_state(dc);
3475187d
FB		 986 gen_op_trap_ifnofpu();
987#endif
988 target = GET_FIELD_SP(insn, 0, 18);
3475187d 989 target = sign_extend(target, 19);
ee6c0b51 990 target <<= 2;
3475187d
FB		 991 do_fbranch(dc, target, insn, cc);
992 goto jmp_insn;
993 }
994#endif
cf495bcf 995 case 0x2: /* BN+x */
7a3f1944 996 {
3475187d 997 target = GET_FIELD(insn, 10, 31);
cf495bcf 998 target = sign_extend(target, 22);
ee6c0b51 999 target <<= 2;
3475187d 1000 do_branch(dc, target, insn, 0);
cf495bcf 1001 goto jmp_insn;
7a3f1944 1002 }
e8af50a3
FB		 1003 case 0x6: /* FBN+x */
1004 {
e80cfcfc 1005#if !defined(CONFIG_USER_ONLY)
55e4f664 1006 save_state(dc);
e80cfcfc
FB		 1007 gen_op_trap_ifnofpu();
1008#endif
3475187d 1009 target = GET_FIELD(insn, 10, 31);
e8af50a3 1010 target = sign_extend(target, 22);
ee6c0b51 1011 target <<= 2;
3475187d 1012 do_fbranch(dc, target, insn, 0);
e8af50a3
FB		 1013 goto jmp_insn;
1014 }
cf495bcf 1015 case 0x4: /* SETHI */
e80cfcfc
FB		 1016#define OPTIM
1017#if defined(OPTIM)
1018 if (rd) { // nop
1019#endif
3475187d
FB		 1020 uint32_t value = GET_FIELD(insn, 10, 31);
1021 gen_movl_imm_T0(value << 10);
e80cfcfc
FB		 1022 gen_movl_T0_reg(rd);
1023#if defined(OPTIM)
1024 }
1025#endif
cf495bcf 1026 break;
3475187d
FB		 1027 case 0x0: /* UNIMPL */
1028 default:
1029 goto illegal_insn;
cf495bcf
FB		 1030 }
1031 break;
1032 }
af7bf89b 1033 break;
cf495bcf
FB		 1034 case 1:
1035 /*CALL*/ {
af7bf89b 1036 target_long target = GET_FIELDs(insn, 2, 31) << 2;
cf495bcf 1037
83469015
FB		 1038#ifdef TARGET_SPARC64
1039 if (dc->pc == (uint32_t)dc->pc) {
1040 gen_op_movl_T0_im(dc->pc);
1041 } else {
1042 gen_op_movq_T0_im64(dc->pc >> 32, dc->pc);
1043 }
1044#else
af7bf89b 1045 gen_op_movl_T0_im(dc->pc);
83469015 1046#endif
cf495bcf 1047 gen_movl_T0_reg(15);
af7bf89b 1048 target += dc->pc;
0bee699e 1049 gen_mov_pc_npc(dc);
72cbca10 1050 dc->npc = target;
cf495bcf
FB		 1051 }
1052 goto jmp_insn;
1053 case 2: /* FPU & Logical Operations */
1054 {
1055 unsigned int xop = GET_FIELD(insn, 7, 12);
1056 if (xop == 0x3a) { /* generate trap */
1057 int cond;
3475187d 1058
cf495bcf
FB		 1059 rs1 = GET_FIELD(insn, 13, 17);
1060 gen_movl_reg_T0(rs1);
1061 if (IS_IMM) {
e8af50a3 1062 rs2 = GET_FIELD(insn, 25, 31);
e80cfcfc 1063#if defined(OPTIM)
e8af50a3 1064 if (rs2 != 0) {
e80cfcfc 1065#endif
3475187d 1066 gen_movl_simm_T1(rs2);
e80cfcfc
FB		 1067 gen_op_add_T1_T0();
1068#if defined(OPTIM)
e8af50a3 1069 }
e80cfcfc 1070#endif
cf495bcf
FB		 1071 } else {
1072 rs2 = GET_FIELD(insn, 27, 31);
e80cfcfc
FB		 1073#if defined(OPTIM)
1074 if (rs2 != 0) {
1075#endif
1076 gen_movl_reg_T1(rs2);
1077 gen_op_add_T1_T0();
1078#if defined(OPTIM)
1079 }
1080#endif
cf495bcf 1081 }
cf495bcf
FB		 1082 save_state(dc);
1083 cond = GET_FIELD(insn, 3, 6);
1084 if (cond == 0x8) {
1085 gen_op_trap_T0();
1086 dc->is_br = 1;
1087 goto jmp_insn;
af7bf89b 1088 } else if (cond != 0) {
3475187d
FB		 1089#ifdef TARGET_SPARC64
1090 /* V9 icc/xcc */
1091 int cc = GET_FIELD_SP(insn, 11, 12);
1092 if (cc == 0)
1093 gen_cond[0][cond]();
1094 else if (cc == 2)
1095 gen_cond[1][cond]();
1096 else
1097 goto illegal_insn;
1098#else
1099 gen_cond[0][cond]();
1100#endif
cf495bcf
FB		 1101 gen_op_trapcc_T0();
1102 }
1103 } else if (xop == 0x28) {
1104 rs1 = GET_FIELD(insn, 13, 17);
1105 switch(rs1) {
1106 case 0: /* rdy */
3475187d 1107 gen_op_movtl_T0_env(offsetof(CPUSPARCState, y));
cf495bcf
FB		 1108 gen_movl_T0_reg(rd);
1109 break;
af7bf89b 1110 case 15: /* stbar / V9 membar */
e8af50a3 1111 break; /* no effect? */
3475187d 1112#ifdef TARGET_SPARC64
af7bf89b 1113 case 0x2: /* V9 rdccr */
3475187d
FB		 1114 gen_op_rdccr();
1115 gen_movl_T0_reg(rd);
1116 break;
af7bf89b 1117 case 0x3: /* V9 rdasi */
3475187d
FB		 1118 gen_op_movl_T0_env(offsetof(CPUSPARCState, asi));
1119 gen_movl_T0_reg(rd);
1120 break;
af7bf89b 1121 case 0x4: /* V9 rdtick */
3475187d
FB		 1122 gen_op_rdtick();
1123 gen_movl_T0_reg(rd);
1124 break;
af7bf89b 1125 case 0x5: /* V9 rdpc */
ded3ab80
PB		 1126 if (dc->pc == (uint32_t)dc->pc) {
1127 gen_op_movl_T0_im(dc->pc);
1128 } else {
1129 gen_op_movq_T0_im64(dc->pc >> 32, dc->pc);
1130 }
3475187d
FB		 1131 gen_movl_T0_reg(rd);
1132 break;
af7bf89b 1133 case 0x6: /* V9 rdfprs */
3475187d
FB		 1134 gen_op_movl_T0_env(offsetof(CPUSPARCState, fprs));
1135 gen_movl_T0_reg(rd);
1136 break;
83469015
FB		 1137 case 0x17: /* Tick compare */
1138 gen_op_movtl_T0_env(offsetof(CPUSPARCState, tick_cmpr));
1139 gen_movl_T0_reg(rd);
1140 break;
1141 case 0x18: /* System tick */
1142 gen_op_rdtick(); // XXX
1143 gen_movl_T0_reg(rd);
1144 break;
1145 case 0x19: /* System tick compare */
1146 gen_op_movtl_T0_env(offsetof(CPUSPARCState, stick_cmpr));
1147 gen_movl_T0_reg(rd);
1148 break;
1149 case 0x10: /* Performance Control */
1150 case 0x11: /* Performance Instrumentation Counter */
1151 case 0x12: /* Dispatch Control */
1152 case 0x13: /* Graphics Status */
1153 case 0x14: /* Softint set, WO */
1154 case 0x15: /* Softint clear, WO */
1155 case 0x16: /* Softint write */
3475187d
FB		 1156#endif
1157 default:
cf495bcf
FB		 1158 goto illegal_insn;
1159 }
e8af50a3 1160#if !defined(CONFIG_USER_ONLY)
3475187d
FB		 1161#ifndef TARGET_SPARC64
1162 } else if (xop == 0x29) { /* rdpsr / V9 unimp */
e8af50a3
FB		 1163 if (!supervisor(dc))
1164 goto priv_insn;
1165 gen_op_rdpsr();
1166 gen_movl_T0_reg(rd);
1167 break;
3475187d
FB		 1168#endif
1169 } else if (xop == 0x2a) { /* rdwim / V9 rdpr */
e8af50a3
FB		 1170 if (!supervisor(dc))
1171 goto priv_insn;
3475187d
FB		 1172#ifdef TARGET_SPARC64
1173 rs1 = GET_FIELD(insn, 13, 17);
1174 switch (rs1) {
1175 case 0: // tpc
1176 gen_op_rdtpc();
1177 break;
1178 case 1: // tnpc
1179 gen_op_rdtnpc();
1180 break;
1181 case 2: // tstate
1182 gen_op_rdtstate();
1183 break;
1184 case 3: // tt
1185 gen_op_rdtt();
1186 break;
1187 case 4: // tick
1188 gen_op_rdtick();
1189 break;
1190 case 5: // tba
1191 gen_op_movtl_T0_env(offsetof(CPUSPARCState, tbr));
1192 break;
1193 case 6: // pstate
1194 gen_op_rdpstate();
1195 break;
1196 case 7: // tl
1197 gen_op_movl_T0_env(offsetof(CPUSPARCState, tl));
1198 break;
1199 case 8: // pil
1200 gen_op_movl_T0_env(offsetof(CPUSPARCState, psrpil));
1201 break;
1202 case 9: // cwp
1203 gen_op_rdcwp();
1204 break;
1205 case 10: // cansave
1206 gen_op_movl_T0_env(offsetof(CPUSPARCState, cansave));
1207 break;
1208 case 11: // canrestore
1209 gen_op_movl_T0_env(offsetof(CPUSPARCState, canrestore));
1210 break;
1211 case 12: // cleanwin
1212 gen_op_movl_T0_env(offsetof(CPUSPARCState, cleanwin));
1213 break;
1214 case 13: // otherwin
1215 gen_op_movl_T0_env(offsetof(CPUSPARCState, otherwin));
1216 break;
1217 case 14: // wstate
1218 gen_op_movl_T0_env(offsetof(CPUSPARCState, wstate));
1219 break;
1220 case 31: // ver
1221 gen_op_movtl_T0_env(offsetof(CPUSPARCState, version));
1222 break;
1223 case 15: // fq
1224 default:
1225 goto illegal_insn;
1226 }
1227#else
1228 gen_op_movl_T0_env(offsetof(CPUSPARCState, wim));
1229#endif
e8af50a3
FB		 1230 gen_movl_T0_reg(rd);
1231 break;
3475187d
FB		 1232 } else if (xop == 0x2b) { /* rdtbr / V9 flushw */
1233#ifdef TARGET_SPARC64
1234 gen_op_flushw();
1235#else
e8af50a3
FB		 1236 if (!supervisor(dc))
1237 goto priv_insn;
3475187d 1238 gen_op_movtl_T0_env(offsetof(CPUSPARCState, tbr));
e8af50a3 1239 gen_movl_T0_reg(rd);
3475187d 1240#endif
e8af50a3
FB		 1241 break;
1242#endif
e80cfcfc
FB		 1243 } else if (xop == 0x34) { /* FPU Operations */
1244#if !defined(CONFIG_USER_ONLY)
55e4f664 1245 save_state(dc);
e80cfcfc
FB		 1246 gen_op_trap_ifnofpu();
1247#endif
e8af50a3
FB		 1248 rs1 = GET_FIELD(insn, 13, 17);
1249 rs2 = GET_FIELD(insn, 27, 31);
1250 xop = GET_FIELD(insn, 18, 26);
1251 switch (xop) {
1252 case 0x1: /* fmovs */
1253 gen_op_load_fpr_FT0(rs2);
1254 gen_op_store_FT0_fpr(rd);
1255 break;
1256 case 0x5: /* fnegs */
1257 gen_op_load_fpr_FT1(rs2);
1258 gen_op_fnegs();
1259 gen_op_store_FT0_fpr(rd);
1260 break;
1261 case 0x9: /* fabss */
1262 gen_op_load_fpr_FT1(rs2);
1263 gen_op_fabss();
1264 gen_op_store_FT0_fpr(rd);
1265 break;
1266 case 0x29: /* fsqrts */
1267 gen_op_load_fpr_FT1(rs2);
1268 gen_op_fsqrts();
1269 gen_op_store_FT0_fpr(rd);
1270 break;
1271 case 0x2a: /* fsqrtd */
3475187d 1272 gen_op_load_fpr_DT1(DFPREG(rs2));
e8af50a3 1273 gen_op_fsqrtd();
3475187d 1274 gen_op_store_DT0_fpr(DFPREG(rd));
e8af50a3 1275 break;
e80cfcfc
FB		 1276 case 0x2b: /* fsqrtq */
1277 goto nfpu_insn;
e8af50a3
FB		 1278 case 0x41:
1279 gen_op_load_fpr_FT0(rs1);
1280 gen_op_load_fpr_FT1(rs2);
1281 gen_op_fadds();
1282 gen_op_store_FT0_fpr(rd);
1283 break;
1284 case 0x42:
3475187d
FB		 1285 gen_op_load_fpr_DT0(DFPREG(rs1));
1286 gen_op_load_fpr_DT1(DFPREG(rs2));
e8af50a3 1287 gen_op_faddd();
3475187d 1288 gen_op_store_DT0_fpr(DFPREG(rd));
e8af50a3 1289 break;
e80cfcfc
FB		 1290 case 0x43: /* faddq */
1291 goto nfpu_insn;
e8af50a3
FB		 1292 case 0x45:
1293 gen_op_load_fpr_FT0(rs1);
1294 gen_op_load_fpr_FT1(rs2);
1295 gen_op_fsubs();
1296 gen_op_store_FT0_fpr(rd);
1297 break;
1298 case 0x46:
3475187d
FB		 1299 gen_op_load_fpr_DT0(DFPREG(rs1));
1300 gen_op_load_fpr_DT1(DFPREG(rs2));
e8af50a3 1301 gen_op_fsubd();
3475187d 1302 gen_op_store_DT0_fpr(DFPREG(rd));
e8af50a3 1303 break;
e80cfcfc
FB		 1304 case 0x47: /* fsubq */
1305 goto nfpu_insn;
e8af50a3
FB		 1306 case 0x49:
1307 gen_op_load_fpr_FT0(rs1);
1308 gen_op_load_fpr_FT1(rs2);
1309 gen_op_fmuls();
1310 gen_op_store_FT0_fpr(rd);
1311 break;
1312 case 0x4a:
3475187d
FB		 1313 gen_op_load_fpr_DT0(DFPREG(rs1));
1314 gen_op_load_fpr_DT1(DFPREG(rs2));
e8af50a3
FB		 1315 gen_op_fmuld();
1316 gen_op_store_DT0_fpr(rd);
1317 break;
e80cfcfc
FB		 1318 case 0x4b: /* fmulq */
1319 goto nfpu_insn;
e8af50a3
FB		 1320 case 0x4d:
1321 gen_op_load_fpr_FT0(rs1);
1322 gen_op_load_fpr_FT1(rs2);
1323 gen_op_fdivs();
1324 gen_op_store_FT0_fpr(rd);
1325 break;
1326 case 0x4e:
3475187d
FB		 1327 gen_op_load_fpr_DT0(DFPREG(rs1));
1328 gen_op_load_fpr_DT1(DFPREG(rs2));
e8af50a3 1329 gen_op_fdivd();
3475187d 1330 gen_op_store_DT0_fpr(DFPREG(rd));
e8af50a3 1331 break;
e80cfcfc
FB		 1332 case 0x4f: /* fdivq */
1333 goto nfpu_insn;
e8af50a3
FB		 1334 case 0x69:
1335 gen_op_load_fpr_FT0(rs1);
1336 gen_op_load_fpr_FT1(rs2);
1337 gen_op_fsmuld();
3475187d 1338 gen_op_store_DT0_fpr(DFPREG(rd));
e8af50a3 1339 break;
e80cfcfc
FB		 1340 case 0x6e: /* fdmulq */
1341 goto nfpu_insn;
e8af50a3
FB		 1342 case 0xc4:
1343 gen_op_load_fpr_FT1(rs2);
1344 gen_op_fitos();
1345 gen_op_store_FT0_fpr(rd);
1346 break;
1347 case 0xc6:
3475187d 1348 gen_op_load_fpr_DT1(DFPREG(rs2));
e8af50a3
FB		 1349 gen_op_fdtos();
1350 gen_op_store_FT0_fpr(rd);
1351 break;
e80cfcfc
FB		 1352 case 0xc7: /* fqtos */
1353 goto nfpu_insn;
e8af50a3
FB		 1354 case 0xc8:
1355 gen_op_load_fpr_FT1(rs2);
1356 gen_op_fitod();
3475187d 1357 gen_op_store_DT0_fpr(DFPREG(rd));
e8af50a3
FB		 1358 break;
1359 case 0xc9:
1360 gen_op_load_fpr_FT1(rs2);
1361 gen_op_fstod();
3475187d 1362 gen_op_store_DT0_fpr(DFPREG(rd));
e8af50a3 1363 break;
e80cfcfc
FB		 1364 case 0xcb: /* fqtod */
1365 goto nfpu_insn;
1366 case 0xcc: /* fitoq */
1367 goto nfpu_insn;
1368 case 0xcd: /* fstoq */
1369 goto nfpu_insn;
1370 case 0xce: /* fdtoq */
1371 goto nfpu_insn;
e8af50a3
FB		 1372 case 0xd1:
1373 gen_op_load_fpr_FT1(rs2);
1374 gen_op_fstoi();
1375 gen_op_store_FT0_fpr(rd);
1376 break;
1377 case 0xd2:
1378 gen_op_load_fpr_DT1(rs2);
1379 gen_op_fdtoi();
1380 gen_op_store_FT0_fpr(rd);
1381 break;
e80cfcfc
FB		 1382 case 0xd3: /* fqtoi */
1383 goto nfpu_insn;
3475187d 1384#ifdef TARGET_SPARC64
af7bf89b 1385 case 0x2: /* V9 fmovd */
3475187d
FB		 1386 gen_op_load_fpr_DT0(DFPREG(rs2));
1387 gen_op_store_DT0_fpr(DFPREG(rd));
1388 break;
af7bf89b 1389 case 0x6: /* V9 fnegd */
3475187d
FB		 1390 gen_op_load_fpr_DT1(DFPREG(rs2));
1391 gen_op_fnegd();
1392 gen_op_store_DT0_fpr(DFPREG(rd));
1393 break;
af7bf89b 1394 case 0xa: /* V9 fabsd */
3475187d
FB		 1395 gen_op_load_fpr_DT1(DFPREG(rs2));
1396 gen_op_fabsd();
1397 gen_op_store_DT0_fpr(DFPREG(rd));
1398 break;
af7bf89b 1399 case 0x81: /* V9 fstox */
3475187d
FB		 1400 gen_op_load_fpr_FT1(rs2);
1401 gen_op_fstox();
1402 gen_op_store_DT0_fpr(DFPREG(rd));
1403 break;
af7bf89b 1404 case 0x82: /* V9 fdtox */
3475187d
FB		 1405 gen_op_load_fpr_DT1(DFPREG(rs2));
1406 gen_op_fdtox();
1407 gen_op_store_DT0_fpr(DFPREG(rd));
1408 break;
af7bf89b 1409 case 0x84: /* V9 fxtos */
3475187d
FB		 1410 gen_op_load_fpr_DT1(DFPREG(rs2));
1411 gen_op_fxtos();
1412 gen_op_store_FT0_fpr(rd);
1413 break;
af7bf89b 1414 case 0x88: /* V9 fxtod */
3475187d
FB		 1415 gen_op_load_fpr_DT1(DFPREG(rs2));
1416 gen_op_fxtod();
1417 gen_op_store_DT0_fpr(DFPREG(rd));
1418 break;
af7bf89b
FB		 1419 case 0x3: /* V9 fmovq */
1420 case 0x7: /* V9 fnegq */
1421 case 0xb: /* V9 fabsq */
1422 case 0x83: /* V9 fqtox */
1423 case 0x8c: /* V9 fxtoq */
3475187d
FB		 1424 goto nfpu_insn;
1425#endif
1426 default:
e8af50a3
FB		 1427 goto illegal_insn;
1428 }
e80cfcfc 1429 } else if (xop == 0x35) { /* FPU Operations */
3475187d
FB		 1430#ifdef TARGET_SPARC64
1431 int cond;
1432#endif
e80cfcfc 1433#if !defined(CONFIG_USER_ONLY)
55e4f664 1434 save_state(dc);
e80cfcfc
FB		 1435 gen_op_trap_ifnofpu();
1436#endif
cf495bcf 1437 rs1 = GET_FIELD(insn, 13, 17);
e80cfcfc
FB		 1438 rs2 = GET_FIELD(insn, 27, 31);
1439 xop = GET_FIELD(insn, 18, 26);
3475187d
FB		 1440#ifdef TARGET_SPARC64
1441 if ((xop & 0x11f) == 0x005) { // V9 fmovsr
1442 cond = GET_FIELD_SP(insn, 14, 17);
1443 gen_op_load_fpr_FT0(rd);
1444 gen_op_load_fpr_FT1(rs2);
1445 rs1 = GET_FIELD(insn, 13, 17);
1446 gen_movl_reg_T0(rs1);
1447 flush_T2(dc);
1448 gen_cond_reg(cond);
1449 gen_op_fmovs_cc();
1450 gen_op_store_FT0_fpr(rd);
1451 break;
1452 } else if ((xop & 0x11f) == 0x006) { // V9 fmovdr
1453 cond = GET_FIELD_SP(insn, 14, 17);
1454 gen_op_load_fpr_DT0(rd);
1455 gen_op_load_fpr_DT1(rs2);
1456 flush_T2(dc);
1457 rs1 = GET_FIELD(insn, 13, 17);
1458 gen_movl_reg_T0(rs1);
1459 gen_cond_reg(cond);
1460 gen_op_fmovs_cc();
1461 gen_op_store_DT0_fpr(rd);
1462 break;
1463 } else if ((xop & 0x11f) == 0x007) { // V9 fmovqr
1464 goto nfpu_insn;
1465 }
1466#endif
e80cfcfc 1467 switch (xop) {
3475187d
FB		 1468#ifdef TARGET_SPARC64
1469 case 0x001: /* V9 fmovscc %fcc0 */
1470 cond = GET_FIELD_SP(insn, 14, 17);
1471 gen_op_load_fpr_FT0(rd);
1472 gen_op_load_fpr_FT1(rs2);
1473 flush_T2(dc);
1474 gen_fcond[0][cond]();
1475 gen_op_fmovs_cc();
1476 gen_op_store_FT0_fpr(rd);
1477 break;
1478 case 0x002: /* V9 fmovdcc %fcc0 */
1479 cond = GET_FIELD_SP(insn, 14, 17);
1480 gen_op_load_fpr_DT0(rd);
1481 gen_op_load_fpr_DT1(rs2);
1482 flush_T2(dc);
1483 gen_fcond[0][cond]();
1484 gen_op_fmovd_cc();
1485 gen_op_store_DT0_fpr(rd);
1486 break;
1487 case 0x003: /* V9 fmovqcc %fcc0 */
1488 goto nfpu_insn;
1489 case 0x041: /* V9 fmovscc %fcc1 */
1490 cond = GET_FIELD_SP(insn, 14, 17);
1491 gen_op_load_fpr_FT0(rd);
1492 gen_op_load_fpr_FT1(rs2);
1493 flush_T2(dc);
1494 gen_fcond[1][cond]();
1495 gen_op_fmovs_cc();
1496 gen_op_store_FT0_fpr(rd);
1497 break;
1498 case 0x042: /* V9 fmovdcc %fcc1 */
1499 cond = GET_FIELD_SP(insn, 14, 17);
1500 gen_op_load_fpr_DT0(rd);
1501 gen_op_load_fpr_DT1(rs2);
1502 flush_T2(dc);
1503 gen_fcond[1][cond]();
1504 gen_op_fmovd_cc();
1505 gen_op_store_DT0_fpr(rd);
1506 break;
1507 case 0x043: /* V9 fmovqcc %fcc1 */
1508 goto nfpu_insn;
1509 case 0x081: /* V9 fmovscc %fcc2 */
1510 cond = GET_FIELD_SP(insn, 14, 17);
1511 gen_op_load_fpr_FT0(rd);
1512 gen_op_load_fpr_FT1(rs2);
1513 flush_T2(dc);
1514 gen_fcond[2][cond]();
1515 gen_op_fmovs_cc();
1516 gen_op_store_FT0_fpr(rd);
1517 break;
1518 case 0x082: /* V9 fmovdcc %fcc2 */
1519 cond = GET_FIELD_SP(insn, 14, 17);
1520 gen_op_load_fpr_DT0(rd);
1521 gen_op_load_fpr_DT1(rs2);
1522 flush_T2(dc);
1523 gen_fcond[2][cond]();
1524 gen_op_fmovd_cc();
1525 gen_op_store_DT0_fpr(rd);
1526 break;
1527 case 0x083: /* V9 fmovqcc %fcc2 */
1528 goto nfpu_insn;
1529 case 0x0c1: /* V9 fmovscc %fcc3 */
1530 cond = GET_FIELD_SP(insn, 14, 17);
1531 gen_op_load_fpr_FT0(rd);
1532 gen_op_load_fpr_FT1(rs2);
1533 flush_T2(dc);
1534 gen_fcond[3][cond]();
1535 gen_op_fmovs_cc();
1536 gen_op_store_FT0_fpr(rd);
1537 break;
1538 case 0x0c2: /* V9 fmovdcc %fcc3 */
1539 cond = GET_FIELD_SP(insn, 14, 17);
1540 gen_op_load_fpr_DT0(rd);
1541 gen_op_load_fpr_DT1(rs2);
1542 flush_T2(dc);
1543 gen_fcond[3][cond]();
1544 gen_op_fmovd_cc();
1545 gen_op_store_DT0_fpr(rd);
1546 break;
1547 case 0x0c3: /* V9 fmovqcc %fcc3 */
1548 goto nfpu_insn;
1549 case 0x101: /* V9 fmovscc %icc */
1550 cond = GET_FIELD_SP(insn, 14, 17);
1551 gen_op_load_fpr_FT0(rd);
1552 gen_op_load_fpr_FT1(rs2);
1553 flush_T2(dc);
1554 gen_cond[0][cond]();
1555 gen_op_fmovs_cc();
1556 gen_op_store_FT0_fpr(rd);
1557 break;
1558 case 0x102: /* V9 fmovdcc %icc */
1559 cond = GET_FIELD_SP(insn, 14, 17);
1560 gen_op_load_fpr_DT0(rd);
1561 gen_op_load_fpr_DT1(rs2);
1562 flush_T2(dc);
1563 gen_cond[0][cond]();
1564 gen_op_fmovd_cc();
1565 gen_op_store_DT0_fpr(rd);
1566 break;
1567 case 0x103: /* V9 fmovqcc %icc */
1568 goto nfpu_insn;
1569 case 0x181: /* V9 fmovscc %xcc */
1570 cond = GET_FIELD_SP(insn, 14, 17);
1571 gen_op_load_fpr_FT0(rd);
1572 gen_op_load_fpr_FT1(rs2);
1573 flush_T2(dc);
1574 gen_cond[1][cond]();
1575 gen_op_fmovs_cc();
1576 gen_op_store_FT0_fpr(rd);
1577 break;
1578 case 0x182: /* V9 fmovdcc %xcc */
1579 cond = GET_FIELD_SP(insn, 14, 17);
1580 gen_op_load_fpr_DT0(rd);
1581 gen_op_load_fpr_DT1(rs2);
1582 flush_T2(dc);
1583 gen_cond[1][cond]();
1584 gen_op_fmovd_cc();
1585 gen_op_store_DT0_fpr(rd);
1586 break;
1587 case 0x183: /* V9 fmovqcc %xcc */
1588 goto nfpu_insn;
1589#endif
1590 case 0x51: /* V9 %fcc */
e80cfcfc
FB		 1591 gen_op_load_fpr_FT0(rs1);
1592 gen_op_load_fpr_FT1(rs2);
3475187d
FB		 1593#ifdef TARGET_SPARC64
1594 gen_fcmps[rd & 3]();
1595#else
e80cfcfc 1596 gen_op_fcmps();
3475187d 1597#endif
e80cfcfc 1598 break;
3475187d
FB		 1599 case 0x52: /* V9 %fcc */
1600 gen_op_load_fpr_DT0(DFPREG(rs1));
1601 gen_op_load_fpr_DT1(DFPREG(rs2));
1602#ifdef TARGET_SPARC64
1603 gen_fcmpd[rd & 3]();
1604#else
e80cfcfc 1605 gen_op_fcmpd();
3475187d 1606#endif
e80cfcfc
FB		 1607 break;
1608 case 0x53: /* fcmpq */
1609 goto nfpu_insn;
3475187d 1610 case 0x55: /* fcmpes, V9 %fcc */
e80cfcfc
FB		 1611 gen_op_load_fpr_FT0(rs1);
1612 gen_op_load_fpr_FT1(rs2);
3475187d
FB		 1613#ifdef TARGET_SPARC64
1614 gen_fcmps[rd & 3]();
1615#else
e80cfcfc 1616 gen_op_fcmps(); /* XXX should trap if qNaN or sNaN */
3475187d 1617#endif
e80cfcfc 1618 break;
3475187d
FB		 1619 case 0x56: /* fcmped, V9 %fcc */
1620 gen_op_load_fpr_DT0(DFPREG(rs1));
1621 gen_op_load_fpr_DT1(DFPREG(rs2));
1622#ifdef TARGET_SPARC64
1623 gen_fcmpd[rd & 3]();
1624#else
e80cfcfc 1625 gen_op_fcmpd(); /* XXX should trap if qNaN or sNaN */
3475187d 1626#endif
e80cfcfc
FB		 1627 break;
1628 case 0x57: /* fcmpeq */
1629 goto nfpu_insn;
1630 default:
1631 goto illegal_insn;
1632 }
1633#if defined(OPTIM)
1634 } else if (xop == 0x2) {
1635 // clr/mov shortcut
1636
1637 rs1 = GET_FIELD(insn, 13, 17);
1638 if (rs1 == 0) {
1639 // or %g0, x, y -> mov T1, x; mov y, T1
1640 if (IS_IMM) { /* immediate */
1641 rs2 = GET_FIELDs(insn, 19, 31);
3475187d 1642 gen_movl_simm_T1(rs2);
e80cfcfc
FB		 1643 } else { /* register */
1644 rs2 = GET_FIELD(insn, 27, 31);
1645 gen_movl_reg_T1(rs2);
1646 }
1647 gen_movl_T1_reg(rd);
1648 } else {
1649 gen_movl_reg_T0(rs1);
1650 if (IS_IMM) { /* immediate */
1651 // or x, #0, y -> mov T1, x; mov y, T1
1652 rs2 = GET_FIELDs(insn, 19, 31);
1653 if (rs2 != 0) {
3475187d 1654 gen_movl_simm_T1(rs2);
e80cfcfc
FB		 1655 gen_op_or_T1_T0();
1656 }
1657 } else { /* register */
1658 // or x, %g0, y -> mov T1, x; mov y, T1
1659 rs2 = GET_FIELD(insn, 27, 31);
1660 if (rs2 != 0) {
1661 gen_movl_reg_T1(rs2);
1662 gen_op_or_T1_T0();
1663 }
1664 }
1665 gen_movl_T0_reg(rd);
1666 }
83469015
FB		 1667#endif
1668#ifdef TARGET_SPARC64
1669 } else if (xop == 0x25) { /* sll, V9 sllx ( == sll) */
1670 rs1 = GET_FIELD(insn, 13, 17);
1671 gen_movl_reg_T0(rs1);
1672 if (IS_IMM) { /* immediate */
1673 rs2 = GET_FIELDs(insn, 20, 31);
1674 gen_movl_simm_T1(rs2);
1675 } else { /* register */
1676 rs2 = GET_FIELD(insn, 27, 31);
1677 gen_movl_reg_T1(rs2);
1678 }
1679 gen_op_sll();
1680 gen_movl_T0_reg(rd);
1681 } else if (xop == 0x26) { /* srl, V9 srlx */
1682 rs1 = GET_FIELD(insn, 13, 17);
1683 gen_movl_reg_T0(rs1);
1684 if (IS_IMM) { /* immediate */
1685 rs2 = GET_FIELDs(insn, 20, 31);
1686 gen_movl_simm_T1(rs2);
1687 } else { /* register */
1688 rs2 = GET_FIELD(insn, 27, 31);
1689 gen_movl_reg_T1(rs2);
1690 }
1691 if (insn & (1 << 12))
1692 gen_op_srlx();
1693 else
1694 gen_op_srl();
1695 gen_movl_T0_reg(rd);
1696 } else if (xop == 0x27) { /* sra, V9 srax */
1697 rs1 = GET_FIELD(insn, 13, 17);
1698 gen_movl_reg_T0(rs1);
1699 if (IS_IMM) { /* immediate */
1700 rs2 = GET_FIELDs(insn, 20, 31);
1701 gen_movl_simm_T1(rs2);
1702 } else { /* register */
1703 rs2 = GET_FIELD(insn, 27, 31);
1704 gen_movl_reg_T1(rs2);
1705 }
1706 if (insn & (1 << 12))
1707 gen_op_srax();
1708 else
1709 gen_op_sra();
1710 gen_movl_T0_reg(rd);
e80cfcfc
FB		 1711#endif
1712 } else if (xop < 0x38) {
1713 rs1 = GET_FIELD(insn, 13, 17);
1714 gen_movl_reg_T0(rs1);
1715 if (IS_IMM) { /* immediate */
cf495bcf 1716 rs2 = GET_FIELDs(insn, 19, 31);
3475187d 1717 gen_movl_simm_T1(rs2);
cf495bcf
FB		 1718 } else { /* register */
1719 rs2 = GET_FIELD(insn, 27, 31);
1720 gen_movl_reg_T1(rs2);
1721 }
1722 if (xop < 0x20) {
1723 switch (xop & ~0x10) {
1724 case 0x0:
1725 if (xop & 0x10)
1726 gen_op_add_T1_T0_cc();
1727 else
1728 gen_op_add_T1_T0();
1729 break;
1730 case 0x1:
1731 gen_op_and_T1_T0();
1732 if (xop & 0x10)
1733 gen_op_logic_T0_cc();
1734 break;
1735 case 0x2:
e80cfcfc
FB		 1736 gen_op_or_T1_T0();
1737 if (xop & 0x10)
1738 gen_op_logic_T0_cc();
1739 break;
cf495bcf
FB		 1740 case 0x3:
1741 gen_op_xor_T1_T0();
1742 if (xop & 0x10)
1743 gen_op_logic_T0_cc();
1744 break;
1745 case 0x4:
1746 if (xop & 0x10)
1747 gen_op_sub_T1_T0_cc();
1748 else
1749 gen_op_sub_T1_T0();
1750 break;
1751 case 0x5:
1752 gen_op_andn_T1_T0();
1753 if (xop & 0x10)
1754 gen_op_logic_T0_cc();
1755 break;
1756 case 0x6:
1757 gen_op_orn_T1_T0();
1758 if (xop & 0x10)
1759 gen_op_logic_T0_cc();
1760 break;
1761 case 0x7:
1762 gen_op_xnor_T1_T0();
1763 if (xop & 0x10)
1764 gen_op_logic_T0_cc();
1765 break;
1766 case 0x8:
cf495bcf 1767 if (xop & 0x10)
af7bf89b
FB		 1768 gen_op_addx_T1_T0_cc();
1769 else
1770 gen_op_addx_T1_T0();
cf495bcf 1771 break;
ded3ab80
PB		 1772#ifdef TARGET_SPARC64
1773 case 0x9: /* V9 mulx */
1774 gen_op_mulx_T1_T0();
1775 break;
1776#endif
cf495bcf
FB		 1777 case 0xa:
1778 gen_op_umul_T1_T0();
1779 if (xop & 0x10)
1780 gen_op_logic_T0_cc();
1781 break;
1782 case 0xb:
1783 gen_op_smul_T1_T0();
1784 if (xop & 0x10)
1785 gen_op_logic_T0_cc();
1786 break;
1787 case 0xc:
cf495bcf 1788 if (xop & 0x10)
af7bf89b
FB		 1789 gen_op_subx_T1_T0_cc();
1790 else
1791 gen_op_subx_T1_T0();
cf495bcf 1792 break;
ded3ab80
PB		 1793#ifdef TARGET_SPARC64
1794 case 0xd: /* V9 udivx */
1795 gen_op_udivx_T1_T0();
1796 break;
1797#endif
cf495bcf
FB		 1798 case 0xe:
1799 gen_op_udiv_T1_T0();
1800 if (xop & 0x10)
1801 gen_op_div_cc();
1802 break;
1803 case 0xf:
1804 gen_op_sdiv_T1_T0();
1805 if (xop & 0x10)
1806 gen_op_div_cc();
1807 break;
1808 default:
1809 goto illegal_insn;
1810 }
e80cfcfc 1811 gen_movl_T0_reg(rd);
cf495bcf
FB		 1812 } else {
1813 switch (xop) {
e80cfcfc
FB		 1814 case 0x20: /* taddcc */
1815 case 0x21: /* tsubcc */
1816 case 0x22: /* taddcctv */
1817 case 0x23: /* tsubcctv */
1818 goto illegal_insn;
cf495bcf
FB		 1819 case 0x24: /* mulscc */
1820 gen_op_mulscc_T1_T0();
1821 gen_movl_T0_reg(rd);
1822 break;
83469015
FB		 1823#ifndef TARGET_SPARC64
1824 case 0x25: /* sll */
3475187d 1825 gen_op_sll();
cf495bcf
FB		 1826 gen_movl_T0_reg(rd);
1827 break;
83469015 1828 case 0x26: /* srl */
3475187d 1829 gen_op_srl();
cf495bcf
FB		 1830 gen_movl_T0_reg(rd);
1831 break;
83469015 1832 case 0x27: /* sra */
3475187d 1833 gen_op_sra();
cf495bcf
FB		 1834 gen_movl_T0_reg(rd);
1835 break;
83469015 1836#endif
cf495bcf
FB		 1837 case 0x30:
1838 {
cf495bcf 1839 switch(rd) {
3475187d
FB		 1840 case 0: /* wry */
1841 gen_op_xor_T1_T0();
1842 gen_op_movtl_env_T0(offsetof(CPUSPARCState, y));
cf495bcf 1843 break;
3475187d 1844#ifdef TARGET_SPARC64
af7bf89b 1845 case 0x2: /* V9 wrccr */
3475187d
FB		 1846 gen_op_wrccr();
1847 break;
af7bf89b 1848 case 0x3: /* V9 wrasi */
3475187d
FB		 1849 gen_op_movl_env_T0(offsetof(CPUSPARCState, asi));
1850 break;
af7bf89b 1851 case 0x6: /* V9 wrfprs */
3475187d
FB		 1852 gen_op_movl_env_T0(offsetof(CPUSPARCState, fprs));
1853 break;
1854 case 0xf: /* V9 sir, nop if user */
1855#if !defined(CONFIG_USER_ONLY)
1856 if (supervisor(dc))
1857 gen_op_sir();
1858#endif
1859 break;
83469015
FB		 1860 case 0x17: /* Tick compare */
1861#if !defined(CONFIG_USER_ONLY)
1862 if (!supervisor(dc))
1863 goto illegal_insn;
1864#endif
1865 gen_op_movtl_env_T0(offsetof(CPUSPARCState, tick_cmpr));
1866 break;
1867 case 0x18: /* System tick */
1868#if !defined(CONFIG_USER_ONLY)
1869 if (!supervisor(dc))
1870 goto illegal_insn;
1871#endif
1872 gen_op_movtl_env_T0(offsetof(CPUSPARCState, stick_cmpr));
1873 break;
1874 case 0x19: /* System tick compare */
1875#if !defined(CONFIG_USER_ONLY)
1876 if (!supervisor(dc))
1877 goto illegal_insn;
3475187d 1878#endif
83469015
FB		 1879 gen_op_movtl_env_T0(offsetof(CPUSPARCState, stick_cmpr));
1880 break;
1881
3475187d
FB		 1882 case 0x10: /* Performance Control */
1883 case 0x11: /* Performance Instrumentation Counter */
1884 case 0x12: /* Dispatch Control */
1885 case 0x13: /* Graphics Status */
1886 case 0x14: /* Softint set */
1887 case 0x15: /* Softint clear */
1888 case 0x16: /* Softint write */
83469015 1889#endif
3475187d 1890 default:
cf495bcf
FB		 1891 goto illegal_insn;
1892 }
1893 }
1894 break;
e8af50a3 1895#if !defined(CONFIG_USER_ONLY)
af7bf89b 1896 case 0x31: /* wrpsr, V9 saved, restored */
e8af50a3
FB		 1897 {
1898 if (!supervisor(dc))
1899 goto priv_insn;
3475187d
FB		 1900#ifdef TARGET_SPARC64
1901 switch (rd) {
1902 case 0:
1903 gen_op_saved();
1904 break;
1905 case 1:
1906 gen_op_restored();
1907 break;
1908 default:
1909 goto illegal_insn;
1910 }
1911#else
e8af50a3
FB		 1912 gen_op_xor_T1_T0();
1913 gen_op_wrpsr();
9e61bde5
FB		 1914 save_state(dc);
1915 gen_op_next_insn();
1916 gen_op_movl_T0_0();
1917 gen_op_exit_tb();
1918 dc->is_br = 1;
3475187d 1919#endif
e8af50a3
FB		 1920 }
1921 break;
af7bf89b 1922 case 0x32: /* wrwim, V9 wrpr */
e8af50a3
FB		 1923 {
1924 if (!supervisor(dc))
1925 goto priv_insn;
1926 gen_op_xor_T1_T0();
3475187d
FB		 1927#ifdef TARGET_SPARC64
1928 switch (rd) {
1929 case 0: // tpc
1930 gen_op_wrtpc();
1931 break;
1932 case 1: // tnpc
1933 gen_op_wrtnpc();
1934 break;
1935 case 2: // tstate
1936 gen_op_wrtstate();
1937 break;
1938 case 3: // tt
1939 gen_op_wrtt();
1940 break;
1941 case 4: // tick
1942 gen_op_wrtick();
1943 break;
1944 case 5: // tba
83469015 1945 gen_op_movtl_env_T0(offsetof(CPUSPARCState, tbr));
3475187d
FB		 1946 break;
1947 case 6: // pstate
1948 gen_op_wrpstate();
ded3ab80
PB		 1949 save_state(dc);
1950 gen_op_next_insn();
1951 gen_op_movl_T0_0();
1952 gen_op_exit_tb();
1953 dc->is_br = 1;
3475187d
FB		 1954 break;
1955 case 7: // tl
1956 gen_op_movl_env_T0(offsetof(CPUSPARCState, tl));
1957 break;
1958 case 8: // pil
1959 gen_op_movl_env_T0(offsetof(CPUSPARCState, psrpil));
1960 break;
1961 case 9: // cwp
1962 gen_op_wrcwp();
1963 break;
1964 case 10: // cansave
1965 gen_op_movl_env_T0(offsetof(CPUSPARCState, cansave));
1966 break;
1967 case 11: // canrestore
1968 gen_op_movl_env_T0(offsetof(CPUSPARCState, canrestore));
1969 break;
1970 case 12: // cleanwin
1971 gen_op_movl_env_T0(offsetof(CPUSPARCState, cleanwin));
1972 break;
1973 case 13: // otherwin
1974 gen_op_movl_env_T0(offsetof(CPUSPARCState, otherwin));
1975 break;
1976 case 14: // wstate
1977 gen_op_movl_env_T0(offsetof(CPUSPARCState, wstate));
1978 break;
1979 default:
1980 goto illegal_insn;
1981 }
1982#else
1983 gen_op_movl_env_T0(offsetof(CPUSPARCState, wim));
1984#endif
e8af50a3
FB		 1985 }
1986 break;
3475187d
FB		 1987#ifndef TARGET_SPARC64
1988 case 0x33: /* wrtbr, V9 unimp */
e8af50a3
FB		 1989 {
1990 if (!supervisor(dc))
1991 goto priv_insn;
1992 gen_op_xor_T1_T0();
3475187d 1993 gen_op_movtl_env_T0(offsetof(CPUSPARCState, tbr));
e8af50a3
FB		 1994 }
1995 break;
1996#endif
3475187d
FB		 1997#endif
1998#ifdef TARGET_SPARC64
af7bf89b 1999 case 0x2c: /* V9 movcc */
3475187d
FB		 2000 {
2001 int cc = GET_FIELD_SP(insn, 11, 12);
2002 int cond = GET_FIELD_SP(insn, 14, 17);
2003 if (IS_IMM) { /* immediate */
2004 rs2 = GET_FIELD_SPs(insn, 0, 10);
2005 gen_movl_simm_T1(rs2);
2006 }
2007 else {
2008 rs2 = GET_FIELD_SP(insn, 0, 4);
2009 gen_movl_reg_T1(rs2);
2010 }
2011 gen_movl_reg_T0(rd);
2012 flush_T2(dc);
2013 if (insn & (1 << 18)) {
2014 if (cc == 0)
2015 gen_cond[0][cond]();
2016 else if (cc == 2)
2017 gen_cond[1][cond]();
2018 else
2019 goto illegal_insn;
2020 } else {
2021 gen_fcond[cc][cond]();
2022 }
2023 gen_op_mov_cc();
2024 gen_movl_T0_reg(rd);
2025 break;
2026 }
af7bf89b 2027 case 0x2d: /* V9 sdivx */
3475187d
FB		 2028 gen_op_sdivx_T1_T0();
2029 gen_movl_T0_reg(rd);
2030 break;
af7bf89b 2031 case 0x2e: /* V9 popc */
3475187d
FB		 2032 {
2033 if (IS_IMM) { /* immediate */
2034 rs2 = GET_FIELD_SPs(insn, 0, 12);
2035 gen_movl_simm_T1(rs2);
2036 // XXX optimize: popc(constant)
2037 }
2038 else {
2039 rs2 = GET_FIELD_SP(insn, 0, 4);
2040 gen_movl_reg_T1(rs2);
2041 }
2042 gen_op_popc();
2043 gen_movl_T0_reg(rd);
2044 }
af7bf89b 2045 case 0x2f: /* V9 movr */
3475187d
FB		 2046 {
2047 int cond = GET_FIELD_SP(insn, 10, 12);
2048 rs1 = GET_FIELD(insn, 13, 17);
2049 flush_T2(dc);
2050 gen_movl_reg_T0(rs1);
2051 gen_cond_reg(cond);
2052 if (IS_IMM) { /* immediate */
2053 rs2 = GET_FIELD_SPs(insn, 0, 10);
2054 gen_movl_simm_T1(rs2);
2055 }
2056 else {
2057 rs2 = GET_FIELD_SP(insn, 0, 4);
2058 gen_movl_reg_T1(rs2);
2059 }
2060 gen_movl_reg_T0(rd);
2061 gen_op_mov_cc();
2062 gen_movl_T0_reg(rd);
2063 break;
2064 }
2065 case 0x36: /* UltraSparc shutdown, VIS */
2066 {
2067 // XXX
2068 }
2069#endif
2070 default:
e80cfcfc
FB		 2071 goto illegal_insn;
2072 }
2073 }
3475187d
FB		 2074#ifdef TARGET_SPARC64
2075 } else if (xop == 0x39) { /* V9 return */
3475187d
FB		 2076 rs1 = GET_FIELD(insn, 13, 17);
2077 gen_movl_reg_T0(rs1);
2078 if (IS_IMM) { /* immediate */
2079 rs2 = GET_FIELDs(insn, 19, 31);
2080#if defined(OPTIM)
2081 if (rs2) {
2082#endif
2083 gen_movl_simm_T1(rs2);
2084 gen_op_add_T1_T0();
2085#if defined(OPTIM)
2086 }
2087#endif
2088 } else { /* register */
2089 rs2 = GET_FIELD(insn, 27, 31);
2090#if defined(OPTIM)
2091 if (rs2) {
2092#endif
2093 gen_movl_reg_T1(rs2);
2094 gen_op_add_T1_T0();
2095#if defined(OPTIM)
2096 }
2097#endif
2098 }
83469015 2099 gen_op_restore();
3475187d
FB		 2100 gen_mov_pc_npc(dc);
2101 gen_op_movl_npc_T0();
2102 dc->npc = DYNAMIC_PC;
2103 goto jmp_insn;
2104#endif
e80cfcfc
FB		 2105 } else {
2106 rs1 = GET_FIELD(insn, 13, 17);
2107 gen_movl_reg_T0(rs1);
2108 if (IS_IMM) { /* immediate */
2109 rs2 = GET_FIELDs(insn, 19, 31);
2110#if defined(OPTIM)
2111 if (rs2) {
e8af50a3 2112#endif
3475187d 2113 gen_movl_simm_T1(rs2);
e80cfcfc
FB		 2114 gen_op_add_T1_T0();
2115#if defined(OPTIM)
2116 }
e8af50a3 2117#endif
e80cfcfc
FB		 2118 } else { /* register */
2119 rs2 = GET_FIELD(insn, 27, 31);
2120#if defined(OPTIM)
2121 if (rs2) {
2122#endif
2123 gen_movl_reg_T1(rs2);
2124 gen_op_add_T1_T0();
2125#if defined(OPTIM)
2126 }
e8af50a3 2127#endif
cf495bcf 2128 }
e80cfcfc
FB		 2129 switch (xop) {
2130 case 0x38: /* jmpl */
2131 {
e80cfcfc 2132 if (rd != 0) {
ded3ab80
PB		 2133#ifdef TARGET_SPARC64
2134 if (dc->pc == (uint32_t)dc->pc) {
2135 gen_op_movl_T1_im(dc->pc);
2136 } else {
2137 gen_op_movq_T1_im64(dc->pc >> 32, dc->pc);
2138 }
2139#else
0bee699e 2140 gen_op_movl_T1_im(dc->pc);
ded3ab80 2141#endif
0bee699e 2142 gen_movl_T1_reg(rd);
e80cfcfc 2143 }
0bee699e
FB		 2144 gen_mov_pc_npc(dc);
2145 gen_op_movl_npc_T0();
e80cfcfc
FB		 2146 dc->npc = DYNAMIC_PC;
2147 }
2148 goto jmp_insn;
3475187d 2149#if !defined(CONFIG_USER_ONLY) && !defined(TARGET_SPARC64)
af7bf89b 2150 case 0x39: /* rett, V9 return */
e80cfcfc
FB		 2151 {
2152 if (!supervisor(dc))
2153 goto priv_insn;
0bee699e 2154 gen_mov_pc_npc(dc);
e80cfcfc 2155 gen_op_movl_npc_T0();
0bee699e 2156 dc->npc = DYNAMIC_PC;
e80cfcfc
FB		 2157 gen_op_rett();
2158 }
0bee699e 2159 goto jmp_insn;
e80cfcfc
FB		 2160#endif
2161 case 0x3b: /* flush */
2162 gen_op_flush_T0();
2163 break;
2164 case 0x3c: /* save */
2165 save_state(dc);
2166 gen_op_save();
2167 gen_movl_T0_reg(rd);
2168 break;
2169 case 0x3d: /* restore */
2170 save_state(dc);
2171 gen_op_restore();
2172 gen_movl_T0_reg(rd);
2173 break;
3475187d 2174#if !defined(CONFIG_USER_ONLY) && defined(TARGET_SPARC64)
af7bf89b 2175 case 0x3e: /* V9 done/retry */
3475187d
FB		 2176 {
2177 switch (rd) {
2178 case 0:
2179 if (!supervisor(dc))
2180 goto priv_insn;
83469015
FB		 2181 dc->npc = DYNAMIC_PC;
2182 dc->pc = DYNAMIC_PC;
3475187d 2183 gen_op_done();
83469015 2184 goto jmp_insn;
3475187d
FB		 2185 case 1:
2186 if (!supervisor(dc))
2187 goto priv_insn;
83469015
FB		 2188 dc->npc = DYNAMIC_PC;
2189 dc->pc = DYNAMIC_PC;
3475187d 2190 gen_op_retry();
83469015 2191 goto jmp_insn;
3475187d
FB		 2192 default:
2193 goto illegal_insn;
2194 }
2195 }
2196 break;
2197#endif
2198 default:
e80cfcfc
FB		 2199 goto illegal_insn;
2200 }
cf495bcf
FB		 2201 }
2202 break;
2203 }
af7bf89b 2204 break;
cf495bcf
FB		 2205 case 3: /* load/store instructions */
2206 {
2207 unsigned int xop = GET_FIELD(insn, 7, 12);
2208 rs1 = GET_FIELD(insn, 13, 17);
2209 gen_movl_reg_T0(rs1);
2210 if (IS_IMM) { /* immediate */
2211 rs2 = GET_FIELDs(insn, 19, 31);
e80cfcfc 2212#if defined(OPTIM)
e8af50a3 2213 if (rs2 != 0) {
e80cfcfc 2214#endif
3475187d 2215 gen_movl_simm_T1(rs2);
e8af50a3 2216 gen_op_add_T1_T0();
e80cfcfc 2217#if defined(OPTIM)
e8af50a3 2218 }
e80cfcfc 2219#endif
cf495bcf
FB		 2220 } else { /* register */
2221 rs2 = GET_FIELD(insn, 27, 31);
e80cfcfc
FB		 2222#if defined(OPTIM)
2223 if (rs2 != 0) {
2224#endif
2225 gen_movl_reg_T1(rs2);
2226 gen_op_add_T1_T0();
2227#if defined(OPTIM)
2228 }
2229#endif
cf495bcf 2230 }
3475187d
FB		 2231 if (xop < 4 || (xop > 7 && xop < 0x14 && xop != 0x0e) || \
2232 (xop > 0x17 && xop < 0x1d ) || \
2233 (xop > 0x2c && xop < 0x33) || xop == 0x1f) {
cf495bcf
FB		 2234 switch (xop) {
2235 case 0x0: /* load word */
e8af50a3 2236 gen_op_ldst(ld);
cf495bcf
FB		 2237 break;
2238 case 0x1: /* load unsigned byte */
e8af50a3 2239 gen_op_ldst(ldub);
cf495bcf
FB		 2240 break;
2241 case 0x2: /* load unsigned halfword */
e8af50a3 2242 gen_op_ldst(lduh);
cf495bcf
FB		 2243 break;
2244 case 0x3: /* load double word */
e8af50a3 2245 gen_op_ldst(ldd);
cf495bcf
FB		 2246 gen_movl_T0_reg(rd + 1);
2247 break;
2248 case 0x9: /* load signed byte */
e8af50a3 2249 gen_op_ldst(ldsb);
cf495bcf
FB		 2250 break;
2251 case 0xa: /* load signed halfword */
e8af50a3 2252 gen_op_ldst(ldsh);
cf495bcf
FB		 2253 break;
2254 case 0xd: /* ldstub -- XXX: should be atomically */
e8af50a3 2255 gen_op_ldst(ldstub);
cf495bcf
FB		 2256 break;
2257 case 0x0f: /* swap register with memory. Also atomically */
e80cfcfc 2258 gen_movl_reg_T1(rd);
e8af50a3
FB		 2259 gen_op_ldst(swap);
2260 break;
3475187d 2261#if !defined(CONFIG_USER_ONLY) || defined(TARGET_SPARC64)
e8af50a3 2262 case 0x10: /* load word alternate */
3475187d 2263#ifndef TARGET_SPARC64
e8af50a3
FB		 2264 if (!supervisor(dc))
2265 goto priv_insn;
3475187d 2266#endif
e8af50a3
FB		 2267 gen_op_lda(insn, 1, 4, 0);
2268 break;
2269 case 0x11: /* load unsigned byte alternate */
3475187d 2270#ifndef TARGET_SPARC64
e8af50a3
FB		 2271 if (!supervisor(dc))
2272 goto priv_insn;
3475187d 2273#endif
e8af50a3
FB		 2274 gen_op_lduba(insn, 1, 1, 0);
2275 break;
2276 case 0x12: /* load unsigned halfword alternate */
3475187d 2277#ifndef TARGET_SPARC64
e8af50a3
FB		 2278 if (!supervisor(dc))
2279 goto priv_insn;
3475187d 2280#endif
e8af50a3
FB		 2281 gen_op_lduha(insn, 1, 2, 0);
2282 break;
2283 case 0x13: /* load double word alternate */
3475187d 2284#ifndef TARGET_SPARC64
e8af50a3
FB		 2285 if (!supervisor(dc))
2286 goto priv_insn;
3475187d 2287#endif
e8af50a3
FB		 2288 gen_op_ldda(insn, 1, 8, 0);
2289 gen_movl_T0_reg(rd + 1);
2290 break;
2291 case 0x19: /* load signed byte alternate */
3475187d 2292#ifndef TARGET_SPARC64
e8af50a3
FB		 2293 if (!supervisor(dc))
2294 goto priv_insn;
3475187d 2295#endif
e8af50a3
FB		 2296 gen_op_ldsba(insn, 1, 1, 1);
2297 break;
2298 case 0x1a: /* load signed halfword alternate */
3475187d 2299#ifndef TARGET_SPARC64
e8af50a3
FB		 2300 if (!supervisor(dc))
2301 goto priv_insn;
3475187d 2302#endif
e8af50a3
FB		 2303 gen_op_ldsha(insn, 1, 2 ,1);
2304 break;
2305 case 0x1d: /* ldstuba -- XXX: should be atomically */
3475187d 2306#ifndef TARGET_SPARC64
e8af50a3
FB		 2307 if (!supervisor(dc))
2308 goto priv_insn;
3475187d 2309#endif
e8af50a3
FB		 2310 gen_op_ldstuba(insn, 1, 1, 0);
2311 break;
2312 case 0x1f: /* swap reg with alt. memory. Also atomically */
3475187d 2313#ifndef TARGET_SPARC64
e8af50a3
FB		 2314 if (!supervisor(dc))
2315 goto priv_insn;
3475187d 2316#endif
e80cfcfc 2317 gen_movl_reg_T1(rd);
e8af50a3 2318 gen_op_swapa(insn, 1, 4, 0);
cf495bcf 2319 break;
3475187d
FB		 2320
2321#ifndef TARGET_SPARC64
0fa85d43
FB		 2322 /* avoid warnings */
2323 (void) &gen_op_stfa;
2324 (void) &gen_op_stdfa;
2325 (void) &gen_op_ldfa;
2326 (void) &gen_op_lddfa;
3475187d
FB		 2327#else
2328#if !defined(CONFIG_USER_ONLY)
2329 (void) &gen_op_cas;
2330 (void) &gen_op_casx;
e80cfcfc 2331#endif
3475187d
FB		 2332#endif
2333#endif
2334#ifdef TARGET_SPARC64
af7bf89b 2335 case 0x08: /* V9 ldsw */
3475187d
FB		 2336 gen_op_ldst(ldsw);
2337 break;
af7bf89b 2338 case 0x0b: /* V9 ldx */
3475187d
FB		 2339 gen_op_ldst(ldx);
2340 break;
af7bf89b 2341 case 0x18: /* V9 ldswa */
3475187d
FB		 2342 gen_op_ldswa(insn, 1, 4, 1);
2343 break;
af7bf89b 2344 case 0x1b: /* V9 ldxa */
3475187d
FB		 2345 gen_op_ldxa(insn, 1, 8, 0);
2346 break;
2347 case 0x2d: /* V9 prefetch, no effect */
2348 goto skip_move;
af7bf89b 2349 case 0x30: /* V9 ldfa */
3475187d
FB		 2350 gen_op_ldfa(insn, 1, 8, 0); // XXX
2351 break;
af7bf89b 2352 case 0x33: /* V9 lddfa */
3475187d 2353 gen_op_lddfa(insn, 1, 8, 0); // XXX
af7bf89b 2354
3475187d
FB		 2355 break;
2356 case 0x3d: /* V9 prefetcha, no effect */
2357 goto skip_move;
af7bf89b 2358 case 0x32: /* V9 ldqfa */
3475187d
FB		 2359 goto nfpu_insn;
2360#endif
2361 default:
e80cfcfc 2362 goto illegal_insn;
7a3f1944 2363 }
cf495bcf 2364 gen_movl_T1_reg(rd);
3475187d
FB		 2365#ifdef TARGET_SPARC64
2366 skip_move: ;
2367#endif
e8af50a3 2368 } else if (xop >= 0x20 && xop < 0x24) {
3475187d 2369#if !defined(CONFIG_USER_ONLY) || defined(TARGET_SPARC64)
55e4f664 2370 save_state(dc);
e80cfcfc
FB		 2371 gen_op_trap_ifnofpu();
2372#endif
e8af50a3
FB		 2373 switch (xop) {
2374 case 0x20: /* load fpreg */
2375 gen_op_ldst(ldf);
2376 gen_op_store_FT0_fpr(rd);
2377 break;
2378 case 0x21: /* load fsr */
9e61bde5 2379 gen_op_ldst(ldf);
e8af50a3
FB		 2380 gen_op_ldfsr();
2381 break;
af7bf89b
FB		 2382 case 0x22: /* load quad fpreg */
2383 goto nfpu_insn;
e8af50a3
FB		 2384 case 0x23: /* load double fpreg */
2385 gen_op_ldst(lddf);
3475187d 2386 gen_op_store_DT0_fpr(DFPREG(rd));
e8af50a3 2387 break;
e80cfcfc
FB		 2388 default:
2389 goto illegal_insn;
e8af50a3 2390 }
3475187d
FB		 2391 } else if (xop < 8 || (xop >= 0x14 && xop < 0x18) || \
2392 xop == 0xe || xop == 0x1e) {
cf495bcf
FB		 2393 gen_movl_reg_T1(rd);
2394 switch (xop) {
2395 case 0x4:
e8af50a3 2396 gen_op_ldst(st);
cf495bcf
FB		 2397 break;
2398 case 0x5:
e8af50a3 2399 gen_op_ldst(stb);
cf495bcf
FB		 2400 break;
2401 case 0x6:
e8af50a3 2402 gen_op_ldst(sth);
cf495bcf
FB		 2403 break;
2404 case 0x7:
72cbca10 2405 flush_T2(dc);
cf495bcf 2406 gen_movl_reg_T2(rd + 1);
e8af50a3
FB		 2407 gen_op_ldst(std);
2408 break;
3475187d 2409#if !defined(CONFIG_USER_ONLY) || defined(TARGET_SPARC64)
e8af50a3 2410 case 0x14:
3475187d 2411#ifndef TARGET_SPARC64
e8af50a3
FB		 2412 if (!supervisor(dc))
2413 goto priv_insn;
3475187d 2414#endif
e8af50a3 2415 gen_op_sta(insn, 0, 4, 0);
d39c0b99 2416 break;
e8af50a3 2417 case 0x15:
3475187d 2418#ifndef TARGET_SPARC64
e8af50a3
FB		 2419 if (!supervisor(dc))
2420 goto priv_insn;
3475187d 2421#endif
e8af50a3 2422 gen_op_stba(insn, 0, 1, 0);
d39c0b99 2423 break;
e8af50a3 2424 case 0x16:
3475187d 2425#ifndef TARGET_SPARC64
e8af50a3
FB		 2426 if (!supervisor(dc))
2427 goto priv_insn;
3475187d 2428#endif
e8af50a3 2429 gen_op_stha(insn, 0, 2, 0);
d39c0b99 2430 break;
e8af50a3 2431 case 0x17:
3475187d 2432#ifndef TARGET_SPARC64
e8af50a3
FB		 2433 if (!supervisor(dc))
2434 goto priv_insn;
3475187d 2435#endif
e8af50a3
FB		 2436 flush_T2(dc);
2437 gen_movl_reg_T2(rd + 1);
2438 gen_op_stda(insn, 0, 8, 0);
d39c0b99 2439 break;
e80cfcfc 2440#endif
3475187d 2441#ifdef TARGET_SPARC64
af7bf89b 2442 case 0x0e: /* V9 stx */
3475187d
FB		 2443 gen_op_ldst(stx);
2444 break;
af7bf89b 2445 case 0x1e: /* V9 stxa */
3475187d
FB		 2446 gen_op_stxa(insn, 0, 8, 0); // XXX
2447 break;
2448#endif
2449 default:
e80cfcfc 2450 goto illegal_insn;
7a3f1944 2451 }
e8af50a3 2452 } else if (xop > 0x23 && xop < 0x28) {
e80cfcfc
FB		 2453#if !defined(CONFIG_USER_ONLY)
2454 gen_op_trap_ifnofpu();
2455#endif
e8af50a3
FB		 2456 switch (xop) {
2457 case 0x24:
2458 gen_op_load_fpr_FT0(rd);
2459 gen_op_ldst(stf);
2460 break;
af7bf89b 2461 case 0x25: /* stfsr, V9 stxfsr */
e8af50a3 2462 gen_op_stfsr();
9e61bde5 2463 gen_op_ldst(stf);
e8af50a3 2464 break;
af7bf89b
FB		 2465 case 0x26: /* stdfq */
2466 goto nfpu_insn;
e8af50a3 2467 case 0x27:
3475187d 2468 gen_op_load_fpr_DT0(DFPREG(rd));
e8af50a3
FB		 2469 gen_op_ldst(stdf);
2470 break;
e80cfcfc 2471 default:
3475187d
FB		 2472 goto illegal_insn;
2473 }
2474 } else if (xop > 0x33 && xop < 0x3f) {
2475#ifdef TARGET_SPARC64
2476 switch (xop) {
af7bf89b 2477 case 0x34: /* V9 stfa */
3475187d
FB		 2478 gen_op_stfa(insn, 0, 0, 0); // XXX
2479 break;
af7bf89b 2480 case 0x37: /* V9 stdfa */
3475187d
FB		 2481 gen_op_stdfa(insn, 0, 0, 0); // XXX
2482 break;
af7bf89b 2483 case 0x3c: /* V9 casa */
3475187d
FB		 2484 gen_op_casa(insn, 0, 4, 0); // XXX
2485 break;
af7bf89b 2486 case 0x3e: /* V9 casxa */
3475187d
FB		 2487 gen_op_casxa(insn, 0, 8, 0); // XXX
2488 break;
af7bf89b 2489 case 0x36: /* V9 stqfa */
3475187d
FB		 2490 goto nfpu_insn;
2491 default:
e80cfcfc 2492 goto illegal_insn;
e8af50a3 2493 }
3475187d 2494#else
e80cfcfc 2495 goto illegal_insn;
3475187d 2496#endif
e8af50a3 2497 }
e80cfcfc
FB		 2498 else
2499 goto illegal_insn;
7a3f1944 2500 }
af7bf89b 2501 break;
cf495bcf
FB		 2502 }
2503 /* default case for non jump instructions */
72cbca10
FB		 2504 if (dc->npc == DYNAMIC_PC) {
2505 dc->pc = DYNAMIC_PC;
2506 gen_op_next_insn();
2507 } else if (dc->npc == JUMP_PC) {
2508 /* we can do a static jump */
83469015 2509 gen_branch2(dc, (long)dc->tb, dc->jump_pc[0], dc->jump_pc[1]);
72cbca10
FB		 2510 dc->is_br = 1;
2511 } else {
cf495bcf
FB		 2512 dc->pc = dc->npc;
2513 dc->npc = dc->npc + 4;
cf495bcf 2514 }
e80cfcfc 2515 jmp_insn:
cf495bcf
FB		 2516 return;
2517 illegal_insn:
72cbca10 2518 save_state(dc);
cf495bcf
FB		 2519 gen_op_exception(TT_ILL_INSN);
2520 dc->is_br = 1;
e8af50a3 2521 return;
e80cfcfc 2522#if !defined(CONFIG_USER_ONLY)
e8af50a3
FB		 2523 priv_insn:
2524 save_state(dc);
2525 gen_op_exception(TT_PRIV_INSN);
2526 dc->is_br = 1;
e80cfcfc
FB		 2527 return;
2528#endif
2529 nfpu_insn:
2530 save_state(dc);
2531 gen_op_fpexception_im(FSR_FTT_UNIMPFPOP);
2532 dc->is_br = 1;
7a3f1944
FB		 2533}
2534
cf495bcf 2535static inline int gen_intermediate_code_internal(TranslationBlock * tb,
e8af50a3 2536 int spc, CPUSPARCState *env)
7a3f1944 2537{
72cbca10 2538 target_ulong pc_start, last_pc;
cf495bcf
FB		 2539 uint16_t *gen_opc_end;
2540 DisasContext dc1, *dc = &dc1;
e8af50a3 2541 int j, lj = -1;
cf495bcf
FB		 2542
2543 memset(dc, 0, sizeof(DisasContext));
cf495bcf 2544 dc->tb = tb;
72cbca10 2545 pc_start = tb->pc;
cf495bcf 2546 dc->pc = pc_start;
e80cfcfc 2547 last_pc = dc->pc;
72cbca10 2548 dc->npc = (target_ulong) tb->cs_base;
e8af50a3
FB		 2549#if defined(CONFIG_USER_ONLY)
2550 dc->mem_idx = 0;
2551#else
2552 dc->mem_idx = ((env->psrs) != 0);
2553#endif
cf495bcf
FB		 2554 gen_opc_ptr = gen_opc_buf;
2555 gen_opc_end = gen_opc_buf + OPC_MAX_SIZE;
2556 gen_opparam_ptr = gen_opparam_buf;
83469015 2557 nb_gen_labels = 0;
cf495bcf
FB		 2558
2559 do {
e8af50a3
FB		 2560 if (env->nb_breakpoints > 0) {
2561 for(j = 0; j < env->nb_breakpoints; j++) {
2562 if (env->breakpoints[j] == dc->pc) {
e80cfcfc
FB		 2563 if (dc->pc != pc_start)
2564 save_state(dc);
2565 gen_op_debug();
2566 gen_op_movl_T0_0();
2567 gen_op_exit_tb();
2568 dc->is_br = 1;
2569 goto exit_gen_loop;
e8af50a3
FB		 2570 }
2571 }
2572 }
2573 if (spc) {
2574 if (loglevel > 0)
2575 fprintf(logfile, "Search PC...\n");
2576 j = gen_opc_ptr - gen_opc_buf;
2577 if (lj < j) {
2578 lj++;
2579 while (lj < j)
2580 gen_opc_instr_start[lj++] = 0;
2581 gen_opc_pc[lj] = dc->pc;
2582 gen_opc_npc[lj] = dc->npc;
2583 gen_opc_instr_start[lj] = 1;
2584 }
2585 }
cf495bcf
FB		 2586 last_pc = dc->pc;
2587 disas_sparc_insn(dc);
3475187d 2588
cf495bcf
FB		 2589 if (dc->is_br)
2590 break;
2591 /* if the next PC is different, we abort now */
2592 if (dc->pc != (last_pc + 4))
2593 break;
d39c0b99
FB		 2594 /* if we reach a page boundary, we stop generation so that the
2595 PC of a TT_TFAULT exception is always in the right page */
2596 if ((dc->pc & (TARGET_PAGE_SIZE - 1)) == 0)
2597 break;
e80cfcfc
FB		 2598 /* if single step mode, we generate only one instruction and
2599 generate an exception */
2600 if (env->singlestep_enabled) {
3475187d 2601 gen_jmp_im(dc->pc);
e80cfcfc
FB		 2602 gen_op_movl_T0_0();
2603 gen_op_exit_tb();
2604 break;
2605 }
cf495bcf
FB		 2606 } while ((gen_opc_ptr < gen_opc_end) &&
2607 (dc->pc - pc_start) < (TARGET_PAGE_SIZE - 32));
e80cfcfc
FB		 2608
2609 exit_gen_loop:
72cbca10
FB		 2610 if (!dc->is_br) {
2611 if (dc->pc != DYNAMIC_PC &&
2612 (dc->npc != DYNAMIC_PC && dc->npc != JUMP_PC)) {
2613 /* static PC and NPC: we can use direct chaining */
83469015 2614 gen_branch(dc, (long)tb, dc->pc, dc->npc);
72cbca10
FB		 2615 } else {
2616 if (dc->pc != DYNAMIC_PC)
3475187d 2617 gen_jmp_im(dc->pc);
72cbca10
FB		 2618 save_npc(dc);
2619 gen_op_movl_T0_0();
2620 gen_op_exit_tb();
2621 }
2622 }
cf495bcf 2623 *gen_opc_ptr = INDEX_op_end;
e8af50a3
FB		 2624 if (spc) {
2625 j = gen_opc_ptr - gen_opc_buf;
2626 lj++;
2627 while (lj <= j)
2628 gen_opc_instr_start[lj++] = 0;
2629 tb->size = 0;
2630#if 0
2631 if (loglevel > 0) {
2632 page_dump(logfile);
2633 }
2634#endif
c3278b7b
FB		 2635 gen_opc_jump_pc[0] = dc->jump_pc[0];
2636 gen_opc_jump_pc[1] = dc->jump_pc[1];
e8af50a3 2637 } else {
e80cfcfc 2638 tb->size = last_pc + 4 - pc_start;
e8af50a3 2639 }
7a3f1944 2640#ifdef DEBUG_DISAS
e19e89a5 2641 if (loglevel & CPU_LOG_TB_IN_ASM) {
cf495bcf 2642 fprintf(logfile, "--------------\n");
0fa85d43
FB		 2643 fprintf(logfile, "IN: %s\n", lookup_symbol(pc_start));
2644 target_disas(logfile, pc_start, last_pc + 4 - pc_start, 0);
cf495bcf 2645 fprintf(logfile, "\n");
e19e89a5
FB		 2646 if (loglevel & CPU_LOG_TB_OP) {
2647 fprintf(logfile, "OP:\n");
2648 dump_ops(gen_opc_buf, gen_opparam_buf);
2649 fprintf(logfile, "\n");
2650 }
cf495bcf 2651 }
7a3f1944 2652#endif
cf495bcf 2653 return 0;
7a3f1944
FB		 2654}
2655
cf495bcf 2656int gen_intermediate_code(CPUSPARCState * env, TranslationBlock * tb)
7a3f1944 2657{
e8af50a3 2658 return gen_intermediate_code_internal(tb, 0, env);
7a3f1944
FB		 2659}
2660
cf495bcf 2661int gen_intermediate_code_pc(CPUSPARCState * env, TranslationBlock * tb)
7a3f1944 2662{
e8af50a3 2663 return gen_intermediate_code_internal(tb, 1, env);
7a3f1944
FB		 2664}
2665
e80cfcfc 2666extern int ram_size;
cf495bcf 2667
e80cfcfc
FB		 2668void cpu_reset(CPUSPARCState *env)
2669{
cf495bcf 2670 memset(env, 0, sizeof(*env));
bb05683b 2671 tlb_flush(env, 1);
cf495bcf
FB		 2672 env->cwp = 0;
2673 env->wim = 1;
2674 env->regwptr = env->regbase + (env->cwp * 16);
e8af50a3 2675#if defined(CONFIG_USER_ONLY)
cf495bcf 2676 env->user_mode_only = 1;
e8af50a3 2677#else
e8af50a3 2678 env->psrs = 1;
0bee699e 2679 env->psrps = 1;
e80cfcfc 2680 env->gregs[1] = ram_size;
3475187d 2681#ifdef TARGET_SPARC64
83469015 2682 env->pstate = PS_PRIV;
3475187d 2683 env->version = GET_VER(env);
83469015 2684 env->pc = 0x1fff0000000ULL;
3475187d
FB		 2685#else
2686 env->mmuregs[0] = (0x04 << 24); /* Impl 0, ver 4, MMU disabled */
83469015 2687 env->pc = 0xffd00000;
3475187d 2688#endif
83469015 2689 env->npc = env->pc + 4;
e8af50a3 2690#endif
e80cfcfc
FB		 2691}
2692
2693CPUSPARCState *cpu_sparc_init(void)
2694{
2695 CPUSPARCState *env;
2696
c68ea704
FB		 2697 env = qemu_mallocz(sizeof(CPUSPARCState));
2698 if (!env)
2699 return NULL;
2700 cpu_exec_init(env);
e80cfcfc 2701 cpu_reset(env);
cf495bcf 2702 return (env);
7a3f1944
FB		 2703}
2704
2705#define GET_FLAG(a,b) ((env->psr & a)?b:'-')
2706
7fe48483
FB		 2707void cpu_dump_state(CPUState *env, FILE *f,
2708 int (*cpu_fprintf)(FILE *f, const char *fmt, ...),
2709 int flags)
7a3f1944 2710{
cf495bcf
FB		 2711 int i, x;
2712
af7bf89b 2713 cpu_fprintf(f, "pc: " TARGET_FMT_lx " npc: " TARGET_FMT_lx "\n", env->pc, env->npc);
7fe48483 2714 cpu_fprintf(f, "General Registers:\n");
cf495bcf 2715 for (i = 0; i < 4; i++)
af7bf89b 2716 cpu_fprintf(f, "%%g%c: " TARGET_FMT_lx "\t", i + '0', env->gregs[i]);
7fe48483 2717 cpu_fprintf(f, "\n");
cf495bcf 2718 for (; i < 8; i++)
af7bf89b 2719 cpu_fprintf(f, "%%g%c: " TARGET_FMT_lx "\t", i + '0', env->gregs[i]);
7fe48483 2720 cpu_fprintf(f, "\nCurrent Register Window:\n");
cf495bcf
FB		 2721 for (x = 0; x < 3; x++) {
2722 for (i = 0; i < 4; i++)
af7bf89b 2723 cpu_fprintf(f, "%%%c%d: " TARGET_FMT_lx "\t",
cf495bcf
FB		 2724 (x == 0 ? 'o' : (x == 1 ? 'l' : 'i')), i,
2725 env->regwptr[i + x * 8]);
7fe48483 2726 cpu_fprintf(f, "\n");
cf495bcf 2727 for (; i < 8; i++)
af7bf89b 2728 cpu_fprintf(f, "%%%c%d: " TARGET_FMT_lx "\t",
cf495bcf
FB		 2729 (x == 0 ? 'o' : x == 1 ? 'l' : 'i'), i,
2730 env->regwptr[i + x * 8]);
7fe48483 2731 cpu_fprintf(f, "\n");
cf495bcf 2732 }
7fe48483 2733 cpu_fprintf(f, "\nFloating Point Registers:\n");
e8af50a3
FB		 2734 for (i = 0; i < 32; i++) {
2735 if ((i & 3) == 0)
7fe48483
FB		 2736 cpu_fprintf(f, "%%f%02d:", i);
2737 cpu_fprintf(f, " %016lf", env->fpr[i]);
e8af50a3 2738 if ((i & 3) == 3)
7fe48483 2739 cpu_fprintf(f, "\n");
e8af50a3 2740 }
ded3ab80
PB		 2741#ifdef TARGET_SPARC64
2742 cpu_fprintf(f, "pstate: 0x%08x ccr: 0x%02x asi: 0x%02x tl: %d\n",
2743 env->pstate, GET_CCR(env), env->asi, env->tl);
2744 cpu_fprintf(f, "cansave: %d canrestore: %d otherwin: %d wstate %d cleanwin %d cwp %d\n",
2745 env->cansave, env->canrestore, env->otherwin, env->wstate,
2746 env->cleanwin, NWINDOWS - 1 - env->cwp);
2747#else
7fe48483 2748 cpu_fprintf(f, "psr: 0x%08x -> %c%c%c%c %c%c%c wim: 0x%08x\n", GET_PSR(env),
cf495bcf
FB		 2749 GET_FLAG(PSR_ZERO, 'Z'), GET_FLAG(PSR_OVF, 'V'),
2750 GET_FLAG(PSR_NEG, 'N'), GET_FLAG(PSR_CARRY, 'C'),
e8af50a3
FB		 2751 env->psrs?'S':'-', env->psrps?'P':'-',
2752 env->psret?'E':'-', env->wim);
ded3ab80 2753#endif
3475187d 2754 cpu_fprintf(f, "fsr: 0x%08x\n", GET_FSR32(env));
7a3f1944 2755}
edfcbd99 2756
e80cfcfc 2757#if defined(CONFIG_USER_ONLY)
d785e6be 2758target_ulong cpu_get_phys_page_debug(CPUState *env, target_ulong addr)
edfcbd99
FB		 2759{
2760 return addr;
2761}
658138bc 2762
e80cfcfc 2763#else
af7bf89b
FB		 2764extern int get_physical_address (CPUState *env, target_phys_addr_t *physical, int *prot,
2765 int *access_index, target_ulong address, int rw,
0fa85d43
FB		 2766 int is_user);
2767
d785e6be 2768target_ulong cpu_get_phys_page_debug(CPUState *env, target_ulong addr)
e80cfcfc 2769{
af7bf89b 2770 target_phys_addr_t phys_addr;
e80cfcfc
FB		 2771 int prot, access_index;
2772
2773 if (get_physical_address(env, &phys_addr, &prot, &access_index, addr, 2, 0) != 0)
6b1575b7
FB		 2774 if (get_physical_address(env, &phys_addr, &prot, &access_index, addr, 0, 0) != 0)
2775 return -1;
e80cfcfc
FB		 2776 return phys_addr;
2777}
2778#endif
2779
658138bc
FB		 2780void helper_flush(target_ulong addr)
2781{
2782 addr &= ~7;
2783 tb_invalidate_page_range(addr, addr + 8);
2784}
Mirror of https://git.qemu.org/git/qemu.git