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93743d24 TR |
1 | # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause |
2 | %YAML 1.2 | |
3 | --- | |
4 | $id: http://devicetree.org/schemas/display/msm/qcom,sm8650-dpu.yaml# | |
5 | $schema: http://devicetree.org/meta-schemas/core.yaml# | |
6 | ||
7 | title: Qualcomm SM8650 Display DPU | |
8 | ||
9 | maintainers: | |
10 | - Neil Armstrong <neil.armstrong@linaro.org> | |
11 | ||
12 | $ref: /schemas/display/msm/dpu-common.yaml# | |
13 | ||
14 | properties: | |
15 | compatible: | |
16 | const: qcom,sm8650-dpu | |
17 | ||
18 | reg: | |
19 | items: | |
20 | - description: Address offset and size for mdp register set | |
21 | - description: Address offset and size for vbif register set | |
22 | ||
23 | reg-names: | |
24 | items: | |
25 | - const: mdp | |
26 | - const: vbif | |
27 | ||
28 | clocks: | |
29 | items: | |
30 | - description: Display hf axi | |
31 | - description: Display MDSS ahb | |
32 | - description: Display lut | |
33 | - description: Display core | |
34 | - description: Display vsync | |
35 | ||
36 | clock-names: | |
37 | items: | |
38 | - const: nrt_bus | |
39 | - const: iface | |
40 | - const: lut | |
41 | - const: core | |
42 | - const: vsync | |
43 | ||
44 | required: | |
45 | - compatible | |
46 | - reg | |
47 | - reg-names | |
48 | - clocks | |
49 | - clock-names | |
50 | ||
51 | unevaluatedProperties: false | |
52 | ||
53 | examples: | |
54 | - | | |
55 | #include <dt-bindings/interrupt-controller/arm-gic.h> | |
56 | #include <dt-bindings/power/qcom,rpmhpd.h> | |
57 | ||
58 | display-controller@ae01000 { | |
59 | compatible = "qcom,sm8650-dpu"; | |
60 | reg = <0x0ae01000 0x8f000>, | |
61 | <0x0aeb0000 0x2008>; | |
62 | reg-names = "mdp", "vbif"; | |
63 | ||
64 | clocks = <&gcc_axi_clk>, | |
65 | <&dispcc_ahb_clk>, | |
66 | <&dispcc_mdp_lut_clk>, | |
67 | <&dispcc_mdp_clk>, | |
68 | <&dispcc_vsync_clk>; | |
69 | clock-names = "nrt_bus", | |
70 | "iface", | |
71 | "lut", | |
72 | "core", | |
73 | "vsync"; | |
74 | ||
75 | assigned-clocks = <&dispcc_vsync_clk>; | |
76 | assigned-clock-rates = <19200000>; | |
77 | ||
78 | operating-points-v2 = <&mdp_opp_table>; | |
79 | power-domains = <&rpmhpd RPMHPD_MMCX>; | |
80 | ||
81 | interrupt-parent = <&mdss>; | |
82 | interrupts = <0>; | |
83 | ||
84 | ports { | |
85 | #address-cells = <1>; | |
86 | #size-cells = <0>; | |
87 | ||
88 | port@0 { | |
89 | reg = <0>; | |
90 | dpu_intf1_out: endpoint { | |
91 | remote-endpoint = <&dsi0_in>; | |
92 | }; | |
93 | }; | |
94 | ||
95 | port@1 { | |
96 | reg = <1>; | |
97 | dpu_intf2_out: endpoint { | |
98 | remote-endpoint = <&dsi1_in>; | |
99 | }; | |
100 | }; | |
101 | }; | |
102 | ||
103 | mdp_opp_table: opp-table { | |
104 | compatible = "operating-points-v2"; | |
105 | ||
106 | opp-200000000 { | |
107 | opp-hz = /bits/ 64 <200000000>; | |
108 | required-opps = <&rpmhpd_opp_low_svs>; | |
109 | }; | |
110 | ||
111 | opp-325000000 { | |
112 | opp-hz = /bits/ 64 <325000000>; | |
113 | required-opps = <&rpmhpd_opp_svs>; | |
114 | }; | |
115 | ||
116 | opp-375000000 { | |
117 | opp-hz = /bits/ 64 <375000000>; | |
118 | required-opps = <&rpmhpd_opp_svs_l1>; | |
119 | }; | |
120 | ||
121 | opp-514000000 { | |
122 | opp-hz = /bits/ 64 <514000000>; | |
123 | required-opps = <&rpmhpd_opp_nom>; | |
124 | }; | |
125 | }; | |
126 | }; | |
127 | ... |