[people/ms/u-boot.git] / arch / arm / cpu / arm920t / start.S

/*
 *  armboot - Startup Code for ARM920 CPU-core
 *
 *  Copyright (c) 2001	Marius Gröger <mag@sysgo.de>
 *  Copyright (c) 2002	Alex Züpke <azu@sysgo.de>
 *  Copyright (c) 2002	Gary Jennejohn <garyj@denx.de>
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#include <asm-offsets.h>
#include <common.h>
#include <config.h>

/*
 *************************************************************************
 *
 * Startup Code (called from the ARM reset exception vector)
 *
 * do important init only if we don't start from memory!
 * relocate armboot to ram
 * setup stack
 * jump to second stage
 *
 *************************************************************************
 */

	.globl	reset

reset:
	/*
	 * set the cpu to SVC32 mode
	 */
	mrs	r0, cpsr
	bic	r0, r0, #0x1f
	orr	r0, r0, #0xd3
	msr	cpsr, r0

#if	defined(CONFIG_AT91RM9200DK) || defined(CONFIG_AT91RM9200EK)
	/*
	 * relocate exception table
	 */
	ldr	r0, =_start
	ldr	r1, =0x0
	mov	r2, #16
copyex:
	subs	r2, r2, #1
	ldr	r3, [r0], #4
	str	r3, [r1], #4
	bne	copyex
#endif

#ifdef CONFIG_S3C24X0
	/* turn off the watchdog */

# if defined(CONFIG_S3C2400)
#  define pWTCON	0x15300000
#  define INTMSK	0x14400008	/* Interrupt-Controller base addresses */
#  define CLKDIVN	0x14800014	/* clock divisor register */
#else
#  define pWTCON	0x53000000
#  define INTMSK	0x4A000008	/* Interrupt-Controller base addresses */
#  define INTSUBMSK	0x4A00001C
#  define CLKDIVN	0x4C000014	/* clock divisor register */
# endif

	ldr	r0, =pWTCON
	mov	r1, #0x0
	str	r1, [r0]

	/*
	 * mask all IRQs by setting all bits in the INTMR - default
	 */
	mov	r1, #0xffffffff
	ldr	r0, =INTMSK
	str	r1, [r0]
# if defined(CONFIG_S3C2410)
	ldr	r1, =0x3ff
	ldr	r0, =INTSUBMSK
	str	r1, [r0]
# endif

	/* FCLK:HCLK:PCLK = 1:2:4 */
	/* default FCLK is 120 MHz ! */
	ldr	r0, =CLKDIVN
	mov	r1, #3
	str	r1, [r0]
#endif	/* CONFIG_S3C24X0 */

	/*
	 * we do sys-critical inits only at reboot,
	 * not when booting from ram!
	 */
#ifndef CONFIG_SKIP_LOWLEVEL_INIT
	bl	cpu_init_crit
#endif

	bl	_main

/*------------------------------------------------------------------------------*/

	.globl	c_runtime_cpu_setup
c_runtime_cpu_setup:

	mov	pc, lr

/*
 *************************************************************************
 *
 * CPU_init_critical registers
 *
 * setup important registers
 * setup memory timing
 *
 *************************************************************************
 */


#ifndef CONFIG_SKIP_LOWLEVEL_INIT
cpu_init_crit:
	/*
	 * flush v4 I/D caches
	 */
	mov	r0, #0
	mcr	p15, 0, r0, c7, c7, 0	/* flush v3/v4 cache */
	mcr	p15, 0, r0, c8, c7, 0	/* flush v4 TLB */

	/*
	 * disable MMU stuff and caches
	 */
	mrc	p15, 0, r0, c1, c0, 0
	bic	r0, r0, #0x00002300	@ clear bits 13, 9:8 (--V- --RS)
	bic	r0, r0, #0x00000087	@ clear bits 7, 2:0 (B--- -CAM)
	orr	r0, r0, #0x00000002	@ set bit 1 (A) Align
	orr	r0, r0, #0x00001000	@ set bit 12 (I) I-Cache
	mcr	p15, 0, r0, c1, c0, 0

#ifndef CONFIG_SKIP_LOWLEVEL_INIT_ONLY
	/*
	 * before relocating, we have to setup RAM timing
	 * because memory timing is board-dependend, you will
	 * find a lowlevel_init.S in your board directory.
	 */
	mov	ip, lr

	bl	lowlevel_init
	mov	lr, ip
#endif
	mov	pc, lr
#endif /* CONFIG_SKIP_LOWLEVEL_INIT */
Commit	Line	Data
fe8c2806 WD	1	/*
	2	* armboot - Startup Code for ARM920 CPU-core
	3	*
fa82f871 AA	4	* Copyright (c) 2001 Marius Gröger <mag@sysgo.de>
fa82f871 AA	5	* Copyright (c) 2002 Alex Züpke <azu@sysgo.de>
792a09eb	6	* Copyright (c) 2002 Gary Jennejohn <garyj@denx.de>
fe8c2806	7	*
1a459660	8	* SPDX-License-Identifier: GPL-2.0+
fe8c2806 WD	9	*/
fe8c2806 WD	10
25ddd1fb	11	#include <asm-offsets.h>
9689ddcc	12	#include <common.h>
fe8c2806	13	#include <config.h>
fe8c2806	14
fe8c2806 WD	15	/*
	16	*************************************************************************
	17	*
80767a6c	18	* Startup Code (called from the ARM reset exception vector)
fe8c2806 WD	19	*
	20	* do important init only if we don't start from memory!
	21	* relocate armboot to ram
	22	* setup stack
	23	* jump to second stage
	24	*
	25	*************************************************************************
	26	*/
	27
41623c91	28	.globl reset
cc7cdcbd	29
41623c91	30	reset:
fe8c2806 WD	31	/*
	32	* set the cpu to SVC32 mode
	33	*/
d67cce2d	34	mrs r0, cpsr
	35	bic r0, r0, #0x1f
	36	orr r0, r0, #0xd3
	37	msr cpsr, r0
80767a6c	38
ed3b18e0	39	#if defined(CONFIG_AT91RM9200DK) \|\| defined(CONFIG_AT91RM9200EK)
d4fc6012	40	/*
80767a6c	41	* relocate exception table
d4fc6012 PP	42	*/
	43	ldr r0, =_start
	44	ldr r1, =0x0
	45	mov r2, #16
	46	copyex:
	47	subs r2, r2, #1
	48	ldr r3, [r0], #4
	49	str r3, [r1], #4
	50	bne copyex
	51	#endif
	52
ac67804f	53	#ifdef CONFIG_S3C24X0
80767a6c PP	54	/* turn off the watchdog */
	55
	56	# if defined(CONFIG_S3C2400)
d67cce2d	57	# define pWTCON 0x15300000
16263087	58	# define INTMSK 0x14400008 /* Interrupt-Controller base addresses */
80767a6c PP	59	# define CLKDIVN 0x14800014 /* clock divisor register */
80767a6c PP	60	#else
d67cce2d	61	# define pWTCON 0x53000000
16263087	62	# define INTMSK 0x4A000008 /* Interrupt-Controller base addresses */
80767a6c PP	63	# define INTSUBMSK 0x4A00001C
	64	# define CLKDIVN 0x4C000014 /* clock divisor register */
	65	# endif
	66
d67cce2d	67	ldr r0, =pWTCON
	68	mov r1, #0x0
	69	str r1, [r0]
fe8c2806 WD	70
	71	/*
	72	* mask all IRQs by setting all bits in the INTMR - default
	73	*/
	74	mov r1, #0xffffffff
	75	ldr r0, =INTMSK
	76	str r1, [r0]
281e00a3	77	# if defined(CONFIG_S3C2410)
fe8c2806 WD	78	ldr r1, =0x3ff
	79	ldr r0, =INTSUBMSK
	80	str r1, [r0]
281e00a3	81	# endif
fe8c2806 WD	82
	83	/* FCLK:HCLK:PCLK = 1:2:4 */
	84	/* default FCLK is 120 MHz ! */
	85	ldr r0, =CLKDIVN
	86	mov r1, #3
	87	str r1, [r0]
ac67804f	88	#endif /* CONFIG_S3C24X0 */
fe8c2806 WD	89
	90	/*
	91	* we do sys-critical inits only at reboot,
	92	* not when booting from ram!
	93	*/
8aa1a2d1	94	#ifndef CONFIG_SKIP_LOWLEVEL_INIT
fe8c2806 WD	95	bl cpu_init_crit
	96	#endif
	97
e05e5de7	98	bl _main
cc7cdcbd HS	99
	100	/------------------------------------------------------------------------------/
	101
e05e5de7 AA	102	.globl c_runtime_cpu_setup
	103	c_runtime_cpu_setup:
	104
	105	mov pc, lr
	106
fe8c2806 WD	107	/*
	108	*************************************************************************
	109	*
	110	* CPU_init_critical registers
	111	*
	112	* setup important registers
	113	* setup memory timing
	114	*
	115	*************************************************************************
	116	*/
	117
	118
db28ddb4	119	#ifndef CONFIG_SKIP_LOWLEVEL_INIT
fe8c2806 WD	120	cpu_init_crit:
	121	/*
	122	* flush v4 I/D caches
	123	*/
	124	mov r0, #0
	125	mcr p15, 0, r0, c7, c7, 0 /* flush v3/v4 cache */
	126	mcr p15, 0, r0, c8, c7, 0 /* flush v4 TLB */
	127
	128	/*
	129	* disable MMU stuff and caches
	130	*/
	131	mrc p15, 0, r0, c1, c0, 0
	132	bic r0, r0, #0x00002300 @ clear bits 13, 9:8 (--V- --RS)
	133	bic r0, r0, #0x00000087 @ clear bits 7, 2:0 (B--- -CAM)
ba10b852	134	orr r0, r0, #0x00000002 @ set bit 1 (A) Align
fe8c2806 WD	135	orr r0, r0, #0x00001000 @ set bit 12 (I) I-Cache
	136	mcr p15, 0, r0, c1, c0, 0
	137
b5bd0982	138	#ifndef CONFIG_SKIP_LOWLEVEL_INIT_ONLY
fe8c2806 WD	139	/*
	140	* before relocating, we have to setup RAM timing
	141	* because memory timing is board-dependend, you will
400558b5	142	* find a lowlevel_init.S in your board directory.
fe8c2806 WD	143	*/
fe8c2806 WD	144	mov ip, lr
d4fc6012	145
400558b5	146	bl lowlevel_init
fe8c2806	147	mov lr, ip
b5bd0982	148	#endif
fe8c2806	149	mov pc, lr
db28ddb4	150	#endif /* CONFIG_SKIP_LOWLEVEL_INIT */