arch/arm/cpu/arm920t/start.S

   1 /*
   2  *  armboot - Startup Code for ARM920 CPU-core
   3  *
   4  *  Copyright (c) 2001  Marius Gröger <mag@sysgo.de>
   5  *  Copyright (c) 2002  Alex Züpke <azu@sysgo.de>
   6  *  Copyright (c) 2002  Gary Jennejohn <garyj@denx.de>
   7  *
   8  * SPDX-License-Identifier:     GPL-2.0+
   9  */
  10
  11 #include <asm-offsets.h>
  12 #include <common.h>
  13 #include <config.h>
  14
  15 /*
  16  *************************************************************************
  17  *
  18  * Startup Code (called from the ARM reset exception vector)
  19  *
  20  * do important init only if we don't start from memory!
  21  * relocate armboot to ram
  22  * setup stack
  23  * jump to second stage
  24  *
  25  *************************************************************************
  26  */
  27
  28         .globl  reset
  29
  30 reset:
  31         /*
  32          * set the cpu to SVC32 mode
  33          */
  34         mrs     r0, cpsr
  35         bic     r0, r0, #0x1f
  36         orr     r0, r0, #0xd3
  37         msr     cpsr, r0
  38
  39 #if     defined(CONFIG_AT91RM9200DK) || defined(CONFIG_AT91RM9200EK)
  40         /*
  41          * relocate exception table
  42          */
  43         ldr     r0, =_start
  44         ldr     r1, =0x0
  45         mov     r2, #16
  46 copyex:
  47         subs    r2, r2, #1
  48         ldr     r3, [r0], #4
  49         str     r3, [r1], #4
  50         bne     copyex
  51 #endif
  52
  53 #ifdef CONFIG_S3C24X0
  54         /* turn off the watchdog */
  55
  56 # if defined(CONFIG_S3C2400)
  57 #  define pWTCON        0x15300000
  58 #  define INTMSK        0x14400008      /* Interrupt-Controller base addresses */
  59 #  define CLKDIVN       0x14800014      /* clock divisor register */
  60 #else
  61 #  define pWTCON        0x53000000
  62 #  define INTMSK        0x4A000008      /* Interrupt-Controller base addresses */
  63 #  define INTSUBMSK     0x4A00001C
  64 #  define CLKDIVN       0x4C000014      /* clock divisor register */
  65 # endif
  66
  67         ldr     r0, =pWTCON
  68         mov     r1, #0x0
  69         str     r1, [r0]
  70
  71         /*
  72          * mask all IRQs by setting all bits in the INTMR - default
  73          */
  74         mov     r1, #0xffffffff
  75         ldr     r0, =INTMSK
  76         str     r1, [r0]
  77 # if defined(CONFIG_S3C2410)
  78         ldr     r1, =0x3ff
  79         ldr     r0, =INTSUBMSK
  80         str     r1, [r0]
  81 # endif
  82
  83         /* FCLK:HCLK:PCLK = 1:2:4 */
  84         /* default FCLK is 120 MHz ! */
  85         ldr     r0, =CLKDIVN
  86         mov     r1, #3
  87         str     r1, [r0]
  88 #endif  /* CONFIG_S3C24X0 */
  89
  90         /*
  91          * we do sys-critical inits only at reboot,
  92          * not when booting from ram!
  93          */
  94 #ifndef CONFIG_SKIP_LOWLEVEL_INIT
  95         bl      cpu_init_crit
  96 #endif
  97
  98         bl      _main
  99
 100 /*------------------------------------------------------------------------------*/
 101
 102         .globl  c_runtime_cpu_setup
 103 c_runtime_cpu_setup:
 104
 105         mov     pc, lr
 106
 107 /*
 108  *************************************************************************
 109  *
 110  * CPU_init_critical registers
 111  *
 112  * setup important registers
 113  * setup memory timing
 114  *
 115  *************************************************************************
 116  */
 117
 118
 119 #ifndef CONFIG_SKIP_LOWLEVEL_INIT
 120 cpu_init_crit:
 121         /*
 122          * flush v4 I/D caches
 123          */
 124         mov     r0, #0
 125         mcr     p15, 0, r0, c7, c7, 0   /* flush v3/v4 cache */
 126         mcr     p15, 0, r0, c8, c7, 0   /* flush v4 TLB */
 127
 128         /*
 129          * disable MMU stuff and caches
 130          */
 131         mrc     p15, 0, r0, c1, c0, 0
 132         bic     r0, r0, #0x00002300     @ clear bits 13, 9:8 (--V- --RS)
 133         bic     r0, r0, #0x00000087     @ clear bits 7, 2:0 (B--- -CAM)
 134         orr     r0, r0, #0x00000002     @ set bit 1 (A) Align
 135         orr     r0, r0, #0x00001000     @ set bit 12 (I) I-Cache
 136         mcr     p15, 0, r0, c1, c0, 0
 137
 138 #ifndef CONFIG_SKIP_LOWLEVEL_INIT_ONLY
 139         /*
 140          * before relocating, we have to setup RAM timing
 141          * because memory timing is board-dependend, you will
 142          * find a lowlevel_init.S in your board directory.
 143          */
 144         mov     ip, lr
 145
 146         bl      lowlevel_init
 147         mov     lr, ip
 148 #endif
 149         mov     pc, lr
 150 #endif /* CONFIG_SKIP_LOWLEVEL_INIT */