[people/ms/u-boot.git] / arch / arm / cpu / armv7 / ls102xa / Kconfig

config ARCH_LS1021A
	bool
	select SYS_FSL_ERRATUM_A008378
	select SYS_FSL_ERRATUM_A008407
	select SYS_FSL_ERRATUM_A009663
	select SYS_FSL_ERRATUM_A009942
	select SYS_FSL_ERRATUM_A010315
	select SYS_FSL_SRDS_1
	select SYS_HAS_SERDES
	select SYS_FSL_DDR_BE if SYS_FSL_DDR
	select SYS_FSL_DDR_VER_50 if SYS_FSL_DDR
	select SYS_FSL_HAS_DDR3 if SYS_FSL_DDR
	select SYS_FSL_HAS_DDR4 if SYS_FSL_DDR
	select SYS_FSL_HAS_SEC
	select SYS_FSL_SEC_COMPAT_5
	select SYS_FSL_SEC_LE

menu "LS102xA architecture"
	depends on ARCH_LS1021A

config LS1_DEEP_SLEEP
	bool "Deep sleep"
	depends on ARCH_LS1021A

config MAX_CPUS
	int "Maximum number of CPUs permitted for LS102xA"
	depends on ARCH_LS1021A
	default 2
	help
	  Set this number to the maximum number of possible CPUs in the SoC.
	  SoCs may have multiple clusters with each cluster may have multiple
	  ports. If some ports are reserved but higher ports are used for
	  cores, count the reserved ports. This will allocate enough memory
	  in spin table to properly handle all cores.

config NUM_DDR_CONTROLLERS
	int "Maximum DDR controllers"
	default 1

config SECURE_BOOT
	bool	"Secure Boot"
	help
		Enable Freescale Secure Boot feature. Normally selected
		by defconfig. If unsure, do not change.

config SYS_FSL_ERRATUM_A010315
	bool "Workaround for PCIe erratum A010315"

config SYS_FSL_SRDS_1
	bool

config SYS_FSL_SRDS_2
	bool

config SYS_HAS_SERDES
	bool

config SYS_FSL_IFC_BANK_COUNT
	int "Maximum banks of Integrated flash controller"
	depends on ARCH_LS1021A
	default 8

config SYS_FSL_ERRATUM_A008407
	bool

endmenu
Commit	Line	Data
0a37cf8f	1	config ARCH_LS1021A
4a444176	2	bool
ba1b6fb5 YS	3	select SYS_FSL_ERRATUM_A008378
	4	select SYS_FSL_ERRATUM_A008407
	5	select SYS_FSL_ERRATUM_A009663
	6	select SYS_FSL_ERRATUM_A009942
0a37cf8f	7	select SYS_FSL_ERRATUM_A010315
f534b8f5 YS	8	select SYS_FSL_SRDS_1
f534b8f5 YS	9	select SYS_HAS_SERDES
d26e34c4 YS	10	select SYS_FSL_DDR_BE if SYS_FSL_DDR
	11	select SYS_FSL_DDR_VER_50 if SYS_FSL_DDR
	12	select SYS_FSL_HAS_DDR3 if SYS_FSL_DDR
	13	select SYS_FSL_HAS_DDR4 if SYS_FSL_DDR
2c2e2c9e YS	14	select SYS_FSL_HAS_SEC
2c2e2c9e YS	15	select SYS_FSL_SEC_COMPAT_5
90b80386	16	select SYS_FSL_SEC_LE
5e8bd7e1	17
fb2bf8c2 YS	18	menu "LS102xA architecture"
	19	depends on ARCH_LS1021A
	20
5e8bd7e1	21	config LS1_DEEP_SLEEP
4a444176 YS	22	bool "Deep sleep"
4a444176 YS	23	depends on ARCH_LS1021A
fb2bf8c2	24
b4b60d06 YS	25	config MAX_CPUS
	26	int "Maximum number of CPUs permitted for LS102xA"
	27	depends on ARCH_LS1021A
	28	default 2
	29	help
	30	Set this number to the maximum number of possible CPUs in the SoC.
	31	SoCs may have multiple clusters with each cluster may have multiple
	32	ports. If some ports are reserved but higher ports are used for
	33	cores, count the reserved ports. This will allocate enough memory
	34	in spin table to properly handle all cores.
	35
53d76829 YS	36	config NUM_DDR_CONTROLLERS
	37	int "Maximum DDR controllers"
	38	default 1
	39
72ccd31e YS	40	config SECURE_BOOT
	41	bool "Secure Boot"
	42	help
	43	Enable Freescale Secure Boot feature. Normally selected
	44	by defconfig. If unsure, do not change.
	45
fb2bf8c2 YS	46	config SYS_FSL_ERRATUM_A010315
	47	bool "Workaround for PCIe erratum A010315"
	48
f534b8f5 YS	49	config SYS_FSL_SRDS_1
	50	bool
	51
	52	config SYS_FSL_SRDS_2
	53	bool
	54
	55	config SYS_HAS_SERDES
	56	bool
	57
25af7dc1 YS	58	config SYS_FSL_IFC_BANK_COUNT
	59	int "Maximum banks of Integrated flash controller"
	60	depends on ARCH_LS1021A
	61	default 8
	62
ba1b6fb5 YS	63	config SYS_FSL_ERRATUM_A008407
	64	bool
	65
fb2bf8c2	66	endmenu