]> git.ipfire.org Git - people/ms/u-boot.git/commitdiff
arm: layerscape: Move CONFIG_SYS_FSL_ERRATUM_* to Kconfig
authorYork Sun <york.sun@nxp.com>
Wed, 28 Dec 2016 16:43:41 +0000 (08:43 -0800)
committerTom Rini <trini@konsulko.com>
Thu, 5 Jan 2017 00:40:42 +0000 (19:40 -0500)
Use Kconfig to select errata workaround.

Signed-off-by: York Sun <york.sun@nxp.com>
arch/arm/cpu/armv7/ls102xa/Kconfig
arch/arm/cpu/armv8/fsl-layerscape/Kconfig
arch/arm/include/asm/arch-fsl-layerscape/config.h
arch/arm/include/asm/arch-ls102xa/config.h
drivers/ddr/fsl/Kconfig

index eca1d06ca5dcbfc68298c2e08817c034174467fc..4b904f322373dd862cf87ce97c29c3a6b5da4cf2 100644 (file)
@@ -1,5 +1,9 @@
 config ARCH_LS1021A
        bool
+       select SYS_FSL_ERRATUM_A008378
+       select SYS_FSL_ERRATUM_A008407
+       select SYS_FSL_ERRATUM_A009663
+       select SYS_FSL_ERRATUM_A009942
        select SYS_FSL_ERRATUM_A010315
        select SYS_FSL_SRDS_1
        select SYS_HAS_SERDES
@@ -56,4 +60,7 @@ config SYS_FSL_IFC_BANK_COUNT
        depends on ARCH_LS1021A
        default 8
 
+config SYS_FSL_ERRATUM_A008407
+       bool
+
 endmenu
index bee7d1537cb495e3da4118c39998f623e2bf3cce..af84e40664355b4452119d78fa1e733af13d33e9 100644 (file)
@@ -11,6 +11,11 @@ config ARCH_LS1043A
        select SYS_FSL_DDR
        select SYS_FSL_DDR_BE
        select SYS_FSL_DDR_VER_50
+       select SYS_FSL_ERRATUM_A008850
+       select SYS_FSL_ERRATUM_A009660
+       select SYS_FSL_ERRATUM_A009663
+       select SYS_FSL_ERRATUM_A009929
+       select SYS_FSL_ERRATUM_A009942
        select SYS_FSL_ERRATUM_A010315
        select SYS_FSL_ERRATUM_A010539
        select SYS_FSL_HAS_DDR3
@@ -22,6 +27,11 @@ config ARCH_LS1046A
        select SYS_FSL_DDR
        select SYS_FSL_DDR_BE
        select SYS_FSL_DDR_VER_50
+       select SYS_FSL_ERRATUM_A008511
+       select SYS_FSL_ERRATUM_A009801
+       select SYS_FSL_ERRATUM_A009803
+       select SYS_FSL_ERRATUM_A009942
+       select SYS_FSL_ERRATUM_A010165
        select SYS_FSL_ERRATUM_A010539
        select SYS_FSL_HAS_DDR4
        select SYS_FSL_SRDS_2
@@ -38,6 +48,16 @@ config ARCH_LS2080A
        select SYS_FSL_SEC_COMPAT_5
        select SYS_FSL_SEC_LE
        select SYS_FSL_SRDS_2
+       select SYS_FSL_ERRATUM_A008336
+       select SYS_FSL_ERRATUM_A008511
+       select SYS_FSL_ERRATUM_A008514
+       select SYS_FSL_ERRATUM_A008585
+       select SYS_FSL_ERRATUM_A009635
+       select SYS_FSL_ERRATUM_A009663
+       select SYS_FSL_ERRATUM_A009801
+       select SYS_FSL_ERRATUM_A009803
+       select SYS_FSL_ERRATUM_A009942
+       select SYS_FSL_ERRATUM_A010165
 
 config FSL_LSCH2
        bool
@@ -132,3 +152,24 @@ config SYS_HAS_SERDES
        bool
 
 endmenu
+
+config SYS_FSL_ERRATUM_A008336
+       bool
+
+config SYS_FSL_ERRATUM_A008514
+       bool
+
+config SYS_FSL_ERRATUM_A008585
+       bool
+
+config SYS_FSL_ERRATUM_A008850
+       bool
+
+config SYS_FSL_ERRATUM_A009635
+       bool
+
+config SYS_FSL_ERRATUM_A009660
+       bool
+
+config SYS_FSL_ERRATUM_A009929
+       bool
index db40669e67f3fd5a43b806023671397d857a9205..6073d442dfd3145e4ebd2e5f946fbcb0eed7fd1e 100644 (file)
 #define EPU_EPCTR5             0x700060a14ULL
 #define EPU_EPGCR              0x700060000ULL
 
-#define CONFIG_SYS_FSL_ERRATUM_A008336
-#define CONFIG_SYS_FSL_ERRATUM_A008511
-#define CONFIG_SYS_FSL_ERRATUM_A008514
-#define CONFIG_SYS_FSL_ERRATUM_A008585
 #define CONFIG_SYS_FSL_ERRATUM_A008751
-#define CONFIG_SYS_FSL_ERRATUM_A009635
-#define CONFIG_SYS_FSL_ERRATUM_A009663
-#define CONFIG_SYS_FSL_ERRATUM_A009801
-#define CONFIG_SYS_FSL_ERRATUM_A009803
-#define CONFIG_SYS_FSL_ERRATUM_A009942
-#define CONFIG_SYS_FSL_ERRATUM_A010165
 
 /* ARM A57 CORE ERRATA */
 #define CONFIG_ARM_ERRATA_826974
 #define GICD_BASE              0x01401000
 #define GICC_BASE              0x01402000
 
-#define CONFIG_SYS_FSL_ERRATUM_A008850
-#define CONFIG_SYS_FSL_ERRATUM_A009663
-#define CONFIG_SYS_FSL_ERRATUM_A009929
-#define CONFIG_SYS_FSL_ERRATUM_A009942
-#define CONFIG_SYS_FSL_ERRATUM_A009660
 #define CONFIG_SYS_FSL_MAX_NUM_OF_SEC          1
 
 #elif defined(CONFIG_ARCH_LS1012A)
 
 #define CONFIG_SYS_FSL_MAX_NUM_OF_SEC          1
 
-#define CONFIG_SYS_FSL_ERRATUM_A008511
-#define CONFIG_SYS_FSL_ERRATUM_A009801
-#define CONFIG_SYS_FSL_ERRATUM_A009803
-#define CONFIG_SYS_FSL_ERRATUM_A009942
-#define CONFIG_SYS_FSL_ERRATUM_A010165
 #else
 #error SoC not defined
 #endif
index 1c5158b00bd30de65568fcc66fb3f4d7b2c84e03..fccd4ff14302a91663681510c5fac905786ff231 100644 (file)
@@ -91,7 +91,6 @@
 #define CONFIG_SYS_SCSI_MAX_DEVICE             (CONFIG_SYS_SCSI_MAX_SCSI_ID * \
                                                CONFIG_SYS_SCSI_MAX_LUN)
 #define CONFIG_DOS_PARTITION
-#define CONFIG_SYS_FSL_ERRATUM_A008407
 
 #ifdef CONFIG_DDR_SPD
 #define CONFIG_VERY_BIG_RAM
 
 #ifdef CONFIG_LS102XA
 #define CONFIG_USB_MAX_CONTROLLER_COUNT                1
-#define CONFIG_SYS_FSL_ERRATUM_A008378
-#define CONFIG_SYS_FSL_ERRATUM_A009663
-#define CONFIG_SYS_FSL_ERRATUM_A009942
 #define CONFIG_SYS_FSL_MAX_NUM_OF_SEC          1
 #else
 #error SoC not defined
index ad5858d123b186006c7b5a5a03656fef945da0a1..50adca51b2f6274136b48c98371193bb3aceb7f9 100644 (file)
@@ -120,3 +120,24 @@ config SYS_FSL_DDR1
 endchoice
 
 endmenu
+
+config SYS_FSL_ERRATUM_A008378
+       bool
+
+config SYS_FSL_ERRATUM_A008511
+       bool
+
+config SYS_FSL_ERRATUM_A009663
+       bool
+
+config SYS_FSL_ERRATUM_A009801
+       bool
+
+config SYS_FSL_ERRATUM_A009803
+       bool
+
+config SYS_FSL_ERRATUM_A009942
+       bool
+
+config SYS_FSL_ERRATUM_A010165
+       bool