[people/ms/u-boot.git] / arch / arm / dts / keystone.dtsi

/*
 * Copyright 2013 Texas Instruments, Inc.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */

#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/gpio/gpio.h>

#include "skeleton.dtsi"

/ {
	model = "Texas Instruments Keystone 2 SoC";
	#address-cells = <1>;
	#size-cells = <1>;
	interrupt-parent = <&gic>;

	aliases {
		serial0	= &uart0;
	};

	chosen {
		stdout-path = &uart0;
	};

	memory {
		reg = <0x80000000 0x40000000>;
	};

	gic: interrupt-controller {
		compatible = "arm,cortex-a15-gic";
		#interrupt-cells = <3>;
		interrupt-controller;
		reg = <0x02561000 0x1000>,
		      <0x02562000 0x2000>,
		      <0x02564000 0x1000>,
		      <0x02566000 0x2000>;
		interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) |
				IRQ_TYPE_LEVEL_HIGH)>;
	};

	timer {
		compatible = "arm,armv7-timer";
		interrupts =
			<GIC_PPI 13
				(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
			<GIC_PPI 14
				(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
			<GIC_PPI 11
				(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
			<GIC_PPI 10
				(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
	};

	pmu {
		compatible = "arm,cortex-a15-pmu";
		interrupts = <GIC_SPI 20 IRQ_TYPE_EDGE_RISING>,
			     <GIC_SPI 21 IRQ_TYPE_EDGE_RISING>,
			     <GIC_SPI 22 IRQ_TYPE_EDGE_RISING>,
			     <GIC_SPI 23 IRQ_TYPE_EDGE_RISING>;
	};

	soc {
		#address-cells = <1>;
		#size-cells = <1>;
		compatible = "ti,keystone","simple-bus";
		interrupt-parent = <&gic>;
		ranges;

		pllctrl: pll-controller@02310000 {
			compatible = "ti,keystone-pllctrl", "syscon";
			reg = <0x02310000 0x200>;
		};

		devctrl: device-state-control@02620000 {
			compatible = "ti,keystone-devctrl", "syscon";
			reg = <0x02620000 0x1000>;
		};

		rstctrl: reset-controller {
			compatible = "ti,keystone-reset";
			ti,syscon-pll = <&pllctrl 0xe4>;
			ti,syscon-dev = <&devctrl 0x328>;
			ti,wdt-list = <0>;
		};

		/include/ "keystone-clocks.dtsi"

		uart0: serial@02530c00 {
			compatible = "ns16550a";
			current-speed = <115200>;
			reg-shift = <2>;
			reg-io-width = <4>;
			reg = <0x02530c00 0x100>;
			clocks	= <&clkuart0>;
			interrupts = <GIC_SPI 277 IRQ_TYPE_EDGE_RISING>;
		};

		uart1:	serial@02531000 {
			compatible = "ns16550a";
			current-speed = <115200>;
			reg-shift = <2>;
			reg-io-width = <4>;
			reg = <0x02531000 0x100>;
			clocks	= <&clkuart1>;
			interrupts = <GIC_SPI 280 IRQ_TYPE_EDGE_RISING>;
		};

		i2c0: i2c@2530000 {
			compatible = "ti,davinci-i2c";
			reg = <0x02530000 0x400>;
			clock-frequency = <100000>;
			clocks = <&clki2c>;
			interrupts = <GIC_SPI 283 IRQ_TYPE_EDGE_RISING>;
			#address-cells = <1>;
			#size-cells = <0>;
		};

		i2c1: i2c@2530400 {
			compatible = "ti,davinci-i2c";
			reg = <0x02530400 0x400>;
			clock-frequency = <100000>;
			clocks = <&clki2c>;
			interrupts = <GIC_SPI 286 IRQ_TYPE_EDGE_RISING>;
			#address-cells = <1>;
			#size-cells = <0>;
		};

		i2c2: i2c@2530800 {
			compatible = "ti,davinci-i2c";
			reg = <0x02530800 0x400>;
			clock-frequency = <100000>;
			clocks = <&clki2c>;
			interrupts = <GIC_SPI 289 IRQ_TYPE_EDGE_RISING>;
			#address-cells = <1>;
			#size-cells = <0>;
		};

		spi0: spi@21000400 {
			compatible = "ti,dm6441-spi";
			reg = <0x21000400 0x200>;
			num-cs = <4>;
			ti,davinci-spi-intr-line = <0>;
			interrupts = <GIC_SPI 292 IRQ_TYPE_EDGE_RISING>;
			clocks = <&clkspi>;
			#address-cells = <1>;
			#size-cells = <0>;
		};

		spi1: spi@21000600 {
			compatible = "ti,dm6441-spi";
			reg = <0x21000600 0x200>;
			num-cs = <4>;
			ti,davinci-spi-intr-line = <0>;
			interrupts = <GIC_SPI 296 IRQ_TYPE_EDGE_RISING>;
			clocks = <&clkspi>;
			#address-cells = <1>;
			#size-cells = <0>;
		};

		spi2: spi@21000800 {
			compatible = "ti,dm6441-spi";
			reg = <0x21000800 0x200>;
			num-cs = <4>;
			ti,davinci-spi-intr-line = <0>;
			interrupts = <GIC_SPI 300 IRQ_TYPE_EDGE_RISING>;
			clocks = <&clkspi>;
			#address-cells = <1>;
			#size-cells = <0>;
		};

		usb_phy: usb_phy@2620738 {
			compatible = "ti,keystone-usbphy";
			#address-cells = <1>;
			#size-cells = <1>;
			reg = <0x2620738 24>;
			status = "disabled";
		};

		usb: usb@2680000 {
			compatible = "ti,keystone-dwc3";
			#address-cells = <1>;
			#size-cells = <1>;
			reg = <0x2680000 0x10000>;
			clocks = <&clkusb>;
			clock-names = "usb";
			interrupts = <GIC_SPI 393 IRQ_TYPE_EDGE_RISING>;
			ranges;
			dma-coherent;
			dma-ranges;
			status = "disabled";

			dwc3@2690000 {
				compatible = "synopsys,dwc3";
				reg = <0x2690000 0x70000>;
				interrupts = <GIC_SPI 393 IRQ_TYPE_EDGE_RISING>;
				usb-phy = <&usb_phy>, <&usb_phy>;
			};
		};

		wdt: wdt@022f0080 {
			compatible = "ti,keystone-wdt","ti,davinci-wdt";
			reg = <0x022f0080 0x80>;
			clocks = <&clkwdtimer0>;
		};

		clock_event: timer@22f0000 {
			compatible = "ti,keystone-timer";
			reg = <0x022f0000 0x80>;
			interrupts = <GIC_SPI 110 IRQ_TYPE_EDGE_RISING>;
			clocks = <&clktimer15>;
		};

		gpio0: gpio@260bf00 {
			compatible = "ti,keystone-gpio";
			reg = <0x0260bf00 0x100>;
			gpio-controller;
			#gpio-cells = <2>;
			/* HW Interrupts mapped to GPIO pins */
			interrupts = <GIC_SPI 120 IRQ_TYPE_EDGE_RISING>,
					<GIC_SPI 121 IRQ_TYPE_EDGE_RISING>,
					<GIC_SPI 122 IRQ_TYPE_EDGE_RISING>,
					<GIC_SPI 123 IRQ_TYPE_EDGE_RISING>,
					<GIC_SPI 124 IRQ_TYPE_EDGE_RISING>,
					<GIC_SPI 125 IRQ_TYPE_EDGE_RISING>,
					<GIC_SPI 126 IRQ_TYPE_EDGE_RISING>,
					<GIC_SPI 127 IRQ_TYPE_EDGE_RISING>,
					<GIC_SPI 128 IRQ_TYPE_EDGE_RISING>,
					<GIC_SPI 129 IRQ_TYPE_EDGE_RISING>,
					<GIC_SPI 130 IRQ_TYPE_EDGE_RISING>,
					<GIC_SPI 131 IRQ_TYPE_EDGE_RISING>,
					<GIC_SPI 132 IRQ_TYPE_EDGE_RISING>,
					<GIC_SPI 133 IRQ_TYPE_EDGE_RISING>,
					<GIC_SPI 134 IRQ_TYPE_EDGE_RISING>,
					<GIC_SPI 135 IRQ_TYPE_EDGE_RISING>,
					<GIC_SPI 136 IRQ_TYPE_EDGE_RISING>,
					<GIC_SPI 137 IRQ_TYPE_EDGE_RISING>,
					<GIC_SPI 138 IRQ_TYPE_EDGE_RISING>,
					<GIC_SPI 139 IRQ_TYPE_EDGE_RISING>,
					<GIC_SPI 140 IRQ_TYPE_EDGE_RISING>,
					<GIC_SPI 141 IRQ_TYPE_EDGE_RISING>,
					<GIC_SPI 142 IRQ_TYPE_EDGE_RISING>,
					<GIC_SPI 143 IRQ_TYPE_EDGE_RISING>,
					<GIC_SPI 144 IRQ_TYPE_EDGE_RISING>,
					<GIC_SPI 145 IRQ_TYPE_EDGE_RISING>,
					<GIC_SPI 146 IRQ_TYPE_EDGE_RISING>,
					<GIC_SPI 147 IRQ_TYPE_EDGE_RISING>,
					<GIC_SPI 148 IRQ_TYPE_EDGE_RISING>,
					<GIC_SPI 149 IRQ_TYPE_EDGE_RISING>,
					<GIC_SPI 150 IRQ_TYPE_EDGE_RISING>,
					<GIC_SPI 151 IRQ_TYPE_EDGE_RISING>;
			clocks = <&clkgpio>;
			clock-names = "gpio";
			ti,ngpio = <32>;
			ti,davinci-gpio-unbanked = <32>;
		};

		aemif: aemif@21000A00 {
			compatible = "ti,keystone-aemif", "ti,davinci-aemif";
			#address-cells = <2>;
			#size-cells = <1>;
			clocks = <&clkaemif>;
			clock-names = "aemif";
			clock-ranges;

			reg = <0x21000A00 0x00000100>;
			ranges = <0 0 0x30000000 0x10000000
				  1 0 0x21000A00 0x00000100>;
		};

		kirq0: keystone_irq@26202a0 {
			compatible = "ti,keystone-irq";
			interrupts = <GIC_SPI 4 IRQ_TYPE_EDGE_RISING>;
			interrupt-controller;
			#interrupt-cells = <1>;
			ti,syscon-dev = <&devctrl 0x2a0>;
		};

		pcie0: pcie@21800000 {
			compatible = "ti,keystone-pcie", "snps,dw-pcie";
			clocks = <&clkpcie>;
			clock-names = "pcie";
			#address-cells = <3>;
			#size-cells = <2>;
			reg =  <0x21801000 0x2000>, <0x21800000 0x1000>, <0x02620128 4>;
			ranges = <0x81000000 0 0 0x23250000 0 0x4000
				0x82000000 0 0x50000000 0x50000000 0 0x10000000>;

			status = "disabled";
			device_type = "pci";
			num-lanes = <2>;

			#interrupt-cells = <1>;
			interrupt-map-mask = <0 0 0 7>;
			interrupt-map = <0 0 0 1 &pcie_intc0 0>, /* INT A */
					<0 0 0 2 &pcie_intc0 1>, /* INT B */
					<0 0 0 3 &pcie_intc0 2>, /* INT C */
					<0 0 0 4 &pcie_intc0 3>; /* INT D */

			pcie_msi_intc0: msi-interrupt-controller {
				interrupt-controller;
				#interrupt-cells = <1>;
				interrupt-parent = <&gic>;
				interrupts = <GIC_SPI 30 IRQ_TYPE_EDGE_RISING>,
					<GIC_SPI 31 IRQ_TYPE_EDGE_RISING>,
					<GIC_SPI 32 IRQ_TYPE_EDGE_RISING>,
					<GIC_SPI 33 IRQ_TYPE_EDGE_RISING>,
					<GIC_SPI 34 IRQ_TYPE_EDGE_RISING>,
					<GIC_SPI 35 IRQ_TYPE_EDGE_RISING>,
					<GIC_SPI 36 IRQ_TYPE_EDGE_RISING>,
					<GIC_SPI 37 IRQ_TYPE_EDGE_RISING>;
			};

			pcie_intc0: legacy-interrupt-controller {
				interrupt-controller;
				#interrupt-cells = <1>;
				interrupt-parent = <&gic>;
				interrupts = <GIC_SPI 26 IRQ_TYPE_EDGE_RISING>,
					<GIC_SPI 27 IRQ_TYPE_EDGE_RISING>,
					<GIC_SPI 28 IRQ_TYPE_EDGE_RISING>,
					<GIC_SPI 29 IRQ_TYPE_EDGE_RISING>;
			};
		};
	};
};
Commit	Line	Data
351f9690 LV	1	/*
	2	* Copyright 2013 Texas Instruments, Inc.
	3	*
	4	* This program is free software; you can redistribute it and/or modify
	5	* it under the terms of the GNU General Public License version 2 as
	6	* published by the Free Software Foundation.
	7	*/
	8
	9	#include <dt-bindings/interrupt-controller/arm-gic.h>
	10	#include <dt-bindings/gpio/gpio.h>
	11
	12	#include "skeleton.dtsi"
	13
	14	/ {
	15	model = "Texas Instruments Keystone 2 SoC";
8a9bb065 LV	16	#address-cells = <1>;
8a9bb065 LV	17	#size-cells = <1>;
351f9690 LV	18	interrupt-parent = <&gic>;
	19
	20	aliases {
	21	serial0 = &uart0;
	22	};
	23
391839fb LV	24	chosen {
	25	stdout-path = &uart0;
	26	};
	27
351f9690	28	memory {
8a9bb065	29	reg = <0x80000000 0x40000000>;
351f9690 LV	30	};
	31
	32	gic: interrupt-controller {
	33	compatible = "arm,cortex-a15-gic";
	34	#interrupt-cells = <3>;
	35	interrupt-controller;
8a9bb065 LV	36	reg = <0x02561000 0x1000>,
	37	<0x02562000 0x2000>,
	38	<0x02564000 0x1000>,
	39	<0x02566000 0x2000>;
351f9690 LV	40	interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) \|
	41	IRQ_TYPE_LEVEL_HIGH)>;
	42	};
	43
	44	timer {
	45	compatible = "arm,armv7-timer";
	46	interrupts =
	47	<GIC_PPI 13
	48	(GIC_CPU_MASK_SIMPLE(4) \| IRQ_TYPE_LEVEL_LOW)>,
	49	<GIC_PPI 14
	50	(GIC_CPU_MASK_SIMPLE(4) \| IRQ_TYPE_LEVEL_LOW)>,
	51	<GIC_PPI 11
	52	(GIC_CPU_MASK_SIMPLE(4) \| IRQ_TYPE_LEVEL_LOW)>,
	53	<GIC_PPI 10
	54	(GIC_CPU_MASK_SIMPLE(4) \| IRQ_TYPE_LEVEL_LOW)>;
	55	};
	56
	57	pmu {
	58	compatible = "arm,cortex-a15-pmu";
	59	interrupts = <GIC_SPI 20 IRQ_TYPE_EDGE_RISING>,
	60	<GIC_SPI 21 IRQ_TYPE_EDGE_RISING>,
	61	<GIC_SPI 22 IRQ_TYPE_EDGE_RISING>,
	62	<GIC_SPI 23 IRQ_TYPE_EDGE_RISING>;
	63	};
	64
	65	soc {
	66	#address-cells = <1>;
	67	#size-cells = <1>;
	68	compatible = "ti,keystone","simple-bus";
	69	interrupt-parent = <&gic>;
8a9bb065	70	ranges;
351f9690 LV	71
	72	pllctrl: pll-controller@02310000 {
	73	compatible = "ti,keystone-pllctrl", "syscon";
	74	reg = <0x02310000 0x200>;
	75	};
	76
	77	devctrl: device-state-control@02620000 {
	78	compatible = "ti,keystone-devctrl", "syscon";
	79	reg = <0x02620000 0x1000>;
	80	};
	81
	82	rstctrl: reset-controller {
	83	compatible = "ti,keystone-reset";
	84	ti,syscon-pll = <&pllctrl 0xe4>;
	85	ti,syscon-dev = <&devctrl 0x328>;
	86	ti,wdt-list = <0>;
	87	};
	88
	89	/include/ "keystone-clocks.dtsi"
	90
	91	uart0: serial@02530c00 {
	92	compatible = "ns16550a";
	93	current-speed = <115200>;
	94	reg-shift = <2>;
	95	reg-io-width = <4>;
	96	reg = <0x02530c00 0x100>;
	97	clocks = <&clkuart0>;
	98	interrupts = <GIC_SPI 277 IRQ_TYPE_EDGE_RISING>;
	99	};
	100
	101	uart1: serial@02531000 {
	102	compatible = "ns16550a";
	103	current-speed = <115200>;
	104	reg-shift = <2>;
	105	reg-io-width = <4>;
	106	reg = <0x02531000 0x100>;
	107	clocks = <&clkuart1>;
	108	interrupts = <GIC_SPI 280 IRQ_TYPE_EDGE_RISING>;
	109	};
	110
	111	i2c0: i2c@2530000 {
	112	compatible = "ti,davinci-i2c";
	113	reg = <0x02530000 0x400>;
	114	clock-frequency = <100000>;
	115	clocks = <&clki2c>;
	116	interrupts = <GIC_SPI 283 IRQ_TYPE_EDGE_RISING>;
	117	#address-cells = <1>;
	118	#size-cells = <0>;
	119	};
	120
	121	i2c1: i2c@2530400 {
	122	compatible = "ti,davinci-i2c";
	123	reg = <0x02530400 0x400>;
	124	clock-frequency = <100000>;
	125	clocks = <&clki2c>;
	126	interrupts = <GIC_SPI 286 IRQ_TYPE_EDGE_RISING>;
	127	#address-cells = <1>;
	128	#size-cells = <0>;
	129	};
	130
	131	i2c2: i2c@2530800 {
	132	compatible = "ti,davinci-i2c";
	133	reg = <0x02530800 0x400>;
	134	clock-frequency = <100000>;
135	clocks = <&clki2c>;
136	interrupts = <GIC_SPI 289 IRQ_TYPE_EDGE_RISING>;
137	#address-cells = <1>;
138	#size-cells = <0>;
139	};
140
141	spi0: spi@21000400 {
142	compatible = "ti,dm6441-spi";
143	reg = <0x21000400 0x200>;
144	num-cs = <4>;
145	ti,davinci-spi-intr-line = <0>;
146	interrupts = <GIC_SPI 292 IRQ_TYPE_EDGE_RISING>;
147	clocks = <&clkspi>;
148	#address-cells = <1>;
149	#size-cells = <0>;
150	};
151
152	spi1: spi@21000600 {
153	compatible = "ti,dm6441-spi";
154	reg = <0x21000600 0x200>;
155	num-cs = <4>;
156	ti,davinci-spi-intr-line = <0>;
157	interrupts = <GIC_SPI 296 IRQ_TYPE_EDGE_RISING>;
158	clocks = <&clkspi>;
159	#address-cells = <1>;
160	#size-cells = <0>;
161	};
162
163	spi2: spi@21000800 {
164	compatible = "ti,dm6441-spi";
165	reg = <0x21000800 0x200>;
166	num-cs = <4>;
167	ti,davinci-spi-intr-line = <0>;
168	interrupts = <GIC_SPI 300 IRQ_TYPE_EDGE_RISING>;
169	clocks = <&clkspi>;
170	#address-cells = <1>;
171	#size-cells = <0>;
172	};
173
174	usb_phy: usb_phy@2620738 {
175	compatible = "ti,keystone-usbphy";
176	#address-cells = <1>;
177	#size-cells = <1>;
178	reg = <0x2620738 24>;
179	status = "disabled";
180	};
181
182	usb: usb@2680000 {
183	compatible = "ti,keystone-dwc3";
184	#address-cells = <1>;
185	#size-cells = <1>;
186	reg = <0x2680000 0x10000>;
187	clocks = <&clkusb>;
188	clock-names = "usb";
189	interrupts = <GIC_SPI 393 IRQ_TYPE_EDGE_RISING>;
190	ranges;
191	dma-coherent;
192	dma-ranges;
193	status = "disabled";
194
195	dwc3@2690000 {
196	compatible = "synopsys,dwc3";
197	reg = <0x2690000 0x70000>;
198	interrupts = <GIC_SPI 393 IRQ_TYPE_EDGE_RISING>;
199	usb-phy = <&usb_phy>, <&usb_phy>;
200	};
201	};
202
203	wdt: wdt@022f0080 {
204	compatible = "ti,keystone-wdt","ti,davinci-wdt";
205	reg = <0x022f0080 0x80>;
206	clocks = <&clkwdtimer0>;
207	};
208
209	clock_event: timer@22f0000 {
210	compatible = "ti,keystone-timer";
211	reg = <0x022f0000 0x80>;
212	interrupts = <GIC_SPI 110 IRQ_TYPE_EDGE_RISING>;
213	clocks = <&clktimer15>;
214	};
215
216	gpio0: gpio@260bf00 {
217	compatible = "ti,keystone-gpio";
218	reg = <0x0260bf00 0x100>;
219	gpio-controller;
220	#gpio-cells = <2>;
221	/* HW Interrupts mapped to GPIO pins */
222	interrupts = <GIC_SPI 120 IRQ_TYPE_EDGE_RISING>,
223	<GIC_SPI 121 IRQ_TYPE_EDGE_RISING>,
224	<GIC_SPI 122 IRQ_TYPE_EDGE_RISING>,
225	<GIC_SPI 123 IRQ_TYPE_EDGE_RISING>,
226	<GIC_SPI 124 IRQ_TYPE_EDGE_RISING>,
227	<GIC_SPI 125 IRQ_TYPE_EDGE_RISING>,
228	<GIC_SPI 126 IRQ_TYPE_EDGE_RISING>,
229	<GIC_SPI 127 IRQ_TYPE_EDGE_RISING>,
230	<GIC_SPI 128 IRQ_TYPE_EDGE_RISING>,
231	<GIC_SPI 129 IRQ_TYPE_EDGE_RISING>,
232	<GIC_SPI 130 IRQ_TYPE_EDGE_RISING>,
233	<GIC_SPI 131 IRQ_TYPE_EDGE_RISING>,
234	<GIC_SPI 132 IRQ_TYPE_EDGE_RISING>,
235	<GIC_SPI 133 IRQ_TYPE_EDGE_RISING>,
236	<GIC_SPI 134 IRQ_TYPE_EDGE_RISING>,
237	<GIC_SPI 135 IRQ_TYPE_EDGE_RISING>,
238	<GIC_SPI 136 IRQ_TYPE_EDGE_RISING>,
239	<GIC_SPI 137 IRQ_TYPE_EDGE_RISING>,
240	<GIC_SPI 138 IRQ_TYPE_EDGE_RISING>,
241	<GIC_SPI 139 IRQ_TYPE_EDGE_RISING>,
242	<GIC_SPI 140 IRQ_TYPE_EDGE_RISING>,
243	<GIC_SPI 141 IRQ_TYPE_EDGE_RISING>,
244	<GIC_SPI 142 IRQ_TYPE_EDGE_RISING>,
245	<GIC_SPI 143 IRQ_TYPE_EDGE_RISING>,
246	<GIC_SPI 144 IRQ_TYPE_EDGE_RISING>,
247	<GIC_SPI 145 IRQ_TYPE_EDGE_RISING>,
248	<GIC_SPI 146 IRQ_TYPE_EDGE_RISING>,
249	<GIC_SPI 147 IRQ_TYPE_EDGE_RISING>,
250	<GIC_SPI 148 IRQ_TYPE_EDGE_RISING>,
251	<GIC_SPI 149 IRQ_TYPE_EDGE_RISING>,
252	<GIC_SPI 150 IRQ_TYPE_EDGE_RISING>,
253	<GIC_SPI 151 IRQ_TYPE_EDGE_RISING>;
254	clocks = <&clkgpio>;
255	clock-names = "gpio";
256	ti,ngpio = <32>;
257	ti,davinci-gpio-unbanked = <32>;
258	};
259
260	aemif: aemif@21000A00 {
261	compatible = "ti,keystone-aemif", "ti,davinci-aemif";
262	#address-cells = <2>;
263	#size-cells = <1>;
264	clocks = <&clkaemif>;
265	clock-names = "aemif";
266	clock-ranges;
267
268	reg = <0x21000A00 0x00000100>;
269	ranges = <0 0 0x30000000 0x10000000
270	1 0 0x21000A00 0x00000100>;
271	};
272
273	kirq0: keystone_irq@26202a0 {
274	compatible = "ti,keystone-irq";
275	interrupts = <GIC_SPI 4 IRQ_TYPE_EDGE_RISING>;
276	interrupt-controller;
277	#interrupt-cells = <1>;
278	ti,syscon-dev = <&devctrl 0x2a0>;
279	};
280
281	pcie0: pcie@21800000 {
282	compatible = "ti,keystone-pcie", "snps,dw-pcie";
283	clocks = <&clkpcie>;
284	clock-names = "pcie";
285	#address-cells = <3>;
286	#size-cells = <2>;
287	reg = <0x21801000 0x2000>, <0x21800000 0x1000>, <0x02620128 4>;
288	ranges = <0x81000000 0 0 0x23250000 0 0x4000
289	0x82000000 0 0x50000000 0x50000000 0 0x10000000>;
290
291	status = "disabled";
292	device_type = "pci";
293	num-lanes = <2>;
294
295	#interrupt-cells = <1>;
296	interrupt-map-mask = <0 0 0 7>;
297	interrupt-map = <0 0 0 1 &pcie_intc0 0>, /* INT A */
298	<0 0 0 2 &pcie_intc0 1>, /* INT B */
299	<0 0 0 3 &pcie_intc0 2>, /* INT C */
300	<0 0 0 4 &pcie_intc0 3>; /* INT D */
301
302	pcie_msi_intc0: msi-interrupt-controller {
303	interrupt-controller;
304	#interrupt-cells = <1>;
305	interrupt-parent = <&gic>;
306	interrupts = <GIC_SPI 30 IRQ_TYPE_EDGE_RISING>,
307	<GIC_SPI 31 IRQ_TYPE_EDGE_RISING>,
308	<GIC_SPI 32 IRQ_TYPE_EDGE_RISING>,
309	<GIC_SPI 33 IRQ_TYPE_EDGE_RISING>,
310	<GIC_SPI 34 IRQ_TYPE_EDGE_RISING>,
311	<GIC_SPI 35 IRQ_TYPE_EDGE_RISING>,
312	<GIC_SPI 36 IRQ_TYPE_EDGE_RISING>,
313	<GIC_SPI 37 IRQ_TYPE_EDGE_RISING>;
314	};
315
316	pcie_intc0: legacy-interrupt-controller {
317	interrupt-controller;
318	#interrupt-cells = <1>;
319	interrupt-parent = <&gic>;
320	interrupts = <GIC_SPI 26 IRQ_TYPE_EDGE_RISING>,
321	<GIC_SPI 27 IRQ_TYPE_EDGE_RISING>,
322	<GIC_SPI 28 IRQ_TYPE_EDGE_RISING>,
323	<GIC_SPI 29 IRQ_TYPE_EDGE_RISING>;
324	};
325	};
326	};
327	};