[people/ms/u-boot.git] / arch / arm / dts / sun5i.dtsi

/*
 * Copyright 2012-2015 Maxime Ripard
 *
 * Maxime Ripard <maxime.ripard@free-electrons.com>
 *
 * This file is dual-licensed: you can use it either under the terms
 * of the GPL or the X11 license, at your option. Note that this dual
 * licensing only applies to this file, and not this project as a
 * whole.
 *
 *  a) This library is free software; you can redistribute it and/or
 *     modify it under the terms of the GNU General Public License as
 *     published by the Free Software Foundation; either version 2 of the
 *     License, or (at your option) any later version.
 *
 *     This library is distributed in the hope that it will be useful,
 *     but WITHOUT ANY WARRANTY; without even the implied warranty of
 *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 *     GNU General Public License for more details.
 *
 * Or, alternatively,
 *
 *  b) Permission is hereby granted, free of charge, to any person
 *     obtaining a copy of this software and associated documentation
 *     files (the "Software"), to deal in the Software without
 *     restriction, including without limitation the rights to use,
 *     copy, modify, merge, publish, distribute, sublicense, and/or
 *     sell copies of the Software, and to permit persons to whom the
 *     Software is furnished to do so, subject to the following
 *     conditions:
 *
 *     The above copyright notice and this permission notice shall be
 *     included in all copies or substantial portions of the Software.
 *
 *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
 *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
 *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
 *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
 *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
 *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
 *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 *     OTHER DEALINGS IN THE SOFTWARE.
 */

#include "skeleton.dtsi"

#include <dt-bindings/dma/sun4i-a10.h>
#include <dt-bindings/pinctrl/sun4i-a10.h>

/ {
	interrupt-parent = <&intc>;

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		cpu0: cpu@0 {
			device_type = "cpu";
			compatible = "arm,cortex-a8";
			reg = <0x0>;
			clocks = <&cpu>;
		};
	};

	clocks {
		#address-cells = <1>;
		#size-cells = <1>;
		ranges;

		/*
		 * This is a dummy clock, to be used as placeholder on
		 * other mux clocks when a specific parent clock is not
		 * yet implemented. It should be dropped when the driver
		 * is complete.
		 */
		dummy: dummy {
			#clock-cells = <0>;
			compatible = "fixed-clock";
			clock-frequency = <0>;
		};

		osc24M: clk@01c20050 {
			#clock-cells = <0>;
			compatible = "allwinner,sun4i-a10-osc-clk";
			reg = <0x01c20050 0x4>;
			clock-frequency = <24000000>;
			clock-output-names = "osc24M";
		};

		osc32k: clk@0 {
			#clock-cells = <0>;
			compatible = "fixed-clock";
			clock-frequency = <32768>;
			clock-output-names = "osc32k";
		};

		pll1: clk@01c20000 {
			#clock-cells = <0>;
			compatible = "allwinner,sun4i-a10-pll1-clk";
			reg = <0x01c20000 0x4>;
			clocks = <&osc24M>;
			clock-output-names = "pll1";
		};

		pll4: clk@01c20018 {
			#clock-cells = <0>;
			compatible = "allwinner,sun4i-a10-pll1-clk";
			reg = <0x01c20018 0x4>;
			clocks = <&osc24M>;
			clock-output-names = "pll4";
		};

		pll5: clk@01c20020 {
			#clock-cells = <1>;
			compatible = "allwinner,sun4i-a10-pll5-clk";
			reg = <0x01c20020 0x4>;
			clocks = <&osc24M>;
			clock-output-names = "pll5_ddr", "pll5_other";
		};

		pll6: clk@01c20028 {
			#clock-cells = <1>;
			compatible = "allwinner,sun4i-a10-pll6-clk";
			reg = <0x01c20028 0x4>;
			clocks = <&osc24M>;
			clock-output-names = "pll6_sata", "pll6_other", "pll6";
		};

		/* dummy is 200M */
		cpu: cpu@01c20054 {
			#clock-cells = <0>;
			compatible = "allwinner,sun4i-a10-cpu-clk";
			reg = <0x01c20054 0x4>;
			clocks = <&osc32k>, <&osc24M>, <&pll1>, <&dummy>;
			clock-output-names = "cpu";
		};

		axi: axi@01c20054 {
			#clock-cells = <0>;
			compatible = "allwinner,sun4i-a10-axi-clk";
			reg = <0x01c20054 0x4>;
			clocks = <&cpu>;
			clock-output-names = "axi";
		};

		ahb: ahb@01c20054 {
			#clock-cells = <0>;
			compatible = "allwinner,sun5i-a13-ahb-clk";
			reg = <0x01c20054 0x4>;
			clocks = <&axi>, <&cpu>, <&pll6 1>;
			clock-output-names = "ahb";
			/*
			 * Use PLL6 as parent, instead of CPU/AXI
			 * which has rate changes due to cpufreq
			 */
			assigned-clocks = <&ahb>;
			assigned-clock-parents = <&pll6 1>;
		};

		apb0: apb0@01c20054 {
			#clock-cells = <0>;
			compatible = "allwinner,sun4i-a10-apb0-clk";
			reg = <0x01c20054 0x4>;
			clocks = <&ahb>;
			clock-output-names = "apb0";
		};

		apb1: clk@01c20058 {
			#clock-cells = <0>;
			compatible = "allwinner,sun4i-a10-apb1-clk";
			reg = <0x01c20058 0x4>;
			clocks = <&osc24M>, <&pll6 1>, <&osc32k>;
			clock-output-names = "apb1";
		};

		axi_gates: clk@01c2005c {
			#clock-cells = <1>;
			compatible = "allwinner,sun4i-a10-axi-gates-clk";
			reg = <0x01c2005c 0x4>;
			clocks = <&axi>;
			clock-indices = <0>;
			clock-output-names = "axi_dram";
		};

		nand_clk: clk@01c20080 {
			#clock-cells = <0>;
			compatible = "allwinner,sun4i-a10-mod0-clk";
			reg = <0x01c20080 0x4>;
			clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
			clock-output-names = "nand";
		};

		ms_clk: clk@01c20084 {
			#clock-cells = <0>;
			compatible = "allwinner,sun4i-a10-mod0-clk";
			reg = <0x01c20084 0x4>;
			clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
			clock-output-names = "ms";
		};

		mmc0_clk: clk@01c20088 {
			#clock-cells = <1>;
			compatible = "allwinner,sun4i-a10-mmc-clk";
			reg = <0x01c20088 0x4>;
			clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
			clock-output-names = "mmc0",
					     "mmc0_output",
					     "mmc0_sample";
		};

		mmc1_clk: clk@01c2008c {
			#clock-cells = <1>;
			compatible = "allwinner,sun4i-a10-mmc-clk";
			reg = <0x01c2008c 0x4>;
			clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
			clock-output-names = "mmc1",
					     "mmc1_output",
					     "mmc1_sample";
		};

		mmc2_clk: clk@01c20090 {
			#clock-cells = <1>;
			compatible = "allwinner,sun4i-a10-mmc-clk";
			reg = <0x01c20090 0x4>;
			clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
			clock-output-names = "mmc2",
					     "mmc2_output",
					     "mmc2_sample";
		};

		ts_clk: clk@01c20098 {
			#clock-cells = <0>;
			compatible = "allwinner,sun4i-a10-mod0-clk";
			reg = <0x01c20098 0x4>;
			clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
			clock-output-names = "ts";
		};

		ss_clk: clk@01c2009c {
			#clock-cells = <0>;
			compatible = "allwinner,sun4i-a10-mod0-clk";
			reg = <0x01c2009c 0x4>;
			clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
			clock-output-names = "ss";
		};

		spi0_clk: clk@01c200a0 {
			#clock-cells = <0>;
			compatible = "allwinner,sun4i-a10-mod0-clk";
			reg = <0x01c200a0 0x4>;
			clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
			clock-output-names = "spi0";
		};

		spi1_clk: clk@01c200a4 {
			#clock-cells = <0>;
			compatible = "allwinner,sun4i-a10-mod0-clk";
			reg = <0x01c200a4 0x4>;
			clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
			clock-output-names = "spi1";
		};

		spi2_clk: clk@01c200a8 {
			#clock-cells = <0>;
			compatible = "allwinner,sun4i-a10-mod0-clk";
			reg = <0x01c200a8 0x4>;
			clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
			clock-output-names = "spi2";
		};

		ir0_clk: clk@01c200b0 {
			#clock-cells = <0>;
			compatible = "allwinner,sun4i-a10-mod0-clk";
			reg = <0x01c200b0 0x4>;
			clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
			clock-output-names = "ir0";
		};

		usb_clk: clk@01c200cc {
			#clock-cells = <1>;
			#reset-cells = <1>;
			compatible = "allwinner,sun5i-a13-usb-clk";
			reg = <0x01c200cc 0x4>;
			clocks = <&pll6 1>;
			clock-output-names = "usb_ohci0", "usb_phy";
		};

		mbus_clk: clk@01c2015c {
			#clock-cells = <0>;
			compatible = "allwinner,sun5i-a13-mbus-clk";
			reg = <0x01c2015c 0x4>;
			clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
			clock-output-names = "mbus";
		};
	};

	soc@01c00000 {
		compatible = "simple-bus";
		#address-cells = <1>;
		#size-cells = <1>;
		ranges;

		sram-controller@01c00000 {
			compatible = "allwinner,sun4i-a10-sram-controller";
			reg = <0x01c00000 0x30>;
			#address-cells = <1>;
			#size-cells = <1>;
			ranges;

			sram_a: sram@00000000 {
				compatible = "mmio-sram";
				reg = <0x00000000 0xc000>;
				#address-cells = <1>;
				#size-cells = <1>;
				ranges = <0 0x00000000 0xc000>;
			};

			sram_d: sram@00010000 {
				compatible = "mmio-sram";
				reg = <0x00010000 0x1000>;
				#address-cells = <1>;
				#size-cells = <1>;
				ranges = <0 0x00010000 0x1000>;

				otg_sram: sram-section@0000 {
					compatible = "allwinner,sun4i-a10-sram-d";
					reg = <0x0000 0x1000>;
					status = "disabled";
				};
			};
		};

		dma: dma-controller@01c02000 {
			compatible = "allwinner,sun4i-a10-dma";
			reg = <0x01c02000 0x1000>;
			interrupts = <27>;
			clocks = <&ahb_gates 6>;
			#dma-cells = <2>;
		};

		spi0: spi@01c05000 {
			compatible = "allwinner,sun4i-a10-spi";
			reg = <0x01c05000 0x1000>;
			interrupts = <10>;
			clocks = <&ahb_gates 20>, <&spi0_clk>;
			clock-names = "ahb", "mod";
			dmas = <&dma SUN4I_DMA_DEDICATED 27>,
			       <&dma SUN4I_DMA_DEDICATED 26>;
			dma-names = "rx", "tx";
			status = "disabled";
			#address-cells = <1>;
			#size-cells = <0>;
		};

		spi1: spi@01c06000 {
			compatible = "allwinner,sun4i-a10-spi";
			reg = <0x01c06000 0x1000>;
			interrupts = <11>;
			clocks = <&ahb_gates 21>, <&spi1_clk>;
			clock-names = "ahb", "mod";
			dmas = <&dma SUN4I_DMA_DEDICATED 9>,
			       <&dma SUN4I_DMA_DEDICATED 8>;
			dma-names = "rx", "tx";
			status = "disabled";
			#address-cells = <1>;
			#size-cells = <0>;
		};

		mmc0: mmc@01c0f000 {
			compatible = "allwinner,sun5i-a13-mmc";
			reg = <0x01c0f000 0x1000>;
			clocks = <&ahb_gates 8>,
				 <&mmc0_clk 0>,
				 <&mmc0_clk 1>,
				 <&mmc0_clk 2>;
			clock-names = "ahb",
				      "mmc",
				      "output",
				      "sample";
			interrupts = <32>;
			status = "disabled";
			#address-cells = <1>;
			#size-cells = <0>;
		};

		mmc1: mmc@01c10000 {
			compatible = "allwinner,sun5i-a13-mmc";
			reg = <0x01c10000 0x1000>;
			clocks = <&ahb_gates 9>,
				 <&mmc1_clk 0>,
				 <&mmc1_clk 1>,
				 <&mmc1_clk 2>;
			clock-names = "ahb",
				      "mmc",
				      "output",
				      "sample";
			interrupts = <33>;
			status = "disabled";
			#address-cells = <1>;
			#size-cells = <0>;
		};

		mmc2: mmc@01c11000 {
			compatible = "allwinner,sun5i-a13-mmc";
			reg = <0x01c11000 0x1000>;
			clocks = <&ahb_gates 10>,
				 <&mmc2_clk 0>,
				 <&mmc2_clk 1>,
				 <&mmc2_clk 2>;
			clock-names = "ahb",
				      "mmc",
				      "output",
				      "sample";
			interrupts = <34>;
			status = "disabled";
			#address-cells = <1>;
			#size-cells = <0>;
		};

		usb_otg: usb@01c13000 {
			compatible = "allwinner,sun4i-a10-musb";
			reg = <0x01c13000 0x0400>;
			clocks = <&ahb_gates 0>;
			interrupts = <38>;
			interrupt-names = "mc";
			phys = <&usbphy 0>;
			phy-names = "usb";
			extcon = <&usbphy 0>;
			allwinner,sram = <&otg_sram 1>;
			status = "disabled";
		};

		usbphy: phy@01c13400 {
			#phy-cells = <1>;
			compatible = "allwinner,sun5i-a13-usb-phy";
			reg = <0x01c13400 0x10 0x01c14800 0x4>;
			reg-names = "phy_ctrl", "pmu1";
			clocks = <&usb_clk 8>;
			clock-names = "usb_phy";
			resets = <&usb_clk 0>, <&usb_clk 1>;
			reset-names = "usb0_reset", "usb1_reset";
			status = "disabled";
		};

		ehci0: usb@01c14000 {
			compatible = "allwinner,sun5i-a13-ehci", "generic-ehci";
			reg = <0x01c14000 0x100>;
			interrupts = <39>;
			clocks = <&ahb_gates 1>;
			phys = <&usbphy 1>;
			phy-names = "usb";
			status = "disabled";
		};

		ohci0: usb@01c14400 {
			compatible = "allwinner,sun5i-a13-ohci", "generic-ohci";
			reg = <0x01c14400 0x100>;
			interrupts = <40>;
			clocks = <&usb_clk 6>, <&ahb_gates 2>;
			phys = <&usbphy 1>;
			phy-names = "usb";
			status = "disabled";
		};

		spi2: spi@01c17000 {
			compatible = "allwinner,sun4i-a10-spi";
			reg = <0x01c17000 0x1000>;
			interrupts = <12>;
			clocks = <&ahb_gates 22>, <&spi2_clk>;
			clock-names = "ahb", "mod";
			dmas = <&dma SUN4I_DMA_DEDICATED 29>,
			       <&dma SUN4I_DMA_DEDICATED 28>;
			dma-names = "rx", "tx";
			status = "disabled";
			#address-cells = <1>;
			#size-cells = <0>;
		};

		intc: interrupt-controller@01c20400 {
			compatible = "allwinner,sun4i-a10-ic";
			reg = <0x01c20400 0x400>;
			interrupt-controller;
			#interrupt-cells = <1>;
		};

		pio: pinctrl@01c20800 {
			reg = <0x01c20800 0x400>;
			interrupts = <28>;
			clocks = <&apb0_gates 5>;
			gpio-controller;
			interrupt-controller;
			#interrupt-cells = <3>;
			#gpio-cells = <3>;

			i2c0_pins_a: i2c0@0 {
				allwinner,pins = "PB0", "PB1";
				allwinner,function = "i2c0";
				allwinner,drive = <SUN4I_PINCTRL_10_MA>;
				allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
			};

			i2c1_pins_a: i2c1@0 {
				allwinner,pins = "PB15", "PB16";
				allwinner,function = "i2c1";
				allwinner,drive = <SUN4I_PINCTRL_10_MA>;
				allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
			};

			i2c2_pins_a: i2c2@0 {
				allwinner,pins = "PB17", "PB18";
				allwinner,function = "i2c2";
				allwinner,drive = <SUN4I_PINCTRL_10_MA>;
				allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
			};

			mmc0_pins_a: mmc0@0 {
				allwinner,pins = "PF0", "PF1", "PF2", "PF3",
						 "PF4", "PF5";
				allwinner,function = "mmc0";
				allwinner,drive = <SUN4I_PINCTRL_30_MA>;
				allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
			};

			mmc2_pins_a: mmc2@0 {
				allwinner,pins = "PC6", "PC7", "PC8", "PC9",
					"PC10", "PC11", "PC12", "PC13",
					"PC14", "PC15";
				allwinner,function = "mmc2";
				allwinner,drive = <SUN4I_PINCTRL_30_MA>;
				allwinner,pull = <SUN4I_PINCTRL_PULL_UP>;
			};

			uart3_pins_a: uart3@0 {
				allwinner,pins = "PG9", "PG10";
				allwinner,function = "uart3";
				allwinner,drive = <SUN4I_PINCTRL_10_MA>;
				allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
			};

			uart3_pins_cts_rts_a: uart3-cts-rts@0 {
				allwinner,pins = "PG11", "PG12";
				allwinner,function = "uart3";
				allwinner,drive = <SUN4I_PINCTRL_10_MA>;
				allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
			};

			pwm0_pins: pwm0 {
				allwinner,pins = "PB2";
				allwinner,function = "pwm";
				allwinner,drive = <SUN4I_PINCTRL_10_MA>;
				allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
			};
		};

		timer@01c20c00 {
			compatible = "allwinner,sun4i-a10-timer";
			reg = <0x01c20c00 0x90>;
			interrupts = <22>;
			clocks = <&osc24M>;
		};

		wdt: watchdog@01c20c90 {
			compatible = "allwinner,sun4i-a10-wdt";
			reg = <0x01c20c90 0x10>;
		};

		lradc: lradc@01c22800 {
			compatible = "allwinner,sun4i-a10-lradc-keys";
			reg = <0x01c22800 0x100>;
			interrupts = <31>;
			status = "disabled";
		};

		sid: eeprom@01c23800 {
			compatible = "allwinner,sun4i-a10-sid";
			reg = <0x01c23800 0x10>;
		};

		rtp: rtp@01c25000 {
			compatible = "allwinner,sun5i-a13-ts";
			reg = <0x01c25000 0x100>;
			interrupts = <29>;
			#thermal-sensor-cells = <0>;
		};

		uart1: serial@01c28400 {
			compatible = "snps,dw-apb-uart";
			reg = <0x01c28400 0x400>;
			interrupts = <2>;
			reg-shift = <2>;
			reg-io-width = <4>;
			clocks = <&apb1_gates 17>;
			status = "disabled";
		};

		uart3: serial@01c28c00 {
			compatible = "snps,dw-apb-uart";
			reg = <0x01c28c00 0x400>;
			interrupts = <4>;
			reg-shift = <2>;
			reg-io-width = <4>;
			clocks = <&apb1_gates 19>;
			status = "disabled";
		};

		i2c0: i2c@01c2ac00 {
			compatible = "allwinner,sun4i-a10-i2c";
			reg = <0x01c2ac00 0x400>;
			interrupts = <7>;
			clocks = <&apb1_gates 0>;
			status = "disabled";
			#address-cells = <1>;
			#size-cells = <0>;
		};

		i2c1: i2c@01c2b000 {
			compatible = "allwinner,sun4i-a10-i2c";
			reg = <0x01c2b000 0x400>;
			interrupts = <8>;
			clocks = <&apb1_gates 1>;
			status = "disabled";
			#address-cells = <1>;
			#size-cells = <0>;
		};

		i2c2: i2c@01c2b400 {
			compatible = "allwinner,sun4i-a10-i2c";
			reg = <0x01c2b400 0x400>;
			interrupts = <9>;
			clocks = <&apb1_gates 2>;
			status = "disabled";
			#address-cells = <1>;
			#size-cells = <0>;
		};

		timer@01c60000 {
			compatible = "allwinner,sun5i-a13-hstimer";
			reg = <0x01c60000 0x1000>;
			interrupts = <82>, <83>;
			clocks = <&ahb_gates 28>;
		};
	};
};
Commit	Line	Data
53ab4af3 HG	1	/*
	2	* Copyright 2012-2015 Maxime Ripard
	3	*
	4	* Maxime Ripard <maxime.ripard@free-electrons.com>
	5	*
	6	* This file is dual-licensed: you can use it either under the terms
	7	* of the GPL or the X11 license, at your option. Note that this dual
	8	* licensing only applies to this file, and not this project as a
	9	* whole.
	10	*
	11	* a) This library is free software; you can redistribute it and/or
	12	* modify it under the terms of the GNU General Public License as
	13	* published by the Free Software Foundation; either version 2 of the
	14	* License, or (at your option) any later version.
	15	*
	16	* This library is distributed in the hope that it will be useful,
	17	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	18	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	19	* GNU General Public License for more details.
	20	*
53ab4af3 HG	21	* Or, alternatively,
	22	*
	23	* b) Permission is hereby granted, free of charge, to any person
	24	* obtaining a copy of this software and associated documentation
	25	* files (the "Software"), to deal in the Software without
	26	* restriction, including without limitation the rights to use,
	27	* copy, modify, merge, publish, distribute, sublicense, and/or
	28	* sell copies of the Software, and to permit persons to whom the
	29	* Software is furnished to do so, subject to the following
	30	* conditions:
	31	*
	32	* The above copyright notice and this permission notice shall be
	33	* included in all copies or substantial portions of the Software.
	34	*
	35	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
	36	* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
	37	* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
	38	* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
	39	* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
	40	* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
	41	* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
	42	* OTHER DEALINGS IN THE SOFTWARE.
	43	*/
	44
	45	#include "skeleton.dtsi"
	46
	47	#include <dt-bindings/dma/sun4i-a10.h>
	48	#include <dt-bindings/pinctrl/sun4i-a10.h>
	49
	50	/ {
	51	interrupt-parent = <&intc>;
	52
	53	cpus {
	54	#address-cells = <1>;
	55	#size-cells = <0>;
	56
	57	cpu0: cpu@0 {
	58	device_type = "cpu";
	59	compatible = "arm,cortex-a8";
	60	reg = <0x0>;
	61	clocks = <&cpu>;
	62	};
	63	};
	64
	65	clocks {
	66	#address-cells = <1>;
	67	#size-cells = <1>;
	68	ranges;
	69
	70	/*
	71	* This is a dummy clock, to be used as placeholder on
	72	* other mux clocks when a specific parent clock is not
	73	* yet implemented. It should be dropped when the driver
	74	* is complete.
	75	*/
	76	dummy: dummy {
	77	#clock-cells = <0>;
	78	compatible = "fixed-clock";
	79	clock-frequency = <0>;
	80	};
	81
	82	osc24M: clk@01c20050 {
	83	#clock-cells = <0>;
	84	compatible = "allwinner,sun4i-a10-osc-clk";
85	reg = <0x01c20050 0x4>;
86	clock-frequency = <24000000>;
87	clock-output-names = "osc24M";
88	};
89
90	osc32k: clk@0 {
91	#clock-cells = <0>;
92	compatible = "fixed-clock";
93	clock-frequency = <32768>;
94	clock-output-names = "osc32k";
95	};
96
97	pll1: clk@01c20000 {
98	#clock-cells = <0>;
99	compatible = "allwinner,sun4i-a10-pll1-clk";
100	reg = <0x01c20000 0x4>;
101	clocks = <&osc24M>;
102	clock-output-names = "pll1";
103	};
104
105	pll4: clk@01c20018 {
106	#clock-cells = <0>;
107	compatible = "allwinner,sun4i-a10-pll1-clk";
108	reg = <0x01c20018 0x4>;
109	clocks = <&osc24M>;
110	clock-output-names = "pll4";
111	};
112
113	pll5: clk@01c20020 {
114	#clock-cells = <1>;
115	compatible = "allwinner,sun4i-a10-pll5-clk";
116	reg = <0x01c20020 0x4>;
117	clocks = <&osc24M>;
118	clock-output-names = "pll5_ddr", "pll5_other";
119	};
120
121	pll6: clk@01c20028 {
122	#clock-cells = <1>;
123	compatible = "allwinner,sun4i-a10-pll6-clk";
124	reg = <0x01c20028 0x4>;
125	clocks = <&osc24M>;
126	clock-output-names = "pll6_sata", "pll6_other", "pll6";
127	};
128
129	/* dummy is 200M */
130	cpu: cpu@01c20054 {
131	#clock-cells = <0>;
132	compatible = "allwinner,sun4i-a10-cpu-clk";
133	reg = <0x01c20054 0x4>;
134	clocks = <&osc32k>, <&osc24M>, <&pll1>, <&dummy>;
135	clock-output-names = "cpu";
136	};
137
138	axi: axi@01c20054 {
139	#clock-cells = <0>;
140	compatible = "allwinner,sun4i-a10-axi-clk";
141	reg = <0x01c20054 0x4>;
142	clocks = <&cpu>;
143	clock-output-names = "axi";
144	};
145
146	ahb: ahb@01c20054 {
147	#clock-cells = <0>;
8b1ba941	148	compatible = "allwinner,sun5i-a13-ahb-clk";
53ab4af3	149	reg = <0x01c20054 0x4>;
8b1ba941	150	clocks = <&axi>, <&cpu>, <&pll6 1>;
53ab4af3	151	clock-output-names = "ahb";
8b1ba941 HG	152	/*
	153	* Use PLL6 as parent, instead of CPU/AXI
	154	* which has rate changes due to cpufreq
	155	*/
	156	assigned-clocks = <&ahb>;
	157	assigned-clock-parents = <&pll6 1>;
53ab4af3 HG	158	};
	159
	160	apb0: apb0@01c20054 {
	161	#clock-cells = <0>;
	162	compatible = "allwinner,sun4i-a10-apb0-clk";
	163	reg = <0x01c20054 0x4>;
	164	clocks = <&ahb>;
	165	clock-output-names = "apb0";
	166	};
	167
	168	apb1: clk@01c20058 {
	169	#clock-cells = <0>;
	170	compatible = "allwinner,sun4i-a10-apb1-clk";
	171	reg = <0x01c20058 0x4>;
	172	clocks = <&osc24M>, <&pll6 1>, <&osc32k>;
	173	clock-output-names = "apb1";
	174	};
	175
	176	axi_gates: clk@01c2005c {
	177	#clock-cells = <1>;
	178	compatible = "allwinner,sun4i-a10-axi-gates-clk";
	179	reg = <0x01c2005c 0x4>;
	180	clocks = <&axi>;
f0e8e8da	181	clock-indices = <0>;
53ab4af3 HG	182	clock-output-names = "axi_dram";
	183	};
	184
	185	nand_clk: clk@01c20080 {
	186	#clock-cells = <0>;
	187	compatible = "allwinner,sun4i-a10-mod0-clk";
	188	reg = <0x01c20080 0x4>;
	189	clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
	190	clock-output-names = "nand";
	191	};
	192
	193	ms_clk: clk@01c20084 {
	194	#clock-cells = <0>;
	195	compatible = "allwinner,sun4i-a10-mod0-clk";
	196	reg = <0x01c20084 0x4>;
	197	clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
	198	clock-output-names = "ms";
	199	};
	200
	201	mmc0_clk: clk@01c20088 {
	202	#clock-cells = <1>;
	203	compatible = "allwinner,sun4i-a10-mmc-clk";
	204	reg = <0x01c20088 0x4>;
	205	clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
	206	clock-output-names = "mmc0",
	207	"mmc0_output",
	208	"mmc0_sample";
	209	};
	210
	211	mmc1_clk: clk@01c2008c {
	212	#clock-cells = <1>;
	213	compatible = "allwinner,sun4i-a10-mmc-clk";
	214	reg = <0x01c2008c 0x4>;
	215	clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
	216	clock-output-names = "mmc1",
	217	"mmc1_output",
	218	"mmc1_sample";
	219	};
	220
	221	mmc2_clk: clk@01c20090 {
	222	#clock-cells = <1>;
	223	compatible = "allwinner,sun4i-a10-mmc-clk";
	224	reg = <0x01c20090 0x4>;
	225	clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
	226	clock-output-names = "mmc2",
	227	"mmc2_output",
	228	"mmc2_sample";
	229	};
	230
	231	ts_clk: clk@01c20098 {
	232	#clock-cells = <0>;
	233	compatible = "allwinner,sun4i-a10-mod0-clk";
	234	reg = <0x01c20098 0x4>;
	235	clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
	236	clock-output-names = "ts";
	237	};
	238
	239	ss_clk: clk@01c2009c {
	240	#clock-cells = <0>;
	241	compatible = "allwinner,sun4i-a10-mod0-clk";
	242	reg = <0x01c2009c 0x4>;
	243	clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
	244	clock-output-names = "ss";
	245	};
246
247	spi0_clk: clk@01c200a0 {
248	#clock-cells = <0>;
249	compatible = "allwinner,sun4i-a10-mod0-clk";
250	reg = <0x01c200a0 0x4>;
251	clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
252	clock-output-names = "spi0";
253	};
254
255	spi1_clk: clk@01c200a4 {
256	#clock-cells = <0>;
257	compatible = "allwinner,sun4i-a10-mod0-clk";
258	reg = <0x01c200a4 0x4>;
259	clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
260	clock-output-names = "spi1";
261	};
262
263	spi2_clk: clk@01c200a8 {
264	#clock-cells = <0>;
265	compatible = "allwinner,sun4i-a10-mod0-clk";
266	reg = <0x01c200a8 0x4>;
267	clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
268	clock-output-names = "spi2";
269	};
270
271	ir0_clk: clk@01c200b0 {
272	#clock-cells = <0>;
273	compatible = "allwinner,sun4i-a10-mod0-clk";
274	reg = <0x01c200b0 0x4>;
275	clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
276	clock-output-names = "ir0";
277	};
278
279	usb_clk: clk@01c200cc {
280	#clock-cells = <1>;
8b1ba941	281	#reset-cells = <1>;
53ab4af3 HG	282	compatible = "allwinner,sun5i-a13-usb-clk";
	283	reg = <0x01c200cc 0x4>;
	284	clocks = <&pll6 1>;
	285	clock-output-names = "usb_ohci0", "usb_phy";
	286	};
	287
	288	mbus_clk: clk@01c2015c {
	289	#clock-cells = <0>;
	290	compatible = "allwinner,sun5i-a13-mbus-clk";
	291	reg = <0x01c2015c 0x4>;
	292	clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
	293	clock-output-names = "mbus";
	294	};
	295	};
	296
53ab4af3 HG	297	soc@01c00000 {
	298	compatible = "simple-bus";
	299	#address-cells = <1>;
	300	#size-cells = <1>;
	301	ranges;
	302
53ab4af3 HG	303	sram-controller@01c00000 {
	304	compatible = "allwinner,sun4i-a10-sram-controller";
	305	reg = <0x01c00000 0x30>;
8b1ba941 HG	306	#address-cells = <1>;
	307	#size-cells = <1>;
	308	ranges;
	309
	310	sram_a: sram@00000000 {
	311	compatible = "mmio-sram";
	312	reg = <0x00000000 0xc000>;
	313	#address-cells = <1>;
	314	#size-cells = <1>;
	315	ranges = <0 0x00000000 0xc000>;
	316	};
	317
	318	sram_d: sram@00010000 {
	319	compatible = "mmio-sram";
	320	reg = <0x00010000 0x1000>;
	321	#address-cells = <1>;
	322	#size-cells = <1>;
	323	ranges = <0 0x00010000 0x1000>;
	324
	325	otg_sram: sram-section@0000 {
	326	compatible = "allwinner,sun4i-a10-sram-d";
	327	reg = <0x0000 0x1000>;
	328	status = "disabled";
	329	};
	330	};
53ab4af3 HG	331	};
	332
	333	dma: dma-controller@01c02000 {
	334	compatible = "allwinner,sun4i-a10-dma";
	335	reg = <0x01c02000 0x1000>;
	336	interrupts = <27>;
	337	clocks = <&ahb_gates 6>;
	338	#dma-cells = <2>;
	339	};
	340
	341	spi0: spi@01c05000 {
	342	compatible = "allwinner,sun4i-a10-spi";
	343	reg = <0x01c05000 0x1000>;
	344	interrupts = <10>;
	345	clocks = <&ahb_gates 20>, <&spi0_clk>;
	346	clock-names = "ahb", "mod";
	347	dmas = <&dma SUN4I_DMA_DEDICATED 27>,
	348	<&dma SUN4I_DMA_DEDICATED 26>;
	349	dma-names = "rx", "tx";
	350	status = "disabled";
	351	#address-cells = <1>;
	352	#size-cells = <0>;
	353	};
	354
	355	spi1: spi@01c06000 {
	356	compatible = "allwinner,sun4i-a10-spi";
	357	reg = <0x01c06000 0x1000>;
	358	interrupts = <11>;
	359	clocks = <&ahb_gates 21>, <&spi1_clk>;
	360	clock-names = "ahb", "mod";
	361	dmas = <&dma SUN4I_DMA_DEDICATED 9>,
	362	<&dma SUN4I_DMA_DEDICATED 8>;
	363	dma-names = "rx", "tx";
	364	status = "disabled";
	365	#address-cells = <1>;
	366	#size-cells = <0>;
	367	};
	368
	369	mmc0: mmc@01c0f000 {
	370	compatible = "allwinner,sun5i-a13-mmc";
	371	reg = <0x01c0f000 0x1000>;
	372	clocks = <&ahb_gates 8>,
	373	<&mmc0_clk 0>,
	374	<&mmc0_clk 1>,
	375	<&mmc0_clk 2>;
	376	clock-names = "ahb",
	377	"mmc",
	378	"output",
	379	"sample";
	380	interrupts = <32>;
	381	status = "disabled";
	382	#address-cells = <1>;
	383	#size-cells = <0>;
	384	};
	385
	386	mmc1: mmc@01c10000 {
	387	compatible = "allwinner,sun5i-a13-mmc";
	388	reg = <0x01c10000 0x1000>;
	389	clocks = <&ahb_gates 9>,
	390	<&mmc1_clk 0>,
	391	<&mmc1_clk 1>,
	392	<&mmc1_clk 2>;
	393	clock-names = "ahb",
	394	"mmc",
395	"output",
396	"sample";
397	interrupts = <33>;
398	status = "disabled";
399	#address-cells = <1>;
400	#size-cells = <0>;
401	};
402
403	mmc2: mmc@01c11000 {
404	compatible = "allwinner,sun5i-a13-mmc";
405	reg = <0x01c11000 0x1000>;
406	clocks = <&ahb_gates 10>,
407	<&mmc2_clk 0>,
408	<&mmc2_clk 1>,
409	<&mmc2_clk 2>;
410	clock-names = "ahb",
411	"mmc",
412	"output",
413	"sample";
414	interrupts = <34>;
415	status = "disabled";
416	#address-cells = <1>;
417	#size-cells = <0>;
418	};
419
da52a4a3 HG	420	usb_otg: usb@01c13000 {
	421	compatible = "allwinner,sun4i-a10-musb";
	422	reg = <0x01c13000 0x0400>;
	423	clocks = <&ahb_gates 0>;
	424	interrupts = <38>;
	425	interrupt-names = "mc";
	426	phys = <&usbphy 0>;
	427	phy-names = "usb";
	428	extcon = <&usbphy 0>;
	429	allwinner,sram = <&otg_sram 1>;
	430	status = "disabled";
	431	};
	432
53ab4af3 HG	433	usbphy: phy@01c13400 {
	434	#phy-cells = <1>;
	435	compatible = "allwinner,sun5i-a13-usb-phy";
	436	reg = <0x01c13400 0x10 0x01c14800 0x4>;
	437	reg-names = "phy_ctrl", "pmu1";
	438	clocks = <&usb_clk 8>;
	439	clock-names = "usb_phy";
	440	resets = <&usb_clk 0>, <&usb_clk 1>;
	441	reset-names = "usb0_reset", "usb1_reset";
	442	status = "disabled";
	443	};
	444
	445	ehci0: usb@01c14000 {
	446	compatible = "allwinner,sun5i-a13-ehci", "generic-ehci";
	447	reg = <0x01c14000 0x100>;
	448	interrupts = <39>;
	449	clocks = <&ahb_gates 1>;
	450	phys = <&usbphy 1>;
	451	phy-names = "usb";
	452	status = "disabled";
	453	};
	454
	455	ohci0: usb@01c14400 {
	456	compatible = "allwinner,sun5i-a13-ohci", "generic-ohci";
	457	reg = <0x01c14400 0x100>;
	458	interrupts = <40>;
	459	clocks = <&usb_clk 6>, <&ahb_gates 2>;
	460	phys = <&usbphy 1>;
	461	phy-names = "usb";
	462	status = "disabled";
	463	};
	464
	465	spi2: spi@01c17000 {
	466	compatible = "allwinner,sun4i-a10-spi";
	467	reg = <0x01c17000 0x1000>;
	468	interrupts = <12>;
	469	clocks = <&ahb_gates 22>, <&spi2_clk>;
	470	clock-names = "ahb", "mod";
	471	dmas = <&dma SUN4I_DMA_DEDICATED 29>,
	472	<&dma SUN4I_DMA_DEDICATED 28>;
	473	dma-names = "rx", "tx";
	474	status = "disabled";
	475	#address-cells = <1>;
	476	#size-cells = <0>;
	477	};
	478
	479	intc: interrupt-controller@01c20400 {
	480	compatible = "allwinner,sun4i-a10-ic";
	481	reg = <0x01c20400 0x400>;
	482	interrupt-controller;
	483	#interrupt-cells = <1>;
	484	};
	485
	486	pio: pinctrl@01c20800 {
	487	reg = <0x01c20800 0x400>;
	488	interrupts = <28>;
	489	clocks = <&apb0_gates 5>;
	490	gpio-controller;
	491	interrupt-controller;
da52a4a3	492	#interrupt-cells = <3>;
53ab4af3 HG	493	#gpio-cells = <3>;
	494
	495	i2c0_pins_a: i2c0@0 {
	496	allwinner,pins = "PB0", "PB1";
	497	allwinner,function = "i2c0";
	498	allwinner,drive = <SUN4I_PINCTRL_10_MA>;
	499	allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
	500	};
	501
	502	i2c1_pins_a: i2c1@0 {
	503	allwinner,pins = "PB15", "PB16";
	504	allwinner,function = "i2c1";
	505	allwinner,drive = <SUN4I_PINCTRL_10_MA>;
	506	allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
	507	};
	508
	509	i2c2_pins_a: i2c2@0 {
	510	allwinner,pins = "PB17", "PB18";
	511	allwinner,function = "i2c2";
	512	allwinner,drive = <SUN4I_PINCTRL_10_MA>;
	513	allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
	514	};
	515
	516	mmc0_pins_a: mmc0@0 {
8b1ba941 HG	517	allwinner,pins = "PF0", "PF1", "PF2", "PF3",
8b1ba941 HG	518	"PF4", "PF5";
53ab4af3 HG	519	allwinner,function = "mmc0";
	520	allwinner,drive = <SUN4I_PINCTRL_30_MA>;
	521	allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
	522	};
	523
	524	mmc2_pins_a: mmc2@0 {
	525	allwinner,pins = "PC6", "PC7", "PC8", "PC9",
	526	"PC10", "PC11", "PC12", "PC13",
	527	"PC14", "PC15";
	528	allwinner,function = "mmc2";
	529	allwinner,drive = <SUN4I_PINCTRL_30_MA>;
	530	allwinner,pull = <SUN4I_PINCTRL_PULL_UP>;
	531	};
f0e8e8da MR	532
	533	uart3_pins_a: uart3@0 {
	534	allwinner,pins = "PG9", "PG10";
	535	allwinner,function = "uart3";
	536	allwinner,drive = <SUN4I_PINCTRL_10_MA>;
	537	allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
	538	};
	539
	540	uart3_pins_cts_rts_a: uart3-cts-rts@0 {
	541	allwinner,pins = "PG11", "PG12";
	542	allwinner,function = "uart3";
	543	allwinner,drive = <SUN4I_PINCTRL_10_MA>;
	544	allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
	545	};
	546
	547	pwm0_pins: pwm0 {
	548	allwinner,pins = "PB2";
	549	allwinner,function = "pwm";
	550	allwinner,drive = <SUN4I_PINCTRL_10_MA>;
	551	allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
	552	};
53ab4af3 HG	553	};
	554
	555	timer@01c20c00 {
	556	compatible = "allwinner,sun4i-a10-timer";
	557	reg = <0x01c20c00 0x90>;
	558	interrupts = <22>;
	559	clocks = <&osc24M>;
	560	};
	561
	562	wdt: watchdog@01c20c90 {
	563	compatible = "allwinner,sun4i-a10-wdt";
	564	reg = <0x01c20c90 0x10>;
	565	};
	566
	567	lradc: lradc@01c22800 {
	568	compatible = "allwinner,sun4i-a10-lradc-keys";
	569	reg = <0x01c22800 0x100>;
	570	interrupts = <31>;
	571	status = "disabled";
	572	};
	573
	574	sid: eeprom@01c23800 {
	575	compatible = "allwinner,sun4i-a10-sid";
	576	reg = <0x01c23800 0x10>;
	577	};
	578
	579	rtp: rtp@01c25000 {
	580	compatible = "allwinner,sun5i-a13-ts";
	581	reg = <0x01c25000 0x100>;
	582	interrupts = <29>;
	583	#thermal-sensor-cells = <0>;
	584	};
	585
	586	uart1: serial@01c28400 {
	587	compatible = "snps,dw-apb-uart";
	588	reg = <0x01c28400 0x400>;
	589	interrupts = <2>;
	590	reg-shift = <2>;
	591	reg-io-width = <4>;
	592	clocks = <&apb1_gates 17>;
	593	status = "disabled";
	594	};
	595
	596	uart3: serial@01c28c00 {
	597	compatible = "snps,dw-apb-uart";
	598	reg = <0x01c28c00 0x400>;
	599	interrupts = <4>;
	600	reg-shift = <2>;
	601	reg-io-width = <4>;
	602	clocks = <&apb1_gates 19>;
	603	status = "disabled";
	604	};
	605
	606	i2c0: i2c@01c2ac00 {
	607	compatible = "allwinner,sun4i-a10-i2c";
	608	reg = <0x01c2ac00 0x400>;
	609	interrupts = <7>;
	610	clocks = <&apb1_gates 0>;
	611	status = "disabled";
	612	#address-cells = <1>;
	613	#size-cells = <0>;
	614	};
	615
	616	i2c1: i2c@01c2b000 {
617	compatible = "allwinner,sun4i-a10-i2c";
618	reg = <0x01c2b000 0x400>;
619	interrupts = <8>;
620	clocks = <&apb1_gates 1>;
621	status = "disabled";
622	#address-cells = <1>;
623	#size-cells = <0>;
624	};
625
626	i2c2: i2c@01c2b400 {
627	compatible = "allwinner,sun4i-a10-i2c";
628	reg = <0x01c2b400 0x400>;
629	interrupts = <9>;
630	clocks = <&apb1_gates 2>;
631	status = "disabled";
632	#address-cells = <1>;
633	#size-cells = <0>;
634	};
635
636	timer@01c60000 {
637	compatible = "allwinner,sun5i-a13-hstimer";
638	reg = <0x01c60000 0x1000>;
639	interrupts = <82>, <83>;
640	clocks = <&ahb_gates 28>;
641	};
642	};
643	};