]> git.ipfire.org Git - people/ms/u-boot.git/blame - arch/arm/dts/tegra20-harmony.dts
tegra: video: Move LCD driver to use the DM PWM driver
[people/ms/u-boot.git] / arch / arm / dts / tegra20-harmony.dts
CommitLineData
f3d93309
SW
1/dts-v1/;
2
6c5be646 3#include "tegra20.dtsi"
f3d93309
SW
4
5/ {
00a2749d 6 model = "NVIDIA Tegra20 Harmony evaluation board";
f3d93309
SW
7 compatible = "nvidia,harmony", "nvidia,tegra20";
8
c3691392
SG
9 chosen {
10 stdout-path = &uartd;
11 };
12
f3d93309
SW
13 aliases {
14 usb0 = "/usb@c5008000";
699c40e8 15 usb1 = "/usb@c5004000";
126685ad
TW
16 sdhci0 = "/sdhci@c8000600";
17 sdhci1 = "/sdhci@c8000200";
f3d93309
SW
18 };
19
20 memory {
21 reg = <0x00000000 0x40000000>;
22 };
23
ee7d755a 24 host1x@50000000 {
b46694df
SW
25 status = "okay";
26 dc@54200000 {
27 status = "okay";
28 rgb {
29 status = "okay";
30 nvidia,panel = <&lcd_panel>;
31 };
32 };
33 };
34
f3d93309
SW
35 serial@70006300 {
36 clock-frequency = < 216000000 >;
37 };
38
b7723f3f 39 nand-controller@70008000 {
2b2b50bc 40 nvidia,wp-gpios = <&gpio TEGRA_GPIO(C, 7) GPIO_ACTIVE_HIGH>;
b7723f3f
AM
41 nvidia,width = <8>;
42 nvidia,timing = <26 100 20 80 20 10 12 10 70>;
43 nand@0 {
44 reg = <0>;
45 compatible = "hynix,hy27uf4g2b", "nand-flash";
46 };
47 };
48
f3d93309 49 usb@c5004000 {
ee7d755a 50 statuc = "okay";
2b2b50bc 51 nvidia,phy-reset-gpio = <&gpio TEGRA_GPIO(V, 1) 0>;
f3d93309 52 };
126685ad 53
ee7d755a
SG
54 usb@c5008000 {
55 status = "okay";
56 };
57
126685ad
TW
58 sdhci@c8000200 {
59 status = "okay";
2b2b50bc
SG
60 cd-gpios = <&gpio TEGRA_GPIO(I, 5) GPIO_ACTIVE_LOW>;
61 wp-gpios = <&gpio TEGRA_GPIO(H, 1) GPIO_ACTIVE_HIGH>;
62 power-gpios = <&gpio TEGRA_GPIO(T, 3) GPIO_ACTIVE_HIGH>;
126685ad
TW
63 bus-width = <4>;
64 };
65
66 sdhci@c8000600 {
67 status = "okay";
2b2b50bc
SG
68 cd-gpios = <&gpio TEGRA_GPIO(H, 2) GPIO_ACTIVE_LOW>;
69 wp-gpios = <&gpio TEGRA_GPIO(H, 3) GPIO_ACTIVE_HIGH>;
70 power-gpios = <&gpio TEGRA_GPIO(I, 6) GPIO_ACTIVE_HIGH>;
126685ad
TW
71 bus-width = <8>;
72 };
b46694df 73
ee7d755a
SG
74 clocks {
75 compatible = "simple-bus";
76 #address-cells = <1>;
77 #size-cells = <0>;
78
79 clk32k_in: clock@0 {
80 compatible = "fixed-clock";
81 reg=<0>;
82 #clock-cells = <0>;
83 clock-frequency = <32768>;
84 };
85 };
86
91c08afe
SG
87 pwm: pwm@7000a000 {
88 status = "okay";
89 };
90
b46694df
SW
91 lcd_panel: panel {
92 clock = <42430000>;
93 xres = <1024>;
94 yres = <600>;
95 left-margin = <138>;
96 right-margin = <34>;
97 hsync-len = <136>;
98 lower-margin = <4>;
99 upper-margin = <21>;
100 vsync-len = <4>;
101 hsync-active-high;
102 vsyncx-active-high;
103 nvidia,bits-per-pixel = <16>;
104 nvidia,pwm = <&pwm 0 0>;
2b2b50bc
SG
105 nvidia,backlight-enable-gpios = <&gpio TEGRA_GPIO(B, 5)
106 GPIO_ACTIVE_HIGH>;
107 nvidia,lvds-shutdown-gpios = <&gpio TEGRA_GPIO(B, 2)
108 GPIO_ACTIVE_HIGH>;
109 nvidia,backlight-vdd-gpios = <&gpio TEGRA_GPIO(W, 0)
110 GPIO_ACTIVE_HIGH>;
111 nvidia,panel-vdd-gpios = <&gpio TEGRA_GPIO(C, 6)
112 GPIO_ACTIVE_HIGH>;
b46694df
SW
113 nvidia,panel-timings = <0 0 200 0 0>;
114 };
f3d93309 115};