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83d290c5 | 1 | /* SPDX-License-Identifier: GPL-2.0+ */ |
cf946c6d LW |
2 | /* |
3 | * (C) Copyright 2011 | |
4 | * Marvell Semiconductor <www.marvell.com> | |
5 | * Written-by: Lei Wen <leiwen@marvell.com> | |
cf946c6d LW |
6 | */ |
7 | ||
8 | /* | |
9 | * This file should be included in board config header file. | |
10 | * | |
11 | * It supports common definitions for Kirkwood platform | |
12 | */ | |
13 | ||
14 | #ifndef _KW_CONFIG_H | |
15 | #define _KW_CONFIG_H | |
16 | ||
17 | #if defined (CONFIG_KW88F6281) | |
18 | #include <asm/arch/kw88f6281.h> | |
19 | #elif defined (CONFIG_KW88F6192) | |
20 | #include <asm/arch/kw88f6192.h> | |
21 | #else | |
22 | #error "SOC Name not defined" | |
23 | #endif /* CONFIG_KW88F6281 */ | |
24 | ||
3dc23f78 | 25 | #include <asm/arch/soc.h> |
cf946c6d LW |
26 | #define CONFIG_KIRKWOOD_EGIGA_INIT /* Enable GbePort0/1 for kernel */ |
27 | #define CONFIG_KIRKWOOD_RGMII_PAD_1V8 /* Set RGMII Pad voltage to 1.8V */ | |
28 | #define CONFIG_KIRKWOOD_PCIE_INIT /* Enable PCIE Port0 for kernel */ | |
29 | ||
30 | /* | |
31 | * By default kwbimage.cfg from board specific folder is used | |
32 | * If for some board, different configuration file need to be used, | |
33 | * CONFIG_SYS_KWD_CONFIG should be defined in board specific header file | |
34 | */ | |
35 | #ifndef CONFIG_SYS_KWD_CONFIG | |
4ab3fc5e | 36 | #define CONFIG_SYS_KWD_CONFIG $(CONFIG_BOARDDIR)/kwbimage.cfg |
cf946c6d LW |
37 | #endif /* CONFIG_SYS_KWD_CONFIG */ |
38 | ||
39 | /* Kirkwood has 2k of Security SRAM, use it for SP */ | |
40 | #define CONFIG_SYS_INIT_SP_ADDR 0xC8012000 | |
cf946c6d | 41 | |
dd82242b | 42 | #define CONFIG_I2C_MVTWSI_BASE0 KW_TWSI_BASE |
cf946c6d LW |
43 | #define MV_UART_CONSOLE_BASE KW_UART0_BASE |
44 | #define MV_SATA_BASE KW_SATA_BASE | |
45 | #define MV_SATA_PORT0_OFFSET KW_SATA_PORT0_OFFSET | |
46 | #define MV_SATA_PORT1_OFFSET KW_SATA_PORT1_OFFSET | |
47 | ||
48 | /* | |
49 | * NAND configuration | |
50 | */ | |
51 | #ifdef CONFIG_CMD_NAND | |
52 | #define CONFIG_NAND_KIRKWOOD | |
53 | #define CONFIG_SYS_NAND_BASE 0xD8000000 /* MV_DEFADR_NANDF */ | |
54 | #define NAND_ALLOW_ERASE_ALL 1 | |
55 | #endif | |
56 | ||
cf946c6d LW |
57 | /* |
58 | * Ethernet Driver configuration | |
59 | */ | |
60 | #ifdef CONFIG_CMD_NET | |
cf946c6d | 61 | #define CONFIG_SYS_FAULT_ECHO_LINK_DOWN /* detect link using phy */ |
cf946c6d LW |
62 | #define CONFIG_RESET_PHY_R /* use reset_phy() to init mv8831116 PHY */ |
63 | #endif /* CONFIG_CMD_NET */ | |
64 | ||
65 | /* | |
66 | * USB/EHCI | |
67 | */ | |
68 | #ifdef CONFIG_CMD_USB | |
cf946c6d LW |
69 | #define CONFIG_EHCI_IS_TDI |
70 | #endif /* CONFIG_CMD_USB */ | |
71 | ||
72 | /* | |
73 | * IDE Support on SATA ports | |
74 | */ | |
fc843a02 | 75 | #ifdef CONFIG_IDE |
cf946c6d | 76 | #define __io |
cf946c6d LW |
77 | /* Needs byte-swapping for ATA data register */ |
78 | #define CONFIG_IDE_SWAP_IO | |
79 | /* Data, registers and alternate blocks are at the same offset */ | |
80 | #define CONFIG_SYS_ATA_DATA_OFFSET (0x0100) | |
81 | #define CONFIG_SYS_ATA_REG_OFFSET (0x0100) | |
82 | #define CONFIG_SYS_ATA_ALT_OFFSET (0x0100) | |
83 | /* Each 8-bit ATA register is aligned to a 4-bytes address */ | |
84 | #define CONFIG_SYS_ATA_STRIDE 4 | |
85 | /* Controller supports 48-bits LBA addressing */ | |
86 | #define CONFIG_LBA48 | |
fc843a02 | 87 | /* CONFIG_IDE requires some #defines for ATA registers */ |
cf946c6d LW |
88 | #define CONFIG_SYS_IDE_MAXBUS 2 |
89 | #define CONFIG_SYS_IDE_MAXDEVICE 2 | |
90 | /* ATA registers base is at SATA controller base */ | |
91 | #define CONFIG_SYS_ATA_BASE_ADDR MV_SATA_BASE | |
fc843a02 | 92 | #endif /* CONFIG_IDE */ |
cf946c6d LW |
93 | |
94 | /* | |
95 | * I2C related stuff | |
96 | */ | |
2147a169 | 97 | #if defined(CONFIG_CMD_I2C) && !CONFIG_IS_ENABLED(DM_I2C) |
ea818dbb | 98 | #ifndef CONFIG_SYS_I2C_SOFT |
69d9eda4 | 99 | #define CONFIG_SYS_I2C_LEGACY |
0db2bbdc | 100 | #define CONFIG_SYS_I2C_MVTWSI |
b31a82e9 | 101 | #endif |
cf946c6d LW |
102 | #define CONFIG_SYS_I2C_SLAVE 0x0 |
103 | #define CONFIG_SYS_I2C_SPEED 100000 | |
104 | #endif | |
105 | ||
2fbc18fe SR |
106 | /* Use common timer */ |
107 | #define CONFIG_SYS_TIMER_COUNTS_DOWN | |
108 | #define CONFIG_SYS_TIMER_COUNTER (MVEBU_TIMER_BASE + 0x14) | |
109 | #define CONFIG_SYS_TIMER_RATE CONFIG_SYS_TCLK | |
110 | ||
cf946c6d | 111 | #endif /* _KW_CONFIG_H */ |