[people/ms/u-boot.git] / arch / arm / mach-rockchip / rk322x-board.c

/*
 * (C) Copyright 2017 Rockchip Electronics Co., Ltd.
 *
 * SPDX-License-Identifier:     GPL-2.0+
 */
#include <common.h>
#include <clk.h>
#include <dm.h>
#include <ram.h>
#include <syscon.h>
#include <asm/io.h>
#include <asm/arch/clock.h>
#include <asm/arch/periph.h>
#include <asm/arch/grf_rk322x.h>
#include <asm/arch/boot_mode.h>

DECLARE_GLOBAL_DATA_PTR;

#define GRF_BASE	0x11000000

static void setup_boot_mode(void)
{
	struct rk322x_grf *const grf = (void *)GRF_BASE;
	int boot_mode = readl(&grf->os_reg[0]);

	debug("boot mode %x.\n", boot_mode);

	/* Clear boot mode */
	writel(BOOT_NORMAL, &grf->os_reg[0]);

	switch (boot_mode) {
	case BOOT_FASTBOOT:
		printf("enter fastboot!\n");
		env_set("preboot", "setenv preboot; fastboot usb0");
		break;
	case BOOT_UMS:
		printf("enter UMS!\n");
		env_set("preboot", "setenv preboot; ums mmc 0");
		break;
	}
}

__weak int rk_board_late_init(void)
{
	return 0;
}

int board_late_init(void)
{
	setup_boot_mode();

	return rk_board_late_init();
}

int board_init(void)
{
#include <asm/arch/grf_rk322x.h>
	/* Enable early UART2 channel 1 on the RK322x */
#define GRF_BASE	0x11000000
	struct rk322x_grf * const grf = (void *)GRF_BASE;

	rk_clrsetreg(&grf->gpio1b_iomux,
		     GPIO1B1_MASK | GPIO1B2_MASK,
		     GPIO1B2_UART21_SIN << GPIO1B2_SHIFT |
		     GPIO1B1_UART21_SOUT << GPIO1B1_SHIFT);
	/* Set channel C as UART2 input */
	rk_clrsetreg(&grf->con_iomux,
		     CON_IOMUX_UART2SEL_MASK,
		     CON_IOMUX_UART2SEL_21 << CON_IOMUX_UART2SEL_SHIFT);

	/*
	* The integrated macphy is enabled by default, disable it
	* for saving power consuming.
	*/
	rk_clrsetreg(&grf->macphy_con[0],
		     MACPHY_CFG_ENABLE_MASK,
		     0 << MACPHY_CFG_ENABLE_SHIFT);

	return 0;
}

int dram_init_banksize(void)
{
	gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
	gd->bd->bi_dram[0].size = 0x8400000;
	/* Reserve 0x200000 for OPTEE */
	gd->bd->bi_dram[1].start = CONFIG_SYS_SDRAM_BASE
				+ gd->bd->bi_dram[0].size + 0x200000;
	gd->bd->bi_dram[1].size = gd->bd->bi_dram[0].start
				+ gd->ram_size - gd->bd->bi_dram[1].start;

	return 0;
}

#ifndef CONFIG_SYS_DCACHE_OFF
void enable_caches(void)
{
	/* Enable D-cache. I-cache is already enabled in start.S */
	dcache_enable();
}
#endif

#if defined(CONFIG_USB_GADGET) && defined(CONFIG_USB_GADGET_DWC2_OTG)
#include <usb.h>
#include <usb/dwc2_udc.h>

static struct dwc2_plat_otg_data rk322x_otg_data = {
	.rx_fifo_sz	= 512,
	.np_tx_fifo_sz	= 16,
	.tx_fifo_sz	= 128,
};

int board_usb_init(int index, enum usb_init_type init)
{
	int node;
	const char *mode;
	bool matched = false;
	const void *blob = gd->fdt_blob;

	/* find the usb_otg node */
	node = fdt_node_offset_by_compatible(blob, -1,
					"rockchip,rk3288-usb");

	while (node > 0) {
		mode = fdt_getprop(blob, node, "dr_mode", NULL);
		if (mode && strcmp(mode, "otg") == 0) {
			matched = true;
			break;
		}

		node = fdt_node_offset_by_compatible(blob, node,
					"rockchip,rk3288-usb");
	}
	if (!matched) {
		debug("Not found usb_otg device\n");
		return -ENODEV;
	}
	rk322x_otg_data.regs_otg = fdtdec_get_addr(blob, node, "reg");

	return dwc2_udc_probe(&rk322x_otg_data);
}

int board_usb_cleanup(int index, enum usb_init_type init)
{
	return 0;
}
#endif

#if defined(CONFIG_USB_FUNCTION_FASTBOOT)
int fb_set_reboot_flag(void)
{
	struct rk322x_grf *grf;

	printf("Setting reboot to fastboot flag ...\n");
	grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
	/* Set boot mode to fastboot */
	writel(BOOT_FASTBOOT, &grf->os_reg[0]);

	return 0;
}
#endif
Commit	Line	Data
168eef7a KY	1	/*
	2	* (C) Copyright 2017 Rockchip Electronics Co., Ltd.
	3	*
	4	* SPDX-License-Identifier: GPL-2.0+
	5	*/
	6	#include <common.h>
	7	#include <clk.h>
	8	#include <dm.h>
	9	#include <ram.h>
c964a0dc	10	#include <syscon.h>
168eef7a KY	11	#include <asm/io.h>
	12	#include <asm/arch/clock.h>
	13	#include <asm/arch/periph.h>
	14	#include <asm/arch/grf_rk322x.h>
	15	#include <asm/arch/boot_mode.h>
	16
	17	DECLARE_GLOBAL_DATA_PTR;
	18
	19	#define GRF_BASE 0x11000000
	20
	21	static void setup_boot_mode(void)
	22	{
	23	struct rk322x_grf const grf = (void )GRF_BASE;
4a187297	24	int boot_mode = readl(&grf->os_reg[0]);
168eef7a KY	25
	26	debug("boot mode %x.\n", boot_mode);
	27
	28	/* Clear boot mode */
4a187297	29	writel(BOOT_NORMAL, &grf->os_reg[0]);
168eef7a KY	30
	31	switch (boot_mode) {
	32	case BOOT_FASTBOOT:
	33	printf("enter fastboot!\n");
382bee57	34	env_set("preboot", "setenv preboot; fastboot usb0");
168eef7a KY	35	break;
	36	case BOOT_UMS:
	37	printf("enter UMS!\n");
382bee57	38	env_set("preboot", "setenv preboot; ums mmc 0");
168eef7a KY	39	break;
	40	}
	41	}
	42
	43	__weak int rk_board_late_init(void)
	44	{
	45	return 0;
	46	}
	47
	48	int board_late_init(void)
	49	{
	50	setup_boot_mode();
	51
	52	return rk_board_late_init();
	53	}
	54
	55	int board_init(void)
	56	{
	57	#include <asm/arch/grf_rk322x.h>
	58	/* Enable early UART2 channel 1 on the RK322x */
	59	#define GRF_BASE 0x11000000
	60	struct rk322x_grf * const grf = (void *)GRF_BASE;
	61
	62	rk_clrsetreg(&grf->gpio1b_iomux,
	63	GPIO1B1_MASK \| GPIO1B2_MASK,
	64	GPIO1B2_UART21_SIN << GPIO1B2_SHIFT \|
	65	GPIO1B1_UART21_SOUT << GPIO1B1_SHIFT);
	66	/* Set channel C as UART2 input */
	67	rk_clrsetreg(&grf->con_iomux,
	68	CON_IOMUX_UART2SEL_MASK,
	69	CON_IOMUX_UART2SEL_21 << CON_IOMUX_UART2SEL_SHIFT);
	70
4c94aacd DW	71	/*
	72	* The integrated macphy is enabled by default, disable it
	73	* for saving power consuming.
	74	*/
	75	rk_clrsetreg(&grf->macphy_con[0],
	76	MACPHY_CFG_ENABLE_MASK,
	77	0 << MACPHY_CFG_ENABLE_SHIFT);
	78
168eef7a KY	79	return 0;
	80	}
	81
	82	int dram_init_banksize(void)
	83	{
44c5ba55	84	gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
168eef7a	85	gd->bd->bi_dram[0].size = 0x8400000;
44c5ba55 KY	86	/* Reserve 0x200000 for OPTEE */
	87	gd->bd->bi_dram[1].start = CONFIG_SYS_SDRAM_BASE
	88	+ gd->bd->bi_dram[0].size + 0x200000;
	89	gd->bd->bi_dram[1].size = gd->bd->bi_dram[0].start
	90	+ gd->ram_size - gd->bd->bi_dram[1].start;
168eef7a KY	91
	92	return 0;
	93	}
	94
	95	#ifndef CONFIG_SYS_DCACHE_OFF
	96	void enable_caches(void)
	97	{
	98	/* Enable D-cache. I-cache is already enabled in start.S */
	99	dcache_enable();
	100	}
	101	#endif
	102
	103	#if defined(CONFIG_USB_GADGET) && defined(CONFIG_USB_GADGET_DWC2_OTG)
	104	#include <usb.h>
	105	#include <usb/dwc2_udc.h>
	106
	107	static struct dwc2_plat_otg_data rk322x_otg_data = {
	108	.rx_fifo_sz = 512,
	109	.np_tx_fifo_sz = 16,
	110	.tx_fifo_sz = 128,
	111	};
	112
	113	int board_usb_init(int index, enum usb_init_type init)
	114	{
	115	int node;
	116	const char *mode;
	117	bool matched = false;
	118	const void *blob = gd->fdt_blob;
	119
	120	/* find the usb_otg node */
	121	node = fdt_node_offset_by_compatible(blob, -1,
	122	"rockchip,rk3288-usb");
	123
	124	while (node > 0) {
	125	mode = fdt_getprop(blob, node, "dr_mode", NULL);
	126	if (mode && strcmp(mode, "otg") == 0) {
	127	matched = true;
	128	break;
	129	}
	130
	131	node = fdt_node_offset_by_compatible(blob, node,
	132	"rockchip,rk3288-usb");
	133	}
	134	if (!matched) {
	135	debug("Not found usb_otg device\n");
	136	return -ENODEV;
	137	}
	138	rk322x_otg_data.regs_otg = fdtdec_get_addr(blob, node, "reg");
	139
	140	return dwc2_udc_probe(&rk322x_otg_data);
	141	}
	142
	143	int board_usb_cleanup(int index, enum usb_init_type init)
	144	{
	145	return 0;
	146	}
	147	#endif
c964a0dc KY	148
	149	#if defined(CONFIG_USB_FUNCTION_FASTBOOT)
	150	int fb_set_reboot_flag(void)
	151	{
	152	struct rk322x_grf *grf;
	153
	154	printf("Setting reboot to fastboot flag ...\n");
	155	grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
	156	/* Set boot mode to fastboot */
	157	writel(BOOT_FASTBOOT, &grf->os_reg[0]);
	158
	159	return 0;
	160	}
	161	#endif