projects / people / ms / u-boot.git / blame
| Commit | Line | Data |
|---|---|---|
| 7865f4b0 MY |
1 | if ARCH_SOCFPGA |
| 2 | ||
| 77d2f7f5 SG |
3 | config SPL_LIBCOMMON_SUPPORT |
| 4 | default y | |
| 5 | ||
| 1646eba8 SG |
6 | config SPL_LIBDISK_SUPPORT |
| 7 | default y | |
| 8 | ||
| cc4288ef SG |
9 | config SPL_LIBGENERIC_SUPPORT |
| 10 | default y | |
| 11 | ||
| 1fdf7c64 SG |
12 | config SPL_MMC_SUPPORT |
| 13 | default y if DM_MMC | |
| 14 | ||
| d6b9bd89 SG |
15 | config SPL_NAND_SUPPORT |
| 16 | default y if SPL_NAND_DENALI | |
| 17 | ||
| e00f76ce SG |
18 | config SPL_SERIAL_SUPPORT |
| 19 | default y | |
| 20 | ||
| e404ade4 | 21 | config SPL_SPI_FLASH_SUPPORT |
| f35ed9ed SG |
22 | default y if SPL_SPI_SUPPORT |
| 23 | ||
| 24 | config SPL_SPI_SUPPORT | |
| e404ade4 SG |
25 | default y if DM_SPI |
| 26 | ||
| 02e69a5d SG |
27 | config SPL_WATCHDOG_SUPPORT |
| 28 | default y | |
| 29 | ||
| f0fb4fa7 DW |
30 | config SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION_TYPE |
| 31 | default y | |
| 32 | ||
| 33 | config SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION_TYPE | |
| 34 | default 0xa2 | |
| 35 | ||
| cd9b7317 MV |
36 | config TARGET_SOCFPGA_ARRIA5 |
| 37 | bool | |
| ed77aeb5 | 38 | select TARGET_SOCFPGA_GEN5 |
| cd9b7317 MV |
39 | |
| 40 | config TARGET_SOCFPGA_CYCLONE5 | |
| 41 | bool | |
| ed77aeb5 DN |
42 | select TARGET_SOCFPGA_GEN5 |
| 43 | ||
| 44 | config TARGET_SOCFPGA_GEN5 | |
| 45 | bool | |
| 707cd012 | 46 | select ALTERA_SDRAM |
| cd9b7317 | 47 | |
| 7865f4b0 MY |
48 | choice |
| 49 | prompt "Altera SOCFPGA board select" | |
| a26cd049 | 50 | optional |
| 7865f4b0 | 51 | |
| cd9b7317 MV |
52 | config TARGET_SOCFPGA_ARRIA5_SOCDK |
| 53 | bool "Altera SOCFPGA SoCDK (Arria V)" | |
| 54 | select TARGET_SOCFPGA_ARRIA5 | |
| 7865f4b0 | 55 | |
| cd9b7317 MV |
56 | config TARGET_SOCFPGA_CYCLONE5_SOCDK |
| 57 | bool "Altera SOCFPGA SoCDK (Cyclone V)" | |
| 58 | select TARGET_SOCFPGA_CYCLONE5 | |
| 7865f4b0 | 59 | |
| a548bc51 MV |
60 | config TARGET_SOCFPGA_ARIES_MCVEVK |
| 61 | bool "Aries MCVEVK (Cyclone V)" | |
| d88995a8 MV |
62 | select TARGET_SOCFPGA_CYCLONE5 |
| 63 | ||
| 856b30da MV |
64 | config TARGET_SOCFPGA_EBV_SOCRATES |
| 65 | bool "EBV SoCrates (Cyclone V)" | |
| 66 | select TARGET_SOCFPGA_CYCLONE5 | |
| 67 | ||
| 35546f6f PM |
68 | config TARGET_SOCFPGA_IS1 |
| 69 | bool "IS1 (Cyclone V)" | |
| 70 | select TARGET_SOCFPGA_CYCLONE5 | |
| 71 | ||
| 569a191a MV |
72 | config TARGET_SOCFPGA_SAMTEC_VINING_FPGA |
| 73 | bool "samtec VIN|ING FPGA (Cyclone V)" | |
| e5ec4815 | 74 | select BOARD_LATE_INIT |
| 569a191a MV |
75 | select TARGET_SOCFPGA_CYCLONE5 |
| 76 | ||
| cf0a8dab MV |
77 | config TARGET_SOCFPGA_SR1500 |
| 78 | bool "SR1500 (Cyclone V)" | |
| 79 | select TARGET_SOCFPGA_CYCLONE5 | |
| 80 | ||
| 55c7a765 DN |
81 | config TARGET_SOCFPGA_TERASIC_DE0_NANO |
| 82 | bool "Terasic DE0-Nano-Atlas (Cyclone V)" | |
| 83 | select TARGET_SOCFPGA_CYCLONE5 | |
| 84 | ||
| 6bd041f0 DW |
85 | config TARGET_SOCFPGA_TERASIC_DE10_NANO |
| 86 | bool "Terasic DE10-Nano (Cyclone V)" | |
| 87 | select TARGET_SOCFPGA_CYCLONE5 | |
| 88 | ||
| e9c847c3 AG |
89 | config TARGET_SOCFPGA_TERASIC_DE1_SOC |
| 90 | bool "Terasic DE1-SoC (Cyclone V)" | |
| 91 | select TARGET_SOCFPGA_CYCLONE5 | |
| 92 | ||
| 952caa28 MV |
93 | config TARGET_SOCFPGA_TERASIC_SOCKIT |
| 94 | bool "Terasic SoCkit (Cyclone V)" | |
| 95 | select TARGET_SOCFPGA_CYCLONE5 | |
| 96 | ||
| 7865f4b0 MY |
97 | endchoice |
| 98 | ||
| 99 | config SYS_BOARD | |
| f0892401 MV |
100 | default "arria5-socdk" if TARGET_SOCFPGA_ARRIA5_SOCDK |
| 101 | default "cyclone5-socdk" if TARGET_SOCFPGA_CYCLONE5_SOCDK | |
| 55c7a765 | 102 | default "de0-nano-soc" if TARGET_SOCFPGA_TERASIC_DE0_NANO |
| e9c847c3 | 103 | default "de1-soc" if TARGET_SOCFPGA_TERASIC_DE1_SOC |
| 6bd041f0 | 104 | default "de10-nano" if TARGET_SOCFPGA_TERASIC_DE10_NANO |
| 35546f6f | 105 | default "is1" if TARGET_SOCFPGA_IS1 |
| a548bc51 | 106 | default "mcvevk" if TARGET_SOCFPGA_ARIES_MCVEVK |
| 952caa28 | 107 | default "sockit" if TARGET_SOCFPGA_TERASIC_SOCKIT |
| 856b30da | 108 | default "socrates" if TARGET_SOCFPGA_EBV_SOCRATES |
| ae9996c8 | 109 | default "sr1500" if TARGET_SOCFPGA_SR1500 |
| 569a191a | 110 | default "vining_fpga" if TARGET_SOCFPGA_SAMTEC_VINING_FPGA |
| 7865f4b0 MY |
111 | |
| 112 | config SYS_VENDOR | |
| cd9b7317 MV |
113 | default "altera" if TARGET_SOCFPGA_ARRIA5_SOCDK |
| 114 | default "altera" if TARGET_SOCFPGA_CYCLONE5_SOCDK | |
| a548bc51 | 115 | default "aries" if TARGET_SOCFPGA_ARIES_MCVEVK |
| 856b30da | 116 | default "ebv" if TARGET_SOCFPGA_EBV_SOCRATES |
| 569a191a | 117 | default "samtec" if TARGET_SOCFPGA_SAMTEC_VINING_FPGA |
| 55c7a765 | 118 | default "terasic" if TARGET_SOCFPGA_TERASIC_DE0_NANO |
| e9c847c3 | 119 | default "terasic" if TARGET_SOCFPGA_TERASIC_DE1_SOC |
| 6bd041f0 | 120 | default "terasic" if TARGET_SOCFPGA_TERASIC_DE10_NANO |
| 952caa28 | 121 | default "terasic" if TARGET_SOCFPGA_TERASIC_SOCKIT |
| 7865f4b0 MY |
122 | |
| 123 | config SYS_SOC | |
| 124 | default "socfpga" | |
| 125 | ||
| 126 | config SYS_CONFIG_NAME | |
| 3cbc7b87 DN |
127 | default "socfpga_arria5_socdk" if TARGET_SOCFPGA_ARRIA5_SOCDK |
| 128 | default "socfpga_cyclone5_socdk" if TARGET_SOCFPGA_CYCLONE5_SOCDK | |
| 55c7a765 | 129 | default "socfpga_de0_nano_soc" if TARGET_SOCFPGA_TERASIC_DE0_NANO |
| e9c847c3 | 130 | default "socfpga_de1_soc" if TARGET_SOCFPGA_TERASIC_DE1_SOC |
| 6bd041f0 | 131 | default "socfpga_de10_nano" if TARGET_SOCFPGA_TERASIC_DE10_NANO |
| 35546f6f | 132 | default "socfpga_is1" if TARGET_SOCFPGA_IS1 |
| a548bc51 | 133 | default "socfpga_mcvevk" if TARGET_SOCFPGA_ARIES_MCVEVK |
| 952caa28 | 134 | default "socfpga_sockit" if TARGET_SOCFPGA_TERASIC_SOCKIT |
| 856b30da | 135 | default "socfpga_socrates" if TARGET_SOCFPGA_EBV_SOCRATES |
| ae9996c8 | 136 | default "socfpga_sr1500" if TARGET_SOCFPGA_SR1500 |
| 569a191a | 137 | default "socfpga_vining_fpga" if TARGET_SOCFPGA_SAMTEC_VINING_FPGA |
| 7865f4b0 MY |
138 | |
| 139 | endif |