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Commit | Line | Data |
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77754408 DN |
1 | /* |
2 | * Copyright (C) 2012 Altera Corporation <www.altera.com> | |
3 | * | |
1a459660 | 4 | * SPDX-License-Identifier: GPL-2.0+ |
77754408 DN |
5 | */ |
6 | ||
7 | #include <common.h> | |
8 | #include <asm/io.h> | |
0ef44d11 | 9 | #include <asm/pl310.h> |
77754408 DN |
10 | #include <asm/u-boot.h> |
11 | #include <asm/utils.h> | |
77754408 | 12 | #include <image.h> |
77754408 DN |
13 | #include <asm/arch/reset_manager.h> |
14 | #include <spl.h> | |
5d649d2b | 15 | #include <asm/arch/system_manager.h> |
4c544197 | 16 | #include <asm/arch/freeze_controller.h> |
3ab019e1 CLS |
17 | #include <asm/arch/clock_manager.h> |
18 | #include <asm/arch/scan_manager.h> | |
37ef0c70 | 19 | #include <asm/arch/sdram.h> |
232fcc6e MV |
20 | #include <asm/arch/scu.h> |
21 | #include <asm/arch/nic301.h> | |
8f4c80c4 LFT |
22 | #include <asm/sections.h> |
23 | #include <fdtdec.h> | |
24 | #include <watchdog.h> | |
25 | #if defined(CONFIG_TARGET_SOCFPGA_ARRIA10) | |
26 | #include <asm/arch/pinmux.h> | |
27 | #endif | |
77754408 DN |
28 | |
29 | DECLARE_GLOBAL_DATA_PTR; | |
30 | ||
8f4c80c4 | 31 | #if defined(CONFIG_TARGET_SOCFPGA_GEN5) |
0ef44d11 DN |
32 | static struct pl310_regs *const pl310 = |
33 | (struct pl310_regs *)CONFIG_SYS_PL310_BASE; | |
232fcc6e MV |
34 | static struct scu_registers *scu_regs = |
35 | (struct scu_registers *)SOCFPGA_MPUSCU_ADDRESS; | |
36 | static struct nic301_registers *nic301_regs = | |
37 | (struct nic301_registers *)SOCFPGA_L3REGS_ADDRESS; | |
8f4c80c4 LFT |
38 | #endif |
39 | ||
40 | static const struct socfpga_system_manager *sysmgr_regs = | |
066ad14a | 41 | (struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS; |
232fcc6e | 42 | |
6473054a MV |
43 | u32 spl_boot_device(void) |
44 | { | |
066ad14a MV |
45 | const u32 bsel = readl(&sysmgr_regs->bootinfo); |
46 | ||
8f4c80c4 | 47 | switch (SYSMGR_GET_BOOTINFO_BSEL(bsel)) { |
066ad14a MV |
48 | case 0x1: /* FPGA (HPS2FPGA Bridge) */ |
49 | return BOOT_DEVICE_RAM; | |
50 | case 0x2: /* NAND Flash (1.8V) */ | |
51 | case 0x3: /* NAND Flash (3.0V) */ | |
ac242e16 | 52 | socfpga_per_reset(SOCFPGA_RESET(NAND), 0); |
066ad14a MV |
53 | return BOOT_DEVICE_NAND; |
54 | case 0x4: /* SD/MMC External Transceiver (1.8V) */ | |
55 | case 0x5: /* SD/MMC Internal Transceiver (3.0V) */ | |
56 | socfpga_per_reset(SOCFPGA_RESET(SDMMC), 0); | |
57 | socfpga_per_reset(SOCFPGA_RESET(DMA), 0); | |
58 | return BOOT_DEVICE_MMC1; | |
59 | case 0x6: /* QSPI Flash (1.8V) */ | |
60 | case 0x7: /* QSPI Flash (3.0V) */ | |
61 | socfpga_per_reset(SOCFPGA_RESET(QSPI), 0); | |
62 | return BOOT_DEVICE_SPI; | |
63 | default: | |
64 | printf("Invalid boot device (bsel=%08x)!\n", bsel); | |
65 | hang(); | |
66 | } | |
d3f34e75 MV |
67 | } |
68 | ||
8f4c80c4 | 69 | #if defined(CONFIG_TARGET_SOCFPGA_GEN5) |
232fcc6e MV |
70 | static void socfpga_nic301_slave_ns(void) |
71 | { | |
72 | writel(0x1, &nic301_regs->lwhps2fpgaregs); | |
73 | writel(0x1, &nic301_regs->hps2fpgaregs); | |
74 | writel(0x1, &nic301_regs->acp); | |
75 | writel(0x1, &nic301_regs->rom); | |
76 | writel(0x1, &nic301_regs->ocram); | |
77 | writel(0x1, &nic301_regs->sdrdata); | |
78 | } | |
0ef44d11 | 79 | |
0ef44d11 DN |
80 | void board_init_f(ulong dummy) |
81 | { | |
6473054a MV |
82 | #ifndef CONFIG_SOCFPGA_VIRTUAL_TARGET |
83 | const struct cm_config *cm_default_cfg = cm_get_default_config(); | |
84 | #endif | |
6473054a | 85 | unsigned long sdram_size; |
0ef44d11 | 86 | unsigned long reg; |
6473054a | 87 | |
0ef44d11 DN |
88 | /* |
89 | * First C code to run. Clear fake OCRAM ECC first as SBE | |
90 | * and DBE might triggered during power on | |
91 | */ | |
92 | reg = readl(&sysmgr_regs->eccgrp_ocram); | |
93 | if (reg & SYSMGR_ECC_OCRAM_SERR) | |
94 | writel(SYSMGR_ECC_OCRAM_SERR | SYSMGR_ECC_OCRAM_EN, | |
95 | &sysmgr_regs->eccgrp_ocram); | |
96 | if (reg & SYSMGR_ECC_OCRAM_DERR) | |
97 | writel(SYSMGR_ECC_OCRAM_DERR | SYSMGR_ECC_OCRAM_EN, | |
98 | &sysmgr_regs->eccgrp_ocram); | |
99 | ||
100 | memset(__bss_start, 0, __bss_end - __bss_start); | |
101 | ||
232fcc6e MV |
102 | socfpga_nic301_slave_ns(); |
103 | ||
104 | /* Configure ARM MPU SNSAC register. */ | |
105 | setbits_le32(&scu_regs->sacr, 0xfff); | |
106 | ||
0ef44d11 | 107 | /* Remap SDRAM to 0x0 */ |
232fcc6e | 108 | writel(0x1, &nic301_regs->remap); /* remap.mpuzero */ |
0ef44d11 DN |
109 | writel(0x1, &pl310->pl310_addr_filter_start); |
110 | ||
5d649d2b | 111 | #ifndef CONFIG_SOCFPGA_VIRTUAL_TARGET |
4c544197 CLS |
112 | debug("Freezing all I/O banks\n"); |
113 | /* freeze all IO banks */ | |
114 | sys_mgr_frzctrl_freeze_req(); | |
115 | ||
bd65fe35 MV |
116 | /* Put everything into reset but L4WD0. */ |
117 | socfpga_per_reset_all(); | |
118 | /* Put FPGA bridges into reset too. */ | |
119 | socfpga_bridges_reset(1); | |
120 | ||
a71df7aa MV |
121 | socfpga_per_reset(SOCFPGA_RESET(SDR), 0); |
122 | socfpga_per_reset(SOCFPGA_RESET(UART0), 0); | |
123 | socfpga_per_reset(SOCFPGA_RESET(OSC1TIMER0), 0); | |
0812a1d3 | 124 | |
9fd565db DN |
125 | timer_init(); |
126 | ||
ddfeb0aa CLS |
127 | debug("Reconfigure Clock Manager\n"); |
128 | /* reconfigure the PLLs */ | |
de778115 LFT |
129 | if (cm_basic_init(cm_default_cfg)) |
130 | hang(); | |
ddfeb0aa | 131 | |
08e463ee | 132 | /* Enable bootrom to configure IOs. */ |
40687b4f | 133 | sysmgr_config_warmrstcfgio(1); |
08e463ee | 134 | |
dc4d4aa1 CLS |
135 | /* configure the IOCSR / IO buffer settings */ |
136 | if (scan_mgr_configure_iocsr()) | |
137 | hang(); | |
138 | ||
4a0080d9 MV |
139 | sysmgr_config_warmrstcfgio(0); |
140 | ||
5d649d2b | 141 | /* configure the pin muxing through system manager */ |
4a0080d9 | 142 | sysmgr_config_warmrstcfgio(1); |
5d649d2b | 143 | sysmgr_pinmux_init(); |
4a0080d9 MV |
144 | sysmgr_config_warmrstcfgio(0); |
145 | ||
5d649d2b CLS |
146 | #endif /* CONFIG_SOCFPGA_VIRTUAL_TARGET */ |
147 | ||
bd65fe35 | 148 | /* De-assert reset for peripherals and bridges based on handoff */ |
77754408 | 149 | reset_deassert_peripherals_handoff(); |
bd65fe35 | 150 | socfpga_bridges_reset(0); |
77754408 | 151 | |
4c544197 CLS |
152 | debug("Unfreezing/Thaw all I/O banks\n"); |
153 | /* unfreeze / thaw all IO banks */ | |
154 | sys_mgr_frzctrl_thaw_req(); | |
155 | ||
77754408 DN |
156 | /* enable console uart printing */ |
157 | preloader_console_init(); | |
37ef0c70 DN |
158 | |
159 | if (sdram_mmr_init_full(0xffffffff) != 0) { | |
160 | puts("SDRAM init failed.\n"); | |
161 | hang(); | |
162 | } | |
163 | ||
164 | debug("SDRAM: Calibrating PHY\n"); | |
165 | /* SDRAM calibration */ | |
166 | if (sdram_calibration_full() == 0) { | |
167 | puts("SDRAM calibration failed.\n"); | |
168 | hang(); | |
169 | } | |
89ba8247 DN |
170 | |
171 | sdram_size = sdram_calculate_size(); | |
172 | debug("SDRAM: %ld MiB\n", sdram_size >> 20); | |
9ad3a4ac DN |
173 | |
174 | /* Sanity check ensure correct SDRAM size specified */ | |
175 | if (get_ram_size(0, sdram_size) != sdram_size) { | |
176 | puts("SDRAM size check failed!\n"); | |
177 | hang(); | |
178 | } | |
bd65fe35 MV |
179 | |
180 | socfpga_bridges_reset(1); | |
6473054a | 181 | |
7599b53d MV |
182 | /* Configure simple malloc base pointer into RAM. */ |
183 | gd->malloc_base = CONFIG_SYS_TEXT_BASE + (1024 * 1024); | |
77754408 | 184 | } |
8f4c80c4 LFT |
185 | #elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10) |
186 | void spl_board_init(void) | |
187 | { | |
188 | /* configuring the clock based on handoff */ | |
189 | cm_basic_init(gd->fdt_blob); | |
190 | WATCHDOG_RESET(); | |
191 | ||
192 | config_dedicated_pins(gd->fdt_blob); | |
193 | WATCHDOG_RESET(); | |
194 | ||
195 | /* Release UART from reset */ | |
196 | socfpga_reset_uart(0); | |
197 | ||
198 | /* enable console uart printing */ | |
199 | preloader_console_init(); | |
200 | } | |
201 | ||
202 | void board_init_f(ulong dummy) | |
203 | { | |
204 | /* | |
205 | * Configure Clock Manager to use intosc clock instead external osc to | |
206 | * ensure success watchdog operation. We do it as early as possible. | |
207 | */ | |
208 | cm_use_intosc(); | |
209 | ||
210 | socfpga_watchdog_disable(); | |
211 | ||
212 | arch_early_init_r(); | |
213 | ||
214 | #ifdef CONFIG_HW_WATCHDOG | |
215 | /* release osc1 watchdog timer 0 from reset */ | |
216 | socfpga_reset_deassert_osc1wd0(); | |
217 | ||
218 | /* reconfigure and enable the watchdog */ | |
219 | hw_watchdog_init(); | |
220 | WATCHDOG_RESET(); | |
221 | #endif /* CONFIG_HW_WATCHDOG */ | |
222 | } | |
223 | #endif |