[people/ms/u-boot.git] / arch / powerpc / cpu / mpc512x / start.S

/*
 * Copyright (C) 1998  Dan Malek <dmalek@jlc.net>
 * Copyright (C) 1999  Magnus Damm <kieraypc01.p.y.kie.era.ericsson.se>
 * Copyright (C) 2000-2009 Wolfgang Denk <wd@denx.de>
 * Copyright Freescale Semiconductor, Inc. 2004, 2006.
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 *
 * Based on the MPC83xx code.
 */

/*
 *  U-Boot - Startup Code for MPC512x based Embedded Boards
 */

#include <asm-offsets.h>
#include <config.h>
#ifndef  CONFIG_IDENT_STRING
#define  CONFIG_IDENT_STRING "MPC512X"
#endif
#include <version.h>

#define CONFIG_521X	1		/* needed for Linux kernel header files*/

#include <asm/immap_512x.h>
#include "asm-offsets.h"

#include <ppc_asm.tmpl>
#include <ppc_defs.h>

#include <asm/cache.h>
#include <asm/mmu.h>
#include <asm/u-boot.h>

/*
 * Floating Point enable, Machine Check and Recoverable Interr.
 */
#undef	MSR_KERNEL
#ifdef DEBUG
#define MSR_KERNEL (MSR_FP|MSR_RI)
#else
#define MSR_KERNEL (MSR_FP|MSR_ME|MSR_RI)
#endif

/* Macros for manipulating CSx_START/STOP */
#define START_REG(start)	((start) >> 16)
#define STOP_REG(start, size)	(((start) + (size) - 1) >> 16)

/*
 * Set up GOT: Global Offset Table
 *
 * Use r12 to access the GOT
 */
	START_GOT
	GOT_ENTRY(_GOT2_TABLE_)
	GOT_ENTRY(_FIXUP_TABLE_)

	GOT_ENTRY(_start)
	GOT_ENTRY(_start_of_vectors)
	GOT_ENTRY(_end_of_vectors)
	GOT_ENTRY(transfer_to_handler)

	GOT_ENTRY(__init_end)
	GOT_ENTRY(__bss_end)
	GOT_ENTRY(__bss_start)
	END_GOT

/*
 * Magic number and version string
 */
	.long	0x27051956		/* U-Boot Magic Number */
	.globl	version_string
version_string:
	.ascii U_BOOT_VERSION_STRING, "\0"

/*
 * Vector Table
 */
	.text
	. = EXC_OFF_SYS_RESET

	.globl	_start
	/* Start from here after reset/power on */
_start:
	b	boot_cold

	.globl	_start_of_vectors
_start_of_vectors:

/* Machine check */
	STD_EXCEPTION(0x200, MachineCheck, MachineCheckException)

/* Data Storage exception. */
	STD_EXCEPTION(0x300, DataStorage, UnknownException)

/* Instruction Storage exception. */
	STD_EXCEPTION(0x400, InstStorage, UnknownException)

/* External Interrupt exception. */
	STD_EXCEPTION(0x500, ExtInterrupt, UnknownException)

/* Alignment exception. */
	. = 0x600
Alignment:
	EXCEPTION_PROLOG(SRR0, SRR1)
	mfspr	r4,DAR
	stw	r4,_DAR(r21)
	mfspr	r5,DSISR
	stw	r5,_DSISR(r21)
	addi	r3,r1,STACK_FRAME_OVERHEAD
	EXC_XFER_TEMPLATE(Alignment, AlignmentException, MSR_KERNEL, COPY_EE)

/* Program check exception */
	. = 0x700
ProgramCheck:
	EXCEPTION_PROLOG(SRR0, SRR1)
	addi	r3,r1,STACK_FRAME_OVERHEAD
	EXC_XFER_TEMPLATE(ProgramCheck, ProgramCheckException,
		MSR_KERNEL, COPY_EE)

/* Floating Point Unit unavailable exception */
	STD_EXCEPTION(0x800, FPUnavailable, UnknownException)

/* Decrementer */
	STD_EXCEPTION(0x900, Decrementer, timer_interrupt)

/* Critical interrupt */
	STD_EXCEPTION(0xa00, Critical, UnknownException)

/* System Call */
	STD_EXCEPTION(0xc00, SystemCall, UnknownException)

/* Trace interrupt */
	STD_EXCEPTION(0xd00, Trace, UnknownException)

/* Performance Monitor interrupt */
	STD_EXCEPTION(0xf00, PerfMon, UnknownException)

/* Intruction Translation Miss */
	STD_EXCEPTION(0x1000, InstructionTLBMiss, UnknownException)

/* Data Load Translation Miss */
	STD_EXCEPTION(0x1100, DataLoadTLBMiss, UnknownException)

/* Data Store Translation Miss */
	STD_EXCEPTION(0x1200, DataStoreTLBMiss, UnknownException)

/* Instruction Address Breakpoint */
	STD_EXCEPTION(0x1300, InstructionAddrBreakpoint, DebugException)

/* System Management interrupt */
	STD_EXCEPTION(0x1400, SystemMgmtInterrupt, UnknownException)

	.globl	_end_of_vectors
_end_of_vectors:

	. = 0x3000
boot_cold:
	/* Save msr contents */
	mfmsr	r5

	/* Set IMMR area to our preferred location */
	lis	r4, CONFIG_DEFAULT_IMMR@h
	lis	r3, CONFIG_SYS_IMMR@h
	ori	r3, r3, CONFIG_SYS_IMMR@l
	stw	r3, IMMRBAR(r4)
	mtspr	MBAR, r3		/* IMMRBAR is mirrored into the MBAR SPR (311) */

	/* Initialise the machine */
	bl	cpu_early_init

	/*
	 * Set up Local Access Windows:
	 *
	 * 1) Boot/CS0 (boot FLASH)
	 * 2) On-chip SRAM (initial stack purposes)
	 */

	/* Boot CS/CS0 window range */
	lis     r3, CONFIG_SYS_IMMR@h
	ori     r3, r3, CONFIG_SYS_IMMR@l

	lis	r4, START_REG(CONFIG_SYS_FLASH_BASE)
	ori	r4, r4, STOP_REG(CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_SIZE)
	stw	r4, LPCS0AW(r3)

	/*
	 * The SRAM window has a fixed size (256K), so only the start address
	 * is necessary
	 */
	lis	r4, START_REG(CONFIG_SYS_SRAM_BASE) & 0xff00
	stw	r4, SRAMBAR(r3)

	/*
	 * According to MPC5121e RM, configuring local access windows should
	 * be followed by a dummy read of the config register that was
	 * modified last and an isync
	 */
	lwz	r4, SRAMBAR(r3)
	isync

	/*
	 * Set configuration of the Boot/CS0, the SRAM window does not have a
	 * config register so no params can be set for it
	 */
	lis     r3, (CONFIG_SYS_IMMR + LPC_OFFSET)@h
	ori     r3, r3, (CONFIG_SYS_IMMR + LPC_OFFSET)@l

	lis     r4, CONFIG_SYS_CS0_CFG@h
	ori     r4, r4, CONFIG_SYS_CS0_CFG@l
	stw     r4, CS0_CONFIG(r3)

	/* Master enable all CS's */
	lis	r4, CS_CTRL_ME@h
	ori	r4, r4, CS_CTRL_ME@l
	stw	r4, CS_CTRL(r3)

	lis	r4, (CONFIG_SYS_MONITOR_BASE)@h
	ori	r4, r4, (CONFIG_SYS_MONITOR_BASE)@l
	addi	r5, r4, in_flash - _start + EXC_OFF_SYS_RESET
	mtlr	r5
	blr

in_flash:
	lis	r1, (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET)@h
	ori	r1, r1, (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET)@l

	li	r0, 0		/* Make room for stack frame header and	*/
	stwu	r0, -4(r1)	/* clear final stack frame so that	*/
	stwu	r0, -4(r1)	/* stack backtraces terminate cleanly	*/

	/* let the C-code set up the rest			*/
	/*							*/
	/* Be careful to keep code relocatable & stack humble	*/
	/*------------------------------------------------------*/

	GET_GOT			/* initialize GOT access	*/

	/* r3: IMMR */
	lis	r3, CONFIG_SYS_IMMR@h
	/* run low-level CPU init code (in Flash) */
	bl	cpu_init_f

	/* run 1st part of board init code (in Flash) */
	bl	board_init_f

	/* NOTREACHED - board_init_f() does not return */

/*
 * This code finishes saving the registers to the exception frame
 * and jumps to the appropriate handler for the exception.
 * Register r21 is pointer into trap frame, r1 has new stack pointer.
 */
	.globl	transfer_to_handler
transfer_to_handler:
	stw	r22,_NIP(r21)
	lis	r22,MSR_POW@h
	andc	r23,r23,r22
	stw	r23,_MSR(r21)
	SAVE_GPR(7, r21)
	SAVE_4GPRS(8, r21)
	SAVE_8GPRS(12, r21)
	SAVE_8GPRS(24, r21)
	mflr	r23
	andi.	r24,r23,0x3f00		/* get vector offset */
	stw	r24,TRAP(r21)
	li	r22,0
	stw	r22,RESULT(r21)
	lwz	r24,0(r23)		/* virtual address of handler */
	lwz	r23,4(r23)		/* where to go when done */
	mtspr	SRR0,r24
	mtspr	SRR1,r20
	mtlr	r23
	SYNC
	rfi				/* jump to handler, enable MMU */

int_return:
	mfmsr	r28		/* Disable interrupts */
	li	r4,0
	ori	r4,r4,MSR_EE
	andc	r28,r28,r4
	SYNC			/* Some chip revs need this... */
	mtmsr	r28
	SYNC
	lwz	r2,_CTR(r1)
	lwz	r0,_LINK(r1)
	mtctr	r2
	mtlr	r0
	lwz	r2,_XER(r1)
	lwz	r0,_CCR(r1)
	mtspr	XER,r2
	mtcrf	0xFF,r0
	REST_10GPRS(3, r1)
	REST_10GPRS(13, r1)
	REST_8GPRS(23, r1)
	REST_GPR(31, r1)
	lwz	r2,_NIP(r1)	/* Restore environment */
	lwz	r0,_MSR(r1)
	mtspr	SRR0,r2
	mtspr	SRR1,r0
	lwz	r0,GPR0(r1)
	lwz	r2,GPR2(r1)
	lwz	r1,GPR1(r1)
	SYNC
	rfi

/*
 * This code initialises the machine, it expects original MSR contents to be in r5.
 */
cpu_early_init:
	/* Initialize machine status; enable machine check interrupt */
	/*-----------------------------------------------------------*/

	li	r3, MSR_KERNEL			/* Set ME and RI flags */
	rlwimi	r3, r5, 0, 25, 25		/* preserve IP bit */
#ifdef DEBUG
	rlwimi	r3, r5, 0, 21, 22		/* debugger might set SE, BE bits */
#endif
	mtmsr	r3
	SYNC
	mtspr	SRR1, r3			/* Mirror current MSR state in SRR1 */

	lis	r3, CONFIG_SYS_IMMR@h

#if defined(CONFIG_WATCHDOG)
	/* Initialise the watchdog and reset it */
	/*--------------------------------------*/
	lis r4, CONFIG_SYS_WATCHDOG_VALUE
	ori r4, r4, (SWCRR_SWEN | SWCRR_SWRI | SWCRR_SWPR)
	stw r4, SWCRR(r3)

	/* reset */
	li	r4, 0x556C
	sth	r4, SWSRR@l(r3)
	li	r4, 0x0
	ori	r4, r4, 0xAA39
	sth	r4, SWSRR@l(r3)
#else
	/* Disable the watchdog */
	/*----------------------*/
	lwz r4, SWCRR(r3)
	/*
	 * Check to see if it's enabled for disabling: once disabled by s/w
	 * it's not possible to re-enable it
	 */
	andi. r4, r4, 0x4
	beq 1f
	xor r4, r4, r4
	stw r4, SWCRR(r3)
1:
#endif /* CONFIG_WATCHDOG */

	/* Initialize the Hardware Implementation-dependent Registers */
	/* HID0 also contains cache control			*/
	/*------------------------------------------------------*/
	lis	r3, CONFIG_SYS_HID0_INIT@h
	ori	r3, r3, CONFIG_SYS_HID0_INIT@l
	SYNC
	mtspr	HID0, r3

	lis	r3, CONFIG_SYS_HID0_FINAL@h
	ori	r3, r3, CONFIG_SYS_HID0_FINAL@l
	SYNC
	mtspr	HID0, r3

	lis	r3, CONFIG_SYS_HID2@h
	ori	r3, r3, CONFIG_SYS_HID2@l
	SYNC
	mtspr	HID2, r3
	sync
	blr


/* Cache functions.
 *
 * Note: requires that all cache bits in
 * HID0 are in the low half word.
 */
	.globl	icache_enable
icache_enable:
	mfspr	r3, HID0
	ori	r3, r3, HID0_ICE
	lis	r4, 0
	ori	r4, r4, HID0_ILOCK
	andc	r3, r3, r4
	ori	r4, r3, HID0_ICFI
	isync
	mtspr	HID0, r4    /* sets enable and invalidate, clears lock */
	isync
	mtspr	HID0, r3	/* clears invalidate */
	blr

	.globl	icache_disable
icache_disable:
	mfspr	r3, HID0
	lis	r4, 0
	ori	r4, r4, HID0_ICE|HID0_ILOCK
	andc	r3, r3, r4
	ori	r4, r3, HID0_ICFI
	isync
	mtspr	HID0, r4     /* sets invalidate, clears enable and lock*/
	isync
	mtspr	HID0, r3	/* clears invalidate */
	blr

	.globl	icache_status
icache_status:
	mfspr	r3, HID0
	rlwinm	r3, r3, (31 - HID0_ICE_SHIFT + 1), 31, 31
	blr

	.globl	dcache_enable
dcache_enable:
	mfspr	r3, HID0
	li	r5, HID0_DCFI|HID0_DLOCK
	andc	r3, r3, r5
	mtspr	HID0, r3		/* no invalidate, unlock */
	ori	r3, r3, HID0_DCE
	ori	r5, r3, HID0_DCFI
	mtspr	HID0, r5		/* enable + invalidate */
	mtspr	HID0, r3		/* enable */
	sync
	blr

	.globl	dcache_disable
dcache_disable:
	mfspr	r3, HID0
	lis	r4, 0
	ori	r4, r4, HID0_DCE|HID0_DLOCK
	andc	r3, r3, r4
	ori	r4, r3, HID0_DCI
	sync
	mtspr	HID0, r4	/* sets invalidate, clears enable and lock */
	sync
	mtspr	HID0, r3	/* clears invalidate */
	blr

	.globl	dcache_status
dcache_status:
	mfspr	r3, HID0
	rlwinm	r3, r3, (31 - HID0_DCE_SHIFT + 1), 31, 31
	blr

	.globl get_pvr
get_pvr:
	mfspr	r3, PVR
	blr

/*-------------------------------------------------------------------*/

/*
 * void relocate_code (addr_sp, gd, addr_moni)
 *
 * This "function" does not return, instead it continues in RAM
 * after relocating the monitor code.
 *
 * r3 = dest
 * r4 = src
 * r5 = length in bytes
 * r6 = cachelinesize
 */
	.globl	relocate_code
relocate_code:
	mr	r1,  r3		/* Set new stack pointer	*/
	mr	r9,  r4		/* Save copy of Global Data pointer */
	mr	r10, r5		/* Save copy of Destination Address */

	GET_GOT
	mr	r3,  r5				/* Destination Address */
	lis	r4, CONFIG_SYS_MONITOR_BASE@h		/* Source      Address */
	ori	r4, r4, CONFIG_SYS_MONITOR_BASE@l
	lwz	r5, GOT(__init_end)
	sub	r5, r5, r4
	li	r6, CONFIG_SYS_CACHELINE_SIZE		/* Cache Line Size */

	/*
	 * Fix GOT pointer:
	 *
	 * New GOT-PTR = (old GOT-PTR - CONFIG_SYS_MONITOR_BASE)
	 *		+ Destination Address
	 *
	 * Offset:
	 */
	sub	r15, r10, r4

	/* First our own GOT */
	add	r12, r12, r15
	/* then the one used by the C code */
	add	r30, r30, r15

	/*
	 * Now relocate code
	 */
	cmplw	cr1,r3,r4
	addi	r0,r5,3
	srwi.	r0,r0,2
	beq	cr1,4f		/* In place copy is not necessary */
	beq	7f		/* Protect against 0 count	  */
	mtctr	r0
	bge	cr1,2f
	la	r8,-4(r4)
	la	r7,-4(r3)

	/* copy */
1:	lwzu	r0,4(r8)
	stwu	r0,4(r7)
	bdnz	1b

	addi	r0,r5,3
	srwi.	r0,r0,2
	mtctr	r0
	la	r8,-4(r4)
	la	r7,-4(r3)

	/* and compare */
20:	lwzu	r20,4(r8)
	lwzu	r21,4(r7)
	xor. r22, r20, r21
	bne  30f
	bdnz	20b
	b 4f

	/* compare failed */
30:	li r3, 0
	blr

2:	slwi	r0,r0,2 /* re copy in reverse order ... y do we needed it? */
	add	r8,r4,r0
	add	r7,r3,r0
3:	lwzu	r0,-4(r8)
	stwu	r0,-4(r7)
	bdnz	3b

/*
 * Now flush the cache: note that we must start from a cache aligned
 * address. Otherwise we might miss one cache line.
 */
4:	cmpwi	r6,0
	add	r5,r3,r5
	beq	7f		/* Always flush prefetch queue in any case */
	subi	r0,r6,1
	andc	r3,r3,r0
	mr	r4,r3
5:	dcbst	0,r4
	add	r4,r4,r6
	cmplw	r4,r5
	blt	5b
	sync			/* Wait for all dcbst to complete on bus */
	mr	r4,r3
6:	icbi	0,r4
	add	r4,r4,r6
	cmplw	r4,r5
	blt	6b
7:	sync			/* Wait for all icbi to complete on bus	*/
	isync

/*
 * We are done. Do not return, instead branch to second part of board
 * initialization, now running from RAM.
 */
	addi	r0, r10, in_ram - _start + EXC_OFF_SYS_RESET
	mtlr	r0
	blr

in_ram:
	/*
	 * Relocation Function, r12 point to got2+0x8000
	 *
	 * Adjust got2 pointers, no need to check for 0, this code
	 * already puts a few entries in the table.
	 */
	li	r0,__got2_entries@sectoff@l
	la	r3,GOT(_GOT2_TABLE_)
	lwz	r11,GOT(_GOT2_TABLE_)
	mtctr	r0
	sub	r11,r3,r11
	addi	r3,r3,-4
1:	lwzu	r0,4(r3)
	cmpwi	r0,0
	beq-	2f
	add	r0,r0,r11
	stw	r0,0(r3)
2:	bdnz	1b

	/*
	 * Now adjust the fixups and the pointers to the fixups
	 * in case we need to move ourselves again.
	 */
	li	r0,__fixup_entries@sectoff@l
	lwz	r3,GOT(_FIXUP_TABLE_)
	cmpwi	r0,0
	mtctr	r0
	addi	r3,r3,-4
	beq	4f
3:	lwzu	r4,4(r3)
	lwzux	r0,r4,r11
	cmpwi	r0,0
	add	r0,r0,r11
	stw	r4,0(r3)
	beq-	5f
	stw	r0,0(r4)
5:	bdnz	3b
4:
clear_bss:
	/*
	 * Now clear BSS segment
	 */
	lwz	r3,GOT(__bss_start)
	lwz	r4,GOT(__bss_end)

	cmplw	0, r3, r4
	beq	6f

	li	r0, 0
5:
	stw	r0, 0(r3)
	addi	r3, r3, 4
	cmplw	0, r3, r4
	bne	5b
6:
	mr	r3, r9		/* Global Data pointer		*/
	mr	r4, r10		/* Destination Address		*/
	bl	board_init_r

	/*
	 * Copy exception vector code to low memory
	 *
	 * r3: dest_addr
	 * r7: source address, r8: end address, r9: target address
	 */
	.globl	trap_init
trap_init:
	mflr	r4		/* save link register */
	GET_GOT
	lwz	r7, GOT(_start)
	lwz	r8, GOT(_end_of_vectors)

	li	r9, 0x100	/* reset vector at 0x100 */

	cmplw	0, r7, r8
	bgelr			/* return if r7>=r8 - just in case */
1:
	lwz	r0, 0(r7)
	stw	r0, 0(r9)
	addi	r7, r7, 4
	addi	r9, r9, 4
	cmplw	0, r7, r8
	bne	1b

	/*
	 * relocate `hdlr' and `int_return' entries
	 */
	li	r7, .L_MachineCheck - _start + EXC_OFF_SYS_RESET
	li	r8, Alignment - _start + EXC_OFF_SYS_RESET
2:
	bl	trap_reloc
	addi	r7, r7, 0x100		/* next exception vector */
	cmplw	0, r7, r8
	blt	2b

	li	r7, .L_Alignment - _start + EXC_OFF_SYS_RESET
	bl	trap_reloc

	li	r7, .L_ProgramCheck - _start + EXC_OFF_SYS_RESET
	bl	trap_reloc

	li	r7, .L_FPUnavailable - _start + EXC_OFF_SYS_RESET
	li	r8, SystemCall - _start + EXC_OFF_SYS_RESET
3:
	bl	trap_reloc
	addi	r7, r7, 0x100		/* next exception vector */
	cmplw	0, r7, r8
	blt	3b

	li	r7, .L_Trace - _start + EXC_OFF_SYS_RESET
	li	r8, _end_of_vectors - _start + EXC_OFF_SYS_RESET
4:
	bl	trap_reloc
	addi	r7, r7, 0x100		/* next exception vector */
	cmplw	0, r7, r8
	blt	4b

	mfmsr	r3			/* now that the vectors have */
	lis	r7, MSR_IP@h		/* relocated into low memory */
	ori	r7, r7, MSR_IP@l	/* MSR[IP] can be turned off */
	andc	r3, r3, r7		/* (if it was on) */
	SYNC				/* Some chip revs need this... */
	mtmsr	r3
	SYNC

	mtlr	r4			/* restore link register    */
	blr
Commit	Line	Data
8993e54b RJ	1	/*
	2	* Copyright (C) 1998 Dan Malek <dmalek@jlc.net>
	3	* Copyright (C) 1999 Magnus Damm <kieraypc01.p.y.kie.era.ericsson.se>
3b74e7ec	4	* Copyright (C) 2000-2009 Wolfgang Denk <wd@denx.de>
4c2e3da8	5	* Copyright Freescale Semiconductor, Inc. 2004, 2006.
8993e54b RJ	6	*
	7	* See file CREDITS for list of people who contributed to this
	8	* project.
	9	*
	10	* This program is free software; you can redistribute it and/or
	11	* modify it under the terms of the GNU General Public License as
	12	* published by the Free Software Foundation; either version 2 of
	13	* the License, or (at your option) any later version.
	14	*
	15	* This program is distributed in the hope that it will be useful,
	16	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	17	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	18	* GNU General Public License for more details.
	19	*
	20	* You should have received a copy of the GNU General Public License
	21	* along with this program; if not, write to the Free Software
	22	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	23	* MA 02111-1307 USA
	24	*
	25	* Based on the MPC83xx code.
	26	*/
	27
	28	/*
	29	* U-Boot - Startup Code for MPC512x based Embedded Boards
	30	*/
	31
25ddd1fb	32	#include <asm-offsets.h>
8993e54b	33	#include <config.h>
09c2e90c AB	34	#ifndef CONFIG_IDENT_STRING
	35	#define CONFIG_IDENT_STRING "MPC512X"
	36	#endif
8993e54b RJ	37	#include <version.h>
	38
	39	#define CONFIG_521X 1 /* needed for Linux kernel header files*/
	40
3b74e7ec WD	41	#include <asm/immap_512x.h>
	42	#include "asm-offsets.h"
	43
8993e54b RJ	44	#include <ppc_asm.tmpl>
	45	#include <ppc_defs.h>
	46
	47	#include <asm/cache.h>
	48	#include <asm/mmu.h>
d98b0523	49	#include <asm/u-boot.h>
8993e54b	50
8993e54b RJ	51	/*
	52	* Floating Point enable, Machine Check and Recoverable Interr.
	53	*/
	54	#undef MSR_KERNEL
	55	#ifdef DEBUG
	56	#define MSR_KERNEL (MSR_FP\|MSR_RI)
	57	#else
	58	#define MSR_KERNEL (MSR_FP\|MSR_ME\|MSR_RI)
	59	#endif
	60
	61	/* Macros for manipulating CSx_START/STOP */
	62	#define START_REG(start) ((start) >> 16)
	63	#define STOP_REG(start, size) (((start) + (size) - 1) >> 16)
	64
	65	/*
	66	* Set up GOT: Global Offset Table
	67	*
0f8aa159	68	* Use r12 to access the GOT
8993e54b RJ	69	*/
	70	START_GOT
	71	GOT_ENTRY(_GOT2_TABLE_)
	72	GOT_ENTRY(_FIXUP_TABLE_)
	73
	74	GOT_ENTRY(_start)
	75	GOT_ENTRY(_start_of_vectors)
	76	GOT_ENTRY(_end_of_vectors)
	77	GOT_ENTRY(transfer_to_handler)
	78
	79	GOT_ENTRY(__init_end)
3929fb0a	80	GOT_ENTRY(__bss_end)
8993e54b RJ	81	GOT_ENTRY(__bss_start)
	82	END_GOT
	83
	84	/*
	85	* Magic number and version string
	86	*/
	87	.long 0x27051956 /* U-Boot Magic Number */
	88	.globl version_string
	89	version_string:
09c2e90c	90	.ascii U_BOOT_VERSION_STRING, "\0"
8993e54b RJ	91
	92	/*
	93	* Vector Table
	94	*/
	95	.text
	96	. = EXC_OFF_SYS_RESET
	97
	98	.globl _start
	99	/* Start from here after reset/power on */
	100	_start:
8993e54b RJ	101	b boot_cold
	102
	103	.globl _start_of_vectors
	104	_start_of_vectors:
	105
	106	/* Machine check */
	107	STD_EXCEPTION(0x200, MachineCheck, MachineCheckException)
	108
	109	/* Data Storage exception. */
	110	STD_EXCEPTION(0x300, DataStorage, UnknownException)
	111
	112	/* Instruction Storage exception. */
	113	STD_EXCEPTION(0x400, InstStorage, UnknownException)
	114
	115	/* External Interrupt exception. */
	116	STD_EXCEPTION(0x500, ExtInterrupt, UnknownException)
	117
	118	/* Alignment exception. */
	119	. = 0x600
	120	Alignment:
	121	EXCEPTION_PROLOG(SRR0, SRR1)
	122	mfspr r4,DAR
	123	stw r4,_DAR(r21)
	124	mfspr r5,DSISR
	125	stw r5,_DSISR(r21)
	126	addi r3,r1,STACK_FRAME_OVERHEAD
fc4e1887	127	EXC_XFER_TEMPLATE(Alignment, AlignmentException, MSR_KERNEL, COPY_EE)
8993e54b RJ	128
	129	/* Program check exception */
	130	. = 0x700
	131	ProgramCheck:
	132	EXCEPTION_PROLOG(SRR0, SRR1)
	133	addi r3,r1,STACK_FRAME_OVERHEAD
fc4e1887 JT	134	EXC_XFER_TEMPLATE(ProgramCheck, ProgramCheckException,
fc4e1887 JT	135	MSR_KERNEL, COPY_EE)
8993e54b RJ	136
	137	/* Floating Point Unit unavailable exception */
	138	STD_EXCEPTION(0x800, FPUnavailable, UnknownException)
	139
	140	/* Decrementer */
	141	STD_EXCEPTION(0x900, Decrementer, timer_interrupt)
	142
	143	/* Critical interrupt */
	144	STD_EXCEPTION(0xa00, Critical, UnknownException)
	145
	146	/* System Call */
	147	STD_EXCEPTION(0xc00, SystemCall, UnknownException)
	148
	149	/* Trace interrupt */
	150	STD_EXCEPTION(0xd00, Trace, UnknownException)
	151
	152	/* Performance Monitor interrupt */
	153	STD_EXCEPTION(0xf00, PerfMon, UnknownException)
	154
	155	/* Intruction Translation Miss */
	156	STD_EXCEPTION(0x1000, InstructionTLBMiss, UnknownException)
	157
	158	/* Data Load Translation Miss */
	159	STD_EXCEPTION(0x1100, DataLoadTLBMiss, UnknownException)
	160
	161	/* Data Store Translation Miss */
	162	STD_EXCEPTION(0x1200, DataStoreTLBMiss, UnknownException)
	163
	164	/* Instruction Address Breakpoint */
	165	STD_EXCEPTION(0x1300, InstructionAddrBreakpoint, DebugException)
	166
	167	/* System Management interrupt */
	168	STD_EXCEPTION(0x1400, SystemMgmtInterrupt, UnknownException)
	169
	170	.globl _end_of_vectors
	171	_end_of_vectors:
	172
	173	. = 0x3000
	174	boot_cold:
	175	/* Save msr contents */
	176	mfmsr r5
	177
	178	/* Set IMMR area to our preferred location */
	179	lis r4, CONFIG_DEFAULT_IMMR@h
6d0f6bcf JCPV	180	lis r3, CONFIG_SYS_IMMR@h
6d0f6bcf JCPV	181	ori r3, r3, CONFIG_SYS_IMMR@l
8993e54b RJ	182	stw r3, IMMRBAR(r4)
	183	mtspr MBAR, r3 /* IMMRBAR is mirrored into the MBAR SPR (311) */
	184
	185	/* Initialise the machine */
	186	bl cpu_early_init
	187
	188	/*
	189	* Set up Local Access Windows:
	190	*
	191	* 1) Boot/CS0 (boot FLASH)
	192	* 2) On-chip SRAM (initial stack purposes)
	193	*/
	194
	195	/* Boot CS/CS0 window range */
6d0f6bcf JCPV	196	lis r3, CONFIG_SYS_IMMR@h
6d0f6bcf JCPV	197	ori r3, r3, CONFIG_SYS_IMMR@l
8993e54b	198
6d0f6bcf JCPV	199	lis r4, START_REG(CONFIG_SYS_FLASH_BASE)
6d0f6bcf JCPV	200	ori r4, r4, STOP_REG(CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_SIZE)
8993e54b RJ	201	stw r4, LPCS0AW(r3)
	202
	203	/*
	204	* The SRAM window has a fixed size (256K), so only the start address
	205	* is necessary
	206	*/
6d0f6bcf	207	lis r4, START_REG(CONFIG_SYS_SRAM_BASE) & 0xff00
8993e54b RJ	208	stw r4, SRAMBAR(r3)
8993e54b RJ	209
b1b54e35	210	/*
8993e54b	211	* According to MPC5121e RM, configuring local access windows should
b1b54e35	212	* be followed by a dummy read of the config register that was
8993e54b	213	* modified last and an isync
b1b54e35	214	*/
8993e54b RJ	215	lwz r4, SRAMBAR(r3)
	216	isync
	217
	218	/*
	219	* Set configuration of the Boot/CS0, the SRAM window does not have a
	220	* config register so no params can be set for it
	221	*/
6d0f6bcf JCPV	222	lis r3, (CONFIG_SYS_IMMR + LPC_OFFSET)@h
6d0f6bcf JCPV	223	ori r3, r3, (CONFIG_SYS_IMMR + LPC_OFFSET)@l
8993e54b	224
6d0f6bcf JCPV	225	lis r4, CONFIG_SYS_CS0_CFG@h
6d0f6bcf JCPV	226	ori r4, r4, CONFIG_SYS_CS0_CFG@l
b1b54e35	227	stw r4, CS0_CONFIG(r3)
8993e54b RJ	228
	229	/* Master enable all CS's */
	230	lis r4, CS_CTRL_ME@h
	231	ori r4, r4, CS_CTRL_ME@l
	232	stw r4, CS_CTRL(r3)
	233
6d0f6bcf JCPV	234	lis r4, (CONFIG_SYS_MONITOR_BASE)@h
6d0f6bcf JCPV	235	ori r4, r4, (CONFIG_SYS_MONITOR_BASE)@l
8993e54b RJ	236	addi r5, r4, in_flash - _start + EXC_OFF_SYS_RESET
	237	mtlr r5
	238	blr
	239
	240	in_flash:
6d0f6bcf JCPV	241	lis r1, (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET)@h
6d0f6bcf JCPV	242	ori r1, r1, (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET)@l
8993e54b RJ	243
	244	li r0, 0 /* Make room for stack frame header and */
	245	stwu r0, -4(r1) /* clear final stack frame so that */
	246	stwu r0, -4(r1) /* stack backtraces terminate cleanly */
	247
	248	/* let the C-code set up the rest */
	249	/* */
	250	/* Be careful to keep code relocatable & stack humble */
	251	/------------------------------------------------------/
	252
	253	GET_GOT /* initialize GOT access */
8c4734e9	254
8993e54b	255	/* r3: IMMR */
6d0f6bcf	256	lis r3, CONFIG_SYS_IMMR@h
8993e54b RJ	257	/* run low-level CPU init code (in Flash) */
	258	bl cpu_init_f
	259
8993e54b RJ	260	/* run 1st part of board init code (in Flash) */
	261	bl board_init_f
	262
	263	/* NOTREACHED - board_init_f() does not return */
	264
	265	/*
	266	* This code finishes saving the registers to the exception frame
	267	* and jumps to the appropriate handler for the exception.
	268	* Register r21 is pointer into trap frame, r1 has new stack pointer.
	269	*/
	270	.globl transfer_to_handler
	271	transfer_to_handler:
	272	stw r22,_NIP(r21)
	273	lis r22,MSR_POW@h
	274	andc r23,r23,r22
	275	stw r23,_MSR(r21)
	276	SAVE_GPR(7, r21)
	277	SAVE_4GPRS(8, r21)
	278	SAVE_8GPRS(12, r21)
	279	SAVE_8GPRS(24, r21)
	280	mflr r23
	281	andi. r24,r23,0x3f00 /* get vector offset */
	282	stw r24,TRAP(r21)
	283	li r22,0
	284	stw r22,RESULT(r21)
	285	lwz r24,0(r23) /* virtual address of handler */
	286	lwz r23,4(r23) /* where to go when done */
	287	mtspr SRR0,r24
	288	mtspr SRR1,r20
	289	mtlr r23
	290	SYNC
	291	rfi /* jump to handler, enable MMU */
	292
	293	int_return:
	294	mfmsr r28 /* Disable interrupts */
	295	li r4,0
	296	ori r4,r4,MSR_EE
	297	andc r28,r28,r4
	298	SYNC /* Some chip revs need this... */
	299	mtmsr r28
	300	SYNC
	301	lwz r2,_CTR(r1)
	302	lwz r0,_LINK(r1)
	303	mtctr r2
	304	mtlr r0
	305	lwz r2,_XER(r1)
	306	lwz r0,_CCR(r1)
	307	mtspr XER,r2
	308	mtcrf 0xFF,r0
	309	REST_10GPRS(3, r1)
	310	REST_10GPRS(13, r1)
	311	REST_8GPRS(23, r1)
	312	REST_GPR(31, r1)
	313	lwz r2,_NIP(r1) /* Restore environment */
	314	lwz r0,_MSR(r1)
	315	mtspr SRR0,r2
	316	mtspr SRR1,r0
	317	lwz r0,GPR0(r1)
	318	lwz r2,GPR2(r1)
	319	lwz r1,GPR1(r1)
	320	SYNC
	321	rfi
	322
	323	/*
324	* This code initialises the machine, it expects original MSR contents to be in r5.
325	*/
326	cpu_early_init:
327	/* Initialize machine status; enable machine check interrupt */
328	/-----------------------------------------------------------/
329
330	li r3, MSR_KERNEL /* Set ME and RI flags */
331	rlwimi r3, r5, 0, 25, 25 /* preserve IP bit */
332	#ifdef DEBUG
333	rlwimi r3, r5, 0, 21, 22 /* debugger might set SE, BE bits */
334	#endif
335	mtmsr r3
336	SYNC
337	mtspr SRR1, r3 /* Mirror current MSR state in SRR1 */
338
6d0f6bcf	339	lis r3, CONFIG_SYS_IMMR@h
8993e54b RJ	340
	341	#if defined(CONFIG_WATCHDOG)
	342	/* Initialise the watchdog and reset it */
	343	/--------------------------------------/
6d0f6bcf	344	lis r4, CONFIG_SYS_WATCHDOG_VALUE
8993e54b RJ	345	ori r4, r4, (SWCRR_SWEN \| SWCRR_SWRI \| SWCRR_SWPR)
	346	stw r4, SWCRR(r3)
	347
	348	/* reset */
	349	li r4, 0x556C
	350	sth r4, SWSRR@l(r3)
	351	li r4, 0x0
	352	ori r4, r4, 0xAA39
	353	sth r4, SWSRR@l(r3)
	354	#else
	355	/* Disable the watchdog */
	356	/----------------------/
	357	lwz r4, SWCRR(r3)
	358	/*
	359	* Check to see if it's enabled for disabling: once disabled by s/w
	360	* it's not possible to re-enable it
	361	*/
	362	andi. r4, r4, 0x4
	363	beq 1f
	364	xor r4, r4, r4
	365	stw r4, SWCRR(r3)
	366	1:
	367	#endif /* CONFIG_WATCHDOG */
	368
	369	/* Initialize the Hardware Implementation-dependent Registers */
	370	/* HID0 also contains cache control */
	371	/------------------------------------------------------/
6d0f6bcf JCPV	372	lis r3, CONFIG_SYS_HID0_INIT@h
6d0f6bcf JCPV	373	ori r3, r3, CONFIG_SYS_HID0_INIT@l
8993e54b RJ	374	SYNC
	375	mtspr HID0, r3
	376
6d0f6bcf JCPV	377	lis r3, CONFIG_SYS_HID0_FINAL@h
6d0f6bcf JCPV	378	ori r3, r3, CONFIG_SYS_HID0_FINAL@l
8993e54b RJ	379	SYNC
	380	mtspr HID0, r3
	381
6d0f6bcf JCPV	382	lis r3, CONFIG_SYS_HID2@h
6d0f6bcf JCPV	383	ori r3, r3, CONFIG_SYS_HID2@l
8993e54b RJ	384	SYNC
	385	mtspr HID2, r3
	386	sync
	387	blr
	388
	389
	390	/* Cache functions.
	391	*
	392	* Note: requires that all cache bits in
	393	* HID0 are in the low half word.
	394	*/
	395	.globl icache_enable
	396	icache_enable:
	397	mfspr r3, HID0
	398	ori r3, r3, HID0_ICE
	399	lis r4, 0
	400	ori r4, r4, HID0_ILOCK
	401	andc r3, r3, r4
	402	ori r4, r3, HID0_ICFI
	403	isync
	404	mtspr HID0, r4 /* sets enable and invalidate, clears lock */
	405	isync
	406	mtspr HID0, r3 /* clears invalidate */
	407	blr
	408
	409	.globl icache_disable
	410	icache_disable:
	411	mfspr r3, HID0
	412	lis r4, 0
	413	ori r4, r4, HID0_ICE\|HID0_ILOCK
	414	andc r3, r3, r4
	415	ori r4, r3, HID0_ICFI
	416	isync
	417	mtspr HID0, r4 /* sets invalidate, clears enable and lock*/
	418	isync
	419	mtspr HID0, r3 /* clears invalidate */
	420	blr
	421
	422	.globl icache_status
	423	icache_status:
	424	mfspr r3, HID0
	425	rlwinm r3, r3, (31 - HID0_ICE_SHIFT + 1), 31, 31
	426	blr
	427
	428	.globl dcache_enable
	429	dcache_enable:
	430	mfspr r3, HID0
	431	li r5, HID0_DCFI\|HID0_DLOCK
	432	andc r3, r3, r5
	433	mtspr HID0, r3 /* no invalidate, unlock */
	434	ori r3, r3, HID0_DCE
	435	ori r5, r3, HID0_DCFI
	436	mtspr HID0, r5 /* enable + invalidate */
	437	mtspr HID0, r3 /* enable */
	438	sync
	439	blr
	440
	441	.globl dcache_disable
	442	dcache_disable:
	443	mfspr r3, HID0
	444	lis r4, 0
	445	ori r4, r4, HID0_DCE\|HID0_DLOCK
	446	andc r3, r3, r4
	447	ori r4, r3, HID0_DCI
448	sync
449	mtspr HID0, r4 /* sets invalidate, clears enable and lock */
450	sync
451	mtspr HID0, r3 /* clears invalidate */
452	blr
453
454	.globl dcache_status
455	dcache_status:
456	mfspr r3, HID0
457	rlwinm r3, r3, (31 - HID0_DCE_SHIFT + 1), 31, 31
458	blr
459
460	.globl get_pvr
461	get_pvr:
462	mfspr r3, PVR
463	blr
464
8993e54b RJ	465	/-------------------------------------------------------------------/
	466
	467	/*
	468	* void relocate_code (addr_sp, gd, addr_moni)
	469	*
	470	* This "function" does not return, instead it continues in RAM
	471	* after relocating the monitor code.
	472	*
	473	* r3 = dest
	474	* r4 = src
	475	* r5 = length in bytes
	476	* r6 = cachelinesize
	477	*/
	478	.globl relocate_code
	479	relocate_code:
	480	mr r1, r3 /* Set new stack pointer */
	481	mr r9, r4 /* Save copy of Global Data pointer */
	482	mr r10, r5 /* Save copy of Destination Address */
	483
0f8aa159	484	GET_GOT
8993e54b	485	mr r3, r5 /* Destination Address */
6d0f6bcf JCPV	486	lis r4, CONFIG_SYS_MONITOR_BASE@h /* Source Address */
6d0f6bcf JCPV	487	ori r4, r4, CONFIG_SYS_MONITOR_BASE@l
8993e54b RJ	488	lwz r5, GOT(__init_end)
8993e54b RJ	489	sub r5, r5, r4
6d0f6bcf	490	li r6, CONFIG_SYS_CACHELINE_SIZE /* Cache Line Size */
8993e54b RJ	491
	492	/*
	493	* Fix GOT pointer:
	494	*
6d0f6bcf	495	* New GOT-PTR = (old GOT-PTR - CONFIG_SYS_MONITOR_BASE)
8993e54b RJ	496	* + Destination Address
	497	*
	498	* Offset:
	499	*/
	500	sub r15, r10, r4
	501
	502	/* First our own GOT */
0f8aa159	503	add r12, r12, r15
8993e54b RJ	504	/* then the one used by the C code */
	505	add r30, r30, r15
	506
	507	/*
	508	* Now relocate code
	509	*/
	510	cmplw cr1,r3,r4
	511	addi r0,r5,3
	512	srwi. r0,r0,2
	513	beq cr1,4f /* In place copy is not necessary */
	514	beq 7f /* Protect against 0 count */
	515	mtctr r0
	516	bge cr1,2f
	517	la r8,-4(r4)
	518	la r7,-4(r3)
	519
	520	/* copy */
	521	1: lwzu r0,4(r8)
	522	stwu r0,4(r7)
	523	bdnz 1b
	524
	525	addi r0,r5,3
	526	srwi. r0,r0,2
	527	mtctr r0
	528	la r8,-4(r4)
	529	la r7,-4(r3)
	530
	531	/* and compare */
	532	20: lwzu r20,4(r8)
	533	lwzu r21,4(r7)
	534	xor. r22, r20, r21
	535	bne 30f
	536	bdnz 20b
	537	b 4f
	538
	539	/* compare failed */
	540	30: li r3, 0
	541	blr
	542
	543	2: slwi r0,r0,2 /* re copy in reverse order ... y do we needed it? */
	544	add r8,r4,r0
	545	add r7,r3,r0
	546	3: lwzu r0,-4(r8)
	547	stwu r0,-4(r7)
	548	bdnz 3b
	549
	550	/*
	551	* Now flush the cache: note that we must start from a cache aligned
	552	* address. Otherwise we might miss one cache line.
	553	*/
	554	4: cmpwi r6,0
	555	add r5,r3,r5
	556	beq 7f /* Always flush prefetch queue in any case */
	557	subi r0,r6,1
	558	andc r3,r3,r0
	559	mr r4,r3
	560	5: dcbst 0,r4
	561	add r4,r4,r6
	562	cmplw r4,r5
	563	blt 5b
	564	sync /* Wait for all dcbst to complete on bus */
	565	mr r4,r3
	566	6: icbi 0,r4
	567	add r4,r4,r6
568	cmplw r4,r5
569	blt 6b
570	7: sync /* Wait for all icbi to complete on bus */
571	isync
572
573	/*
574	* We are done. Do not return, instead branch to second part of board
575	* initialization, now running from RAM.
576	*/
577	addi r0, r10, in_ram - _start + EXC_OFF_SYS_RESET
578	mtlr r0
579	blr
580
581	in_ram:
582	/*
0f8aa159	583	* Relocation Function, r12 point to got2+0x8000
8993e54b RJ	584	*
	585	* Adjust got2 pointers, no need to check for 0, this code
	586	* already puts a few entries in the table.
	587	*/
	588	li r0,__got2_entries@sectoff@l
	589	la r3,GOT(_GOT2_TABLE_)
	590	lwz r11,GOT(_GOT2_TABLE_)
	591	mtctr r0
	592	sub r11,r3,r11
	593	addi r3,r3,-4
	594	1: lwzu r0,4(r3)
afc3ba0f JT	595	cmpwi r0,0
afc3ba0f JT	596	beq- 2f
8993e54b RJ	597	add r0,r0,r11
8993e54b RJ	598	stw r0,0(r3)
afc3ba0f	599	2: bdnz 1b
8993e54b RJ	600
	601	/*
	602	* Now adjust the fixups and the pointers to the fixups
	603	* in case we need to move ourselves again.
	604	*/
afc3ba0f	605	li r0,__fixup_entries@sectoff@l
8993e54b RJ	606	lwz r3,GOT(_FIXUP_TABLE_)
	607	cmpwi r0,0
	608	mtctr r0
	609	addi r3,r3,-4
	610	beq 4f
	611	3: lwzu r4,4(r3)
	612	lwzux r0,r4,r11
d1e0b10a	613	cmpwi r0,0
8993e54b	614	add r0,r0,r11
34bbf618	615	stw r4,0(r3)
d1e0b10a	616	beq- 5f
8993e54b	617	stw r0,0(r4)
d1e0b10a	618	5: bdnz 3b
8993e54b RJ	619	4:
	620	clear_bss:
	621	/*
	622	* Now clear BSS segment
	623	*/
	624	lwz r3,GOT(__bss_start)
3929fb0a	625	lwz r4,GOT(__bss_end)
8993e54b RJ	626
	627	cmplw 0, r3, r4
	628	beq 6f
	629
	630	li r0, 0
	631	5:
	632	stw r0, 0(r3)
	633	addi r3, r3, 4
	634	cmplw 0, r3, r4
	635	bne 5b
	636	6:
	637	mr r3, r9 /* Global Data pointer */
	638	mr r4, r10 /* Destination Address */
	639	bl board_init_r
	640
	641	/*
	642	* Copy exception vector code to low memory
	643	*
	644	* r3: dest_addr
	645	* r7: source address, r8: end address, r9: target address
	646	*/
	647	.globl trap_init
	648	trap_init:
0f8aa159 JT	649	mflr r4 /* save link register */
0f8aa159 JT	650	GET_GOT
8993e54b RJ	651	lwz r7, GOT(_start)
	652	lwz r8, GOT(_end_of_vectors)
	653
	654	li r9, 0x100 /* reset vector at 0x100 */
	655
	656	cmplw 0, r7, r8
	657	bgelr /* return if r7>=r8 - just in case */
8993e54b RJ	658	1:
	659	lwz r0, 0(r7)
	660	stw r0, 0(r9)
	661	addi r7, r7, 4
	662	addi r9, r9, 4
	663	cmplw 0, r7, r8
	664	bne 1b
	665
	666	/*
	667	* relocate `hdlr' and `int_return' entries
	668	*/
	669	li r7, .L_MachineCheck - _start + EXC_OFF_SYS_RESET
	670	li r8, Alignment - _start + EXC_OFF_SYS_RESET
	671	2:
	672	bl trap_reloc
	673	addi r7, r7, 0x100 /* next exception vector */
	674	cmplw 0, r7, r8
	675	blt 2b
	676
	677	li r7, .L_Alignment - _start + EXC_OFF_SYS_RESET
	678	bl trap_reloc
	679
	680	li r7, .L_ProgramCheck - _start + EXC_OFF_SYS_RESET
	681	bl trap_reloc
	682
	683	li r7, .L_FPUnavailable - _start + EXC_OFF_SYS_RESET
	684	li r8, SystemCall - _start + EXC_OFF_SYS_RESET
	685	3:
	686	bl trap_reloc
	687	addi r7, r7, 0x100 /* next exception vector */
	688	cmplw 0, r7, r8
	689	blt 3b
	690
	691	li r7, .L_Trace - _start + EXC_OFF_SYS_RESET
	692	li r8, _end_of_vectors - _start + EXC_OFF_SYS_RESET
	693	4:
	694	bl trap_reloc
	695	addi r7, r7, 0x100 /* next exception vector */
	696	cmplw 0, r7, r8
	697	blt 4b
	698
	699	mfmsr r3 /* now that the vectors have */
	700	lis r7, MSR_IP@h /* relocated into low memory */
	701	ori r7, r7, MSR_IP@l /* MSR[IP] can be turned off */
	702	andc r3, r3, r7 /* (if it was on) */
	703	SYNC /* Some chip revs need this... */
	704	mtmsr r3
	705	SYNC
	706
	707	mtlr r4 /* restore link register */
	708	blr