[people/ms/u-boot.git] / arch / powerpc / cpu / mpc85xx / cpu_init.c

/*
 * Copyright 2007-2010 Freescale Semiconductor, Inc.
 *
 * (C) Copyright 2003 Motorola Inc.
 * Modified by Xianghua Xiao, X.Xiao@motorola.com
 *
 * (C) Copyright 2000
 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

#include <common.h>
#include <watchdog.h>
#include <asm/processor.h>
#include <ioports.h>
#include <sata.h>
#include <asm/io.h>
#include <asm/cache.h>
#include <asm/mmu.h>
#include <asm/fsl_law.h>
#include <asm/fsl_serdes.h>
#include "mp.h"

DECLARE_GLOBAL_DATA_PTR;

#ifdef CONFIG_QE
extern qe_iop_conf_t qe_iop_conf_tab[];
extern void qe_config_iopin(u8 port, u8 pin, int dir,
				int open_drain, int assign);
extern void qe_init(uint qe_base);
extern void qe_reset(void);

static void config_qe_ioports(void)
{
	u8      port, pin;
	int     dir, open_drain, assign;
	int     i;

	for (i = 0; qe_iop_conf_tab[i].assign != QE_IOP_TAB_END; i++) {
		port		= qe_iop_conf_tab[i].port;
		pin		= qe_iop_conf_tab[i].pin;
		dir		= qe_iop_conf_tab[i].dir;
		open_drain	= qe_iop_conf_tab[i].open_drain;
		assign		= qe_iop_conf_tab[i].assign;
		qe_config_iopin(port, pin, dir, open_drain, assign);
	}
}
#endif

#ifdef CONFIG_CPM2
void config_8560_ioports (volatile ccsr_cpm_t * cpm)
{
	int portnum;

	for (portnum = 0; portnum < 4; portnum++) {
		uint pmsk = 0,
		     ppar = 0,
		     psor = 0,
		     pdir = 0,
		     podr = 0,
		     pdat = 0;
		iop_conf_t *iopc = (iop_conf_t *) & iop_conf_tab[portnum][0];
		iop_conf_t *eiopc = iopc + 32;
		uint msk = 1;

		/*
		 * NOTE:
		 * index 0 refers to pin 31,
		 * index 31 refers to pin 0
		 */
		while (iopc < eiopc) {
			if (iopc->conf) {
				pmsk |= msk;
				if (iopc->ppar)
					ppar |= msk;
				if (iopc->psor)
					psor |= msk;
				if (iopc->pdir)
					pdir |= msk;
				if (iopc->podr)
					podr |= msk;
				if (iopc->pdat)
					pdat |= msk;
			}

			msk <<= 1;
			iopc++;
		}

		if (pmsk != 0) {
			volatile ioport_t *iop = ioport_addr (cpm, portnum);
			uint tpmsk = ~pmsk;

			/*
			 * the (somewhat confused) paragraph at the
			 * bottom of page 35-5 warns that there might
			 * be "unknown behaviour" when programming
			 * PSORx and PDIRx, if PPARx = 1, so I
			 * decided this meant I had to disable the
			 * dedicated function first, and enable it
			 * last.
			 */
			iop->ppar &= tpmsk;
			iop->psor = (iop->psor & tpmsk) | psor;
			iop->podr = (iop->podr & tpmsk) | podr;
			iop->pdat = (iop->pdat & tpmsk) | pdat;
			iop->pdir = (iop->pdir & tpmsk) | pdir;
			iop->ppar |= ppar;
		}
	}
}
#endif

#ifdef CONFIG_SYS_FSL_CPC
static void enable_cpc(void)
{
	int i;
	u32 size = 0;

	cpc_corenet_t *cpc = (cpc_corenet_t *)CONFIG_SYS_FSL_CPC_ADDR;

	for (i = 0; i < CONFIG_SYS_NUM_CPC; i++, cpc++) {
		u32 cpccfg0 = in_be32(&cpc->cpccfg0);
		size += CPC_CFG0_SZ_K(cpccfg0);

		out_be32(&cpc->cpccsr0, CPC_CSR0_CE | CPC_CSR0_PE);
		/* Read back to sync write */
		in_be32(&cpc->cpccsr0);

	}

	printf("Corenet Platform Cache: %d KB enabled\n", size);
}

void invalidate_cpc(void)
{
	int i;
	cpc_corenet_t *cpc = (cpc_corenet_t *)CONFIG_SYS_FSL_CPC_ADDR;

	for (i = 0; i < CONFIG_SYS_NUM_CPC; i++, cpc++) {
		/* Flash invalidate the CPC and clear all the locks */
		out_be32(&cpc->cpccsr0, CPC_CSR0_FI | CPC_CSR0_LFC);
		while (in_be32(&cpc->cpccsr0) & (CPC_CSR0_FI | CPC_CSR0_LFC))
			;
	}
}
#else
#define enable_cpc()
#define invalidate_cpc()
#endif /* CONFIG_SYS_FSL_CPC */

/*
 * Breathe some life into the CPU...
 *
 * Set up the memory map
 * initialize a bunch of registers
 */

#ifdef CONFIG_FSL_CORENET
static void corenet_tb_init(void)
{
	volatile ccsr_rcpm_t *rcpm =
		(void *)(CONFIG_SYS_FSL_CORENET_RCPM_ADDR);
	volatile ccsr_pic_t *pic =
		(void *)(CONFIG_SYS_MPC8xxx_PIC_ADDR);
	u32 whoami = in_be32(&pic->whoami);

	/* Enable the timebase register for this core */
	out_be32(&rcpm->ctbenrl, (1 << whoami));
}
#endif

void cpu_init_f (void)
{
	extern void m8560_cpm_reset (void);
#ifdef CONFIG_MPC8548
	ccsr_local_ecm_t *ecm = (void *)(CONFIG_SYS_MPC85xx_ECM_ADDR);
	uint svr = get_svr();

	/*
	 * CPU2 errata workaround: A core hang possible while executing
	 * a msync instruction and a snoopable transaction from an I/O
	 * master tagged to make quick forward progress is present.
	 * Fixed in silicon rev 2.1.
	 */
	if ((SVR_MAJ(svr) == 1) || ((SVR_MAJ(svr) == 2 && SVR_MIN(svr) == 0x0)))
		out_be32(&ecm->eebpcr, in_be32(&ecm->eebpcr) | (1 << 16));
#endif

	disable_tlb(14);
	disable_tlb(15);

#ifdef CONFIG_CPM2
	config_8560_ioports((ccsr_cpm_t *)CONFIG_SYS_MPC85xx_CPM_ADDR);
#endif

       init_early_memctl_regs();

#if defined(CONFIG_CPM2)
	m8560_cpm_reset();
#endif
#ifdef CONFIG_QE
	/* Config QE ioports */
	config_qe_ioports();
#endif
#if defined(CONFIG_FSL_DMA)
	dma_init();
#endif
#ifdef CONFIG_FSL_CORENET
	corenet_tb_init();
#endif
	init_used_tlb_cams();

	/* Invalidate the CPC before DDR gets enabled */
	invalidate_cpc();
}

/* Implement a dummy function for those platforms w/o SERDES */
static void __fsl_serdes__init(void)
{
	return ;
}
__attribute__((weak, alias("__fsl_serdes__init"))) void fsl_serdes_init(void);

/*
 * Initialize L2 as cache.
 *
 * The newer 8548, etc, parts have twice as much cache, but
 * use the same bit-encoding as the older 8555, etc, parts.
 *
 */
int cpu_init_r(void)
{
#ifdef CONFIG_SYS_LBC_LCRR
	volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
#endif

#if defined(CONFIG_SYS_P4080_ERRATUM_CPU22)
	flush_dcache();
	mtspr(L1CSR2, (mfspr(L1CSR2) | L1CSR2_DCWS));
	sync();
#endif

	puts ("L2:    ");

#if defined(CONFIG_L2_CACHE)
	volatile ccsr_l2cache_t *l2cache = (void *)CONFIG_SYS_MPC85xx_L2_ADDR;
	volatile uint cache_ctl;
	uint svr, ver;
	uint l2srbar;
	u32 l2siz_field;

	svr = get_svr();
	ver = SVR_SOC_VER(svr);

	asm("msync;isync");
	cache_ctl = l2cache->l2ctl;

#if defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SYS_INIT_L2_ADDR)
	if (cache_ctl & MPC85xx_L2CTL_L2E) {
		/* Clear L2 SRAM memory-mapped base address */
		out_be32(&l2cache->l2srbar0, 0x0);
		out_be32(&l2cache->l2srbar1, 0x0);

		/* set MBECCDIS=0, SBECCDIS=0 */
		clrbits_be32(&l2cache->l2errdis,
				(MPC85xx_L2ERRDIS_MBECC |
				 MPC85xx_L2ERRDIS_SBECC));

		/* set L2E=0, L2SRAM=0 */
		clrbits_be32(&l2cache->l2ctl,
				(MPC85xx_L2CTL_L2E |
				 MPC85xx_L2CTL_L2SRAM_ENTIRE));
	}
#endif

	l2siz_field = (cache_ctl >> 28) & 0x3;

	switch (l2siz_field) {
	case 0x0:
		printf(" unknown size (0x%08x)\n", cache_ctl);
		return -1;
		break;
	case 0x1:
		if (ver == SVR_8540 || ver == SVR_8560   ||
		    ver == SVR_8541 || ver == SVR_8541_E ||
		    ver == SVR_8555 || ver == SVR_8555_E) {
			puts("128 KB ");
			/* set L2E=1, L2I=1, & L2BLKSZ=1 (128 Kbyte) */
			cache_ctl = 0xc4000000;
		} else {
			puts("256 KB ");
			cache_ctl = 0xc0000000; /* set L2E=1, L2I=1, & L2SRAM=0 */
		}
		break;
	case 0x2:
		if (ver == SVR_8540 || ver == SVR_8560   ||
		    ver == SVR_8541 || ver == SVR_8541_E ||
		    ver == SVR_8555 || ver == SVR_8555_E) {
			puts("256 KB ");
			/* set L2E=1, L2I=1, & L2BLKSZ=2 (256 Kbyte) */
			cache_ctl = 0xc8000000;
		} else {
			puts ("512 KB ");
			/* set L2E=1, L2I=1, & L2SRAM=0 */
			cache_ctl = 0xc0000000;
		}
		break;
	case 0x3:
		puts("1024 KB ");
		/* set L2E=1, L2I=1, & L2SRAM=0 */
		cache_ctl = 0xc0000000;
		break;
	}

	if (l2cache->l2ctl & MPC85xx_L2CTL_L2E) {
		puts("already enabled");
		l2srbar = l2cache->l2srbar0;
#if defined(CONFIG_SYS_INIT_L2_ADDR) && defined(CONFIG_SYS_FLASH_BASE)
		if (l2cache->l2ctl & MPC85xx_L2CTL_L2SRAM_ENTIRE
				&& l2srbar >= CONFIG_SYS_FLASH_BASE) {
			l2srbar = CONFIG_SYS_INIT_L2_ADDR;
			l2cache->l2srbar0 = l2srbar;
			printf("moving to 0x%08x", CONFIG_SYS_INIT_L2_ADDR);
		}
#endif /* CONFIG_SYS_INIT_L2_ADDR */
		puts("\n");
	} else {
		asm("msync;isync");
		l2cache->l2ctl = cache_ctl; /* invalidate & enable */
		asm("msync;isync");
		puts("enabled\n");
	}
#elif defined(CONFIG_BACKSIDE_L2_CACHE)
	u32 l2cfg0 = mfspr(SPRN_L2CFG0);

	/* invalidate the L2 cache */
	mtspr(SPRN_L2CSR0, (L2CSR0_L2FI|L2CSR0_L2LFC));
	while (mfspr(SPRN_L2CSR0) & (L2CSR0_L2FI|L2CSR0_L2LFC))
		;

#ifdef CONFIG_SYS_CACHE_STASHING
	/* set stash id to (coreID) * 2 + 32 + L2 (1) */
	mtspr(SPRN_L2CSR1, (32 + 1));
#endif

	/* enable the cache */
	mtspr(SPRN_L2CSR0, CONFIG_SYS_INIT_L2CSR0);

	if (CONFIG_SYS_INIT_L2CSR0 & L2CSR0_L2E) {
		while (!(mfspr(SPRN_L2CSR0) & L2CSR0_L2E))
			;
		printf("%d KB enabled\n", (l2cfg0 & 0x3fff) * 64);
	}
#else
	puts("disabled\n");
#endif

	enable_cpc();

#ifdef CONFIG_QE
	uint qe_base = CONFIG_SYS_IMMR + 0x00080000; /* QE immr base */
	qe_init(qe_base);
	qe_reset();
#endif

	/* needs to be in ram since code uses global static vars */
	fsl_serdes_init();

#if defined(CONFIG_MP)
	setup_mp();
#endif

#ifdef CONFIG_SYS_LBC_LCRR
	/*
	 * Modify the CLKDIV field of LCRR register to improve the writing
	 * speed for NOR flash.
	 */
	clrsetbits_be32(&lbc->lcrr, LCRR_CLKDIV, CONFIG_SYS_LBC_LCRR);
	__raw_readl(&lbc->lcrr);
	isync();
#endif

	return 0;
}

extern void setup_ivors(void);

void arch_preboot_os(void)
{
	u32 msr;

	/*
	 * We are changing interrupt offsets and are about to boot the OS so
	 * we need to make sure we disable all async interrupts. EE is already
	 * disabled by the time we get called.
	 */
	msr = mfmsr();
	msr &= ~(MSR_ME|MSR_CE|MSR_DE);
	mtmsr(msr);

	setup_ivors();
}

#if defined(CONFIG_CMD_SATA) && defined(CONFIG_FSL_SATA)
int sata_initialize(void)
{
	if (is_serdes_configured(SATA1) || is_serdes_configured(SATA2))
		return __sata_initialize();

	return 1;
}
#endif
Commit	Line	Data
42d1f039	1	/*
f54fe87a	2	* Copyright 2007-2010 Freescale Semiconductor, Inc.
29372ff3	3	*
42d1f039 WD	4	* (C) Copyright 2003 Motorola Inc.
	5	* Modified by Xianghua Xiao, X.Xiao@motorola.com
	6	*
	7	* (C) Copyright 2000
	8	* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
	9	*
	10	* See file CREDITS for list of people who contributed to this
	11	* project.
	12	*
	13	* This program is free software; you can redistribute it and/or
	14	* modify it under the terms of the GNU General Public License as
	15	* published by the Free Software Foundation; either version 2 of
	16	* the License, or (at your option) any later version.
	17	*
	18	* This program is distributed in the hope that it will be useful,
	19	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	20	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	21	* GNU General Public License for more details.
	22	*
	23	* You should have received a copy of the GNU General Public License
	24	* along with this program; if not, write to the Free Software
	25	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	26	* MA 02111-1307 USA
	27	*/
	28
	29	#include <common.h>
	30	#include <watchdog.h>
	31	#include <asm/processor.h>
	32	#include <ioports.h>
f54fe87a	33	#include <sata.h>
42d1f039	34	#include <asm/io.h>
fd3c9bef	35	#include <asm/cache.h>
87163180	36	#include <asm/mmu.h>
83d40dfd	37	#include <asm/fsl_law.h>
f54fe87a	38	#include <asm/fsl_serdes.h>
ec2b74ff	39	#include "mp.h"
42d1f039	40
d87080b7 WD	41	DECLARE_GLOBAL_DATA_PTR;
d87080b7 WD	42
da9d4610 AF	43	#ifdef CONFIG_QE
	44	extern qe_iop_conf_t qe_iop_conf_tab[];
	45	extern void qe_config_iopin(u8 port, u8 pin, int dir,
	46	int open_drain, int assign);
	47	extern void qe_init(uint qe_base);
	48	extern void qe_reset(void);
	49
	50	static void config_qe_ioports(void)
	51	{
	52	u8 port, pin;
	53	int dir, open_drain, assign;
	54	int i;
	55
	56	for (i = 0; qe_iop_conf_tab[i].assign != QE_IOP_TAB_END; i++) {
	57	port = qe_iop_conf_tab[i].port;
	58	pin = qe_iop_conf_tab[i].pin;
	59	dir = qe_iop_conf_tab[i].dir;
	60	open_drain = qe_iop_conf_tab[i].open_drain;
	61	assign = qe_iop_conf_tab[i].assign;
	62	qe_config_iopin(port, pin, dir, open_drain, assign);
	63	}
	64	}
	65	#endif
40d5fa35	66
9c4c5ae3	67	#ifdef CONFIG_CPM2
aafeefbd	68	void config_8560_ioports (volatile ccsr_cpm_t * cpm)
42d1f039 WD	69	{
	70	int portnum;
	71
	72	for (portnum = 0; portnum < 4; portnum++) {
	73	uint pmsk = 0,
	74	ppar = 0,
	75	psor = 0,
	76	pdir = 0,
	77	podr = 0,
	78	pdat = 0;
	79	iop_conf_t iopc = (iop_conf_t ) & iop_conf_tab[portnum][0];
	80	iop_conf_t *eiopc = iopc + 32;
	81	uint msk = 1;
	82
	83	/*
	84	* NOTE:
	85	* index 0 refers to pin 31,
	86	* index 31 refers to pin 0
	87	*/
	88	while (iopc < eiopc) {
	89	if (iopc->conf) {
	90	pmsk \|= msk;
	91	if (iopc->ppar)
	92	ppar \|= msk;
	93	if (iopc->psor)
	94	psor \|= msk;
	95	if (iopc->pdir)
	96	pdir \|= msk;
	97	if (iopc->podr)
	98	podr \|= msk;
	99	if (iopc->pdat)
	100	pdat \|= msk;
	101	}
	102
	103	msk <<= 1;
	104	iopc++;
	105	}
	106
	107	if (pmsk != 0) {
aafeefbd	108	volatile ioport_t *iop = ioport_addr (cpm, portnum);
42d1f039 WD	109	uint tpmsk = ~pmsk;
	110
	111	/*
	112	* the (somewhat confused) paragraph at the
	113	* bottom of page 35-5 warns that there might
	114	* be "unknown behaviour" when programming
	115	* PSORx and PDIRx, if PPARx = 1, so I
	116	* decided this meant I had to disable the
	117	* dedicated function first, and enable it
	118	* last.
	119	*/
	120	iop->ppar &= tpmsk;
	121	iop->psor = (iop->psor & tpmsk) \| psor;
	122	iop->podr = (iop->podr & tpmsk) \| podr;
	123	iop->pdat = (iop->pdat & tpmsk) \| pdat;
	124	iop->pdir = (iop->pdir & tpmsk) \| pdir;
	125	iop->ppar \|= ppar;
	126	}
	127	}
	128	}
	129	#endif
	130
6aba33e9 KG	131	#ifdef CONFIG_SYS_FSL_CPC
	132	static void enable_cpc(void)
	133	{
	134	int i;
	135	u32 size = 0;
	136
	137	cpc_corenet_t cpc = (cpc_corenet_t )CONFIG_SYS_FSL_CPC_ADDR;
	138
	139	for (i = 0; i < CONFIG_SYS_NUM_CPC; i++, cpc++) {
	140	u32 cpccfg0 = in_be32(&cpc->cpccfg0);
	141	size += CPC_CFG0_SZ_K(cpccfg0);
	142
	143	out_be32(&cpc->cpccsr0, CPC_CSR0_CE \| CPC_CSR0_PE);
	144	/* Read back to sync write */
	145	in_be32(&cpc->cpccsr0);
	146
	147	}
	148
	149	printf("Corenet Platform Cache: %d KB enabled\n", size);
	150	}
	151
	152	void invalidate_cpc(void)
	153	{
	154	int i;
	155	cpc_corenet_t cpc = (cpc_corenet_t )CONFIG_SYS_FSL_CPC_ADDR;
	156
	157	for (i = 0; i < CONFIG_SYS_NUM_CPC; i++, cpc++) {
	158	/* Flash invalidate the CPC and clear all the locks */
	159	out_be32(&cpc->cpccsr0, CPC_CSR0_FI \| CPC_CSR0_LFC);
	160	while (in_be32(&cpc->cpccsr0) & (CPC_CSR0_FI \| CPC_CSR0_LFC))
	161	;
	162	}
	163	}
	164	#else
	165	#define enable_cpc()
	166	#define invalidate_cpc()
	167	#endif /* CONFIG_SYS_FSL_CPC */
	168
42d1f039 WD	169	/*
	170	* Breathe some life into the CPU...
	171	*
	172	* Set up the memory map
	173	* initialize a bunch of registers
	174	*/
	175
3c2a67ee KG	176	#ifdef CONFIG_FSL_CORENET
	177	static void corenet_tb_init(void)
	178	{
	179	volatile ccsr_rcpm_t *rcpm =
	180	(void *)(CONFIG_SYS_FSL_CORENET_RCPM_ADDR);
	181	volatile ccsr_pic_t *pic =
680c613a	182	(void *)(CONFIG_SYS_MPC8xxx_PIC_ADDR);
3c2a67ee KG	183	u32 whoami = in_be32(&pic->whoami);
	184
	185	/* Enable the timebase register for this core */
	186	out_be32(&rcpm->ctbenrl, (1 << whoami));
	187	}
	188	#endif
	189
42d1f039 WD	190	void cpu_init_f (void)
42d1f039 WD	191	{
42d1f039	192	extern void m8560_cpm_reset (void);
a2cd50ed PT	193	#ifdef CONFIG_MPC8548
	194	ccsr_local_ecm_t ecm = (void )(CONFIG_SYS_MPC85xx_ECM_ADDR);
	195	uint svr = get_svr();
	196
	197	/*
	198	* CPU2 errata workaround: A core hang possible while executing
	199	* a msync instruction and a snoopable transaction from an I/O
	200	* master tagged to make quick forward progress is present.
	201	* Fixed in silicon rev 2.1.
	202	*/
	203	if ((SVR_MAJ(svr) == 1) \|\| ((SVR_MAJ(svr) == 2 && SVR_MIN(svr) == 0x0)))
	204	out_be32(&ecm->eebpcr, in_be32(&ecm->eebpcr) \| (1 << 16));
	205	#endif
42d1f039	206
87163180 KG	207	disable_tlb(14);
	208	disable_tlb(15);
	209
9c4c5ae3	210	#ifdef CONFIG_CPM2
6d0f6bcf	211	config_8560_ioports((ccsr_cpm_t *)CONFIG_SYS_MPC85xx_CPM_ADDR);
42d1f039 WD	212	#endif
42d1f039 WD	213
f51cdaf1	214	init_early_memctl_regs();
42d1f039	215
9c4c5ae3	216	#if defined(CONFIG_CPM2)
42d1f039 WD	217	m8560_cpm_reset();
42d1f039 WD	218	#endif
da9d4610 AF	219	#ifdef CONFIG_QE
	220	/* Config QE ioports */
	221	config_qe_ioports();
	222	#endif
79f4333c PT	223	#if defined(CONFIG_FSL_DMA)
	224	dma_init();
	225	#endif
3c2a67ee KG	226	#ifdef CONFIG_FSL_CORENET
	227	corenet_tb_init();
	228	#endif
94e9411b	229	init_used_tlb_cams();
6aba33e9 KG	230
	231	/* Invalidate the CPC before DDR gets enabled */
	232	invalidate_cpc();
42d1f039 WD	233	}
42d1f039 WD	234
35079aa9 KG	235	/* Implement a dummy function for those platforms w/o SERDES */
	236	static void __fsl_serdes__init(void)
	237	{
	238	return ;
	239	}
	240	__attribute__((weak, alias("__fsl_serdes__init"))) void fsl_serdes_init(void);
d9b94f28	241
42d1f039	242	/*
d9b94f28 JL	243	* Initialize L2 as cache.
	244	*
	245	* The newer 8548, etc, parts have twice as much cache, but
	246	* use the same bit-encoding as the older 8555, etc, parts.
	247	*
42d1f039	248	*/
d9b94f28	249	int cpu_init_r(void)
42d1f039	250	{
3f0202ed	251	#ifdef CONFIG_SYS_LBC_LCRR
f51cdaf1	252	volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
3f0202ed LC	253	#endif
3f0202ed LC	254
fd3c9bef KG	255	#if defined(CONFIG_SYS_P4080_ERRATUM_CPU22)
	256	flush_dcache();
	257	mtspr(L1CSR2, (mfspr(L1CSR2) \| L1CSR2_DCWS));
	258	sync();
	259	#endif
	260
6beecfbb WG	261	puts ("L2: ");
6beecfbb WG	262
42d1f039	263	#if defined(CONFIG_L2_CACHE)
6d0f6bcf	264	volatile ccsr_l2cache_t l2cache = (void )CONFIG_SYS_MPC85xx_L2_ADDR;
d9b94f28 JL	265	volatile uint cache_ctl;
d9b94f28 JL	266	uint svr, ver;
29372ff3	267	uint l2srbar;
73f15a06	268	u32 l2siz_field;
d9b94f28 JL	269
d9b94f28 JL	270	svr = get_svr();
f3e04bdc	271	ver = SVR_SOC_VER(svr);
42d1f039	272
d65cfe89	273	asm("msync;isync");
d9b94f28	274	cache_ctl = l2cache->l2ctl;
7da53351 MH	275
	276	#if defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SYS_INIT_L2_ADDR)
	277	if (cache_ctl & MPC85xx_L2CTL_L2E) {
	278	/* Clear L2 SRAM memory-mapped base address */
	279	out_be32(&l2cache->l2srbar0, 0x0);
	280	out_be32(&l2cache->l2srbar1, 0x0);
	281
	282	/* set MBECCDIS=0, SBECCDIS=0 */
	283	clrbits_be32(&l2cache->l2errdis,
	284	(MPC85xx_L2ERRDIS_MBECC \|
	285	MPC85xx_L2ERRDIS_SBECC));
	286
	287	/* set L2E=0, L2SRAM=0 */
	288	clrbits_be32(&l2cache->l2ctl,
	289	(MPC85xx_L2CTL_L2E \|
	290	MPC85xx_L2CTL_L2SRAM_ENTIRE));
	291	}
	292	#endif
	293
73f15a06	294	l2siz_field = (cache_ctl >> 28) & 0x3;
d9b94f28	295
73f15a06 KG	296	switch (l2siz_field) {
	297	case 0x0:
	298	printf(" unknown size (0x%08x)\n", cache_ctl);
	299	return -1;
	300	break;
	301	case 0x1:
	302	if (ver == SVR_8540 \|\| ver == SVR_8560 \|\|
	303	ver == SVR_8541 \|\| ver == SVR_8541_E \|\|
	304	ver == SVR_8555 \|\| ver == SVR_8555_E) {
	305	puts("128 KB ");
	306	/* set L2E=1, L2I=1, & L2BLKSZ=1 (128 Kbyte) */
	307	cache_ctl = 0xc4000000;
d9b94f28	308	} else {
73f15a06 KG	309	puts("256 KB ");
	310	cache_ctl = 0xc0000000; /* set L2E=1, L2I=1, & L2SRAM=0 */
	311	}
	312	break;
	313	case 0x2:
	314	if (ver == SVR_8540 \|\| ver == SVR_8560 \|\|
	315	ver == SVR_8541 \|\| ver == SVR_8541_E \|\|
	316	ver == SVR_8555 \|\| ver == SVR_8555_E) {
6beecfbb	317	puts("256 KB ");
29372ff3 ES	318	/* set L2E=1, L2I=1, & L2BLKSZ=2 (256 Kbyte) */
29372ff3 ES	319	cache_ctl = 0xc8000000;
73f15a06 KG	320	} else {
	321	puts ("512 KB ");
	322	/* set L2E=1, L2I=1, & L2SRAM=0 */
	323	cache_ctl = 0xc0000000;
d9b94f28	324	}
d65cfe89	325	break;
73f15a06 KG	326	case 0x3:
	327	puts("1024 KB ");
	328	/* set L2E=1, L2I=1, & L2SRAM=0 */
	329	cache_ctl = 0xc0000000;
29372ff3	330	break;
d65cfe89 JL	331	}
d65cfe89 JL	332
76b474e2	333	if (l2cache->l2ctl & MPC85xx_L2CTL_L2E) {
6beecfbb	334	puts("already enabled");
29372ff3	335	l2srbar = l2cache->l2srbar0;
888279b5	336	#if defined(CONFIG_SYS_INIT_L2_ADDR) && defined(CONFIG_SYS_FLASH_BASE)
76b474e2 MH	337	if (l2cache->l2ctl & MPC85xx_L2CTL_L2SRAM_ENTIRE
76b474e2 MH	338	&& l2srbar >= CONFIG_SYS_FLASH_BASE) {
6d0f6bcf	339	l2srbar = CONFIG_SYS_INIT_L2_ADDR;
29372ff3	340	l2cache->l2srbar0 = l2srbar;
6d0f6bcf	341	printf("moving to 0x%08x", CONFIG_SYS_INIT_L2_ADDR);
29372ff3	342	}
6d0f6bcf	343	#endif /* CONFIG_SYS_INIT_L2_ADDR */
29372ff3 ES	344	puts("\n");
	345	} else {
	346	asm("msync;isync");
	347	l2cache->l2ctl = cache_ctl; /* invalidate & enable */
	348	asm("msync;isync");
6beecfbb	349	puts("enabled\n");
29372ff3	350	}
1b3e4044 KG	351	#elif defined(CONFIG_BACKSIDE_L2_CACHE)
	352	u32 l2cfg0 = mfspr(SPRN_L2CFG0);
	353
	354	/* invalidate the L2 cache */
25bacf7a KG	355	mtspr(SPRN_L2CSR0, (L2CSR0_L2FI\|L2CSR0_L2LFC));
25bacf7a KG	356	while (mfspr(SPRN_L2CSR0) & (L2CSR0_L2FI\|L2CSR0_L2LFC))
1b3e4044 KG	357	;
1b3e4044 KG	358
82fd1f8d KG	359	#ifdef CONFIG_SYS_CACHE_STASHING
	360	/* set stash id to (coreID) * 2 + 32 + L2 (1) */
	361	mtspr(SPRN_L2CSR1, (32 + 1));
	362	#endif
	363
1b3e4044 KG	364	/* enable the cache */
	365	mtspr(SPRN_L2CSR0, CONFIG_SYS_INIT_L2CSR0);
	366
654ea1f3 DL	367	if (CONFIG_SYS_INIT_L2CSR0 & L2CSR0_L2E) {
	368	while (!(mfspr(SPRN_L2CSR0) & L2CSR0_L2E))
	369	;
1b3e4044	370	printf("%d KB enabled\n", (l2cfg0 & 0x3fff) * 64);
654ea1f3	371	}
42d1f039	372	#else
6beecfbb	373	puts("disabled\n");
42d1f039	374	#endif
6aba33e9 KG	375
	376	enable_cpc();
	377
da9d4610	378	#ifdef CONFIG_QE
6d0f6bcf	379	uint qe_base = CONFIG_SYS_IMMR + 0x00080000; /* QE immr base */
da9d4610 AF	380	qe_init(qe_base);
	381	qe_reset();
	382	#endif
42d1f039	383
af025065 KG	384	/* needs to be in ram since code uses global static vars */
af025065 KG	385	fsl_serdes_init();
af025065	386
ec2b74ff KG	387	#if defined(CONFIG_MP)
	388	setup_mp();
	389	#endif
3f0202ed LC	390
	391	#ifdef CONFIG_SYS_LBC_LCRR
	392	/*
	393	* Modify the CLKDIV field of LCRR register to improve the writing
	394	* speed for NOR flash.
	395	*/
	396	clrsetbits_be32(&lbc->lcrr, LCRR_CLKDIV, CONFIG_SYS_LBC_LCRR);
	397	__raw_readl(&lbc->lcrr);
	398	isync();
	399	#endif
	400
42d1f039 WD	401	return 0;
42d1f039 WD	402	}
26f4cdba KG	403
	404	extern void setup_ivors(void);
	405
	406	void arch_preboot_os(void)
	407	{
15fba327 KG	408	u32 msr;
	409
	410	/*
	411	* We are changing interrupt offsets and are about to boot the OS so
	412	* we need to make sure we disable all async interrupts. EE is already
	413	* disabled by the time we get called.
	414	*/
	415	msr = mfmsr();
	416	msr &= ~(MSR_ME\|MSR_CE\|MSR_DE);
	417	mtmsr(msr);
	418
26f4cdba KG	419	setup_ivors();
26f4cdba KG	420	}
f54fe87a KG	421
	422	#if defined(CONFIG_CMD_SATA) && defined(CONFIG_FSL_SATA)
	423	int sata_initialize(void)
	424	{
	425	if (is_serdes_configured(SATA1) \|\| is_serdes_configured(SATA2))
	426	return __sata_initialize();
	427
	428	return 1;
	429	}
	430	#endif