[people/ms/u-boot.git] / arch / powerpc / cpu / mpc85xx / speed.c

/*
 * Copyright 2004, 2007-2011 Freescale Semiconductor, Inc.
 *
 * (C) Copyright 2003 Motorola Inc.
 * Xianghua Xiao, (X.Xiao@motorola.com)
 *
 * (C) Copyright 2000
 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#include <common.h>
#include <ppc_asm.tmpl>
#include <linux/compiler.h>
#include <asm/processor.h>
#include <asm/io.h>

DECLARE_GLOBAL_DATA_PTR;


#ifndef CONFIG_SYS_FSL_NUM_CC_PLLS
#define CONFIG_SYS_FSL_NUM_CC_PLLS	6
#endif
/* --------------------------------------------------------------- */

void get_sys_info(sys_info_t *sys_info)
{
	volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
#ifdef CONFIG_FSL_IFC
	struct fsl_ifc *ifc_regs = (void *)CONFIG_SYS_IFC_ADDR;
	u32 ccr;
#endif
#ifdef CONFIG_FSL_CORENET
	volatile ccsr_clk_t *clk = (void *)(CONFIG_SYS_FSL_CORENET_CLK_ADDR);
	unsigned int cpu;
#ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2
	int cc_group[12] = CONFIG_SYS_FSL_CLUSTER_CLOCKS;
#endif

	const u8 core_cplx_PLL[16] = {
		[ 0] = 0,	/* CC1 PPL / 1 */
		[ 1] = 0,	/* CC1 PPL / 2 */
		[ 2] = 0,	/* CC1 PPL / 4 */
		[ 4] = 1,	/* CC2 PPL / 1 */
		[ 5] = 1,	/* CC2 PPL / 2 */
		[ 6] = 1,	/* CC2 PPL / 4 */
		[ 8] = 2,	/* CC3 PPL / 1 */
		[ 9] = 2,	/* CC3 PPL / 2 */
		[10] = 2,	/* CC3 PPL / 4 */
		[12] = 3,	/* CC4 PPL / 1 */
		[13] = 3,	/* CC4 PPL / 2 */
		[14] = 3,	/* CC4 PPL / 4 */
	};

	const u8 core_cplx_pll_div[16] = {
		[ 0] = 1,	/* CC1 PPL / 1 */
		[ 1] = 2,	/* CC1 PPL / 2 */
		[ 2] = 4,	/* CC1 PPL / 4 */
		[ 4] = 1,	/* CC2 PPL / 1 */
		[ 5] = 2,	/* CC2 PPL / 2 */
		[ 6] = 4,	/* CC2 PPL / 4 */
		[ 8] = 1,	/* CC3 PPL / 1 */
		[ 9] = 2,	/* CC3 PPL / 2 */
		[10] = 4,	/* CC3 PPL / 4 */
		[12] = 1,	/* CC4 PPL / 1 */
		[13] = 2,	/* CC4 PPL / 2 */
		[14] = 4,	/* CC4 PPL / 4 */
	};
	uint i, freq_c_pll[CONFIG_SYS_FSL_NUM_CC_PLLS];
#if !defined(CONFIG_FM_PLAT_CLK_DIV) || !defined(CONFIG_PME_PLAT_CLK_DIV)
	uint rcw_tmp;
#endif
	uint ratio[CONFIG_SYS_FSL_NUM_CC_PLLS];
	unsigned long sysclk = CONFIG_SYS_CLK_FREQ;
	uint mem_pll_rat;

	sys_info->freq_systembus = sysclk;
#ifdef CONFIG_DDR_CLK_FREQ
	sys_info->freq_ddrbus = CONFIG_DDR_CLK_FREQ;
#else
	sys_info->freq_ddrbus = sysclk;
#endif

	sys_info->freq_systembus *= (in_be32(&gur->rcwsr[0]) >> 25) & 0x1f;
	mem_pll_rat = (in_be32(&gur->rcwsr[0]) >>
			FSL_CORENET_RCWSR0_MEM_PLL_RAT_SHIFT)
			& FSL_CORENET_RCWSR0_MEM_PLL_RAT_MASK;
	/* T4240/T4160 Rev2.0 MEM_PLL_RAT uses a value which is half of
	 * T4240/T4160 Rev1.0. eg. It's 12 in Rev1.0, however, for Rev2.0
	 * it uses 6.
	 */
#if defined(CONFIG_PPC_T4240) || defined(CONFIG_PPC_T4160)
	if (SVR_MAJ(get_svr()) >= 2)
		mem_pll_rat *= 2;
#endif
	if (mem_pll_rat > 2)
		sys_info->freq_ddrbus *= mem_pll_rat;
	else
		sys_info->freq_ddrbus = sys_info->freq_systembus * mem_pll_rat;

	for (i = 0; i < CONFIG_SYS_FSL_NUM_CC_PLLS; i++) {
		ratio[i] = (in_be32(&clk->pllcgsr[i].pllcngsr) >> 1) & 0x3f;
		if (ratio[i] > 4)
			freq_c_pll[i] = sysclk * ratio[i];
		else
			freq_c_pll[i] = sys_info->freq_systembus * ratio[i];
	}
#ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2
	/*
	 * As per CHASSIS2 architeture total 12 clusters are posible and
	 * Each cluster has up to 4 cores, sharing the same PLL selection.
	 * The cluster clock assignment is SoC defined.
	 *
	 * Total 4 clock groups are possible with 3 PLLs each.
	 * as per array indices, clock group A has 0, 1, 2 numbered PLLs &
	 * clock group B has 3, 4, 6 and so on.
	 *
	 * Clock group A having PLL1, PLL2, PLL3, feeding cores of any cluster
	 * depends upon the SoC architeture. Same applies to other
	 * clock groups and clusters.
	 *
	 */
	for_each_cpu(i, cpu, cpu_numcores(), cpu_mask()) {
		int cluster = fsl_qoriq_core_to_cluster(cpu);
		u32 c_pll_sel = (in_be32(&clk->clkcsr[cluster].clkcncsr) >> 27)
				& 0xf;
		u32 cplx_pll = core_cplx_PLL[c_pll_sel];
		cplx_pll += cc_group[cluster] - 1;
		sys_info->freq_processor[cpu] =
			 freq_c_pll[cplx_pll] / core_cplx_pll_div[c_pll_sel];
	}
#if defined(CONFIG_PPC_B4860) || defined(CONFIG_PPC_T2080)
#define FM1_CLK_SEL	0xe0000000
#define FM1_CLK_SHIFT	29
#else
#define PME_CLK_SEL	0xe0000000
#define PME_CLK_SHIFT	29
#define FM1_CLK_SEL	0x1c000000
#define FM1_CLK_SHIFT	26
#endif
#if !defined(CONFIG_FM_PLAT_CLK_DIV) || !defined(CONFIG_PME_PLAT_CLK_DIV)
	rcw_tmp = in_be32(&gur->rcwsr[7]);
#endif

#ifdef CONFIG_SYS_DPAA_PME
#ifndef CONFIG_PME_PLAT_CLK_DIV
	switch ((rcw_tmp & PME_CLK_SEL) >> PME_CLK_SHIFT) {
	case 1:
		sys_info->freq_pme = freq_c_pll[CONFIG_SYS_PME_CLK];
		break;
	case 2:
		sys_info->freq_pme = freq_c_pll[CONFIG_SYS_PME_CLK] / 2;
		break;
	case 3:
		sys_info->freq_pme = freq_c_pll[CONFIG_SYS_PME_CLK] / 3;
		break;
	case 4:
		sys_info->freq_pme = freq_c_pll[CONFIG_SYS_PME_CLK] / 4;
		break;
	case 6:
		sys_info->freq_pme = freq_c_pll[CONFIG_SYS_PME_CLK + 1] / 2;
		break;
	case 7:
		sys_info->freq_pme = freq_c_pll[CONFIG_SYS_PME_CLK + 1] / 3;
		break;
	default:
		printf("Error: Unknown PME clock select!\n");
	case 0:
		sys_info->freq_pme = sys_info->freq_systembus / 2;
		break;

	}
#else
	sys_info->freq_pme = sys_info->freq_systembus / CONFIG_SYS_PME_CLK;

#endif
#endif

#ifdef CONFIG_SYS_DPAA_QBMAN
	sys_info->freq_qman = sys_info->freq_systembus / 2;
#endif

#ifdef CONFIG_SYS_DPAA_FMAN
#ifndef CONFIG_FM_PLAT_CLK_DIV
	switch ((rcw_tmp & FM1_CLK_SEL) >> FM1_CLK_SHIFT) {
	case 1:
		sys_info->freq_fman[0] = freq_c_pll[CONFIG_SYS_FM1_CLK];
		break;
	case 2:
		sys_info->freq_fman[0] = freq_c_pll[CONFIG_SYS_FM1_CLK] / 2;
		break;
	case 3:
		sys_info->freq_fman[0] = freq_c_pll[CONFIG_SYS_FM1_CLK] / 3;
		break;
	case 4:
		sys_info->freq_fman[0] = freq_c_pll[CONFIG_SYS_FM1_CLK] / 4;
		break;
	case 5:
		sys_info->freq_fman[0] = sys_info->freq_systembus;
		break;
	case 6:
		sys_info->freq_fman[0] = freq_c_pll[CONFIG_SYS_FM1_CLK + 1] / 2;
		break;
	case 7:
		sys_info->freq_fman[0] = freq_c_pll[CONFIG_SYS_FM1_CLK + 1] / 3;
		break;
	default:
		printf("Error: Unknown FMan1 clock select!\n");
	case 0:
		sys_info->freq_fman[0] = sys_info->freq_systembus / 2;
		break;
	}
#if (CONFIG_SYS_NUM_FMAN) == 2
#ifdef CONFIG_SYS_FM2_CLK
#define FM2_CLK_SEL	0x00000038
#define FM2_CLK_SHIFT	3
	rcw_tmp = in_be32(&gur->rcwsr[15]);
	switch ((rcw_tmp & FM2_CLK_SEL) >> FM2_CLK_SHIFT) {
	case 1:
		sys_info->freq_fman[1] = freq_c_pll[CONFIG_SYS_FM2_CLK + 1];
		break;
	case 2:
		sys_info->freq_fman[1] = freq_c_pll[CONFIG_SYS_FM2_CLK + 1] / 2;
		break;
	case 3:
		sys_info->freq_fman[1] = freq_c_pll[CONFIG_SYS_FM2_CLK + 1] / 3;
		break;
	case 4:
		sys_info->freq_fman[1] = freq_c_pll[CONFIG_SYS_FM2_CLK + 1] / 4;
		break;
	case 6:
		sys_info->freq_fman[1] = freq_c_pll[CONFIG_SYS_FM2_CLK] / 2;
		break;
	case 7:
		sys_info->freq_fman[1] = freq_c_pll[CONFIG_SYS_FM2_CLK] / 3;
		break;
	default:
		printf("Error: Unknown FMan2 clock select!\n");
	case 0:
		sys_info->freq_fman[1] = sys_info->freq_systembus / 2;
		break;
	}
#endif
#endif	/* CONFIG_SYS_NUM_FMAN == 2 */
#else
	sys_info->freq_fman[0] = sys_info->freq_systembus / CONFIG_SYS_FM1_CLK;
#endif
#endif

#else /* CONFIG_SYS_FSL_QORIQ_CHASSIS2 */

	for_each_cpu(i, cpu, cpu_numcores(), cpu_mask()) {
		u32 c_pll_sel = (in_be32(&clk->clkcsr[cpu].clkcncsr) >> 27)
				& 0xf;
		u32 cplx_pll = core_cplx_PLL[c_pll_sel];

		sys_info->freq_processor[cpu] =
			 freq_c_pll[cplx_pll] / core_cplx_pll_div[c_pll_sel];
	}
#define PME_CLK_SEL	0x80000000
#define FM1_CLK_SEL	0x40000000
#define FM2_CLK_SEL	0x20000000
#define HWA_ASYNC_DIV	0x04000000
#if (CONFIG_SYS_FSL_NUM_CC_PLLS == 2)
#define HWA_CC_PLL	1
#elif (CONFIG_SYS_FSL_NUM_CC_PLLS == 3)
#define HWA_CC_PLL	2
#elif (CONFIG_SYS_FSL_NUM_CC_PLLS == 4)
#define HWA_CC_PLL	2
#else
#error CONFIG_SYS_FSL_NUM_CC_PLLS not set or unknown case
#endif
	rcw_tmp = in_be32(&gur->rcwsr[7]);

#ifdef CONFIG_SYS_DPAA_PME
	if (rcw_tmp & PME_CLK_SEL) {
		if (rcw_tmp & HWA_ASYNC_DIV)
			sys_info->freq_pme = freq_c_pll[HWA_CC_PLL] / 4;
		else
			sys_info->freq_pme = freq_c_pll[HWA_CC_PLL] / 2;
	} else {
		sys_info->freq_pme = sys_info->freq_systembus / 2;
	}
#endif

#ifdef CONFIG_SYS_DPAA_FMAN
	if (rcw_tmp & FM1_CLK_SEL) {
		if (rcw_tmp & HWA_ASYNC_DIV)
			sys_info->freq_fman[0] = freq_c_pll[HWA_CC_PLL] / 4;
		else
			sys_info->freq_fman[0] = freq_c_pll[HWA_CC_PLL] / 2;
	} else {
		sys_info->freq_fman[0] = sys_info->freq_systembus / 2;
	}
#if (CONFIG_SYS_NUM_FMAN) == 2
	if (rcw_tmp & FM2_CLK_SEL) {
		if (rcw_tmp & HWA_ASYNC_DIV)
			sys_info->freq_fman[1] = freq_c_pll[HWA_CC_PLL] / 4;
		else
			sys_info->freq_fman[1] = freq_c_pll[HWA_CC_PLL] / 2;
	} else {
		sys_info->freq_fman[1] = sys_info->freq_systembus / 2;
	}
#endif
#endif

#ifdef CONFIG_SYS_DPAA_QBMAN
	sys_info->freq_qman = sys_info->freq_systembus / 2;
#endif

#endif /* CONFIG_SYS_FSL_QORIQ_CHASSIS2 */

#else /* CONFIG_FSL_CORENET */
	uint plat_ratio, e500_ratio, half_freq_systembus;
	int i;
#ifdef CONFIG_QE
	__maybe_unused u32 qe_ratio;
#endif

	plat_ratio = (gur->porpllsr) & 0x0000003e;
	plat_ratio >>= 1;
	sys_info->freq_systembus = plat_ratio * CONFIG_SYS_CLK_FREQ;

	/* Divide before multiply to avoid integer
	 * overflow for processor speeds above 2GHz */
	half_freq_systembus = sys_info->freq_systembus/2;
	for (i = 0; i < cpu_numcores(); i++) {
		e500_ratio = ((gur->porpllsr) >> (i * 8 + 16)) & 0x3f;
		sys_info->freq_processor[i] = e500_ratio * half_freq_systembus;
	}

	/* Note: freq_ddrbus is the MCLK frequency, not the data rate. */
	sys_info->freq_ddrbus = sys_info->freq_systembus;

#ifdef CONFIG_DDR_CLK_FREQ
	{
		u32 ddr_ratio = ((gur->porpllsr) & MPC85xx_PORPLLSR_DDR_RATIO)
			>> MPC85xx_PORPLLSR_DDR_RATIO_SHIFT;
		if (ddr_ratio != 0x7)
			sys_info->freq_ddrbus = ddr_ratio * CONFIG_DDR_CLK_FREQ;
	}
#endif

#ifdef CONFIG_QE
#if defined(CONFIG_P1012) || defined(CONFIG_P1021) || defined(CONFIG_P1025)
	sys_info->freq_qe =  sys_info->freq_systembus;
#else
	qe_ratio = ((gur->porpllsr) & MPC85xx_PORPLLSR_QE_RATIO)
			>> MPC85xx_PORPLLSR_QE_RATIO_SHIFT;
	sys_info->freq_qe = qe_ratio * CONFIG_SYS_CLK_FREQ;
#endif
#endif

#ifdef CONFIG_SYS_DPAA_FMAN
		sys_info->freq_fman[0] = sys_info->freq_systembus;
#endif

#endif /* CONFIG_FSL_CORENET */

#if defined(CONFIG_FSL_LBC)
	uint lcrr_div;
#if defined(CONFIG_SYS_LBC_LCRR)
	/* We will program LCRR to this value later */
	lcrr_div = CONFIG_SYS_LBC_LCRR & LCRR_CLKDIV;
#else
	lcrr_div = in_be32(&(LBC_BASE_ADDR)->lcrr) & LCRR_CLKDIV;
#endif
	if (lcrr_div == 2 || lcrr_div == 4 || lcrr_div == 8) {
#if defined(CONFIG_FSL_CORENET)
		/* If this is corenet based SoC, bit-representation
		 * for four times the clock divider values.
		 */
		lcrr_div *= 4;
#elif !defined(CONFIG_MPC8540) && !defined(CONFIG_MPC8541) && \
    !defined(CONFIG_MPC8555) && !defined(CONFIG_MPC8560)
		/*
		 * Yes, the entire PQ38 family use the same
		 * bit-representation for twice the clock divider values.
		 */
		lcrr_div *= 2;
#endif
		sys_info->freq_localbus = sys_info->freq_systembus / lcrr_div;
	} else {
		/* In case anyone cares what the unknown value is */
		sys_info->freq_localbus = lcrr_div;
	}
#endif

#if defined(CONFIG_FSL_IFC)
	ccr = in_be32(&ifc_regs->ifc_ccr);
	ccr = ((ccr & IFC_CCR_CLK_DIV_MASK) >> IFC_CCR_CLK_DIV_SHIFT) + 1;

	sys_info->freq_localbus = sys_info->freq_systembus / ccr;
#endif
}


int get_clocks (void)
{
	sys_info_t sys_info;
#ifdef CONFIG_MPC8544
	volatile ccsr_gur_t *gur = (void *) CONFIG_SYS_MPC85xx_GUTS_ADDR;
#endif
#if defined(CONFIG_CPM2)
	volatile ccsr_cpm_t *cpm = (ccsr_cpm_t *)CONFIG_SYS_MPC85xx_CPM_ADDR;
	uint sccr, dfbrg;

	/* set VCO = 4 * BRG */
	cpm->im_cpm_intctl.sccr &= 0xfffffffc;
	sccr = cpm->im_cpm_intctl.sccr;
	dfbrg = (sccr & SCCR_DFBRG_MSK) >> SCCR_DFBRG_SHIFT;
#endif
	get_sys_info (&sys_info);
	gd->cpu_clk = sys_info.freq_processor[0];
	gd->bus_clk = sys_info.freq_systembus;
	gd->mem_clk = sys_info.freq_ddrbus;
	gd->arch.lbc_clk = sys_info.freq_localbus;

#ifdef CONFIG_QE
	gd->arch.qe_clk = sys_info.freq_qe;
	gd->arch.brg_clk = gd->arch.qe_clk / 2;
#endif
	/*
	 * The base clock for I2C depends on the actual SOC.  Unfortunately,
	 * there is no pattern that can be used to determine the frequency, so
	 * the only choice is to look up the actual SOC number and use the value
	 * for that SOC. This information is taken from application note
	 * AN2919.
	 */
#if defined(CONFIG_MPC8540) || defined(CONFIG_MPC8541) || \
	defined(CONFIG_MPC8560) || defined(CONFIG_MPC8555) || \
	defined(CONFIG_P1022)
	gd->arch.i2c1_clk = sys_info.freq_systembus;
#elif defined(CONFIG_MPC8544)
	/*
	 * On the 8544, the I2C clock is the same as the SEC clock.  This can be
	 * either CCB/2 or CCB/3, depending on the value of cfg_sec_freq. See
	 * 4.4.3.3 of the 8544 RM.  Note that this might actually work for all
	 * 85xx, but only the 8544 has cfg_sec_freq, so it's unknown if the
	 * PORDEVSR2_SEC_CFG bit is 0 on all 85xx boards that are not an 8544.
	 */
	if (gur->pordevsr2 & MPC85xx_PORDEVSR2_SEC_CFG)
		gd->arch.i2c1_clk = sys_info.freq_systembus / 3;
	else
		gd->arch.i2c1_clk = sys_info.freq_systembus / 2;
#else
	/* Most 85xx SOCs use CCB/2, so this is the default behavior. */
	gd->arch.i2c1_clk = sys_info.freq_systembus / 2;
#endif
	gd->arch.i2c2_clk = gd->arch.i2c1_clk;

#if defined(CONFIG_FSL_ESDHC)
#if defined(CONFIG_MPC8569) || defined(CONFIG_P1010) ||\
       defined(CONFIG_P1014)
	gd->arch.sdhc_clk = gd->bus_clk;
#else
	gd->arch.sdhc_clk = gd->bus_clk / 2;
#endif
#endif /* defined(CONFIG_FSL_ESDHC) */

#if defined(CONFIG_CPM2)
	gd->arch.vco_out = 2*sys_info.freq_systembus;
	gd->arch.cpm_clk = gd->arch.vco_out / 2;
	gd->arch.scc_clk = gd->arch.vco_out / 4;
	gd->arch.brg_clk = gd->arch.vco_out / (1 << (2 * (dfbrg + 1)));
#endif

	if(gd->cpu_clk != 0) return (0);
	else return (1);
}


/********************************************
 * get_bus_freq
 * return system bus freq in Hz
 *********************************************/
ulong get_bus_freq (ulong dummy)
{
	return gd->bus_clk;
}

/********************************************
 * get_ddr_freq
 * return ddr bus freq in Hz
 *********************************************/
ulong get_ddr_freq (ulong dummy)
{
	return gd->mem_clk;
}
Commit	Line	Data
42d1f039	1	/*
beba93ed	2	* Copyright 2004, 2007-2011 Freescale Semiconductor, Inc.
39aaca1f	3	*
42d1f039 WD	4	* (C) Copyright 2003 Motorola Inc.
	5	* Xianghua Xiao, (X.Xiao@motorola.com)
	6	*
	7	* (C) Copyright 2000
	8	* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
	9	*
1a459660	10	* SPDX-License-Identifier: GPL-2.0+
42d1f039 WD	11	*/
	12
	13	#include <common.h>
	14	#include <ppc_asm.tmpl>
a52d2f81	15	#include <linux/compiler.h>
42d1f039	16	#include <asm/processor.h>
ada591d2	17	#include <asm/io.h>
42d1f039	18
d87080b7 WD	19	DECLARE_GLOBAL_DATA_PTR;
d87080b7 WD	20
ce746fe0 PK	21
	22	#ifndef CONFIG_SYS_FSL_NUM_CC_PLLS
	23	#define CONFIG_SYS_FSL_NUM_CC_PLLS 6
	24	#endif
42d1f039 WD	25	/* --------------------------------------------------------------- */
42d1f039 WD	26
997399fa	27	void get_sys_info(sys_info_t *sys_info)
42d1f039	28	{
6d0f6bcf	29	volatile ccsr_gur_t gur = (void )(CONFIG_SYS_MPC85xx_GUTS_ADDR);
800c73c4 KG	30	#ifdef CONFIG_FSL_IFC
	31	struct fsl_ifc ifc_regs = (void )CONFIG_SYS_IFC_ADDR;
	32	u32 ccr;
	33	#endif
39aaca1f KG	34	#ifdef CONFIG_FSL_CORENET
39aaca1f KG	35	volatile ccsr_clk_t clk = (void )(CONFIG_SYS_FSL_CORENET_CLK_ADDR);
fbb9ecf7	36	unsigned int cpu;
ce746fe0 PK	37	#ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2
	38	int cc_group[12] = CONFIG_SYS_FSL_CLUSTER_CLOCKS;
	39	#endif
39aaca1f KG	40
	41	const u8 core_cplx_PLL[16] = {
	42	[ 0] = 0, /* CC1 PPL / 1 */
	43	[ 1] = 0, /* CC1 PPL / 2 */
	44	[ 2] = 0, /* CC1 PPL / 4 */
	45	[ 4] = 1, /* CC2 PPL / 1 */
	46	[ 5] = 1, /* CC2 PPL / 2 */
	47	[ 6] = 1, /* CC2 PPL / 4 */
	48	[ 8] = 2, /* CC3 PPL / 1 */
	49	[ 9] = 2, /* CC3 PPL / 2 */
	50	[10] = 2, /* CC3 PPL / 4 */
	51	[12] = 3, /* CC4 PPL / 1 */
	52	[13] = 3, /* CC4 PPL / 2 */
	53	[14] = 3, /* CC4 PPL / 4 */
	54	};
	55
997399fa	56	const u8 core_cplx_pll_div[16] = {
39aaca1f KG	57	[ 0] = 1, /* CC1 PPL / 1 */
	58	[ 1] = 2, /* CC1 PPL / 2 */
	59	[ 2] = 4, /* CC1 PPL / 4 */
	60	[ 4] = 1, /* CC2 PPL / 1 */
	61	[ 5] = 2, /* CC2 PPL / 2 */
	62	[ 6] = 4, /* CC2 PPL / 4 */
	63	[ 8] = 1, /* CC3 PPL / 1 */
	64	[ 9] = 2, /* CC3 PPL / 2 */
	65	[10] = 4, /* CC3 PPL / 4 */
	66	[12] = 1, /* CC4 PPL / 1 */
	67	[13] = 2, /* CC4 PPL / 2 */
	68	[14] = 4, /* CC4 PPL / 4 */
	69	};
ce746fe0 PK	70	uint i, freq_c_pll[CONFIG_SYS_FSL_NUM_CC_PLLS];
	71	#if !defined(CONFIG_FM_PLAT_CLK_DIV) \|\| !defined(CONFIG_PME_PLAT_CLK_DIV)
	72	uint rcw_tmp;
	73	#endif
	74	uint ratio[CONFIG_SYS_FSL_NUM_CC_PLLS];
39aaca1f	75	unsigned long sysclk = CONFIG_SYS_CLK_FREQ;
ab48ca1a	76	uint mem_pll_rat;
39aaca1f	77
997399fa	78	sys_info->freq_systembus = sysclk;
98ffa190	79	#ifdef CONFIG_DDR_CLK_FREQ
997399fa	80	sys_info->freq_ddrbus = CONFIG_DDR_CLK_FREQ;
98ffa190	81	#else
997399fa	82	sys_info->freq_ddrbus = sysclk;
98ffa190	83	#endif
39aaca1f	84
997399fa	85	sys_info->freq_systembus *= (in_be32(&gur->rcwsr[0]) >> 25) & 0x1f;
f77329cf YS	86	mem_pll_rat = (in_be32(&gur->rcwsr[0]) >>
	87	FSL_CORENET_RCWSR0_MEM_PLL_RAT_SHIFT)
	88	& FSL_CORENET_RCWSR0_MEM_PLL_RAT_MASK;
e88f421e ZRR	89	/* T4240/T4160 Rev2.0 MEM_PLL_RAT uses a value which is half of
	90	* T4240/T4160 Rev1.0. eg. It's 12 in Rev1.0, however, for Rev2.0
	91	* it uses 6.
	92	*/
	93	#if defined(CONFIG_PPC_T4240) \|\| defined(CONFIG_PPC_T4160)
	94	if (SVR_MAJ(get_svr()) >= 2)
	95	mem_pll_rat *= 2;
	96	#endif
ab48ca1a	97	if (mem_pll_rat > 2)
997399fa	98	sys_info->freq_ddrbus *= mem_pll_rat;
ab48ca1a	99	else
997399fa	100	sys_info->freq_ddrbus = sys_info->freq_systembus * mem_pll_rat;
39aaca1f	101
ce746fe0 PK	102	for (i = 0; i < CONFIG_SYS_FSL_NUM_CC_PLLS; i++) {
ce746fe0 PK	103	ratio[i] = (in_be32(&clk->pllcgsr[i].pllcngsr) >> 1) & 0x3f;
ab48ca1a	104	if (ratio[i] > 4)
ce746fe0	105	freq_c_pll[i] = sysclk * ratio[i];
ab48ca1a	106	else
ce746fe0	107	freq_c_pll[i] = sys_info->freq_systembus * ratio[i];
ab48ca1a	108	}
9a653a98 YS	109	#ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2
9a653a98 YS	110	/*
ce746fe0	111	* As per CHASSIS2 architeture total 12 clusters are posible and
9a653a98	112	* Each cluster has up to 4 cores, sharing the same PLL selection.
ce746fe0 PK	113	* The cluster clock assignment is SoC defined.
	114	*
	115	* Total 4 clock groups are possible with 3 PLLs each.
	116	* as per array indices, clock group A has 0, 1, 2 numbered PLLs &
	117	* clock group B has 3, 4, 6 and so on.
	118	*
	119	* Clock group A having PLL1, PLL2, PLL3, feeding cores of any cluster
	120	* depends upon the SoC architeture. Same applies to other
	121	* clock groups and clusters.
	122	*
9a653a98	123	*/
fbb9ecf7	124	for_each_cpu(i, cpu, cpu_numcores(), cpu_mask()) {
f6981439 YS	125	int cluster = fsl_qoriq_core_to_cluster(cpu);
f6981439 YS	126	u32 c_pll_sel = (in_be32(&clk->clkcsr[cluster].clkcncsr) >> 27)
9a653a98	127	& 0xf;
39aaca1f	128	u32 cplx_pll = core_cplx_PLL[c_pll_sel];
ce746fe0	129	cplx_pll += cc_group[cluster] - 1;
997399fa	130	sys_info->freq_processor[cpu] =
ce746fe0	131	freq_c_pll[cplx_pll] / core_cplx_pll_div[c_pll_sel];
39aaca1f	132	}
629d6b32	133	#if defined(CONFIG_PPC_B4860) \|\| defined(CONFIG_PPC_T2080)
0cb3325c SS	134	#define FM1_CLK_SEL 0xe0000000
	135	#define FM1_CLK_SHIFT 29
	136	#else
9a653a98 YS	137	#define PME_CLK_SEL 0xe0000000
	138	#define PME_CLK_SHIFT 29
	139	#define FM1_CLK_SEL 0x1c000000
	140	#define FM1_CLK_SHIFT 26
0cb3325c	141	#endif
ce746fe0	142	#if !defined(CONFIG_FM_PLAT_CLK_DIV) \|\| !defined(CONFIG_PME_PLAT_CLK_DIV)
9a653a98	143	rcw_tmp = in_be32(&gur->rcwsr[7]);
ce746fe0	144	#endif
9a653a98 YS	145
9a653a98 YS	146	#ifdef CONFIG_SYS_DPAA_PME
ce746fe0	147	#ifndef CONFIG_PME_PLAT_CLK_DIV
9a653a98 YS	148	switch ((rcw_tmp & PME_CLK_SEL) >> PME_CLK_SHIFT) {
9a653a98 YS	149	case 1:
ce746fe0	150	sys_info->freq_pme = freq_c_pll[CONFIG_SYS_PME_CLK];
9a653a98 YS	151	break;
9a653a98 YS	152	case 2:
ce746fe0	153	sys_info->freq_pme = freq_c_pll[CONFIG_SYS_PME_CLK] / 2;
9a653a98 YS	154	break;
9a653a98 YS	155	case 3:
ce746fe0	156	sys_info->freq_pme = freq_c_pll[CONFIG_SYS_PME_CLK] / 3;
9a653a98 YS	157	break;
9a653a98 YS	158	case 4:
ce746fe0	159	sys_info->freq_pme = freq_c_pll[CONFIG_SYS_PME_CLK] / 4;
9a653a98 YS	160	break;
9a653a98 YS	161	case 6:
ce746fe0	162	sys_info->freq_pme = freq_c_pll[CONFIG_SYS_PME_CLK + 1] / 2;
9a653a98 YS	163	break;
9a653a98 YS	164	case 7:
ce746fe0	165	sys_info->freq_pme = freq_c_pll[CONFIG_SYS_PME_CLK + 1] / 3;
9a653a98 YS	166	break;
	167	default:
	168	printf("Error: Unknown PME clock select!\n");
	169	case 0:
997399fa	170	sys_info->freq_pme = sys_info->freq_systembus / 2;
9a653a98 YS	171	break;
	172
	173	}
ce746fe0 PK	174	#else
	175	sys_info->freq_pme = sys_info->freq_systembus / CONFIG_SYS_PME_CLK;
	176
	177	#endif
9a653a98 YS	178	#endif
9a653a98 YS	179
990e1a8c	180	#ifdef CONFIG_SYS_DPAA_QBMAN
997399fa	181	sys_info->freq_qman = sys_info->freq_systembus / 2;
990e1a8c HW	182	#endif
990e1a8c HW	183
9a653a98	184	#ifdef CONFIG_SYS_DPAA_FMAN
ce746fe0	185	#ifndef CONFIG_FM_PLAT_CLK_DIV
9a653a98 YS	186	switch ((rcw_tmp & FM1_CLK_SEL) >> FM1_CLK_SHIFT) {
9a653a98 YS	187	case 1:
ce746fe0	188	sys_info->freq_fman[0] = freq_c_pll[CONFIG_SYS_FM1_CLK];
9a653a98 YS	189	break;
9a653a98 YS	190	case 2:
ce746fe0	191	sys_info->freq_fman[0] = freq_c_pll[CONFIG_SYS_FM1_CLK] / 2;
9a653a98 YS	192	break;
9a653a98 YS	193	case 3:
ce746fe0	194	sys_info->freq_fman[0] = freq_c_pll[CONFIG_SYS_FM1_CLK] / 3;
9a653a98 YS	195	break;
9a653a98 YS	196	case 4:
ce746fe0	197	sys_info->freq_fman[0] = freq_c_pll[CONFIG_SYS_FM1_CLK] / 4;
9a653a98	198	break;
0cb3325c	199	case 5:
997399fa	200	sys_info->freq_fman[0] = sys_info->freq_systembus;
0cb3325c	201	break;
9a653a98	202	case 6:
ce746fe0	203	sys_info->freq_fman[0] = freq_c_pll[CONFIG_SYS_FM1_CLK + 1] / 2;
9a653a98 YS	204	break;
9a653a98 YS	205	case 7:
ce746fe0	206	sys_info->freq_fman[0] = freq_c_pll[CONFIG_SYS_FM1_CLK + 1] / 3;
9a653a98 YS	207	break;
	208	default:
	209	printf("Error: Unknown FMan1 clock select!\n");
	210	case 0:
997399fa	211	sys_info->freq_fman[0] = sys_info->freq_systembus / 2;
9a653a98 YS	212	break;
	213	}
	214	#if (CONFIG_SYS_NUM_FMAN) == 2
ce746fe0	215	#ifdef CONFIG_SYS_FM2_CLK
9a653a98 YS	216	#define FM2_CLK_SEL 0x00000038
	217	#define FM2_CLK_SHIFT 3
	218	rcw_tmp = in_be32(&gur->rcwsr[15]);
	219	switch ((rcw_tmp & FM2_CLK_SEL) >> FM2_CLK_SHIFT) {
	220	case 1:
ce746fe0	221	sys_info->freq_fman[1] = freq_c_pll[CONFIG_SYS_FM2_CLK + 1];
9a653a98 YS	222	break;
9a653a98 YS	223	case 2:
ce746fe0	224	sys_info->freq_fman[1] = freq_c_pll[CONFIG_SYS_FM2_CLK + 1] / 2;
9a653a98 YS	225	break;
9a653a98 YS	226	case 3:
ce746fe0	227	sys_info->freq_fman[1] = freq_c_pll[CONFIG_SYS_FM2_CLK + 1] / 3;
9a653a98 YS	228	break;
9a653a98 YS	229	case 4:
ce746fe0	230	sys_info->freq_fman[1] = freq_c_pll[CONFIG_SYS_FM2_CLK + 1] / 4;
9a653a98 YS	231	break;
9a653a98 YS	232	case 6:
ce746fe0	233	sys_info->freq_fman[1] = freq_c_pll[CONFIG_SYS_FM2_CLK] / 2;
9a653a98 YS	234	break;
9a653a98 YS	235	case 7:
ce746fe0	236	sys_info->freq_fman[1] = freq_c_pll[CONFIG_SYS_FM2_CLK] / 3;
9a653a98 YS	237	break;
	238	default:
	239	printf("Error: Unknown FMan2 clock select!\n");
	240	case 0:
997399fa	241	sys_info->freq_fman[1] = sys_info->freq_systembus / 2;
9a653a98 YS	242	break;
9a653a98 YS	243	}
ce746fe0	244	#endif
9a653a98	245	#endif /* CONFIG_SYS_NUM_FMAN == 2 */
ce746fe0 PK	246	#else
	247	sys_info->freq_fman[0] = sys_info->freq_systembus / CONFIG_SYS_FM1_CLK;
	248	#endif
	249	#endif
39aaca1f	250
9a653a98 YS	251	#else /* CONFIG_SYS_FSL_QORIQ_CHASSIS2 */
	252
	253	for_each_cpu(i, cpu, cpu_numcores(), cpu_mask()) {
f6981439 YS	254	u32 c_pll_sel = (in_be32(&clk->clkcsr[cpu].clkcncsr) >> 27)
f6981439 YS	255	& 0xf;
9a653a98 YS	256	u32 cplx_pll = core_cplx_PLL[c_pll_sel];
9a653a98 YS	257
997399fa	258	sys_info->freq_processor[cpu] =
ce746fe0	259	freq_c_pll[cplx_pll] / core_cplx_pll_div[c_pll_sel];
9a653a98	260	}
39aaca1f KG	261	#define PME_CLK_SEL 0x80000000
	262	#define FM1_CLK_SEL 0x40000000
	263	#define FM2_CLK_SEL 0x20000000
b5c8753f KG	264	#define HWA_ASYNC_DIV 0x04000000
	265	#if (CONFIG_SYS_FSL_NUM_CC_PLLS == 2)
	266	#define HWA_CC_PLL 1
4905443f TT	267	#elif (CONFIG_SYS_FSL_NUM_CC_PLLS == 3)
4905443f TT	268	#define HWA_CC_PLL 2
b5c8753f	269	#elif (CONFIG_SYS_FSL_NUM_CC_PLLS == 4)
cd6881b5	270	#define HWA_CC_PLL 2
b5c8753f KG	271	#else
	272	#error CONFIG_SYS_FSL_NUM_CC_PLLS not set or unknown case
	273	#endif
39aaca1f KG	274	rcw_tmp = in_be32(&gur->rcwsr[7]);
	275
	276	#ifdef CONFIG_SYS_DPAA_PME
b5c8753f KG	277	if (rcw_tmp & PME_CLK_SEL) {
b5c8753f KG	278	if (rcw_tmp & HWA_ASYNC_DIV)
ce746fe0	279	sys_info->freq_pme = freq_c_pll[HWA_CC_PLL] / 4;
b5c8753f	280	else
ce746fe0	281	sys_info->freq_pme = freq_c_pll[HWA_CC_PLL] / 2;
b5c8753f	282	} else {
997399fa	283	sys_info->freq_pme = sys_info->freq_systembus / 2;
b5c8753f	284	}
39aaca1f KG	285	#endif
	286
	287	#ifdef CONFIG_SYS_DPAA_FMAN
b5c8753f KG	288	if (rcw_tmp & FM1_CLK_SEL) {
b5c8753f KG	289	if (rcw_tmp & HWA_ASYNC_DIV)
ce746fe0	290	sys_info->freq_fman[0] = freq_c_pll[HWA_CC_PLL] / 4;
b5c8753f	291	else
ce746fe0	292	sys_info->freq_fman[0] = freq_c_pll[HWA_CC_PLL] / 2;
b5c8753f	293	} else {
997399fa	294	sys_info->freq_fman[0] = sys_info->freq_systembus / 2;
b5c8753f	295	}
39aaca1f	296	#if (CONFIG_SYS_NUM_FMAN) == 2
b5c8753f KG	297	if (rcw_tmp & FM2_CLK_SEL) {
b5c8753f KG	298	if (rcw_tmp & HWA_ASYNC_DIV)
ce746fe0	299	sys_info->freq_fman[1] = freq_c_pll[HWA_CC_PLL] / 4;
b5c8753f	300	else
ce746fe0	301	sys_info->freq_fman[1] = freq_c_pll[HWA_CC_PLL] / 2;
b5c8753f	302	} else {
997399fa	303	sys_info->freq_fman[1] = sys_info->freq_systembus / 2;
b5c8753f	304	}
39aaca1f KG	305	#endif
	306	#endif
	307
3e83fc9b	308	#ifdef CONFIG_SYS_DPAA_QBMAN
997399fa	309	sys_info->freq_qman = sys_info->freq_systembus / 2;
3e83fc9b SX	310	#endif
3e83fc9b SX	311
9a653a98 YS	312	#endif /* CONFIG_SYS_FSL_QORIQ_CHASSIS2 */
	313
	314	#else /* CONFIG_FSL_CORENET */
997399fa	315	uint plat_ratio, e500_ratio, half_freq_systembus;
2fc7eb0c	316	int i;
b3d7f20f	317	#ifdef CONFIG_QE
a52d2f81	318	__maybe_unused u32 qe_ratio;
b3d7f20f	319	#endif
42d1f039 WD	320
	321	plat_ratio = (gur->porpllsr) & 0x0000003e;
	322	plat_ratio >>= 1;
997399fa	323	sys_info->freq_systembus = plat_ratio * CONFIG_SYS_CLK_FREQ;
66ed6cca AF	324
	325	/* Divide before multiply to avoid integer
	326	* overflow for processor speeds above 2GHz */
997399fa	327	half_freq_systembus = sys_info->freq_systembus/2;
0e870980	328	for (i = 0; i < cpu_numcores(); i++) {
2fc7eb0c	329	e500_ratio = ((gur->porpllsr) >> (i * 8 + 16)) & 0x3f;
997399fa	330	sys_info->freq_processor[i] = e500_ratio * half_freq_systembus;
2fc7eb0c	331	}
a3e77fa5	332
997399fa PK	333	/* Note: freq_ddrbus is the MCLK frequency, not the data rate. */
997399fa PK	334	sys_info->freq_ddrbus = sys_info->freq_systembus;
d4357932 KG	335
	336	#ifdef CONFIG_DDR_CLK_FREQ
	337	{
c0391111 JJ	338	u32 ddr_ratio = ((gur->porpllsr) & MPC85xx_PORPLLSR_DDR_RATIO)
c0391111 JJ	339	>> MPC85xx_PORPLLSR_DDR_RATIO_SHIFT;
d4357932	340	if (ddr_ratio != 0x7)
997399fa	341	sys_info->freq_ddrbus = ddr_ratio * CONFIG_DDR_CLK_FREQ;
d4357932 KG	342	}
d4357932 KG	343	#endif
ada591d2	344
b3d7f20f	345	#ifdef CONFIG_QE
be7bebea	346	#if defined(CONFIG_P1012) \|\| defined(CONFIG_P1021) \|\| defined(CONFIG_P1025)
997399fa	347	sys_info->freq_qe = sys_info->freq_systembus;
a52d2f81	348	#else
b3d7f20f HW	349	qe_ratio = ((gur->porpllsr) & MPC85xx_PORPLLSR_QE_RATIO)
b3d7f20f HW	350	>> MPC85xx_PORPLLSR_QE_RATIO_SHIFT;
997399fa	351	sys_info->freq_qe = qe_ratio * CONFIG_SYS_CLK_FREQ;
b3d7f20f	352	#endif
a52d2f81	353	#endif
b3d7f20f	354
24995d82	355	#ifdef CONFIG_SYS_DPAA_FMAN
997399fa	356	sys_info->freq_fman[0] = sys_info->freq_systembus;
24995d82 HW	357	#endif
	358
	359	#endif /* CONFIG_FSL_CORENET */
	360
beba93ed	361	#if defined(CONFIG_FSL_LBC)
9a653a98	362	uint lcrr_div;
ada591d2 TP	363	#if defined(CONFIG_SYS_LBC_LCRR)
	364	/* We will program LCRR to this value later */
	365	lcrr_div = CONFIG_SYS_LBC_LCRR & LCRR_CLKDIV;
	366	#else
f51cdaf1	367	lcrr_div = in_be32(&(LBC_BASE_ADDR)->lcrr) & LCRR_CLKDIV;
ada591d2 TP	368	#endif
ada591d2 TP	369	if (lcrr_div == 2 \|\| lcrr_div == 4 \|\| lcrr_div == 8) {
0fd2fa6c DL	370	#if defined(CONFIG_FSL_CORENET)
	371	/* If this is corenet based SoC, bit-representation
	372	* for four times the clock divider values.
	373	*/
	374	lcrr_div *= 4;
	375	#elif !defined(CONFIG_MPC8540) && !defined(CONFIG_MPC8541) && \
ada591d2 TP	376	!defined(CONFIG_MPC8555) && !defined(CONFIG_MPC8560)
	377	/*
	378	* Yes, the entire PQ38 family use the same
	379	* bit-representation for twice the clock divider values.
	380	*/
	381	lcrr_div *= 2;
	382	#endif
997399fa	383	sys_info->freq_localbus = sys_info->freq_systembus / lcrr_div;
ada591d2 TP	384	} else {
ada591d2 TP	385	/* In case anyone cares what the unknown value is */
997399fa	386	sys_info->freq_localbus = lcrr_div;
ada591d2	387	}
beba93ed	388	#endif
800c73c4 KG	389
	390	#if defined(CONFIG_FSL_IFC)
	391	ccr = in_be32(&ifc_regs->ifc_ccr);
	392	ccr = ((ccr & IFC_CCR_CLK_DIV_MASK) >> IFC_CCR_CLK_DIV_SHIFT) + 1;
	393
997399fa	394	sys_info->freq_localbus = sys_info->freq_systembus / ccr;
800c73c4	395	#endif
42d1f039 WD	396	}
42d1f039 WD	397
66ed6cca	398
42d1f039 WD	399	int get_clocks (void)
42d1f039 WD	400	{
42d1f039	401	sys_info_t sys_info;
88353a98	402	#ifdef CONFIG_MPC8544
6d0f6bcf	403	volatile ccsr_gur_t gur = (void ) CONFIG_SYS_MPC85xx_GUTS_ADDR;
88353a98	404	#endif
9c4c5ae3	405	#if defined(CONFIG_CPM2)
6d0f6bcf	406	volatile ccsr_cpm_t cpm = (ccsr_cpm_t )CONFIG_SYS_MPC85xx_CPM_ADDR;
42d1f039 WD	407	uint sccr, dfbrg;
	408
	409	/* set VCO = 4 * BRG */
aafeefbd KG	410	cpm->im_cpm_intctl.sccr &= 0xfffffffc;
aafeefbd KG	411	sccr = cpm->im_cpm_intctl.sccr;
42d1f039 WD	412	dfbrg = (sccr & SCCR_DFBRG_MSK) >> SCCR_DFBRG_SHIFT;
	413	#endif
	414	get_sys_info (&sys_info);
997399fa PK	415	gd->cpu_clk = sys_info.freq_processor[0];
	416	gd->bus_clk = sys_info.freq_systembus;
	417	gd->mem_clk = sys_info.freq_ddrbus;
	418	gd->arch.lbc_clk = sys_info.freq_localbus;
88353a98	419
b3d7f20f	420	#ifdef CONFIG_QE
997399fa	421	gd->arch.qe_clk = sys_info.freq_qe;
45bae2e3	422	gd->arch.brg_clk = gd->arch.qe_clk / 2;
b3d7f20f	423	#endif
88353a98 TT	424	/*
	425	* The base clock for I2C depends on the actual SOC. Unfortunately,
	426	* there is no pattern that can be used to determine the frequency, so
	427	* the only choice is to look up the actual SOC number and use the value
	428	* for that SOC. This information is taken from application note
	429	* AN2919.
	430	*/
	431	#if defined(CONFIG_MPC8540) \|\| defined(CONFIG_MPC8541) \|\| \
f62b1238 TY	432	defined(CONFIG_MPC8560) \|\| defined(CONFIG_MPC8555) \|\| \
f62b1238 TY	433	defined(CONFIG_P1022)
997399fa	434	gd->arch.i2c1_clk = sys_info.freq_systembus;
88353a98 TT	435	#elif defined(CONFIG_MPC8544)
	436	/*
	437	* On the 8544, the I2C clock is the same as the SEC clock. This can be
	438	* either CCB/2 or CCB/3, depending on the value of cfg_sec_freq. See
	439	* 4.4.3.3 of the 8544 RM. Note that this might actually work for all
	440	* 85xx, but only the 8544 has cfg_sec_freq, so it's unknown if the
	441	* PORDEVSR2_SEC_CFG bit is 0 on all 85xx boards that are not an 8544.
	442	*/
	443	if (gur->pordevsr2 & MPC85xx_PORDEVSR2_SEC_CFG)
997399fa	444	gd->arch.i2c1_clk = sys_info.freq_systembus / 3;
42653b82	445	else
997399fa	446	gd->arch.i2c1_clk = sys_info.freq_systembus / 2;
88353a98 TT	447	#else
88353a98 TT	448	/* Most 85xx SOCs use CCB/2, so this is the default behavior. */
997399fa	449	gd->arch.i2c1_clk = sys_info.freq_systembus / 2;
88353a98	450	#endif
609e6ec3	451	gd->arch.i2c2_clk = gd->arch.i2c1_clk;
943afa22	452
6b9ea08c	453	#if defined(CONFIG_FSL_ESDHC)
7d640e9b PJ	454	#if defined(CONFIG_MPC8569) \|\| defined(CONFIG_P1010) \|\|\
7d640e9b PJ	455	defined(CONFIG_P1014)
e9adeca3	456	gd->arch.sdhc_clk = gd->bus_clk;
7f52ed5e	457	#else
e9adeca3	458	gd->arch.sdhc_clk = gd->bus_clk / 2;
ef50d6c0	459	#endif
7f52ed5e	460	#endif /* defined(CONFIG_FSL_ESDHC) */
ef50d6c0	461
9c4c5ae3	462	#if defined(CONFIG_CPM2)
997399fa	463	gd->arch.vco_out = 2*sys_info.freq_systembus;
748cd059 SG	464	gd->arch.cpm_clk = gd->arch.vco_out / 2;
	465	gd->arch.scc_clk = gd->arch.vco_out / 4;
	466	gd->arch.brg_clk = gd->arch.vco_out / (1 << (2 * (dfbrg + 1)));
42d1f039 WD	467	#endif
	468
	469	if(gd->cpu_clk != 0) return (0);
	470	else return (1);
	471	}
	472
	473
	474	/********************************************
	475	* get_bus_freq
	476	* return system bus freq in Hz
	477	*********************************************/
	478	ulong get_bus_freq (ulong dummy)
	479	{
a3e77fa5	480	return gd->bus_clk;
42d1f039	481	}
d4357932 KG	482
	483	/********************************************
	484	* get_ddr_freq
	485	* return ddr bus freq in Hz
	486	*********************************************/
	487	ulong get_ddr_freq (ulong dummy)
	488	{
a3e77fa5	489	return gd->mem_clk;
d4357932	490	}