[people/ms/u-boot.git] / arch / powerpc / cpu / mpc85xx / speed.c

/*
 * Copyright 2004, 2007-2011 Freescale Semiconductor, Inc.
 *
 * (C) Copyright 2003 Motorola Inc.
 * Xianghua Xiao, (X.Xiao@motorola.com)
 *
 * (C) Copyright 2000
 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#include <common.h>
#include <ppc_asm.tmpl>
#include <linux/compiler.h>
#include <asm/processor.h>
#include <asm/io.h>

DECLARE_GLOBAL_DATA_PTR;


#ifndef CONFIG_SYS_FSL_NUM_CC_PLLS
#define CONFIG_SYS_FSL_NUM_CC_PLLS	6
#endif
/* --------------------------------------------------------------- */

void get_sys_info(sys_info_t *sys_info)
{
	volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
#ifdef CONFIG_FSL_IFC
	struct fsl_ifc *ifc_regs = (void *)CONFIG_SYS_IFC_ADDR;
	u32 ccr;
#endif
#ifdef CONFIG_FSL_CORENET
	volatile ccsr_clk_t *clk = (void *)(CONFIG_SYS_FSL_CORENET_CLK_ADDR);
	unsigned int cpu;
#ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2
	int cc_group[12] = CONFIG_SYS_FSL_CLUSTER_CLOCKS;
#endif

	const u8 core_cplx_PLL[16] = {
		[ 0] = 0,	/* CC1 PPL / 1 */
		[ 1] = 0,	/* CC1 PPL / 2 */
		[ 2] = 0,	/* CC1 PPL / 4 */
		[ 4] = 1,	/* CC2 PPL / 1 */
		[ 5] = 1,	/* CC2 PPL / 2 */
		[ 6] = 1,	/* CC2 PPL / 4 */
		[ 8] = 2,	/* CC3 PPL / 1 */
		[ 9] = 2,	/* CC3 PPL / 2 */
		[10] = 2,	/* CC3 PPL / 4 */
		[12] = 3,	/* CC4 PPL / 1 */
		[13] = 3,	/* CC4 PPL / 2 */
		[14] = 3,	/* CC4 PPL / 4 */
	};

	const u8 core_cplx_pll_div[16] = {
		[ 0] = 1,	/* CC1 PPL / 1 */
		[ 1] = 2,	/* CC1 PPL / 2 */
		[ 2] = 4,	/* CC1 PPL / 4 */
		[ 4] = 1,	/* CC2 PPL / 1 */
		[ 5] = 2,	/* CC2 PPL / 2 */
		[ 6] = 4,	/* CC2 PPL / 4 */
		[ 8] = 1,	/* CC3 PPL / 1 */
		[ 9] = 2,	/* CC3 PPL / 2 */
		[10] = 4,	/* CC3 PPL / 4 */
		[12] = 1,	/* CC4 PPL / 1 */
		[13] = 2,	/* CC4 PPL / 2 */
		[14] = 4,	/* CC4 PPL / 4 */
	};
	uint i, freq_c_pll[CONFIG_SYS_FSL_NUM_CC_PLLS];
#if !defined(CONFIG_FM_PLAT_CLK_DIV) || !defined(CONFIG_PME_PLAT_CLK_DIV)
	uint rcw_tmp;
#endif
	uint ratio[CONFIG_SYS_FSL_NUM_CC_PLLS];
	unsigned long sysclk = CONFIG_SYS_CLK_FREQ;
	uint mem_pll_rat;

	sys_info->freq_systembus = sysclk;
#ifdef CONFIG_DDR_CLK_FREQ
	sys_info->freq_ddrbus = CONFIG_DDR_CLK_FREQ;
#else
	sys_info->freq_ddrbus = sysclk;
#endif

	sys_info->freq_systembus *= (in_be32(&gur->rcwsr[0]) >> 25) & 0x1f;
	mem_pll_rat = (in_be32(&gur->rcwsr[0]) >>
			FSL_CORENET_RCWSR0_MEM_PLL_RAT_SHIFT)
			& FSL_CORENET_RCWSR0_MEM_PLL_RAT_MASK;
	if (mem_pll_rat > 2)
		sys_info->freq_ddrbus *= mem_pll_rat;
	else
		sys_info->freq_ddrbus = sys_info->freq_systembus * mem_pll_rat;

	for (i = 0; i < CONFIG_SYS_FSL_NUM_CC_PLLS; i++) {
		ratio[i] = (in_be32(&clk->pllcgsr[i].pllcngsr) >> 1) & 0x3f;
		if (ratio[i] > 4)
			freq_c_pll[i] = sysclk * ratio[i];
		else
			freq_c_pll[i] = sys_info->freq_systembus * ratio[i];
	}
#ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2
	/*
	 * As per CHASSIS2 architeture total 12 clusters are posible and
	 * Each cluster has up to 4 cores, sharing the same PLL selection.
	 * The cluster clock assignment is SoC defined.
	 *
	 * Total 4 clock groups are possible with 3 PLLs each.
	 * as per array indices, clock group A has 0, 1, 2 numbered PLLs &
	 * clock group B has 3, 4, 6 and so on.
	 *
	 * Clock group A having PLL1, PLL2, PLL3, feeding cores of any cluster
	 * depends upon the SoC architeture. Same applies to other
	 * clock groups and clusters.
	 *
	 */
	for_each_cpu(i, cpu, cpu_numcores(), cpu_mask()) {
		int cluster = fsl_qoriq_core_to_cluster(cpu);
		u32 c_pll_sel = (in_be32(&clk->clkcsr[cluster].clkcncsr) >> 27)
				& 0xf;
		u32 cplx_pll = core_cplx_PLL[c_pll_sel];
		cplx_pll += cc_group[cluster] - 1;
		sys_info->freq_processor[cpu] =
			 freq_c_pll[cplx_pll] / core_cplx_pll_div[c_pll_sel];
	}
#if defined(CONFIG_PPC_B4860) || defined(CONFIG_PPC_T2080)
#define FM1_CLK_SEL	0xe0000000
#define FM1_CLK_SHIFT	29
#else
#define PME_CLK_SEL	0xe0000000
#define PME_CLK_SHIFT	29
#define FM1_CLK_SEL	0x1c000000
#define FM1_CLK_SHIFT	26
#endif
#if !defined(CONFIG_FM_PLAT_CLK_DIV) || !defined(CONFIG_PME_PLAT_CLK_DIV)
	rcw_tmp = in_be32(&gur->rcwsr[7]);
#endif

#ifdef CONFIG_SYS_DPAA_PME
#ifndef CONFIG_PME_PLAT_CLK_DIV
	switch ((rcw_tmp & PME_CLK_SEL) >> PME_CLK_SHIFT) {
	case 1:
		sys_info->freq_pme = freq_c_pll[CONFIG_SYS_PME_CLK];
		break;
	case 2:
		sys_info->freq_pme = freq_c_pll[CONFIG_SYS_PME_CLK] / 2;
		break;
	case 3:
		sys_info->freq_pme = freq_c_pll[CONFIG_SYS_PME_CLK] / 3;
		break;
	case 4:
		sys_info->freq_pme = freq_c_pll[CONFIG_SYS_PME_CLK] / 4;
		break;
	case 6:
		sys_info->freq_pme = freq_c_pll[CONFIG_SYS_PME_CLK + 1] / 2;
		break;
	case 7:
		sys_info->freq_pme = freq_c_pll[CONFIG_SYS_PME_CLK + 1] / 3;
		break;
	default:
		printf("Error: Unknown PME clock select!\n");
	case 0:
		sys_info->freq_pme = sys_info->freq_systembus / 2;
		break;

	}
#else
	sys_info->freq_pme = sys_info->freq_systembus / CONFIG_SYS_PME_CLK;

#endif
#endif

#ifdef CONFIG_SYS_DPAA_QBMAN
	sys_info->freq_qman = sys_info->freq_systembus / 2;
#endif

#ifdef CONFIG_SYS_DPAA_FMAN
#ifndef CONFIG_FM_PLAT_CLK_DIV
	switch ((rcw_tmp & FM1_CLK_SEL) >> FM1_CLK_SHIFT) {
	case 1:
		sys_info->freq_fman[0] = freq_c_pll[CONFIG_SYS_FM1_CLK];
		break;
	case 2:
		sys_info->freq_fman[0] = freq_c_pll[CONFIG_SYS_FM1_CLK] / 2;
		break;
	case 3:
		sys_info->freq_fman[0] = freq_c_pll[CONFIG_SYS_FM1_CLK] / 3;
		break;
	case 4:
		sys_info->freq_fman[0] = freq_c_pll[CONFIG_SYS_FM1_CLK] / 4;
		break;
	case 5:
		sys_info->freq_fman[0] = sys_info->freq_systembus;
		break;
	case 6:
		sys_info->freq_fman[0] = freq_c_pll[CONFIG_SYS_FM1_CLK + 1] / 2;
		break;
	case 7:
		sys_info->freq_fman[0] = freq_c_pll[CONFIG_SYS_FM1_CLK + 1] / 3;
		break;
	default:
		printf("Error: Unknown FMan1 clock select!\n");
	case 0:
		sys_info->freq_fman[0] = sys_info->freq_systembus / 2;
		break;
	}
#if (CONFIG_SYS_NUM_FMAN) == 2
#ifdef CONFIG_SYS_FM2_CLK
#define FM2_CLK_SEL	0x00000038
#define FM2_CLK_SHIFT	3
	rcw_tmp = in_be32(&gur->rcwsr[15]);
	switch ((rcw_tmp & FM2_CLK_SEL) >> FM2_CLK_SHIFT) {
	case 1:
		sys_info->freq_fman[1] = freq_c_pll[CONFIG_SYS_FM2_CLK + 1];
		break;
	case 2:
		sys_info->freq_fman[1] = freq_c_pll[CONFIG_SYS_FM2_CLK + 1] / 2;
		break;
	case 3:
		sys_info->freq_fman[1] = freq_c_pll[CONFIG_SYS_FM2_CLK + 1] / 3;
		break;
	case 4:
		sys_info->freq_fman[1] = freq_c_pll[CONFIG_SYS_FM2_CLK + 1] / 4;
		break;
	case 6:
		sys_info->freq_fman[1] = freq_c_pll[CONFIG_SYS_FM2_CLK] / 2;
		break;
	case 7:
		sys_info->freq_fman[1] = freq_c_pll[CONFIG_SYS_FM2_CLK] / 3;
		break;
	default:
		printf("Error: Unknown FMan2 clock select!\n");
	case 0:
		sys_info->freq_fman[1] = sys_info->freq_systembus / 2;
		break;
	}
#endif
#endif	/* CONFIG_SYS_NUM_FMAN == 2 */
#else
	sys_info->freq_fman[0] = sys_info->freq_systembus / CONFIG_SYS_FM1_CLK;
#endif
#endif

#else /* CONFIG_SYS_FSL_QORIQ_CHASSIS2 */

	for_each_cpu(i, cpu, cpu_numcores(), cpu_mask()) {
		u32 c_pll_sel = (in_be32(&clk->clkcsr[cpu].clkcncsr) >> 27)
				& 0xf;
		u32 cplx_pll = core_cplx_PLL[c_pll_sel];

		sys_info->freq_processor[cpu] =
			 freq_c_pll[cplx_pll] / core_cplx_pll_div[c_pll_sel];
	}
#define PME_CLK_SEL	0x80000000
#define FM1_CLK_SEL	0x40000000
#define FM2_CLK_SEL	0x20000000
#define HWA_ASYNC_DIV	0x04000000
#if (CONFIG_SYS_FSL_NUM_CC_PLLS == 2)
#define HWA_CC_PLL	1
#elif (CONFIG_SYS_FSL_NUM_CC_PLLS == 3)
#define HWA_CC_PLL	2
#elif (CONFIG_SYS_FSL_NUM_CC_PLLS == 4)
#define HWA_CC_PLL	2
#else
#error CONFIG_SYS_FSL_NUM_CC_PLLS not set or unknown case
#endif
	rcw_tmp = in_be32(&gur->rcwsr[7]);

#ifdef CONFIG_SYS_DPAA_PME
	if (rcw_tmp & PME_CLK_SEL) {
		if (rcw_tmp & HWA_ASYNC_DIV)
			sys_info->freq_pme = freq_c_pll[HWA_CC_PLL] / 4;
		else
			sys_info->freq_pme = freq_c_pll[HWA_CC_PLL] / 2;
	} else {
		sys_info->freq_pme = sys_info->freq_systembus / 2;
	}
#endif

#ifdef CONFIG_SYS_DPAA_FMAN
	if (rcw_tmp & FM1_CLK_SEL) {
		if (rcw_tmp & HWA_ASYNC_DIV)
			sys_info->freq_fman[0] = freq_c_pll[HWA_CC_PLL] / 4;
		else
			sys_info->freq_fman[0] = freq_c_pll[HWA_CC_PLL] / 2;
	} else {
		sys_info->freq_fman[0] = sys_info->freq_systembus / 2;
	}
#if (CONFIG_SYS_NUM_FMAN) == 2
	if (rcw_tmp & FM2_CLK_SEL) {
		if (rcw_tmp & HWA_ASYNC_DIV)
			sys_info->freq_fman[1] = freq_c_pll[HWA_CC_PLL] / 4;
		else
			sys_info->freq_fman[1] = freq_c_pll[HWA_CC_PLL] / 2;
	} else {
		sys_info->freq_fman[1] = sys_info->freq_systembus / 2;
	}
#endif
#endif

#ifdef CONFIG_SYS_DPAA_QBMAN
	sys_info->freq_qman = sys_info->freq_systembus / 2;
#endif

#endif /* CONFIG_SYS_FSL_QORIQ_CHASSIS2 */

#else /* CONFIG_FSL_CORENET */
	uint plat_ratio, e500_ratio, half_freq_systembus;
	int i;
#ifdef CONFIG_QE
	__maybe_unused u32 qe_ratio;
#endif

	plat_ratio = (gur->porpllsr) & 0x0000003e;
	plat_ratio >>= 1;
	sys_info->freq_systembus = plat_ratio * CONFIG_SYS_CLK_FREQ;

	/* Divide before multiply to avoid integer
	 * overflow for processor speeds above 2GHz */
	half_freq_systembus = sys_info->freq_systembus/2;
	for (i = 0; i < cpu_numcores(); i++) {
		e500_ratio = ((gur->porpllsr) >> (i * 8 + 16)) & 0x3f;
		sys_info->freq_processor[i] = e500_ratio * half_freq_systembus;
	}

	/* Note: freq_ddrbus is the MCLK frequency, not the data rate. */
	sys_info->freq_ddrbus = sys_info->freq_systembus;

#ifdef CONFIG_DDR_CLK_FREQ
	{
		u32 ddr_ratio = ((gur->porpllsr) & MPC85xx_PORPLLSR_DDR_RATIO)
			>> MPC85xx_PORPLLSR_DDR_RATIO_SHIFT;
		if (ddr_ratio != 0x7)
			sys_info->freq_ddrbus = ddr_ratio * CONFIG_DDR_CLK_FREQ;
	}
#endif

#ifdef CONFIG_QE
#if defined(CONFIG_P1012) || defined(CONFIG_P1021) || defined(CONFIG_P1025)
	sys_info->freq_qe =  sys_info->freq_systembus;
#else
	qe_ratio = ((gur->porpllsr) & MPC85xx_PORPLLSR_QE_RATIO)
			>> MPC85xx_PORPLLSR_QE_RATIO_SHIFT;
	sys_info->freq_qe = qe_ratio * CONFIG_SYS_CLK_FREQ;
#endif
#endif

#ifdef CONFIG_SYS_DPAA_FMAN
		sys_info->freq_fman[0] = sys_info->freq_systembus;
#endif

#endif /* CONFIG_FSL_CORENET */

#if defined(CONFIG_FSL_LBC)
	uint lcrr_div;
#if defined(CONFIG_SYS_LBC_LCRR)
	/* We will program LCRR to this value later */
	lcrr_div = CONFIG_SYS_LBC_LCRR & LCRR_CLKDIV;
#else
	lcrr_div = in_be32(&(LBC_BASE_ADDR)->lcrr) & LCRR_CLKDIV;
#endif
	if (lcrr_div == 2 || lcrr_div == 4 || lcrr_div == 8) {
#if defined(CONFIG_FSL_CORENET)
		/* If this is corenet based SoC, bit-representation
		 * for four times the clock divider values.
		 */
		lcrr_div *= 4;
#elif !defined(CONFIG_MPC8540) && !defined(CONFIG_MPC8541) && \
    !defined(CONFIG_MPC8555) && !defined(CONFIG_MPC8560)
		/*
		 * Yes, the entire PQ38 family use the same
		 * bit-representation for twice the clock divider values.
		 */
		lcrr_div *= 2;
#endif
		sys_info->freq_localbus = sys_info->freq_systembus / lcrr_div;
	} else {
		/* In case anyone cares what the unknown value is */
		sys_info->freq_localbus = lcrr_div;
	}
#endif

#if defined(CONFIG_FSL_IFC)
	ccr = in_be32(&ifc_regs->ifc_ccr);
	ccr = ((ccr & IFC_CCR_CLK_DIV_MASK) >> IFC_CCR_CLK_DIV_SHIFT) + 1;

	sys_info->freq_localbus = sys_info->freq_systembus / ccr;
#endif
}


int get_clocks (void)
{
	sys_info_t sys_info;
#ifdef CONFIG_MPC8544
	volatile ccsr_gur_t *gur = (void *) CONFIG_SYS_MPC85xx_GUTS_ADDR;
#endif
#if defined(CONFIG_CPM2)
	volatile ccsr_cpm_t *cpm = (ccsr_cpm_t *)CONFIG_SYS_MPC85xx_CPM_ADDR;
	uint sccr, dfbrg;

	/* set VCO = 4 * BRG */
	cpm->im_cpm_intctl.sccr &= 0xfffffffc;
	sccr = cpm->im_cpm_intctl.sccr;
	dfbrg = (sccr & SCCR_DFBRG_MSK) >> SCCR_DFBRG_SHIFT;
#endif
	get_sys_info (&sys_info);
	gd->cpu_clk = sys_info.freq_processor[0];
	gd->bus_clk = sys_info.freq_systembus;
	gd->mem_clk = sys_info.freq_ddrbus;
	gd->arch.lbc_clk = sys_info.freq_localbus;

#ifdef CONFIG_QE
	gd->arch.qe_clk = sys_info.freq_qe;
	gd->arch.brg_clk = gd->arch.qe_clk / 2;
#endif
	/*
	 * The base clock for I2C depends on the actual SOC.  Unfortunately,
	 * there is no pattern that can be used to determine the frequency, so
	 * the only choice is to look up the actual SOC number and use the value
	 * for that SOC. This information is taken from application note
	 * AN2919.
	 */
#if defined(CONFIG_MPC8540) || defined(CONFIG_MPC8541) || \
	defined(CONFIG_MPC8560) || defined(CONFIG_MPC8555) || \
	defined(CONFIG_P1022)
	gd->arch.i2c1_clk = sys_info.freq_systembus;
#elif defined(CONFIG_MPC8544)
	/*
	 * On the 8544, the I2C clock is the same as the SEC clock.  This can be
	 * either CCB/2 or CCB/3, depending on the value of cfg_sec_freq. See
	 * 4.4.3.3 of the 8544 RM.  Note that this might actually work for all
	 * 85xx, but only the 8544 has cfg_sec_freq, so it's unknown if the
	 * PORDEVSR2_SEC_CFG bit is 0 on all 85xx boards that are not an 8544.
	 */
	if (gur->pordevsr2 & MPC85xx_PORDEVSR2_SEC_CFG)
		gd->arch.i2c1_clk = sys_info.freq_systembus / 3;
	else
		gd->arch.i2c1_clk = sys_info.freq_systembus / 2;
#else
	/* Most 85xx SOCs use CCB/2, so this is the default behavior. */
	gd->arch.i2c1_clk = sys_info.freq_systembus / 2;
#endif
	gd->arch.i2c2_clk = gd->arch.i2c1_clk;

#if defined(CONFIG_FSL_ESDHC)
#if defined(CONFIG_MPC8569) || defined(CONFIG_P1010) ||\
       defined(CONFIG_P1014)
	gd->arch.sdhc_clk = gd->bus_clk;
#else
	gd->arch.sdhc_clk = gd->bus_clk / 2;
#endif
#endif /* defined(CONFIG_FSL_ESDHC) */

#if defined(CONFIG_CPM2)
	gd->arch.vco_out = 2*sys_info.freq_systembus;
	gd->arch.cpm_clk = gd->arch.vco_out / 2;
	gd->arch.scc_clk = gd->arch.vco_out / 4;
	gd->arch.brg_clk = gd->arch.vco_out / (1 << (2 * (dfbrg + 1)));
#endif

	if(gd->cpu_clk != 0) return (0);
	else return (1);
}


/********************************************
 * get_bus_freq
 * return system bus freq in Hz
 *********************************************/
ulong get_bus_freq (ulong dummy)
{
	return gd->bus_clk;
}

/********************************************
 * get_ddr_freq
 * return ddr bus freq in Hz
 *********************************************/
ulong get_ddr_freq (ulong dummy)
{
	return gd->mem_clk;
}
Commit	Line	Data
42d1f039	1	/*
beba93ed	2	* Copyright 2004, 2007-2011 Freescale Semiconductor, Inc.
39aaca1f	3	*
42d1f039 WD	4	* (C) Copyright 2003 Motorola Inc.
	5	* Xianghua Xiao, (X.Xiao@motorola.com)
	6	*
	7	* (C) Copyright 2000
	8	* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
	9	*
1a459660	10	* SPDX-License-Identifier: GPL-2.0+
42d1f039 WD	11	*/
	12
	13	#include <common.h>
	14	#include <ppc_asm.tmpl>
a52d2f81	15	#include <linux/compiler.h>
42d1f039	16	#include <asm/processor.h>
ada591d2	17	#include <asm/io.h>
42d1f039	18
d87080b7 WD	19	DECLARE_GLOBAL_DATA_PTR;
d87080b7 WD	20
ce746fe0 PK	21
	22	#ifndef CONFIG_SYS_FSL_NUM_CC_PLLS
	23	#define CONFIG_SYS_FSL_NUM_CC_PLLS 6
	24	#endif
42d1f039 WD	25	/* --------------------------------------------------------------- */
42d1f039 WD	26
997399fa	27	void get_sys_info(sys_info_t *sys_info)
42d1f039	28	{
6d0f6bcf	29	volatile ccsr_gur_t gur = (void )(CONFIG_SYS_MPC85xx_GUTS_ADDR);
800c73c4 KG	30	#ifdef CONFIG_FSL_IFC
	31	struct fsl_ifc ifc_regs = (void )CONFIG_SYS_IFC_ADDR;
	32	u32 ccr;
	33	#endif
39aaca1f KG	34	#ifdef CONFIG_FSL_CORENET
39aaca1f KG	35	volatile ccsr_clk_t clk = (void )(CONFIG_SYS_FSL_CORENET_CLK_ADDR);
fbb9ecf7	36	unsigned int cpu;
ce746fe0 PK	37	#ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2
	38	int cc_group[12] = CONFIG_SYS_FSL_CLUSTER_CLOCKS;
	39	#endif
39aaca1f KG	40
	41	const u8 core_cplx_PLL[16] = {
	42	[ 0] = 0, /* CC1 PPL / 1 */
	43	[ 1] = 0, /* CC1 PPL / 2 */
	44	[ 2] = 0, /* CC1 PPL / 4 */
	45	[ 4] = 1, /* CC2 PPL / 1 */
	46	[ 5] = 1, /* CC2 PPL / 2 */
	47	[ 6] = 1, /* CC2 PPL / 4 */
	48	[ 8] = 2, /* CC3 PPL / 1 */
	49	[ 9] = 2, /* CC3 PPL / 2 */
	50	[10] = 2, /* CC3 PPL / 4 */
	51	[12] = 3, /* CC4 PPL / 1 */
	52	[13] = 3, /* CC4 PPL / 2 */
	53	[14] = 3, /* CC4 PPL / 4 */
	54	};
	55
997399fa	56	const u8 core_cplx_pll_div[16] = {
39aaca1f KG	57	[ 0] = 1, /* CC1 PPL / 1 */
	58	[ 1] = 2, /* CC1 PPL / 2 */
	59	[ 2] = 4, /* CC1 PPL / 4 */
	60	[ 4] = 1, /* CC2 PPL / 1 */
	61	[ 5] = 2, /* CC2 PPL / 2 */
	62	[ 6] = 4, /* CC2 PPL / 4 */
	63	[ 8] = 1, /* CC3 PPL / 1 */
	64	[ 9] = 2, /* CC3 PPL / 2 */
	65	[10] = 4, /* CC3 PPL / 4 */
	66	[12] = 1, /* CC4 PPL / 1 */
	67	[13] = 2, /* CC4 PPL / 2 */
	68	[14] = 4, /* CC4 PPL / 4 */
	69	};
ce746fe0 PK	70	uint i, freq_c_pll[CONFIG_SYS_FSL_NUM_CC_PLLS];
	71	#if !defined(CONFIG_FM_PLAT_CLK_DIV) \|\| !defined(CONFIG_PME_PLAT_CLK_DIV)
	72	uint rcw_tmp;
	73	#endif
	74	uint ratio[CONFIG_SYS_FSL_NUM_CC_PLLS];
39aaca1f	75	unsigned long sysclk = CONFIG_SYS_CLK_FREQ;
ab48ca1a	76	uint mem_pll_rat;
39aaca1f	77
997399fa	78	sys_info->freq_systembus = sysclk;
98ffa190	79	#ifdef CONFIG_DDR_CLK_FREQ
997399fa	80	sys_info->freq_ddrbus = CONFIG_DDR_CLK_FREQ;
98ffa190	81	#else
997399fa	82	sys_info->freq_ddrbus = sysclk;
98ffa190	83	#endif
39aaca1f	84
997399fa	85	sys_info->freq_systembus *= (in_be32(&gur->rcwsr[0]) >> 25) & 0x1f;
f77329cf YS	86	mem_pll_rat = (in_be32(&gur->rcwsr[0]) >>
	87	FSL_CORENET_RCWSR0_MEM_PLL_RAT_SHIFT)
	88	& FSL_CORENET_RCWSR0_MEM_PLL_RAT_MASK;
ab48ca1a	89	if (mem_pll_rat > 2)
997399fa	90	sys_info->freq_ddrbus *= mem_pll_rat;
ab48ca1a	91	else
997399fa	92	sys_info->freq_ddrbus = sys_info->freq_systembus * mem_pll_rat;
39aaca1f	93
ce746fe0 PK	94	for (i = 0; i < CONFIG_SYS_FSL_NUM_CC_PLLS; i++) {
ce746fe0 PK	95	ratio[i] = (in_be32(&clk->pllcgsr[i].pllcngsr) >> 1) & 0x3f;
ab48ca1a	96	if (ratio[i] > 4)
ce746fe0	97	freq_c_pll[i] = sysclk * ratio[i];
ab48ca1a	98	else
ce746fe0	99	freq_c_pll[i] = sys_info->freq_systembus * ratio[i];
ab48ca1a	100	}
9a653a98 YS	101	#ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2
9a653a98 YS	102	/*
ce746fe0	103	* As per CHASSIS2 architeture total 12 clusters are posible and
9a653a98	104	* Each cluster has up to 4 cores, sharing the same PLL selection.
ce746fe0 PK	105	* The cluster clock assignment is SoC defined.
	106	*
	107	* Total 4 clock groups are possible with 3 PLLs each.
	108	* as per array indices, clock group A has 0, 1, 2 numbered PLLs &
	109	* clock group B has 3, 4, 6 and so on.
	110	*
	111	* Clock group A having PLL1, PLL2, PLL3, feeding cores of any cluster
	112	* depends upon the SoC architeture. Same applies to other
	113	* clock groups and clusters.
	114	*
9a653a98	115	*/
fbb9ecf7	116	for_each_cpu(i, cpu, cpu_numcores(), cpu_mask()) {
f6981439 YS	117	int cluster = fsl_qoriq_core_to_cluster(cpu);
f6981439 YS	118	u32 c_pll_sel = (in_be32(&clk->clkcsr[cluster].clkcncsr) >> 27)
9a653a98	119	& 0xf;
39aaca1f	120	u32 cplx_pll = core_cplx_PLL[c_pll_sel];
ce746fe0	121	cplx_pll += cc_group[cluster] - 1;
997399fa	122	sys_info->freq_processor[cpu] =
ce746fe0	123	freq_c_pll[cplx_pll] / core_cplx_pll_div[c_pll_sel];
39aaca1f	124	}
629d6b32	125	#if defined(CONFIG_PPC_B4860) \|\| defined(CONFIG_PPC_T2080)
0cb3325c SS	126	#define FM1_CLK_SEL 0xe0000000
	127	#define FM1_CLK_SHIFT 29
	128	#else
9a653a98 YS	129	#define PME_CLK_SEL 0xe0000000
	130	#define PME_CLK_SHIFT 29
	131	#define FM1_CLK_SEL 0x1c000000
	132	#define FM1_CLK_SHIFT 26
0cb3325c	133	#endif
ce746fe0	134	#if !defined(CONFIG_FM_PLAT_CLK_DIV) \|\| !defined(CONFIG_PME_PLAT_CLK_DIV)
9a653a98	135	rcw_tmp = in_be32(&gur->rcwsr[7]);
ce746fe0	136	#endif
9a653a98 YS	137
9a653a98 YS	138	#ifdef CONFIG_SYS_DPAA_PME
ce746fe0	139	#ifndef CONFIG_PME_PLAT_CLK_DIV
9a653a98 YS	140	switch ((rcw_tmp & PME_CLK_SEL) >> PME_CLK_SHIFT) {
9a653a98 YS	141	case 1:
ce746fe0	142	sys_info->freq_pme = freq_c_pll[CONFIG_SYS_PME_CLK];
9a653a98 YS	143	break;
9a653a98 YS	144	case 2:
ce746fe0	145	sys_info->freq_pme = freq_c_pll[CONFIG_SYS_PME_CLK] / 2;
9a653a98 YS	146	break;
9a653a98 YS	147	case 3:
ce746fe0	148	sys_info->freq_pme = freq_c_pll[CONFIG_SYS_PME_CLK] / 3;
9a653a98 YS	149	break;
9a653a98 YS	150	case 4:
ce746fe0	151	sys_info->freq_pme = freq_c_pll[CONFIG_SYS_PME_CLK] / 4;
9a653a98 YS	152	break;
9a653a98 YS	153	case 6:
ce746fe0	154	sys_info->freq_pme = freq_c_pll[CONFIG_SYS_PME_CLK + 1] / 2;
9a653a98 YS	155	break;
9a653a98 YS	156	case 7:
ce746fe0	157	sys_info->freq_pme = freq_c_pll[CONFIG_SYS_PME_CLK + 1] / 3;
9a653a98 YS	158	break;
	159	default:
	160	printf("Error: Unknown PME clock select!\n");
	161	case 0:
997399fa	162	sys_info->freq_pme = sys_info->freq_systembus / 2;
9a653a98 YS	163	break;
	164
	165	}
ce746fe0 PK	166	#else
	167	sys_info->freq_pme = sys_info->freq_systembus / CONFIG_SYS_PME_CLK;
	168
	169	#endif
9a653a98 YS	170	#endif
9a653a98 YS	171
990e1a8c	172	#ifdef CONFIG_SYS_DPAA_QBMAN
997399fa	173	sys_info->freq_qman = sys_info->freq_systembus / 2;
990e1a8c HW	174	#endif
990e1a8c HW	175
9a653a98	176	#ifdef CONFIG_SYS_DPAA_FMAN
ce746fe0	177	#ifndef CONFIG_FM_PLAT_CLK_DIV
9a653a98 YS	178	switch ((rcw_tmp & FM1_CLK_SEL) >> FM1_CLK_SHIFT) {
9a653a98 YS	179	case 1:
ce746fe0	180	sys_info->freq_fman[0] = freq_c_pll[CONFIG_SYS_FM1_CLK];
9a653a98 YS	181	break;
9a653a98 YS	182	case 2:
ce746fe0	183	sys_info->freq_fman[0] = freq_c_pll[CONFIG_SYS_FM1_CLK] / 2;
9a653a98 YS	184	break;
9a653a98 YS	185	case 3:
ce746fe0	186	sys_info->freq_fman[0] = freq_c_pll[CONFIG_SYS_FM1_CLK] / 3;
9a653a98 YS	187	break;
9a653a98 YS	188	case 4:
ce746fe0	189	sys_info->freq_fman[0] = freq_c_pll[CONFIG_SYS_FM1_CLK] / 4;
9a653a98	190	break;
0cb3325c	191	case 5:
997399fa	192	sys_info->freq_fman[0] = sys_info->freq_systembus;
0cb3325c	193	break;
9a653a98	194	case 6:
ce746fe0	195	sys_info->freq_fman[0] = freq_c_pll[CONFIG_SYS_FM1_CLK + 1] / 2;
9a653a98 YS	196	break;
9a653a98 YS	197	case 7:
ce746fe0	198	sys_info->freq_fman[0] = freq_c_pll[CONFIG_SYS_FM1_CLK + 1] / 3;
9a653a98 YS	199	break;
	200	default:
	201	printf("Error: Unknown FMan1 clock select!\n");
	202	case 0:
997399fa	203	sys_info->freq_fman[0] = sys_info->freq_systembus / 2;
9a653a98 YS	204	break;
	205	}
	206	#if (CONFIG_SYS_NUM_FMAN) == 2
ce746fe0	207	#ifdef CONFIG_SYS_FM2_CLK
9a653a98 YS	208	#define FM2_CLK_SEL 0x00000038
	209	#define FM2_CLK_SHIFT 3
	210	rcw_tmp = in_be32(&gur->rcwsr[15]);
	211	switch ((rcw_tmp & FM2_CLK_SEL) >> FM2_CLK_SHIFT) {
	212	case 1:
ce746fe0	213	sys_info->freq_fman[1] = freq_c_pll[CONFIG_SYS_FM2_CLK + 1];
9a653a98 YS	214	break;
9a653a98 YS	215	case 2:
ce746fe0	216	sys_info->freq_fman[1] = freq_c_pll[CONFIG_SYS_FM2_CLK + 1] / 2;
9a653a98 YS	217	break;
9a653a98 YS	218	case 3:
ce746fe0	219	sys_info->freq_fman[1] = freq_c_pll[CONFIG_SYS_FM2_CLK + 1] / 3;
9a653a98 YS	220	break;
9a653a98 YS	221	case 4:
ce746fe0	222	sys_info->freq_fman[1] = freq_c_pll[CONFIG_SYS_FM2_CLK + 1] / 4;
9a653a98 YS	223	break;
9a653a98 YS	224	case 6:
ce746fe0	225	sys_info->freq_fman[1] = freq_c_pll[CONFIG_SYS_FM2_CLK] / 2;
9a653a98 YS	226	break;
9a653a98 YS	227	case 7:
ce746fe0	228	sys_info->freq_fman[1] = freq_c_pll[CONFIG_SYS_FM2_CLK] / 3;
9a653a98 YS	229	break;
	230	default:
	231	printf("Error: Unknown FMan2 clock select!\n");
	232	case 0:
997399fa	233	sys_info->freq_fman[1] = sys_info->freq_systembus / 2;
9a653a98 YS	234	break;
9a653a98 YS	235	}
ce746fe0	236	#endif
9a653a98	237	#endif /* CONFIG_SYS_NUM_FMAN == 2 */
ce746fe0 PK	238	#else
	239	sys_info->freq_fman[0] = sys_info->freq_systembus / CONFIG_SYS_FM1_CLK;
	240	#endif
	241	#endif
39aaca1f	242
9a653a98 YS	243	#else /* CONFIG_SYS_FSL_QORIQ_CHASSIS2 */
	244
	245	for_each_cpu(i, cpu, cpu_numcores(), cpu_mask()) {
f6981439 YS	246	u32 c_pll_sel = (in_be32(&clk->clkcsr[cpu].clkcncsr) >> 27)
f6981439 YS	247	& 0xf;
9a653a98 YS	248	u32 cplx_pll = core_cplx_PLL[c_pll_sel];
9a653a98 YS	249
997399fa	250	sys_info->freq_processor[cpu] =
ce746fe0	251	freq_c_pll[cplx_pll] / core_cplx_pll_div[c_pll_sel];
9a653a98	252	}
39aaca1f KG	253	#define PME_CLK_SEL 0x80000000
	254	#define FM1_CLK_SEL 0x40000000
	255	#define FM2_CLK_SEL 0x20000000
b5c8753f KG	256	#define HWA_ASYNC_DIV 0x04000000
	257	#if (CONFIG_SYS_FSL_NUM_CC_PLLS == 2)
	258	#define HWA_CC_PLL 1
4905443f TT	259	#elif (CONFIG_SYS_FSL_NUM_CC_PLLS == 3)
4905443f TT	260	#define HWA_CC_PLL 2
b5c8753f	261	#elif (CONFIG_SYS_FSL_NUM_CC_PLLS == 4)
cd6881b5	262	#define HWA_CC_PLL 2
b5c8753f KG	263	#else
	264	#error CONFIG_SYS_FSL_NUM_CC_PLLS not set or unknown case
	265	#endif
39aaca1f KG	266	rcw_tmp = in_be32(&gur->rcwsr[7]);
	267
	268	#ifdef CONFIG_SYS_DPAA_PME
b5c8753f KG	269	if (rcw_tmp & PME_CLK_SEL) {
b5c8753f KG	270	if (rcw_tmp & HWA_ASYNC_DIV)
ce746fe0	271	sys_info->freq_pme = freq_c_pll[HWA_CC_PLL] / 4;
b5c8753f	272	else
ce746fe0	273	sys_info->freq_pme = freq_c_pll[HWA_CC_PLL] / 2;
b5c8753f	274	} else {
997399fa	275	sys_info->freq_pme = sys_info->freq_systembus / 2;
b5c8753f	276	}
39aaca1f KG	277	#endif
	278
	279	#ifdef CONFIG_SYS_DPAA_FMAN
b5c8753f KG	280	if (rcw_tmp & FM1_CLK_SEL) {
b5c8753f KG	281	if (rcw_tmp & HWA_ASYNC_DIV)
ce746fe0	282	sys_info->freq_fman[0] = freq_c_pll[HWA_CC_PLL] / 4;
b5c8753f	283	else
ce746fe0	284	sys_info->freq_fman[0] = freq_c_pll[HWA_CC_PLL] / 2;
b5c8753f	285	} else {
997399fa	286	sys_info->freq_fman[0] = sys_info->freq_systembus / 2;
b5c8753f	287	}
39aaca1f	288	#if (CONFIG_SYS_NUM_FMAN) == 2
b5c8753f KG	289	if (rcw_tmp & FM2_CLK_SEL) {
b5c8753f KG	290	if (rcw_tmp & HWA_ASYNC_DIV)
ce746fe0	291	sys_info->freq_fman[1] = freq_c_pll[HWA_CC_PLL] / 4;
b5c8753f	292	else
ce746fe0	293	sys_info->freq_fman[1] = freq_c_pll[HWA_CC_PLL] / 2;
b5c8753f	294	} else {
997399fa	295	sys_info->freq_fman[1] = sys_info->freq_systembus / 2;
b5c8753f	296	}
39aaca1f KG	297	#endif
	298	#endif
	299
3e83fc9b	300	#ifdef CONFIG_SYS_DPAA_QBMAN
997399fa	301	sys_info->freq_qman = sys_info->freq_systembus / 2;
3e83fc9b SX	302	#endif
3e83fc9b SX	303
9a653a98 YS	304	#endif /* CONFIG_SYS_FSL_QORIQ_CHASSIS2 */
	305
	306	#else /* CONFIG_FSL_CORENET */
997399fa	307	uint plat_ratio, e500_ratio, half_freq_systembus;
2fc7eb0c	308	int i;
b3d7f20f	309	#ifdef CONFIG_QE
a52d2f81	310	__maybe_unused u32 qe_ratio;
b3d7f20f	311	#endif
42d1f039 WD	312
	313	plat_ratio = (gur->porpllsr) & 0x0000003e;
	314	plat_ratio >>= 1;
997399fa	315	sys_info->freq_systembus = plat_ratio * CONFIG_SYS_CLK_FREQ;
66ed6cca AF	316
	317	/* Divide before multiply to avoid integer
	318	* overflow for processor speeds above 2GHz */
997399fa	319	half_freq_systembus = sys_info->freq_systembus/2;
0e870980	320	for (i = 0; i < cpu_numcores(); i++) {
2fc7eb0c	321	e500_ratio = ((gur->porpllsr) >> (i * 8 + 16)) & 0x3f;
997399fa	322	sys_info->freq_processor[i] = e500_ratio * half_freq_systembus;
2fc7eb0c	323	}
a3e77fa5	324
997399fa PK	325	/* Note: freq_ddrbus is the MCLK frequency, not the data rate. */
997399fa PK	326	sys_info->freq_ddrbus = sys_info->freq_systembus;
d4357932 KG	327
	328	#ifdef CONFIG_DDR_CLK_FREQ
	329	{
c0391111 JJ	330	u32 ddr_ratio = ((gur->porpllsr) & MPC85xx_PORPLLSR_DDR_RATIO)
c0391111 JJ	331	>> MPC85xx_PORPLLSR_DDR_RATIO_SHIFT;
d4357932	332	if (ddr_ratio != 0x7)
997399fa	333	sys_info->freq_ddrbus = ddr_ratio * CONFIG_DDR_CLK_FREQ;
d4357932 KG	334	}
d4357932 KG	335	#endif
ada591d2	336
b3d7f20f	337	#ifdef CONFIG_QE
be7bebea	338	#if defined(CONFIG_P1012) \|\| defined(CONFIG_P1021) \|\| defined(CONFIG_P1025)
997399fa	339	sys_info->freq_qe = sys_info->freq_systembus;
a52d2f81	340	#else
b3d7f20f HW	341	qe_ratio = ((gur->porpllsr) & MPC85xx_PORPLLSR_QE_RATIO)
b3d7f20f HW	342	>> MPC85xx_PORPLLSR_QE_RATIO_SHIFT;
997399fa	343	sys_info->freq_qe = qe_ratio * CONFIG_SYS_CLK_FREQ;
b3d7f20f	344	#endif
a52d2f81	345	#endif
b3d7f20f	346
24995d82	347	#ifdef CONFIG_SYS_DPAA_FMAN
997399fa	348	sys_info->freq_fman[0] = sys_info->freq_systembus;
24995d82 HW	349	#endif
	350
	351	#endif /* CONFIG_FSL_CORENET */
	352
beba93ed	353	#if defined(CONFIG_FSL_LBC)
9a653a98	354	uint lcrr_div;
ada591d2 TP	355	#if defined(CONFIG_SYS_LBC_LCRR)
	356	/* We will program LCRR to this value later */
	357	lcrr_div = CONFIG_SYS_LBC_LCRR & LCRR_CLKDIV;
	358	#else
f51cdaf1	359	lcrr_div = in_be32(&(LBC_BASE_ADDR)->lcrr) & LCRR_CLKDIV;
ada591d2 TP	360	#endif
ada591d2 TP	361	if (lcrr_div == 2 \|\| lcrr_div == 4 \|\| lcrr_div == 8) {
0fd2fa6c DL	362	#if defined(CONFIG_FSL_CORENET)
	363	/* If this is corenet based SoC, bit-representation
	364	* for four times the clock divider values.
	365	*/
	366	lcrr_div *= 4;
	367	#elif !defined(CONFIG_MPC8540) && !defined(CONFIG_MPC8541) && \
ada591d2 TP	368	!defined(CONFIG_MPC8555) && !defined(CONFIG_MPC8560)
	369	/*
	370	* Yes, the entire PQ38 family use the same
	371	* bit-representation for twice the clock divider values.
	372	*/
	373	lcrr_div *= 2;
	374	#endif
997399fa	375	sys_info->freq_localbus = sys_info->freq_systembus / lcrr_div;
ada591d2 TP	376	} else {
ada591d2 TP	377	/* In case anyone cares what the unknown value is */
997399fa	378	sys_info->freq_localbus = lcrr_div;
ada591d2	379	}
beba93ed	380	#endif
800c73c4 KG	381
	382	#if defined(CONFIG_FSL_IFC)
	383	ccr = in_be32(&ifc_regs->ifc_ccr);
	384	ccr = ((ccr & IFC_CCR_CLK_DIV_MASK) >> IFC_CCR_CLK_DIV_SHIFT) + 1;
	385
997399fa	386	sys_info->freq_localbus = sys_info->freq_systembus / ccr;
800c73c4	387	#endif
42d1f039 WD	388	}
42d1f039 WD	389
66ed6cca	390
42d1f039 WD	391	int get_clocks (void)
42d1f039 WD	392	{
42d1f039	393	sys_info_t sys_info;
88353a98	394	#ifdef CONFIG_MPC8544
6d0f6bcf	395	volatile ccsr_gur_t gur = (void ) CONFIG_SYS_MPC85xx_GUTS_ADDR;
88353a98	396	#endif
9c4c5ae3	397	#if defined(CONFIG_CPM2)
6d0f6bcf	398	volatile ccsr_cpm_t cpm = (ccsr_cpm_t )CONFIG_SYS_MPC85xx_CPM_ADDR;
42d1f039 WD	399	uint sccr, dfbrg;
	400
	401	/* set VCO = 4 * BRG */
aafeefbd KG	402	cpm->im_cpm_intctl.sccr &= 0xfffffffc;
aafeefbd KG	403	sccr = cpm->im_cpm_intctl.sccr;
42d1f039 WD	404	dfbrg = (sccr & SCCR_DFBRG_MSK) >> SCCR_DFBRG_SHIFT;
	405	#endif
	406	get_sys_info (&sys_info);
997399fa PK	407	gd->cpu_clk = sys_info.freq_processor[0];
	408	gd->bus_clk = sys_info.freq_systembus;
	409	gd->mem_clk = sys_info.freq_ddrbus;
	410	gd->arch.lbc_clk = sys_info.freq_localbus;
88353a98	411
b3d7f20f	412	#ifdef CONFIG_QE
997399fa	413	gd->arch.qe_clk = sys_info.freq_qe;
45bae2e3	414	gd->arch.brg_clk = gd->arch.qe_clk / 2;
b3d7f20f	415	#endif
88353a98 TT	416	/*
	417	* The base clock for I2C depends on the actual SOC. Unfortunately,
	418	* there is no pattern that can be used to determine the frequency, so
	419	* the only choice is to look up the actual SOC number and use the value
	420	* for that SOC. This information is taken from application note
	421	* AN2919.
	422	*/
	423	#if defined(CONFIG_MPC8540) \|\| defined(CONFIG_MPC8541) \|\| \
f62b1238 TY	424	defined(CONFIG_MPC8560) \|\| defined(CONFIG_MPC8555) \|\| \
f62b1238 TY	425	defined(CONFIG_P1022)
997399fa	426	gd->arch.i2c1_clk = sys_info.freq_systembus;
88353a98 TT	427	#elif defined(CONFIG_MPC8544)
	428	/*
	429	* On the 8544, the I2C clock is the same as the SEC clock. This can be
	430	* either CCB/2 or CCB/3, depending on the value of cfg_sec_freq. See
	431	* 4.4.3.3 of the 8544 RM. Note that this might actually work for all
	432	* 85xx, but only the 8544 has cfg_sec_freq, so it's unknown if the
	433	* PORDEVSR2_SEC_CFG bit is 0 on all 85xx boards that are not an 8544.
	434	*/
	435	if (gur->pordevsr2 & MPC85xx_PORDEVSR2_SEC_CFG)
997399fa	436	gd->arch.i2c1_clk = sys_info.freq_systembus / 3;
42653b82	437	else
997399fa	438	gd->arch.i2c1_clk = sys_info.freq_systembus / 2;
88353a98 TT	439	#else
88353a98 TT	440	/* Most 85xx SOCs use CCB/2, so this is the default behavior. */
997399fa	441	gd->arch.i2c1_clk = sys_info.freq_systembus / 2;
88353a98	442	#endif
609e6ec3	443	gd->arch.i2c2_clk = gd->arch.i2c1_clk;
943afa22	444
6b9ea08c	445	#if defined(CONFIG_FSL_ESDHC)
7d640e9b PJ	446	#if defined(CONFIG_MPC8569) \|\| defined(CONFIG_P1010) \|\|\
7d640e9b PJ	447	defined(CONFIG_P1014)
e9adeca3	448	gd->arch.sdhc_clk = gd->bus_clk;
7f52ed5e	449	#else
e9adeca3	450	gd->arch.sdhc_clk = gd->bus_clk / 2;
ef50d6c0	451	#endif
7f52ed5e	452	#endif /* defined(CONFIG_FSL_ESDHC) */
ef50d6c0	453
9c4c5ae3	454	#if defined(CONFIG_CPM2)
997399fa	455	gd->arch.vco_out = 2*sys_info.freq_systembus;
748cd059 SG	456	gd->arch.cpm_clk = gd->arch.vco_out / 2;
	457	gd->arch.scc_clk = gd->arch.vco_out / 4;
	458	gd->arch.brg_clk = gd->arch.vco_out / (1 << (2 * (dfbrg + 1)));
42d1f039 WD	459	#endif
	460
	461	if(gd->cpu_clk != 0) return (0);
	462	else return (1);
	463	}
	464
	465
	466	/********************************************
	467	* get_bus_freq
	468	* return system bus freq in Hz
	469	*********************************************/
	470	ulong get_bus_freq (ulong dummy)
	471	{
a3e77fa5	472	return gd->bus_clk;
42d1f039	473	}
d4357932 KG	474
	475	/********************************************
	476	* get_ddr_freq
	477	* return ddr bus freq in Hz
	478	*********************************************/
	479	ulong get_ddr_freq (ulong dummy)
	480	{
a3e77fa5	481	return gd->mem_clk;
d4357932	482	}