[thirdparty/linux.git] / arch / riscv / include / asm / csr.h

/* SPDX-License-Identifier: GPL-2.0-only */
/*
 * Copyright (C) 2015 Regents of the University of California
 */

#ifndef _ASM_RISCV_CSR_H
#define _ASM_RISCV_CSR_H

#include <asm/asm.h>
#include <linux/const.h>

/* Status register flags */
#define SR_SIE		_AC(0x00000002, UL) /* Supervisor Interrupt Enable */
#define SR_MIE		_AC(0x00000008, UL) /* Machine Interrupt Enable */
#define SR_SPIE		_AC(0x00000020, UL) /* Previous Supervisor IE */
#define SR_MPIE		_AC(0x00000080, UL) /* Previous Machine IE */
#define SR_SPP		_AC(0x00000100, UL) /* Previously Supervisor */
#define SR_MPP		_AC(0x00001800, UL) /* Previously Machine */
#define SR_SUM		_AC(0x00040000, UL) /* Supervisor User Memory Access */

#define SR_FS		_AC(0x00006000, UL) /* Floating-point Status */
#define SR_FS_OFF	_AC(0x00000000, UL)
#define SR_FS_INITIAL	_AC(0x00002000, UL)
#define SR_FS_CLEAN	_AC(0x00004000, UL)
#define SR_FS_DIRTY	_AC(0x00006000, UL)

#define SR_XS		_AC(0x00018000, UL) /* Extension Status */
#define SR_XS_OFF	_AC(0x00000000, UL)
#define SR_XS_INITIAL	_AC(0x00008000, UL)
#define SR_XS_CLEAN	_AC(0x00010000, UL)
#define SR_XS_DIRTY	_AC(0x00018000, UL)

#ifndef CONFIG_64BIT
#define SR_SD		_AC(0x80000000, UL) /* FS/XS dirty */
#else
#define SR_SD		_AC(0x8000000000000000, UL) /* FS/XS dirty */
#endif

/* SATP flags */
#ifndef CONFIG_64BIT
#define SATP_PPN	_AC(0x003FFFFF, UL)
#define SATP_MODE_32	_AC(0x80000000, UL)
#define SATP_MODE	SATP_MODE_32
#else
#define SATP_PPN	_AC(0x00000FFFFFFFFFFF, UL)
#define SATP_MODE_39	_AC(0x8000000000000000, UL)
#define SATP_MODE	SATP_MODE_39
#endif

/* Exception cause high bit - is an interrupt if set */
#define CAUSE_IRQ_FLAG		(_AC(1, UL) << (__riscv_xlen - 1))

/* Interrupt causes (minus the high bit) */
#define IRQ_S_SOFT		1
#define IRQ_M_SOFT		3
#define IRQ_S_TIMER		5
#define IRQ_M_TIMER		7
#define IRQ_S_EXT		9
#define IRQ_M_EXT		11

/* Exception causes */
#define EXC_INST_MISALIGNED	0
#define EXC_INST_ACCESS		1
#define EXC_BREAKPOINT		3
#define EXC_LOAD_ACCESS		5
#define EXC_STORE_ACCESS	7
#define EXC_SYSCALL		8
#define EXC_INST_PAGE_FAULT	12
#define EXC_LOAD_PAGE_FAULT	13
#define EXC_STORE_PAGE_FAULT	15

/* PMP configuration */
#define PMP_R			0x01
#define PMP_W			0x02
#define PMP_X			0x04
#define PMP_A			0x18
#define PMP_A_TOR		0x08
#define PMP_A_NA4		0x10
#define PMP_A_NAPOT		0x18
#define PMP_L			0x80

/* symbolic CSR names: */
#define CSR_CYCLE		0xc00
#define CSR_TIME		0xc01
#define CSR_INSTRET		0xc02
#define CSR_CYCLEH		0xc80
#define CSR_TIMEH		0xc81
#define CSR_INSTRETH		0xc82

#define CSR_SSTATUS		0x100
#define CSR_SIE			0x104
#define CSR_STVEC		0x105
#define CSR_SCOUNTEREN		0x106
#define CSR_SSCRATCH		0x140
#define CSR_SEPC		0x141
#define CSR_SCAUSE		0x142
#define CSR_STVAL		0x143
#define CSR_SIP			0x144
#define CSR_SATP		0x180

#define CSR_MSTATUS		0x300
#define CSR_MISA		0x301
#define CSR_MIE			0x304
#define CSR_MTVEC		0x305
#define CSR_MSCRATCH		0x340
#define CSR_MEPC		0x341
#define CSR_MCAUSE		0x342
#define CSR_MTVAL		0x343
#define CSR_MIP			0x344
#define CSR_PMPCFG0		0x3a0
#define CSR_PMPADDR0		0x3b0
#define CSR_MHARTID		0xf14

#ifdef CONFIG_RISCV_M_MODE
# define CSR_STATUS	CSR_MSTATUS
# define CSR_IE		CSR_MIE
# define CSR_TVEC	CSR_MTVEC
# define CSR_SCRATCH	CSR_MSCRATCH
# define CSR_EPC	CSR_MEPC
# define CSR_CAUSE	CSR_MCAUSE
# define CSR_TVAL	CSR_MTVAL
# define CSR_IP		CSR_MIP

# define SR_IE		SR_MIE
# define SR_PIE		SR_MPIE
# define SR_PP		SR_MPP

# define RV_IRQ_SOFT		IRQ_M_SOFT
# define RV_IRQ_TIMER	IRQ_M_TIMER
# define RV_IRQ_EXT		IRQ_M_EXT
#else /* CONFIG_RISCV_M_MODE */
# define CSR_STATUS	CSR_SSTATUS
# define CSR_IE		CSR_SIE
# define CSR_TVEC	CSR_STVEC
# define CSR_SCRATCH	CSR_SSCRATCH
# define CSR_EPC	CSR_SEPC
# define CSR_CAUSE	CSR_SCAUSE
# define CSR_TVAL	CSR_STVAL
# define CSR_IP		CSR_SIP

# define SR_IE		SR_SIE
# define SR_PIE		SR_SPIE
# define SR_PP		SR_SPP

# define RV_IRQ_SOFT		IRQ_S_SOFT
# define RV_IRQ_TIMER	IRQ_S_TIMER
# define RV_IRQ_EXT		IRQ_S_EXT
#endif /* CONFIG_RISCV_M_MODE */

/* IE/IP (Supervisor/Machine Interrupt Enable/Pending) flags */
#define IE_SIE		(_AC(0x1, UL) << RV_IRQ_SOFT)
#define IE_TIE		(_AC(0x1, UL) << RV_IRQ_TIMER)
#define IE_EIE		(_AC(0x1, UL) << RV_IRQ_EXT)

#ifndef __ASSEMBLY__

#define csr_swap(csr, val)					\
({								\
	unsigned long __v = (unsigned long)(val);		\
	__asm__ __volatile__ ("csrrw %0, " __ASM_STR(csr) ", %1"\
			      : "=r" (__v) : "rK" (__v)		\
			      : "memory");			\
	__v;							\
})

#define csr_read(csr)						\
({								\
	register unsigned long __v;				\
	__asm__ __volatile__ ("csrr %0, " __ASM_STR(csr)	\
			      : "=r" (__v) :			\
			      : "memory");			\
	__v;							\
})

#define csr_write(csr, val)					\
({								\
	unsigned long __v = (unsigned long)(val);		\
	__asm__ __volatile__ ("csrw " __ASM_STR(csr) ", %0"	\
			      : : "rK" (__v)			\
			      : "memory");			\
})

#define csr_read_set(csr, val)					\
({								\
	unsigned long __v = (unsigned long)(val);		\
	__asm__ __volatile__ ("csrrs %0, " __ASM_STR(csr) ", %1"\
			      : "=r" (__v) : "rK" (__v)		\
			      : "memory");			\
	__v;							\
})

#define csr_set(csr, val)					\
({								\
	unsigned long __v = (unsigned long)(val);		\
	__asm__ __volatile__ ("csrs " __ASM_STR(csr) ", %0"	\
			      : : "rK" (__v)			\
			      : "memory");			\
})

#define csr_read_clear(csr, val)				\
({								\
	unsigned long __v = (unsigned long)(val);		\
	__asm__ __volatile__ ("csrrc %0, " __ASM_STR(csr) ", %1"\
			      : "=r" (__v) : "rK" (__v)		\
			      : "memory");			\
	__v;							\
})

#define csr_clear(csr, val)					\
({								\
	unsigned long __v = (unsigned long)(val);		\
	__asm__ __volatile__ ("csrc " __ASM_STR(csr) ", %0"	\
			      : : "rK" (__v)			\
			      : "memory");			\
})

#endif /* __ASSEMBLY__ */

#endif /* _ASM_RISCV_CSR_H */
Commit	Line	Data
50acfb2b	1	/* SPDX-License-Identifier: GPL-2.0-only */
5d8544e2 PD	2	/*
5d8544e2 PD	3	* Copyright (C) 2015 Regents of the University of California
5d8544e2 PD	4	*/
	5
	6	#ifndef _ASM_RISCV_CSR_H
	7	#define _ASM_RISCV_CSR_H
	8
a3182c91	9	#include <asm/asm.h>
5d8544e2 PD	10	#include <linux/const.h>
	11
	12	/* Status register flags */
196a14d4	13	#define SR_SIE _AC(0x00000002, UL) /* Supervisor Interrupt Enable */
a4c3733d	14	#define SR_MIE _AC(0x00000008, UL) /* Machine Interrupt Enable */
196a14d4	15	#define SR_SPIE _AC(0x00000020, UL) /* Previous Supervisor IE */
a4c3733d	16	#define SR_MPIE _AC(0x00000080, UL) /* Previous Machine IE */
196a14d4	17	#define SR_SPP _AC(0x00000100, UL) /* Previously Supervisor */
a4c3733d	18	#define SR_MPP _AC(0x00001800, UL) /* Previously Machine */
196a14d4	19	#define SR_SUM _AC(0x00040000, UL) /* Supervisor User Memory Access */
5d8544e2	20
196a14d4 AP	21	#define SR_FS _AC(0x00006000, UL) /* Floating-point Status */
	22	#define SR_FS_OFF _AC(0x00000000, UL)
	23	#define SR_FS_INITIAL _AC(0x00002000, UL)
	24	#define SR_FS_CLEAN _AC(0x00004000, UL)
	25	#define SR_FS_DIRTY _AC(0x00006000, UL)
5d8544e2	26
196a14d4 AP	27	#define SR_XS _AC(0x00018000, UL) /* Extension Status */
	28	#define SR_XS_OFF _AC(0x00000000, UL)
	29	#define SR_XS_INITIAL _AC(0x00008000, UL)
	30	#define SR_XS_CLEAN _AC(0x00010000, UL)
	31	#define SR_XS_DIRTY _AC(0x00018000, UL)
5d8544e2 PD	32
5d8544e2 PD	33	#ifndef CONFIG_64BIT
196a14d4	34	#define SR_SD _AC(0x80000000, UL) /* FS/XS dirty */
5d8544e2	35	#else
196a14d4	36	#define SR_SD _AC(0x8000000000000000, UL) /* FS/XS dirty */
5d8544e2 PD	37	#endif
5d8544e2 PD	38
7549cdf5	39	/* SATP flags */
196a14d4 AP	40	#ifndef CONFIG_64BIT
	41	#define SATP_PPN _AC(0x003FFFFF, UL)
	42	#define SATP_MODE_32 _AC(0x80000000, UL)
	43	#define SATP_MODE SATP_MODE_32
5d8544e2	44	#else
196a14d4 AP	45	#define SATP_PPN _AC(0x00000FFFFFFFFFFF, UL)
	46	#define SATP_MODE_39 _AC(0x8000000000000000, UL)
	47	#define SATP_MODE SATP_MODE_39
5d8544e2 PD	48	#endif
5d8544e2 PD	49
a4c3733d CH	50	/* Exception cause high bit - is an interrupt if set */
a4c3733d CH	51	#define CAUSE_IRQ_FLAG (_AC(1, UL) << (__riscv_xlen - 1))
6dcaf004	52
a4c3733d	53	/* Interrupt causes (minus the high bit) */
6dcaf004 AP	54	#define IRQ_S_SOFT 1
6dcaf004 AP	55	#define IRQ_M_SOFT 3
6dcaf004 AP	56	#define IRQ_S_TIMER 5
6dcaf004 AP	57	#define IRQ_M_TIMER 7
6dcaf004 AP	58	#define IRQ_S_EXT 9
6dcaf004 AP	59	#define IRQ_M_EXT 11
5d8544e2	60
a4c3733d	61	/* Exception causes */
196a14d4 AP	62	#define EXC_INST_MISALIGNED 0
	63	#define EXC_INST_ACCESS 1
	64	#define EXC_BREAKPOINT 3
	65	#define EXC_LOAD_ACCESS 5
	66	#define EXC_STORE_ACCESS 7
	67	#define EXC_SYSCALL 8
	68	#define EXC_INST_PAGE_FAULT 12
	69	#define EXC_LOAD_PAGE_FAULT 13
	70	#define EXC_STORE_PAGE_FAULT 15
5d8544e2	71
c68a9032 GH	72	/* PMP configuration */
	73	#define PMP_R 0x01
	74	#define PMP_W 0x02
	75	#define PMP_X 0x04
	76	#define PMP_A 0x18
	77	#define PMP_A_TOR 0x08
	78	#define PMP_A_NA4 0x10
	79	#define PMP_A_NAPOT 0x18
	80	#define PMP_L 0x80
	81
a4c3733d	82	/* symbolic CSR names: */
a3182c91 AP	83	#define CSR_CYCLE 0xc00
	84	#define CSR_TIME 0xc01
	85	#define CSR_INSTRET 0xc02
a4c3733d CH	86	#define CSR_CYCLEH 0xc80
	87	#define CSR_TIMEH 0xc81
	88	#define CSR_INSTRETH 0xc82
	89
a3182c91 AP	90	#define CSR_SSTATUS 0x100
	91	#define CSR_SIE 0x104
	92	#define CSR_STVEC 0x105
	93	#define CSR_SCOUNTEREN 0x106
	94	#define CSR_SSCRATCH 0x140
	95	#define CSR_SEPC 0x141
	96	#define CSR_SCAUSE 0x142
	97	#define CSR_STVAL 0x143
	98	#define CSR_SIP 0x144
	99	#define CSR_SATP 0x180
a4c3733d CH	100
a4c3733d CH	101	#define CSR_MSTATUS 0x300
9e806356	102	#define CSR_MISA 0x301
a4c3733d CH	103	#define CSR_MIE 0x304
	104	#define CSR_MTVEC 0x305
	105	#define CSR_MSCRATCH 0x340
	106	#define CSR_MEPC 0x341
	107	#define CSR_MCAUSE 0x342
	108	#define CSR_MTVAL 0x343
	109	#define CSR_MIP 0x344
c68a9032 GH	110	#define CSR_PMPCFG0 0x3a0
c68a9032 GH	111	#define CSR_PMPADDR0 0x3b0
accb9dbc	112	#define CSR_MHARTID 0xf14
a4c3733d CH	113
	114	#ifdef CONFIG_RISCV_M_MODE
	115	# define CSR_STATUS CSR_MSTATUS
	116	# define CSR_IE CSR_MIE
	117	# define CSR_TVEC CSR_MTVEC
	118	# define CSR_SCRATCH CSR_MSCRATCH
	119	# define CSR_EPC CSR_MEPC
	120	# define CSR_CAUSE CSR_MCAUSE
	121	# define CSR_TVAL CSR_MTVAL
	122	# define CSR_IP CSR_MIP
	123
	124	# define SR_IE SR_MIE
	125	# define SR_PIE SR_MPIE
	126	# define SR_PP SR_MPP
	127
2f3035da PW	128	# define RV_IRQ_SOFT IRQ_M_SOFT
	129	# define RV_IRQ_TIMER IRQ_M_TIMER
	130	# define RV_IRQ_EXT IRQ_M_EXT
a4c3733d CH	131	#else /* CONFIG_RISCV_M_MODE */
	132	# define CSR_STATUS CSR_SSTATUS
	133	# define CSR_IE CSR_SIE
	134	# define CSR_TVEC CSR_STVEC
	135	# define CSR_SCRATCH CSR_SSCRATCH
	136	# define CSR_EPC CSR_SEPC
	137	# define CSR_CAUSE CSR_SCAUSE
	138	# define CSR_TVAL CSR_STVAL
	139	# define CSR_IP CSR_SIP
	140
	141	# define SR_IE SR_SIE
	142	# define SR_PIE SR_SPIE
	143	# define SR_PP SR_SPP
	144
2f3035da PW	145	# define RV_IRQ_SOFT IRQ_S_SOFT
	146	# define RV_IRQ_TIMER IRQ_S_TIMER
	147	# define RV_IRQ_EXT IRQ_S_EXT
a4c3733d CH	148	#endif /* CONFIG_RISCV_M_MODE */
	149
	150	/* IE/IP (Supervisor/Machine Interrupt Enable/Pending) flags */
2f3035da PW	151	#define IE_SIE (_AC(0x1, UL) << RV_IRQ_SOFT)
	152	#define IE_TIE (_AC(0x1, UL) << RV_IRQ_TIMER)
	153	#define IE_EIE (_AC(0x1, UL) << RV_IRQ_EXT)
a3182c91	154
5d8544e2 PD	155	#ifndef __ASSEMBLY__
	156
	157	#define csr_swap(csr, val) \
	158	({ \
	159	unsigned long __v = (unsigned long)(val); \
a3182c91	160	__asm__ __volatile__ ("csrrw %0, " __ASM_STR(csr) ", %1"\
5d8544e2 PD	161	: "=r" (__v) : "rK" (__v) \
	162	: "memory"); \
	163	__v; \
	164	})
	165
	166	#define csr_read(csr) \
	167	({ \
	168	register unsigned long __v; \
a3182c91	169	__asm__ __volatile__ ("csrr %0, " __ASM_STR(csr) \
5d8544e2 PD	170	: "=r" (__v) : \
	171	: "memory"); \
	172	__v; \
	173	})
	174
	175	#define csr_write(csr, val) \
	176	({ \
	177	unsigned long __v = (unsigned long)(val); \
a3182c91	178	__asm__ __volatile__ ("csrw " __ASM_STR(csr) ", %0" \
5d8544e2 PD	179	: : "rK" (__v) \
	180	: "memory"); \
	181	})
	182
	183	#define csr_read_set(csr, val) \
	184	({ \
	185	unsigned long __v = (unsigned long)(val); \
a3182c91	186	__asm__ __volatile__ ("csrrs %0, " __ASM_STR(csr) ", %1"\
5d8544e2 PD	187	: "=r" (__v) : "rK" (__v) \
	188	: "memory"); \
	189	__v; \
	190	})
	191
	192	#define csr_set(csr, val) \
	193	({ \
	194	unsigned long __v = (unsigned long)(val); \
a3182c91	195	__asm__ __volatile__ ("csrs " __ASM_STR(csr) ", %0" \
5d8544e2 PD	196	: : "rK" (__v) \
	197	: "memory"); \
	198	})
	199
	200	#define csr_read_clear(csr, val) \
	201	({ \
	202	unsigned long __v = (unsigned long)(val); \
a3182c91	203	__asm__ __volatile__ ("csrrc %0, " __ASM_STR(csr) ", %1"\
5d8544e2 PD	204	: "=r" (__v) : "rK" (__v) \
	205	: "memory"); \
	206	__v; \
	207	})
	208
	209	#define csr_clear(csr, val) \
	210	({ \
	211	unsigned long __v = (unsigned long)(val); \
a3182c91	212	__asm__ __volatile__ ("csrc " __ASM_STR(csr) ", %0" \
5d8544e2 PD	213	: : "rK" (__v) \
	214	: "memory"); \
	215	})
	216
	217	#endif /* __ASSEMBLY__ */
	218
	219	#endif /* _ASM_RISCV_CSR_H */