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Commit | Line | Data |
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dd84058d MY |
1 | menu "x86 architecture" |
2 | depends on X86 | |
3 | ||
4 | config SYS_ARCH | |
dd84058d MY |
5 | default "x86" |
6 | ||
45ccec8f MY |
7 | config USE_PRIVATE_LIBGCC |
8 | default y | |
9 | ||
dd84058d MY |
10 | choice |
11 | prompt "Target select" | |
12 | ||
13 | config TARGET_COREBOOT | |
14 | bool "Support coreboot" | |
8ef07571 SG |
15 | help |
16 | This target is used for running U-Boot on top of Coreboot. In | |
17 | this case Coreboot does the early inititalisation, and U-Boot | |
18 | takes over once the RAM, video and CPU are fully running. | |
19 | U-Boot is loaded as a fallback payload from Coreboot, in | |
20 | Coreboot terminology. This method was used for the Chromebook | |
21 | Pixel when launched. | |
22 | ||
23 | config TARGET_CHROMEBOOK_LINK | |
24 | bool "Support Chromebook link" | |
25 | help | |
26 | This is the Chromebook Pixel released in 2013. It uses an Intel | |
27 | i5 Ivybridge which is a die-shrink of Sandybridge, with 4GB of | |
28 | SDRAM. It has a Panther Point platform controller hub, PCIe | |
29 | WiFi and Bluetooth. It also includes a 720p webcam, USB SD | |
30 | reader, microphone and speakers, display port and 32GB SATA | |
31 | solid state drive. There is a Chrome OS EC connected on LPC, | |
32 | and it provides a 2560x1700 high resolution touch-enabled LCD | |
33 | display. | |
dd84058d | 34 | |
58f542de BM |
35 | config TARGET_CROWNBAY |
36 | bool "Support Intel Crown Bay CRB" | |
37 | help | |
38 | This is the Intel Crown Bay Customer Reference Board. It contains | |
39 | the Intel Atom Processor E6xx populated on the COM Express module | |
40 | with 1GB DDR2 soldered down memory and a carrier board with the | |
41 | Intel Platform Controller Hub EG20T, other system components and | |
42 | peripheral connectors for PCIe/SATA/USB/LAN/SD/UART/Audio/LVDS. | |
43 | ||
3a1a18ff SG |
44 | config TARGET_MINNOWMAX |
45 | bool "Support Intel Minnowboard MAX" | |
46 | help | |
47 | This is the Intel Minnowboard MAX. It contains an Atom E3800 | |
48 | processor in a small form factor with Ethernet, micro-SD, USB 2, | |
49 | USB 3, SATA, serial console, some GPIOs and HDMI 1.3 video out. | |
50 | It requires some binary blobs - see README.x86 for details. | |
51 | ||
52 | Note that PCIE_ECAM_BASE is set up by the FSP so the value used | |
53 | by U-Boot matches that value. | |
54 | ||
ef46bea0 BM |
55 | config TARGET_GALILEO |
56 | bool "Support Intel Galileo" | |
57 | help | |
58 | This is the Intel Galileo board, which is the first in a family of | |
59 | Arduino-certified development and prototyping boards based on Intel | |
60 | architecture. It includes an Intel Quark SoC X1000 processor, a 32-bit | |
61 | single-core, single-thread, Intel Pentium processor instrunction set | |
62 | architecture (ISA) compatible, operating at speeds up to 400Mhz, | |
63 | along with 256MB DDR3 memory. It supports a wide range of industry | |
64 | standard I/O interfaces, including a full-sized mini-PCIe slot, | |
65 | one 100Mb Ethernet port, a microSD card slot, a USB host port and | |
66 | a USB client port. | |
67 | ||
dd84058d MY |
68 | endchoice |
69 | ||
9a89d50d SG |
70 | config DM |
71 | default y | |
72 | ||
73 | config DM_GPIO | |
74 | default y | |
75 | ||
76 | config DM_SERIAL | |
77 | default y | |
78 | ||
b724bd7d SG |
79 | config SYS_MALLOC_F_LEN |
80 | default 0x800 | |
81 | ||
70a09c6c SG |
82 | config RAMBASE |
83 | hex | |
84 | default 0x100000 | |
85 | ||
70a09c6c SG |
86 | config XIP_ROM_SIZE |
87 | hex | |
7698d36a | 88 | depends on X86_RESET_VECTOR |
bbd43d65 | 89 | default ROM_SIZE |
70a09c6c SG |
90 | |
91 | config CPU_ADDR_BITS | |
92 | int | |
93 | default 36 | |
94 | ||
65dd74a6 SG |
95 | config HPET_ADDRESS |
96 | hex | |
97 | default 0xfed00000 if !HPET_ADDRESS_OVERRIDE | |
98 | ||
99 | config SMM_TSEG | |
100 | bool | |
101 | default n | |
102 | ||
103 | config SMM_TSEG_SIZE | |
104 | hex | |
105 | ||
8cb20ccc BM |
106 | config X86_RESET_VECTOR |
107 | bool | |
108 | default n | |
109 | ||
110 | config SYS_X86_START16 | |
111 | hex | |
112 | depends on X86_RESET_VECTOR | |
113 | default 0xfffff800 | |
114 | ||
64542f46 BM |
115 | config BOARD_ROMSIZE_KB_512 |
116 | bool | |
117 | config BOARD_ROMSIZE_KB_1024 | |
118 | bool | |
119 | config BOARD_ROMSIZE_KB_2048 | |
120 | bool | |
121 | config BOARD_ROMSIZE_KB_4096 | |
122 | bool | |
123 | config BOARD_ROMSIZE_KB_8192 | |
124 | bool | |
125 | config BOARD_ROMSIZE_KB_16384 | |
126 | bool | |
127 | ||
128 | choice | |
129 | prompt "ROM chip size" | |
7698d36a | 130 | depends on X86_RESET_VECTOR |
64542f46 BM |
131 | default UBOOT_ROMSIZE_KB_512 if BOARD_ROMSIZE_KB_512 |
132 | default UBOOT_ROMSIZE_KB_1024 if BOARD_ROMSIZE_KB_1024 | |
133 | default UBOOT_ROMSIZE_KB_2048 if BOARD_ROMSIZE_KB_2048 | |
134 | default UBOOT_ROMSIZE_KB_4096 if BOARD_ROMSIZE_KB_4096 | |
135 | default UBOOT_ROMSIZE_KB_8192 if BOARD_ROMSIZE_KB_8192 | |
136 | default UBOOT_ROMSIZE_KB_16384 if BOARD_ROMSIZE_KB_16384 | |
137 | help | |
138 | Select the size of the ROM chip you intend to flash U-Boot on. | |
139 | ||
140 | The build system will take care of creating a u-boot.rom file | |
141 | of the matching size. | |
142 | ||
143 | config UBOOT_ROMSIZE_KB_512 | |
144 | bool "512 KB" | |
145 | help | |
146 | Choose this option if you have a 512 KB ROM chip. | |
147 | ||
148 | config UBOOT_ROMSIZE_KB_1024 | |
149 | bool "1024 KB (1 MB)" | |
150 | help | |
151 | Choose this option if you have a 1024 KB (1 MB) ROM chip. | |
152 | ||
153 | config UBOOT_ROMSIZE_KB_2048 | |
154 | bool "2048 KB (2 MB)" | |
155 | help | |
156 | Choose this option if you have a 2048 KB (2 MB) ROM chip. | |
157 | ||
158 | config UBOOT_ROMSIZE_KB_4096 | |
159 | bool "4096 KB (4 MB)" | |
160 | help | |
161 | Choose this option if you have a 4096 KB (4 MB) ROM chip. | |
162 | ||
163 | config UBOOT_ROMSIZE_KB_8192 | |
164 | bool "8192 KB (8 MB)" | |
165 | help | |
166 | Choose this option if you have a 8192 KB (8 MB) ROM chip. | |
167 | ||
168 | config UBOOT_ROMSIZE_KB_16384 | |
169 | bool "16384 KB (16 MB)" | |
170 | help | |
171 | Choose this option if you have a 16384 KB (16 MB) ROM chip. | |
172 | ||
173 | endchoice | |
174 | ||
175 | # Map the config names to an integer (KB). | |
176 | config UBOOT_ROMSIZE_KB | |
177 | int | |
178 | default 512 if UBOOT_ROMSIZE_KB_512 | |
179 | default 1024 if UBOOT_ROMSIZE_KB_1024 | |
180 | default 2048 if UBOOT_ROMSIZE_KB_2048 | |
181 | default 4096 if UBOOT_ROMSIZE_KB_4096 | |
182 | default 8192 if UBOOT_ROMSIZE_KB_8192 | |
183 | default 16384 if UBOOT_ROMSIZE_KB_16384 | |
184 | ||
185 | # Map the config names to a hex value (bytes). | |
fce7b276 SG |
186 | config ROM_SIZE |
187 | hex | |
64542f46 BM |
188 | default 0x80000 if UBOOT_ROMSIZE_KB_512 |
189 | default 0x100000 if UBOOT_ROMSIZE_KB_1024 | |
190 | default 0x200000 if UBOOT_ROMSIZE_KB_2048 | |
191 | default 0x400000 if UBOOT_ROMSIZE_KB_4096 | |
192 | default 0x800000 if UBOOT_ROMSIZE_KB_8192 | |
193 | default 0xc00000 if UBOOT_ROMSIZE_KB_12288 | |
194 | default 0x1000000 if UBOOT_ROMSIZE_KB_16384 | |
fce7b276 SG |
195 | |
196 | config HAVE_INTEL_ME | |
197 | bool "Platform requires Intel Management Engine" | |
198 | help | |
199 | Newer higher-end devices have an Intel Management Engine (ME) | |
200 | which is a very large binary blob (typically 1.5MB) which is | |
201 | required for the platform to work. This enforces a particular | |
202 | SPI flash format. You will need to supply the me.bin file in | |
203 | your board directory. | |
204 | ||
65dd74a6 SG |
205 | config X86_RAMTEST |
206 | bool "Perform a simple RAM test after SDRAM initialisation" | |
207 | help | |
208 | If there is something wrong with SDRAM then the platform will | |
209 | often crash within U-Boot or the kernel. This option enables a | |
210 | very simple RAM test that quickly checks whether the SDRAM seems | |
211 | to work correctly. It is not exhaustive but can save time by | |
212 | detecting obvious failures. | |
213 | ||
22465fc4 SG |
214 | config MARK_GRAPHICS_MEM_WRCOMB |
215 | bool "Mark graphics memory as write-combining." | |
216 | default n | |
217 | help | |
218 | The graphics performance may increase if the graphics | |
219 | memory is set as write-combining cache type. This option | |
220 | enables marking the graphics memory as write-combining. | |
221 | ||
222 | menu "Display" | |
223 | ||
224 | config FRAMEBUFFER_SET_VESA_MODE | |
225 | prompt "Set framebuffer graphics resolution" | |
226 | bool | |
227 | help | |
228 | Set VESA/native framebuffer mode (needed for bootsplash and graphical framebuffer console) | |
229 | ||
230 | choice | |
231 | prompt "framebuffer graphics resolution" | |
232 | default FRAMEBUFFER_VESA_MODE_117 | |
233 | depends on FRAMEBUFFER_SET_VESA_MODE | |
234 | help | |
235 | This option sets the resolution used for the coreboot framebuffer (and | |
236 | bootsplash screen). | |
237 | ||
238 | config FRAMEBUFFER_VESA_MODE_100 | |
239 | bool "640x400 256-color" | |
240 | ||
241 | config FRAMEBUFFER_VESA_MODE_101 | |
242 | bool "640x480 256-color" | |
243 | ||
244 | config FRAMEBUFFER_VESA_MODE_102 | |
245 | bool "800x600 16-color" | |
246 | ||
247 | config FRAMEBUFFER_VESA_MODE_103 | |
248 | bool "800x600 256-color" | |
249 | ||
250 | config FRAMEBUFFER_VESA_MODE_104 | |
251 | bool "1024x768 16-color" | |
252 | ||
253 | config FRAMEBUFFER_VESA_MODE_105 | |
254 | bool "1024x7686 256-color" | |
255 | ||
256 | config FRAMEBUFFER_VESA_MODE_106 | |
257 | bool "1280x1024 16-color" | |
258 | ||
259 | config FRAMEBUFFER_VESA_MODE_107 | |
260 | bool "1280x1024 256-color" | |
261 | ||
262 | config FRAMEBUFFER_VESA_MODE_108 | |
263 | bool "80x60 text" | |
264 | ||
265 | config FRAMEBUFFER_VESA_MODE_109 | |
266 | bool "132x25 text" | |
267 | ||
268 | config FRAMEBUFFER_VESA_MODE_10A | |
269 | bool "132x43 text" | |
270 | ||
271 | config FRAMEBUFFER_VESA_MODE_10B | |
272 | bool "132x50 text" | |
273 | ||
274 | config FRAMEBUFFER_VESA_MODE_10C | |
275 | bool "132x60 text" | |
276 | ||
277 | config FRAMEBUFFER_VESA_MODE_10D | |
278 | bool "320x200 32k-color (1:5:5:5)" | |
279 | ||
280 | config FRAMEBUFFER_VESA_MODE_10E | |
281 | bool "320x200 64k-color (5:6:5)" | |
282 | ||
283 | config FRAMEBUFFER_VESA_MODE_10F | |
284 | bool "320x200 16.8M-color (8:8:8)" | |
285 | ||
286 | config FRAMEBUFFER_VESA_MODE_110 | |
287 | bool "640x480 32k-color (1:5:5:5)" | |
288 | ||
289 | config FRAMEBUFFER_VESA_MODE_111 | |
290 | bool "640x480 64k-color (5:6:5)" | |
291 | ||
292 | config FRAMEBUFFER_VESA_MODE_112 | |
293 | bool "640x480 16.8M-color (8:8:8)" | |
294 | ||
295 | config FRAMEBUFFER_VESA_MODE_113 | |
296 | bool "800x600 32k-color (1:5:5:5)" | |
297 | ||
298 | config FRAMEBUFFER_VESA_MODE_114 | |
299 | bool "800x600 64k-color (5:6:5)" | |
300 | ||
301 | config FRAMEBUFFER_VESA_MODE_115 | |
302 | bool "800x600 16.8M-color (8:8:8)" | |
303 | ||
304 | config FRAMEBUFFER_VESA_MODE_116 | |
305 | bool "1024x768 32k-color (1:5:5:5)" | |
306 | ||
307 | config FRAMEBUFFER_VESA_MODE_117 | |
308 | bool "1024x768 64k-color (5:6:5)" | |
309 | ||
310 | config FRAMEBUFFER_VESA_MODE_118 | |
311 | bool "1024x768 16.8M-color (8:8:8)" | |
312 | ||
313 | config FRAMEBUFFER_VESA_MODE_119 | |
314 | bool "1280x1024 32k-color (1:5:5:5)" | |
315 | ||
316 | config FRAMEBUFFER_VESA_MODE_11A | |
317 | bool "1280x1024 64k-color (5:6:5)" | |
318 | ||
319 | config FRAMEBUFFER_VESA_MODE_11B | |
320 | bool "1280x1024 16.8M-color (8:8:8)" | |
321 | ||
322 | config FRAMEBUFFER_VESA_MODE_USER | |
323 | bool "Manually select VESA mode" | |
324 | ||
325 | endchoice | |
326 | ||
327 | # Map the config names to an integer (KB). | |
328 | config FRAMEBUFFER_VESA_MODE | |
329 | prompt "VESA mode" if FRAMEBUFFER_VESA_MODE_USER | |
330 | hex | |
331 | default 0x100 if FRAMEBUFFER_VESA_MODE_100 | |
332 | default 0x101 if FRAMEBUFFER_VESA_MODE_101 | |
333 | default 0x102 if FRAMEBUFFER_VESA_MODE_102 | |
334 | default 0x103 if FRAMEBUFFER_VESA_MODE_103 | |
335 | default 0x104 if FRAMEBUFFER_VESA_MODE_104 | |
336 | default 0x105 if FRAMEBUFFER_VESA_MODE_105 | |
337 | default 0x106 if FRAMEBUFFER_VESA_MODE_106 | |
338 | default 0x107 if FRAMEBUFFER_VESA_MODE_107 | |
339 | default 0x108 if FRAMEBUFFER_VESA_MODE_108 | |
340 | default 0x109 if FRAMEBUFFER_VESA_MODE_109 | |
341 | default 0x10A if FRAMEBUFFER_VESA_MODE_10A | |
342 | default 0x10B if FRAMEBUFFER_VESA_MODE_10B | |
343 | default 0x10C if FRAMEBUFFER_VESA_MODE_10C | |
344 | default 0x10D if FRAMEBUFFER_VESA_MODE_10D | |
345 | default 0x10E if FRAMEBUFFER_VESA_MODE_10E | |
346 | default 0x10F if FRAMEBUFFER_VESA_MODE_10F | |
347 | default 0x110 if FRAMEBUFFER_VESA_MODE_110 | |
348 | default 0x111 if FRAMEBUFFER_VESA_MODE_111 | |
349 | default 0x112 if FRAMEBUFFER_VESA_MODE_112 | |
350 | default 0x113 if FRAMEBUFFER_VESA_MODE_113 | |
351 | default 0x114 if FRAMEBUFFER_VESA_MODE_114 | |
352 | default 0x115 if FRAMEBUFFER_VESA_MODE_115 | |
353 | default 0x116 if FRAMEBUFFER_VESA_MODE_116 | |
354 | default 0x117 if FRAMEBUFFER_VESA_MODE_117 | |
355 | default 0x118 if FRAMEBUFFER_VESA_MODE_118 | |
356 | default 0x119 if FRAMEBUFFER_VESA_MODE_119 | |
357 | default 0x11A if FRAMEBUFFER_VESA_MODE_11A | |
358 | default 0x11B if FRAMEBUFFER_VESA_MODE_11B | |
359 | default 0x117 if FRAMEBUFFER_VESA_MODE_USER | |
360 | ||
361 | endmenu | |
362 | ||
8ce24cd9 SG |
363 | config HAVE_FSP |
364 | bool "Add an Firmware Support Package binary" | |
365 | help | |
366 | Select this option to add an Firmware Support Package binary to | |
367 | the resulting U-Boot image. It is a binary blob which U-Boot uses | |
368 | to set up SDRAM and other chipset specific initialization. | |
369 | ||
370 | Note: Without this binary U-Boot will not be able to set up its | |
371 | SDRAM so will not boot. | |
372 | ||
373 | config FSP_FILE | |
374 | string "Firmware Support Package binary filename" | |
375 | depends on HAVE_FSP | |
376 | default "fsp.bin" | |
377 | help | |
378 | The filename of the file to use as Firmware Support Package binary | |
379 | in the board directory. | |
380 | ||
381 | config FSP_ADDR | |
382 | hex "Firmware Support Package binary location" | |
383 | depends on HAVE_FSP | |
384 | default 0xfffc0000 | |
385 | help | |
386 | FSP is not Position Independent Code (PIC) and the whole FSP has to | |
387 | be rebased if it is placed at a location which is different from the | |
388 | perferred base address specified during the FSP build. Use Intel's | |
389 | Binary Configuration Tool (BCT) to do the rebase. | |
390 | ||
391 | The default base address of 0xfffc0000 indicates that the binary must | |
392 | be located at offset 0xc0000 from the beginning of a 1MB flash device. | |
393 | ||
394 | config FSP_TEMP_RAM_ADDR | |
395 | hex | |
396 | default 0x2000000 | |
397 | help | |
398 | Stack top address which is used in FspInit after DRAM is ready and | |
399 | CAR is disabled. | |
400 | ||
3a1a18ff SG |
401 | source "arch/x86/cpu/baytrail/Kconfig" |
402 | ||
9d74f034 BM |
403 | source "arch/x86/cpu/coreboot/Kconfig" |
404 | ||
8ef07571 SG |
405 | source "arch/x86/cpu/ivybridge/Kconfig" |
406 | ||
ef46bea0 BM |
407 | source "arch/x86/cpu/quark/Kconfig" |
408 | ||
58f542de BM |
409 | source "arch/x86/cpu/queensbay/Kconfig" |
410 | ||
f56aeaa4 BM |
411 | config TSC_CALIBRATION_BYPASS |
412 | bool "Bypass Time-Stamp Counter (TSC) calibration" | |
413 | default n | |
414 | help | |
415 | By default U-Boot automatically calibrates Time-Stamp Counter (TSC) | |
416 | running frequency via Model-Specific Register (MSR) and Programmable | |
417 | Interval Timer (PIT). If the calibration does not work on your board, | |
418 | select this option and provide a hardcoded TSC running frequency with | |
419 | CONFIG_TSC_FREQ_IN_MHZ below. | |
420 | ||
421 | Normally this option should be turned on in a simulation environment | |
422 | like qemu. | |
423 | ||
424 | config TSC_FREQ_IN_MHZ | |
425 | int "Time-Stamp Counter (TSC) running frequency in MHz" | |
426 | depends on TSC_CALIBRATION_BYPASS | |
427 | default 1000 | |
428 | help | |
429 | The running frequency in MHz of Time-Stamp Counter (TSC). | |
430 | ||
fe5b9b44 | 431 | source "board/coreboot/coreboot/Kconfig" |
dd84058d | 432 | |
8ef07571 SG |
433 | source "board/google/chromebook_link/Kconfig" |
434 | ||
58f542de BM |
435 | source "board/intel/crownbay/Kconfig" |
436 | ||
3a1a18ff SG |
437 | source "board/intel/minnowmax/Kconfig" |
438 | ||
ef46bea0 BM |
439 | source "board/intel/galileo/Kconfig" |
440 | ||
2d934e57 SG |
441 | config PCIE_ECAM_BASE |
442 | hex | |
ba877efb | 443 | default 0xe0000000 |
2d934e57 SG |
444 | help |
445 | This is the memory-mapped address of PCI configuration space, which | |
446 | is only available through the Enhanced Configuration Access | |
447 | Mechanism (ECAM) with PCI Express. It can be set up almost | |
448 | anywhere. Before it is set up, it is possible to access PCI | |
449 | configuration space through I/O access, but memory access is more | |
450 | convenient. Using this, PCI can be scanned and configured. This | |
451 | should be set to a region that does not conflict with memory | |
452 | assigned to PCI devices - i.e. the memory and prefetch regions, as | |
453 | passed to pci_set_region(). | |
454 | ||
dd84058d | 455 | endmenu |