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8e1a3fe5 SR |
1 | /* |
2 | * (C) Copyright 2008 | |
3 | * Stefan Roese, DENX Software Engineering, sr@denx.de. | |
4 | * | |
5 | * This program is free software; you can redistribute it and/or | |
6 | * modify it under the terms of the GNU General Public License as | |
7 | * published by the Free Software Foundation; either version 2 of | |
8 | * the License, or (at your option) any later version. | |
9 | * | |
10 | * This program is distributed in the hope that it will be useful, | |
11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
13 | * GNU General Public License for more details. | |
14 | * | |
15 | * You should have received a copy of the GNU General Public License | |
16 | * along with this program; if not, write to the Free Software | |
17 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
18 | * MA 02111-1307 USA | |
19 | */ | |
20 | ||
21 | #include <common.h> | |
22 | #include <ppc440.h> | |
23 | #include <libfdt.h> | |
24 | #include <fdt_support.h> | |
212ed906 | 25 | #include <i2c.h> |
8e1a3fe5 SR |
26 | #include <asm/processor.h> |
27 | #include <asm/io.h> | |
28 | #include <asm/mmu.h> | |
29 | #include <asm/4xx_pcie.h> | |
41712b4e | 30 | #include <asm/gpio.h> |
06dfaeef | 31 | #include <asm/errno.h> |
8e1a3fe5 | 32 | |
6d0f6bcf | 33 | extern flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */ |
8e1a3fe5 SR |
34 | |
35 | DECLARE_GLOBAL_DATA_PTR; | |
36 | ||
6d0f6bcf | 37 | #define CONFIG_SYS_BCSR3_PCIE 0x10 |
cc8e839a SR |
38 | |
39 | #define BOARD_CANYONLANDS_PCIE 1 | |
40 | #define BOARD_CANYONLANDS_SATA 2 | |
41 | #define BOARD_GLACIER 3 | |
f09f09d3 AG |
42 | #define BOARD_ARCHES 4 |
43 | ||
f3ed3c9b | 44 | /* |
a47a12be | 45 | * Override the default functions in arch/powerpc/cpu/ppc4xx/44x_spd_ddr2.c with |
f3ed3c9b SR |
46 | * board specific values. |
47 | */ | |
48 | #if defined(CONFIG_ARCHES) | |
49 | u32 ddr_wrdtr(u32 default_val) { | |
50 | return (SDRAM_WRDTR_LLWP_1_CYC | SDRAM_WRDTR_WTR_0_DEG | 0x823); | |
51 | } | |
52 | #else | |
53 | u32 ddr_wrdtr(u32 default_val) { | |
54 | return (SDRAM_WRDTR_LLWP_1_CYC | SDRAM_WRDTR_WTR_180_DEG_ADV | 0x823); | |
55 | } | |
56 | ||
57 | u32 ddr_clktr(u32 default_val) { | |
58 | return (SDRAM_CLKTR_CLKP_90_DEG_ADV); | |
59 | } | |
60 | #endif | |
61 | ||
f09f09d3 AG |
62 | #if defined(CONFIG_ARCHES) |
63 | /* | |
64 | * FPGA read/write helper macros | |
65 | */ | |
66 | static inline int board_fpga_read(int offset) | |
67 | { | |
68 | int data; | |
69 | ||
70 | data = in_8((void *)(CONFIG_SYS_FPGA_BASE + offset)); | |
71 | ||
72 | return data; | |
73 | } | |
74 | ||
75 | static inline void board_fpga_write(int offset, int data) | |
76 | { | |
77 | out_8((void *)(CONFIG_SYS_FPGA_BASE + offset), data); | |
78 | } | |
79 | ||
80 | /* | |
81 | * CPLD read/write helper macros | |
82 | */ | |
83 | static inline int board_cpld_read(int offset) | |
84 | { | |
85 | int data; | |
86 | ||
87 | out_8((void *)(CONFIG_SYS_CPLD_ADDR), offset); | |
88 | data = in_8((void *)(CONFIG_SYS_CPLD_DATA)); | |
89 | ||
90 | return data; | |
91 | } | |
92 | ||
93 | static inline void board_cpld_write(int offset, int data) | |
94 | { | |
95 | out_8((void *)(CONFIG_SYS_CPLD_ADDR), offset); | |
96 | out_8((void *)(CONFIG_SYS_CPLD_DATA), data); | |
97 | } | |
c3fa4f0c SR |
98 | #else |
99 | static int pvr_460ex(void) | |
100 | { | |
101 | u32 pvr = get_pvr(); | |
102 | ||
103 | if ((pvr == PVR_460EX_RA) || (pvr == PVR_460EX_SE_RA) || | |
104 | (pvr == PVR_460EX_RB)) | |
105 | return 1; | |
106 | ||
107 | return 0; | |
108 | } | |
f09f09d3 | 109 | #endif /* defined(CONFIG_ARCHES) */ |
cc8e839a | 110 | |
8e1a3fe5 SR |
111 | int board_early_init_f(void) |
112 | { | |
f09f09d3 | 113 | #if !defined(CONFIG_ARCHES) |
8e1a3fe5 | 114 | u32 sdr0_cust0; |
f09f09d3 | 115 | #endif |
8e1a3fe5 | 116 | |
1c2926ab | 117 | /* |
8e1a3fe5 | 118 | * Setup the interrupt controller polarities, triggers, etc. |
1c2926ab | 119 | */ |
952e7760 SR |
120 | mtdcr(UIC0SR, 0xffffffff); /* clear all */ |
121 | mtdcr(UIC0ER, 0x00000000); /* disable all */ | |
122 | mtdcr(UIC0CR, 0x00000005); /* ATI & UIC1 crit are critical */ | |
123 | mtdcr(UIC0PR, 0xffffffff); /* per ref-board manual */ | |
124 | mtdcr(UIC0TR, 0x00000000); /* per ref-board manual */ | |
125 | mtdcr(UIC0VR, 0x00000000); /* int31 highest, base=0x000 */ | |
126 | mtdcr(UIC0SR, 0xffffffff); /* clear all */ | |
127 | ||
128 | mtdcr(UIC1SR, 0xffffffff); /* clear all */ | |
129 | mtdcr(UIC1ER, 0x00000000); /* disable all */ | |
130 | mtdcr(UIC1CR, 0x00000000); /* all non-critical */ | |
131 | mtdcr(UIC1PR, 0xffffffff); /* per ref-board manual */ | |
132 | mtdcr(UIC1TR, 0x00000000); /* per ref-board manual */ | |
133 | mtdcr(UIC1VR, 0x00000000); /* int31 highest, base=0x000 */ | |
134 | mtdcr(UIC1SR, 0xffffffff); /* clear all */ | |
135 | ||
136 | mtdcr(UIC2SR, 0xffffffff); /* clear all */ | |
137 | mtdcr(UIC2ER, 0x00000000); /* disable all */ | |
138 | mtdcr(UIC2CR, 0x00000000); /* all non-critical */ | |
139 | mtdcr(UIC2PR, 0xffffffff); /* per ref-board manual */ | |
140 | mtdcr(UIC2TR, 0x00000000); /* per ref-board manual */ | |
141 | mtdcr(UIC2VR, 0x00000000); /* int31 highest, base=0x000 */ | |
142 | mtdcr(UIC2SR, 0xffffffff); /* clear all */ | |
143 | ||
144 | mtdcr(UIC3SR, 0xffffffff); /* clear all */ | |
145 | mtdcr(UIC3ER, 0x00000000); /* disable all */ | |
146 | mtdcr(UIC3CR, 0x00000000); /* all non-critical */ | |
147 | mtdcr(UIC3PR, 0xffffffff); /* per ref-board manual */ | |
148 | mtdcr(UIC3TR, 0x00000000); /* per ref-board manual */ | |
149 | mtdcr(UIC3VR, 0x00000000); /* int31 highest, base=0x000 */ | |
150 | mtdcr(UIC3SR, 0xffffffff); /* clear all */ | |
8e1a3fe5 | 151 | |
f09f09d3 | 152 | #if !defined(CONFIG_ARCHES) |
8e1a3fe5 SR |
153 | /* SDR Setting - enable NDFC */ |
154 | mfsdr(SDR0_CUST0, sdr0_cust0); | |
155 | sdr0_cust0 = SDR0_CUST0_MUX_NDFC_SEL | | |
156 | SDR0_CUST0_NDFC_ENABLE | | |
157 | SDR0_CUST0_NDFC_BW_8_BIT | | |
158 | SDR0_CUST0_NDFC_ARE_MASK | | |
159 | SDR0_CUST0_NDFC_BAC_ENCODE(3) | | |
6d0f6bcf | 160 | (0x80000000 >> (28 + CONFIG_SYS_NAND_CS)); |
8e1a3fe5 | 161 | mtsdr(SDR0_CUST0, sdr0_cust0); |
f09f09d3 | 162 | #endif |
8e1a3fe5 SR |
163 | |
164 | /* | |
165 | * Configure PFC (Pin Function Control) registers | |
166 | * UART0: 4 pins | |
167 | */ | |
168 | mtsdr(SDR0_PFC1, 0x00040000); | |
169 | ||
170 | /* Enable PCI host functionality in SDR0_PCI0 */ | |
171 | mtsdr(SDR0_PCI0, 0xe0000000); | |
172 | ||
f09f09d3 | 173 | #if !defined(CONFIG_ARCHES) |
8e1a3fe5 | 174 | /* Enable ethernet and take out of reset */ |
6d0f6bcf | 175 | out_8((void *)CONFIG_SYS_BCSR_BASE + 6, 0); |
8e1a3fe5 SR |
176 | |
177 | /* Remove NOR-FLASH, NAND-FLASH & EEPROM hardware write protection */ | |
6d0f6bcf | 178 | out_8((void *)CONFIG_SYS_BCSR_BASE + 5, 0); |
8e1a3fe5 SR |
179 | |
180 | /* Enable USB host & USB-OTG */ | |
6d0f6bcf | 181 | out_8((void *)CONFIG_SYS_BCSR_BASE + 7, 0); |
8e1a3fe5 SR |
182 | |
183 | mtsdr(SDR0_SRST1, 0); /* Pull AHB out of reset default=1 */ | |
184 | ||
41712b4e SR |
185 | /* Setup PLB4-AHB bridge based on the system address map */ |
186 | mtdcr(AHB_TOP, 0x8000004B); | |
187 | mtdcr(AHB_BOT, 0x8000004B); | |
188 | ||
c3fa4f0c | 189 | if (pvr_460ex()) { |
4c9e8557 SR |
190 | /* |
191 | * Configure USB-STP pins as alternate and not GPIO | |
192 | * It seems to be neccessary to configure the STP pins as GPIO | |
193 | * input at powerup (perhaps while USB reset is asserted). So | |
194 | * we configure those pins to their "real" function now. | |
195 | */ | |
196 | gpio_config(16, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1); | |
197 | gpio_config(19, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1); | |
198 | } | |
f09f09d3 | 199 | #endif |
41712b4e | 200 | |
8e1a3fe5 SR |
201 | return 0; |
202 | } | |
203 | ||
f09f09d3 | 204 | #if !defined(CONFIG_ARCHES) |
1c2926ab SR |
205 | static void canyonlands_sata_init(int board_type) |
206 | { | |
207 | u32 reg; | |
208 | ||
209 | if (board_type == BOARD_CANYONLANDS_SATA) { | |
210 | /* Put SATA in reset */ | |
211 | SDR_WRITE(SDR0_SRST1, 0x00020001); | |
212 | ||
213 | /* Set the phy for SATA, not PCI-E port 0 */ | |
214 | reg = SDR_READ(PESDR0_PHY_CTL_RST); | |
215 | SDR_WRITE(PESDR0_PHY_CTL_RST, (reg & 0xeffffffc) | 0x00000001); | |
216 | reg = SDR_READ(PESDR0_L0CLK); | |
217 | SDR_WRITE(PESDR0_L0CLK, (reg & 0xfffffff8) | 0x00000007); | |
218 | SDR_WRITE(PESDR0_L0CDRCTL, 0x00003111); | |
219 | SDR_WRITE(PESDR0_L0DRV, 0x00000104); | |
220 | ||
221 | /* Bring SATA out of reset */ | |
222 | SDR_WRITE(SDR0_SRST1, 0x00000000); | |
223 | } | |
224 | } | |
f09f09d3 AG |
225 | #endif /* !defined(CONFIG_ARCHES) */ |
226 | ||
227 | int get_cpu_num(void) | |
228 | { | |
229 | int cpu = NA_OR_UNKNOWN_CPU; | |
230 | ||
231 | #if defined(CONFIG_ARCHES) | |
232 | int cpu_num; | |
233 | ||
234 | cpu_num = board_fpga_read(0x3); | |
235 | ||
236 | /* sanity check; assume cpu numbering starts and increments from 0 */ | |
237 | if ((cpu_num >= 0) && (cpu_num < CONFIG_BD_NUM_CPUS)) | |
238 | cpu = cpu_num; | |
239 | #endif | |
240 | ||
241 | return cpu; | |
242 | } | |
1c2926ab | 243 | |
f09f09d3 | 244 | #if !defined(CONFIG_ARCHES) |
1c2926ab | 245 | int checkboard(void) |
8e1a3fe5 SR |
246 | { |
247 | char *s = getenv("serial#"); | |
8e1a3fe5 | 248 | |
c3fa4f0c | 249 | if (pvr_460ex()) { |
8e1a3fe5 | 250 | printf("Board: Canyonlands - AMCC PPC460EX Evaluation Board"); |
6d0f6bcf | 251 | if (in_8((void *)(CONFIG_SYS_BCSR_BASE + 3)) & CONFIG_SYS_BCSR3_PCIE) |
cc8e839a SR |
252 | gd->board_type = BOARD_CANYONLANDS_PCIE; |
253 | else | |
254 | gd->board_type = BOARD_CANYONLANDS_SATA; | |
c3fa4f0c SR |
255 | } else { |
256 | printf("Board: Glacier - AMCC PPC460GT Evaluation Board"); | |
257 | gd->board_type = BOARD_GLACIER; | |
cc8e839a SR |
258 | } |
259 | ||
260 | switch (gd->board_type) { | |
261 | case BOARD_CANYONLANDS_PCIE: | |
262 | case BOARD_GLACIER: | |
263 | puts(", 2*PCIe"); | |
264 | break; | |
265 | ||
266 | case BOARD_CANYONLANDS_SATA: | |
267 | puts(", 1*PCIe/1*SATA"); | |
268 | break; | |
269 | } | |
270 | ||
6d0f6bcf | 271 | printf(", Rev. %X", in_8((void *)(CONFIG_SYS_BCSR_BASE + 0))); |
8e1a3fe5 SR |
272 | |
273 | if (s != NULL) { | |
274 | puts(", serial# "); | |
275 | puts(s); | |
276 | } | |
277 | putc('\n'); | |
278 | ||
1c2926ab SR |
279 | canyonlands_sata_init(gd->board_type); |
280 | ||
8e1a3fe5 SR |
281 | return (0); |
282 | } | |
283 | ||
f09f09d3 AG |
284 | #else /* defined(CONFIG_ARCHES) */ |
285 | ||
286 | int checkboard(void) | |
287 | { | |
288 | char *s = getenv("serial#"); | |
289 | ||
290 | printf("Board: Arches - AMCC DUAL PPC460GT Reference Design\n"); | |
291 | printf(" Revision %02x.%02x ", | |
292 | board_fpga_read(0x0), board_fpga_read(0x1)); | |
293 | ||
294 | gd->board_type = BOARD_ARCHES; | |
295 | ||
296 | /* Only CPU0 has access to CPLD registers */ | |
297 | if (get_cpu_num() == 0) { | |
298 | u8 cfg_sw = board_cpld_read(0x1); | |
299 | printf("(FPGA=%02x, CPLD=%02x)\n", | |
300 | board_fpga_read(0x2), board_cpld_read(0x0)); | |
301 | printf(" Configuration Switch %d%d%d%d\n", | |
302 | ((cfg_sw >> 3) & 0x01), | |
303 | ((cfg_sw >> 2) & 0x01), | |
304 | ((cfg_sw >> 1) & 0x01), | |
305 | ((cfg_sw >> 0) & 0x01)); | |
306 | } else | |
307 | printf("(FPGA=%02x, CPLD=xx)\n", board_fpga_read(0x2)); | |
308 | ||
309 | ||
310 | if (s != NULL) | |
311 | printf(" Serial# %s\n", s); | |
312 | ||
313 | return 0; | |
314 | } | |
315 | #endif /* !defined(CONFIG_ARCHES) */ | |
316 | ||
71665ebf SR |
317 | #if defined(CONFIG_NAND_U_BOOT) |
318 | /* | |
319 | * NAND booting U-Boot version uses a fixed initialization, since the whole | |
320 | * I2C SPD DIMM autodetection/calibration doesn't fit into the 4k of boot | |
321 | * code. | |
322 | */ | |
9973e3c6 | 323 | phys_size_t initdram(int board_type) |
71665ebf | 324 | { |
6d0f6bcf | 325 | return CONFIG_SYS_MBYTES_SDRAM << 20; |
71665ebf SR |
326 | } |
327 | #endif | |
328 | ||
8e1a3fe5 | 329 | #if defined(CONFIG_PCI) |
b0b86746 | 330 | int board_pcie_first(void) |
8e1a3fe5 | 331 | { |
cc8e839a SR |
332 | /* |
333 | * Canyonlands with SATA enabled has only one PCIe slot | |
334 | * (2nd one). | |
335 | */ | |
336 | if (gd->board_type == BOARD_CANYONLANDS_SATA) | |
b0b86746 | 337 | return 1; |
8e1a3fe5 | 338 | |
b0b86746 | 339 | return 0; |
8e1a3fe5 SR |
340 | } |
341 | #endif /* CONFIG_PCI */ | |
342 | ||
343 | int board_early_init_r (void) | |
344 | { | |
345 | /* | |
346 | * Canyonlands has 64MBytes of NOR FLASH (Spansion 29GL512), but the | |
347 | * boot EBC mapping only supports a maximum of 16MBytes | |
348 | * (4.ff00.0000 - 4.ffff.ffff). | |
349 | * To solve this problem, the FLASH has to get remapped to another | |
350 | * EBC address which accepts bigger regions: | |
351 | * | |
352 | * 0xfc00.0000 -> 4.cc00.0000 | |
8e1a3fe5 SR |
353 | */ |
354 | ||
355 | /* Remap the NOR FLASH to 0xcc00.0000 ... 0xcfff.ffff */ | |
71665ebf | 356 | #if defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL) |
d1c3b275 | 357 | mtebc(PB3CR, CONFIG_SYS_FLASH_BASE_PHYS_L | 0xda000); |
71665ebf | 358 | #else |
d1c3b275 | 359 | mtebc(PB0CR, CONFIG_SYS_FLASH_BASE_PHYS_L | 0xda000); |
71665ebf | 360 | #endif |
8e1a3fe5 SR |
361 | |
362 | /* Remove TLB entry of boot EBC mapping */ | |
6d0f6bcf | 363 | remove_tlb(CONFIG_SYS_BOOT_BASE_ADDR, 16 << 20); |
8e1a3fe5 SR |
364 | |
365 | /* Add TLB entry for 0xfc00.0000 -> 0x4.cc00.0000 */ | |
6d0f6bcf | 366 | program_tlb(CONFIG_SYS_FLASH_BASE_PHYS, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_SIZE, |
8e1a3fe5 SR |
367 | TLB_WORD2_I_ENABLE); |
368 | ||
369 | /* | |
370 | * Now accessing of the whole 64Mbytes of NOR FLASH at virtual address | |
371 | * 0xfc00.0000 is possible | |
372 | */ | |
373 | ||
71665ebf SR |
374 | /* |
375 | * Clear potential errors resulting from auto-calibration. | |
376 | * If not done, then we could get an interrupt later on when | |
377 | * exceptions are enabled. | |
378 | */ | |
379 | set_mcsr(get_mcsr()); | |
380 | ||
8e1a3fe5 SR |
381 | return 0; |
382 | } | |
383 | ||
f09f09d3 | 384 | #if !defined(CONFIG_ARCHES) |
8e1a3fe5 SR |
385 | int misc_init_r(void) |
386 | { | |
387 | u32 sdr0_srst1 = 0; | |
388 | u32 eth_cfg; | |
212ed906 | 389 | u8 val; |
8e1a3fe5 SR |
390 | |
391 | /* | |
392 | * Set EMAC mode/configuration (GMII, SGMII, RGMII...). | |
393 | * This is board specific, so let's do it here. | |
394 | */ | |
395 | mfsdr(SDR0_ETH_CFG, eth_cfg); | |
396 | /* disable SGMII mode */ | |
397 | eth_cfg &= ~(SDR0_ETH_CFG_SGMII2_ENABLE | | |
398 | SDR0_ETH_CFG_SGMII1_ENABLE | | |
399 | SDR0_ETH_CFG_SGMII0_ENABLE); | |
400 | /* Set the for 2 RGMII mode */ | |
401 | /* GMC0 EMAC4_0, GMC0 EMAC4_1, RGMII Bridge 0 */ | |
402 | eth_cfg &= ~SDR0_ETH_CFG_GMC0_BRIDGE_SEL; | |
c3fa4f0c | 403 | if (pvr_460ex()) |
4c9e8557 SR |
404 | eth_cfg |= SDR0_ETH_CFG_GMC1_BRIDGE_SEL; |
405 | else | |
406 | eth_cfg &= ~SDR0_ETH_CFG_GMC1_BRIDGE_SEL; | |
8e1a3fe5 SR |
407 | mtsdr(SDR0_ETH_CFG, eth_cfg); |
408 | ||
409 | /* | |
410 | * The AHB Bridge core is held in reset after power-on or reset | |
411 | * so enable it now | |
412 | */ | |
413 | mfsdr(SDR0_SRST1, sdr0_srst1); | |
414 | sdr0_srst1 &= ~SDR0_SRST1_AHB; | |
415 | mtsdr(SDR0_SRST1, sdr0_srst1); | |
416 | ||
212ed906 SR |
417 | /* |
418 | * RTC/M41T62: | |
419 | * Disable square wave output: Batterie will be drained | |
420 | * quickly, when this output is not disabled | |
421 | */ | |
6d0f6bcf | 422 | val = i2c_reg_read(CONFIG_SYS_I2C_RTC_ADDR, 0xa); |
212ed906 | 423 | val &= ~0x40; |
6d0f6bcf | 424 | i2c_reg_write(CONFIG_SYS_I2C_RTC_ADDR, 0xa, val); |
212ed906 | 425 | |
8e1a3fe5 SR |
426 | return 0; |
427 | } | |
428 | ||
f09f09d3 AG |
429 | #else /* defined(CONFIG_ARCHES) */ |
430 | ||
431 | int misc_init_r(void) | |
432 | { | |
433 | u32 eth_cfg = 0; | |
434 | u32 eth_pll; | |
435 | u32 reg; | |
436 | ||
437 | /* | |
438 | * Set EMAC mode/configuration (GMII, SGMII, RGMII...). | |
439 | * This is board specific, so let's do it here. | |
440 | */ | |
441 | ||
442 | /* enable SGMII mode */ | |
443 | eth_cfg |= (SDR0_ETH_CFG_SGMII0_ENABLE | | |
444 | SDR0_ETH_CFG_SGMII1_ENABLE | | |
445 | SDR0_ETH_CFG_SGMII2_ENABLE); | |
446 | ||
447 | /* Set EMAC for MDIO */ | |
448 | eth_cfg |= SDR0_ETH_CFG_MDIO_SEL_EMAC0; | |
449 | ||
450 | /* bypass the TAHOE0/TAHOE1 cores for U-Boot */ | |
451 | eth_cfg |= (SDR0_ETH_CFG_TAHOE0_BYPASS | SDR0_ETH_CFG_TAHOE1_BYPASS); | |
452 | ||
453 | mtsdr(SDR0_ETH_CFG, eth_cfg); | |
454 | ||
455 | /* reset all SGMII interfaces */ | |
456 | mfsdr(SDR0_SRST1, reg); | |
457 | reg |= (SDR0_SRST1_SGMII0 | SDR0_SRST1_SGMII1 | SDR0_SRST1_SGMII2); | |
458 | mtsdr(SDR0_SRST1, reg); | |
459 | mtsdr(SDR0_ETH_STS, 0xFFFFFFFF); | |
460 | mtsdr(SDR0_SRST1, 0x00000000); | |
461 | ||
462 | do { | |
463 | mfsdr(SDR0_ETH_PLL, eth_pll); | |
464 | } while (!(eth_pll & SDR0_ETH_PLL_PLLLOCK)); | |
465 | ||
466 | return 0; | |
467 | } | |
468 | #endif /* !defined(CONFIG_ARCHES) */ | |
469 | ||
8e1a3fe5 | 470 | #if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) |
26d37f00 FR |
471 | extern void __ft_board_setup(void *blob, bd_t *bd); |
472 | ||
8e1a3fe5 SR |
473 | void ft_board_setup(void *blob, bd_t *bd) |
474 | { | |
26d37f00 | 475 | __ft_board_setup(blob, bd); |
8e1a3fe5 | 476 | |
16bedc66 SR |
477 | if (gd->board_type == BOARD_CANYONLANDS_SATA) { |
478 | /* | |
479 | * When SATA is selected we need to disable the first PCIe | |
480 | * node in the device tree, so that Linux doesn't initialize | |
481 | * it. | |
482 | */ | |
8fd4166c SR |
483 | fdt_find_and_setprop(blob, "/plb/pciex@d00000000", "status", |
484 | "disabled", sizeof("disabled"), 1); | |
16bedc66 SR |
485 | } |
486 | ||
487 | if (gd->board_type == BOARD_CANYONLANDS_PCIE) { | |
488 | /* | |
489 | * When PCIe is selected we need to disable the SATA | |
490 | * node in the device tree, so that Linux doesn't initialize | |
491 | * it. | |
492 | */ | |
8fd4166c SR |
493 | fdt_find_and_setprop(blob, "/plb/sata@bffd1000", "status", |
494 | "disabled", sizeof("disabled"), 1); | |
16bedc66 | 495 | } |
8e1a3fe5 SR |
496 | } |
497 | #endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */ |