[people/ms/u-boot.git] / board / amcc / canyonlands / canyonlands.c

/*
 * (C) Copyright 2008
 * Stefan Roese, DENX Software Engineering, sr@denx.de.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

#include <common.h>
#include <ppc440.h>
#include <libfdt.h>
#include <fdt_support.h>
#include <asm/processor.h>
#include <asm/io.h>
#include <asm/mmu.h>
#include <asm/4xx_pcie.h>

extern flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */

DECLARE_GLOBAL_DATA_PTR;

int board_early_init_f(void)
{
	u32 sdr0_cust0;

	/*------------------------------------------------------------------+
	 * Setup the interrupt controller polarities, triggers, etc.
	 *------------------------------------------------------------------*/
	mtdcr(uic0sr, 0xffffffff);	/* clear all */
	mtdcr(uic0er, 0x00000000);	/* disable all */
	mtdcr(uic0cr, 0x00000005);	/* ATI & UIC1 crit are critical */
	mtdcr(uic0pr, 0xffffffff);	/* per ref-board manual */
	mtdcr(uic0tr, 0x00000000);	/* per ref-board manual */
	mtdcr(uic0vr, 0x00000000);	/* int31 highest, base=0x000 */
	mtdcr(uic0sr, 0xffffffff);	/* clear all */

	mtdcr(uic1sr, 0xffffffff);	/* clear all */
	mtdcr(uic1er, 0x00000000);	/* disable all */
	mtdcr(uic1cr, 0x00000000);	/* all non-critical */
	mtdcr(uic1pr, 0xffffffff);	/* per ref-board manual */
	mtdcr(uic1tr, 0x00000000);	/* per ref-board manual */
	mtdcr(uic1vr, 0x00000000);	/* int31 highest, base=0x000 */
	mtdcr(uic1sr, 0xffffffff);	/* clear all */

	mtdcr(uic2sr, 0xffffffff);	/* clear all */
	mtdcr(uic2er, 0x00000000);	/* disable all */
	mtdcr(uic2cr, 0x00000000);	/* all non-critical */
	mtdcr(uic2pr, 0xffffffff);	/* per ref-board manual */
	mtdcr(uic2tr, 0x00000000);	/* per ref-board manual */
	mtdcr(uic2vr, 0x00000000);	/* int31 highest, base=0x000 */
	mtdcr(uic2sr, 0xffffffff);	/* clear all */

	mtdcr(uic3sr, 0xffffffff);	/* clear all */
	mtdcr(uic3er, 0x00000000);	/* disable all */
	mtdcr(uic3cr, 0x00000000);	/* all non-critical */
	mtdcr(uic3pr, 0xffffffff);	/* per ref-board manual */
	mtdcr(uic3tr, 0x00000000);	/* per ref-board manual */
	mtdcr(uic3vr, 0x00000000);	/* int31 highest, base=0x000 */
	mtdcr(uic3sr, 0xffffffff);	/* clear all */

	/* SDR Setting - enable NDFC */
	mfsdr(SDR0_CUST0, sdr0_cust0);
	sdr0_cust0 = SDR0_CUST0_MUX_NDFC_SEL	|
		SDR0_CUST0_NDFC_ENABLE		|
		SDR0_CUST0_NDFC_BW_8_BIT	|
		SDR0_CUST0_NDFC_ARE_MASK	|
		SDR0_CUST0_NDFC_BAC_ENCODE(3)	|
		(0x80000000 >> (28 + CFG_NAND_CS));
	mtsdr(SDR0_CUST0, sdr0_cust0);

	/*
	 * Configure PFC (Pin Function Control) registers
	 * UART0: 4 pins
	 */
	mtsdr(SDR0_PFC1, 0x00040000);

	/* Enable PCI host functionality in SDR0_PCI0 */
	mtsdr(SDR0_PCI0, 0xe0000000);

	/* Enable ethernet and take out of reset */
	out_8((void *)CFG_BCSR_BASE + 6, 0);

	/* Remove NOR-FLASH, NAND-FLASH & EEPROM hardware write protection */
	out_8((void *)CFG_BCSR_BASE + 5, 0);

	/* Enable USB host & USB-OTG */
	out_8((void *)CFG_BCSR_BASE + 7, 0);

	mtsdr(SDR0_SRST1, 0);	/* Pull AHB out of reset default=1 */

	return 0;
}

int checkboard (void)
{
	char *s = getenv("serial#");
	u32 pvr = get_pvr();

	if ((pvr == PVR_460GT_RA) || (pvr == PVR_460GT_SE_RA))
		printf("Board: Glacier - AMCC PPC460GT Evaluation Board");
	else
		printf("Board: Canyonlands - AMCC PPC460EX Evaluation Board");

	if (s != NULL) {
		puts(", serial# ");
		puts(s);
	}
	putc('\n');

	return (0);
}

/*
 * Override the default functions in cpu/ppc4xx/44x_spd_ddr2.c with
 * board specific values.
 */
u32 ddr_wrdtr(u32 default_val) {
	return (SDRAM_WRDTR_LLWP_1_CYC | SDRAM_WRDTR_WTR_180_DEG_ADV | 0x823);
}

u32 ddr_clktr(u32 default_val) {
	return (SDRAM_CLKTR_CLKP_90_DEG_ADV);
}

#if defined(CFG_DRAM_TEST)
int testdram(void)
{
	unsigned long *mem = (unsigned long *)0;
	const unsigned long kend = (1024 / sizeof(unsigned long));
	unsigned long k, n;

	mtmsr(0);

	for (k = 0; k < CFG_KBYTES_SDRAM;
	     ++k, mem += (1024 / sizeof(unsigned long))) {
		if ((k & 1023) == 0) {
			printf("%3d MB\r", k / 1024);
		}

		memset(mem, 0xaaaaaaaa, 1024);
		for (n = 0; n < kend; ++n) {
			if (mem[n] != 0xaaaaaaaa) {
				printf("SDRAM test fails at: %08x\n",
				       (uint) & mem[n]);
				return 1;
			}
		}

		memset(mem, 0x55555555, 1024);
		for (n = 0; n < kend; ++n) {
			if (mem[n] != 0x55555555) {
				printf("SDRAM test fails at: %08x\n",
				       (uint) & mem[n]);
				return 1;
			}
		}
	}
	printf("SDRAM test passes\n");
	return 0;
}
#endif

/*************************************************************************
 *  pci_target_init
 *
 *	The bootstrap configuration provides default settings for the pci
 *	inbound map (PIM). But the bootstrap config choices are limited and
 *	may not be sufficient for a given board.
 *
 ************************************************************************/
#if defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT)
void pci_target_init(struct pci_controller * hose )
{
	/*-------------------------------------------------------------------+
	 * Disable everything
	 *-------------------------------------------------------------------*/
	out_le32((void *)PCIX0_PIM0SA, 0); /* disable */
	out_le32((void *)PCIX0_PIM1SA, 0); /* disable */
	out_le32((void *)PCIX0_PIM2SA, 0); /* disable */
	out_le32((void *)PCIX0_EROMBA, 0); /* disable expansion rom */

	/*-------------------------------------------------------------------+
	 * Map all of SDRAM to PCI address 0x0000_0000. Note that the 440
	 * strapping options to not support sizes such as 128/256 MB.
	 *-------------------------------------------------------------------*/
	out_le32((void *)PCIX0_PIM0LAL, CFG_SDRAM_BASE);
	out_le32((void *)PCIX0_PIM0LAH, 0);
	out_le32((void *)PCIX0_PIM0SA, ~(gd->ram_size - 1) | 1);
	out_le32((void *)PCIX0_BAR0, 0);

	/*-------------------------------------------------------------------+
	 * Program the board's subsystem id/vendor id
	 *-------------------------------------------------------------------*/
	out_le16((void *)PCIX0_SBSYSVID, CFG_PCI_SUBSYS_VENDORID);
	out_le16((void *)PCIX0_SBSYSID, CFG_PCI_SUBSYS_DEVICEID);

	out_le16((void *)PCIX0_CMD, in16r(PCIX0_CMD) | PCI_COMMAND_MEMORY);
}
#endif	/* defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT) */

#if defined(CONFIG_PCI)
/*
 * is_pci_host
 *
 * This routine is called to determine if a pci scan should be
 * performed. With various hardware environments (especially cPCI and
 * PPMC) it's insufficient to depend on the state of the arbiter enable
 * bit in the strap register, or generic host/adapter assumptions.
 *
 * Rather than hard-code a bad assumption in the general 440 code, the
 * 440 pci code requires the board to decide at runtime.
 *
 * Return 0 for adapter mode, non-zero for host (monarch) mode.
 */
int is_pci_host(struct pci_controller *hose)
{
	/* Board is always configured as host. */
	return (1);
}

static struct pci_controller pcie_hose[2] = {{0},{0}};

void pcie_setup_hoses(int busno)
{
	struct pci_controller *hose;
	int i, bus;
	int ret = 0;
	char *env;
	unsigned int delay;

	/*
	 * assume we're called after the PCIX hose is initialized, which takes
	 * bus ID 0 and therefore start numbering PCIe's from 1.
	 */
	bus = busno;
	for (i = 0; i <= 1; i++) {

		if (is_end_point(i))
			ret = ppc4xx_init_pcie_endport(i);
		else
			ret = ppc4xx_init_pcie_rootport(i);
		if (ret) {
			printf("PCIE%d: initialization as %s failed\n", i,
			       is_end_point(i) ? "endpoint" : "root-complex");
			continue;
		}

		hose = &pcie_hose[i];
		hose->first_busno = bus;
		hose->last_busno = bus;
		hose->current_busno = bus;

		/* setup mem resource */
		pci_set_region(hose->regions + 0,
			       CFG_PCIE_MEMBASE + i * CFG_PCIE_MEMSIZE,
			       CFG_PCIE_MEMBASE + i * CFG_PCIE_MEMSIZE,
			       CFG_PCIE_MEMSIZE,
			       PCI_REGION_MEM);
		hose->region_count = 1;
		pci_register_hose(hose);

		if (is_end_point(i)) {
			ppc4xx_setup_pcie_endpoint(hose, i);
			/*
			 * Reson for no scanning is endpoint can not generate
			 * upstream configuration accesses.
			 */
		} else {
			ppc4xx_setup_pcie_rootpoint(hose, i);
			env = getenv ("pciscandelay");
			if (env != NULL) {
				delay = simple_strtoul(env, NULL, 10);
				if (delay > 5)
					printf("Warning, expect noticable delay before "
					       "PCIe scan due to 'pciscandelay' value!\n");
				mdelay(delay * 1000);
			}

			/*
			 * Config access can only go down stream
			 */
			hose->last_busno = pci_hose_scan(hose);
			bus = hose->last_busno + 1;
		}
	}
}
#endif /* CONFIG_PCI */

int board_early_init_r (void)
{
	/*
	 * Canyonlands has 64MBytes of NOR FLASH (Spansion 29GL512), but the
	 * boot EBC mapping only supports a maximum of 16MBytes
	 * (4.ff00.0000 - 4.ffff.ffff).
	 * To solve this problem, the FLASH has to get remapped to another
	 * EBC address which accepts bigger regions:
	 *
	 * 0xfc00.0000 -> 4.cc00.0000
	 *
	 * For this we have to remap the CS0 and re-relocate the envrironment,
	 * since the original FLASH location which was needed upon startup is
	 * now not correct anymore.
	 */

	/* Remap the NOR FLASH to 0xcc00.0000 ... 0xcfff.ffff */
	mtebc(pb0cr, CFG_FLASH_BASE_PHYS_L | 0xda000);

	/* Remove TLB entry of boot EBC mapping */
	remove_tlb(CFG_BOOT_BASE_ADDR, 16 << 20);

	/* Add TLB entry for 0xfc00.0000 -> 0x4.cc00.0000 */
	program_tlb(CFG_FLASH_BASE_PHYS, CFG_FLASH_BASE, CFG_FLASH_SIZE,
		    TLB_WORD2_I_ENABLE);

	/*
	 * Now accessing of the whole 64Mbytes of NOR FLASH at virtual address
	 * 0xfc00.0000 is possible
	 */

	return 0;
}

int misc_init_r(void)
{
	u32 sdr0_srst1 = 0;
	u32 eth_cfg;

	/*
	 * Set EMAC mode/configuration (GMII, SGMII, RGMII...).
	 * This is board specific, so let's do it here.
	 */
	mfsdr(SDR0_ETH_CFG, eth_cfg);
	/* disable SGMII mode */
	eth_cfg &= ~(SDR0_ETH_CFG_SGMII2_ENABLE |
		     SDR0_ETH_CFG_SGMII1_ENABLE |
		     SDR0_ETH_CFG_SGMII0_ENABLE);
	/* Set the for 2 RGMII mode */
	/* GMC0 EMAC4_0, GMC0 EMAC4_1, RGMII Bridge 0 */
	eth_cfg &= ~SDR0_ETH_CFG_GMC0_BRIDGE_SEL;
	eth_cfg |= SDR0_ETH_CFG_GMC1_BRIDGE_SEL;
	mtsdr(SDR0_ETH_CFG, eth_cfg);

	/*
	 * The AHB Bridge core is held in reset after power-on or reset
	 * so enable it now
	 */
	mfsdr(SDR0_SRST1, sdr0_srst1);
	sdr0_srst1 &= ~SDR0_SRST1_AHB;
	mtsdr(SDR0_SRST1, sdr0_srst1);

	return 0;
}

#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
void ft_board_setup(void *blob, bd_t *bd)
{
	u32 val[4];
	int rc;

	ft_cpu_setup(blob, bd);

	/* Fixup NOR mapping */
	val[0] = 0;				/* chip select number */
	val[1] = 0;				/* always 0 */
	val[2] = gd->bd->bi_flashstart;
	val[3] = gd->bd->bi_flashsize;
	rc = fdt_find_and_setprop(blob, "/plb/opb/ebc", "ranges",
				  val, sizeof(val), 1);
	if (rc)
		printf("Unable to update property NOR mapping, err=%s\n",
		       fdt_strerror(rc));
}
#endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */
Commit	Line	Data
8e1a3fe5 SR	1	/*
	2	* (C) Copyright 2008
	3	* Stefan Roese, DENX Software Engineering, sr@denx.de.
	4	*
	5	* This program is free software; you can redistribute it and/or
	6	* modify it under the terms of the GNU General Public License as
	7	* published by the Free Software Foundation; either version 2 of
	8	* the License, or (at your option) any later version.
	9	*
	10	* This program is distributed in the hope that it will be useful,
	11	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	12	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	13	* GNU General Public License for more details.
	14	*
	15	* You should have received a copy of the GNU General Public License
	16	* along with this program; if not, write to the Free Software
	17	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	18	* MA 02111-1307 USA
	19	*/
	20
	21	#include <common.h>
	22	#include <ppc440.h>
	23	#include <libfdt.h>
	24	#include <fdt_support.h>
	25	#include <asm/processor.h>
	26	#include <asm/io.h>
	27	#include <asm/mmu.h>
	28	#include <asm/4xx_pcie.h>
	29
	30	extern flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */
	31
	32	DECLARE_GLOBAL_DATA_PTR;
	33
	34	int board_early_init_f(void)
	35	{
	36	u32 sdr0_cust0;
	37
	38	/*------------------------------------------------------------------+
	39	* Setup the interrupt controller polarities, triggers, etc.
	40	------------------------------------------------------------------/
	41	mtdcr(uic0sr, 0xffffffff); /* clear all */
	42	mtdcr(uic0er, 0x00000000); /* disable all */
	43	mtdcr(uic0cr, 0x00000005); /* ATI & UIC1 crit are critical */
	44	mtdcr(uic0pr, 0xffffffff); /* per ref-board manual */
	45	mtdcr(uic0tr, 0x00000000); /* per ref-board manual */
	46	mtdcr(uic0vr, 0x00000000); /* int31 highest, base=0x000 */
	47	mtdcr(uic0sr, 0xffffffff); /* clear all */
	48
	49	mtdcr(uic1sr, 0xffffffff); /* clear all */
	50	mtdcr(uic1er, 0x00000000); /* disable all */
	51	mtdcr(uic1cr, 0x00000000); /* all non-critical */
	52	mtdcr(uic1pr, 0xffffffff); /* per ref-board manual */
	53	mtdcr(uic1tr, 0x00000000); /* per ref-board manual */
	54	mtdcr(uic1vr, 0x00000000); /* int31 highest, base=0x000 */
	55	mtdcr(uic1sr, 0xffffffff); /* clear all */
	56
	57	mtdcr(uic2sr, 0xffffffff); /* clear all */
	58	mtdcr(uic2er, 0x00000000); /* disable all */
	59	mtdcr(uic2cr, 0x00000000); /* all non-critical */
	60	mtdcr(uic2pr, 0xffffffff); /* per ref-board manual */
	61	mtdcr(uic2tr, 0x00000000); /* per ref-board manual */
	62	mtdcr(uic2vr, 0x00000000); /* int31 highest, base=0x000 */
	63	mtdcr(uic2sr, 0xffffffff); /* clear all */
	64
65	mtdcr(uic3sr, 0xffffffff); /* clear all */
66	mtdcr(uic3er, 0x00000000); /* disable all */
67	mtdcr(uic3cr, 0x00000000); /* all non-critical */
68	mtdcr(uic3pr, 0xffffffff); /* per ref-board manual */
69	mtdcr(uic3tr, 0x00000000); /* per ref-board manual */
70	mtdcr(uic3vr, 0x00000000); /* int31 highest, base=0x000 */
71	mtdcr(uic3sr, 0xffffffff); /* clear all */
72
73	/* SDR Setting - enable NDFC */
74	mfsdr(SDR0_CUST0, sdr0_cust0);
75	sdr0_cust0 = SDR0_CUST0_MUX_NDFC_SEL \|
76	SDR0_CUST0_NDFC_ENABLE \|
77	SDR0_CUST0_NDFC_BW_8_BIT \|
78	SDR0_CUST0_NDFC_ARE_MASK \|
79	SDR0_CUST0_NDFC_BAC_ENCODE(3) \|
80	(0x80000000 >> (28 + CFG_NAND_CS));
81	mtsdr(SDR0_CUST0, sdr0_cust0);
82
83	/*
84	* Configure PFC (Pin Function Control) registers
85	* UART0: 4 pins
86	*/
87	mtsdr(SDR0_PFC1, 0x00040000);
88
89	/* Enable PCI host functionality in SDR0_PCI0 */
90	mtsdr(SDR0_PCI0, 0xe0000000);
91
92	/* Enable ethernet and take out of reset */
93	out_8((void *)CFG_BCSR_BASE + 6, 0);
94
95	/* Remove NOR-FLASH, NAND-FLASH & EEPROM hardware write protection */
96	out_8((void *)CFG_BCSR_BASE + 5, 0);
97
98	/* Enable USB host & USB-OTG */
99	out_8((void *)CFG_BCSR_BASE + 7, 0);
100
101	mtsdr(SDR0_SRST1, 0); /* Pull AHB out of reset default=1 */
102
103	return 0;
104	}
105
106	int checkboard (void)
107	{
108	char *s = getenv("serial#");
109	u32 pvr = get_pvr();
110
111	if ((pvr == PVR_460GT_RA) \|\| (pvr == PVR_460GT_SE_RA))
112	printf("Board: Glacier - AMCC PPC460GT Evaluation Board");
113	else
114	printf("Board: Canyonlands - AMCC PPC460EX Evaluation Board");
115
116	if (s != NULL) {
117	puts(", serial# ");
118	puts(s);
119	}
120	putc('\n');
121
122	return (0);
123	}
124
125	/*
126	* Override the default functions in cpu/ppc4xx/44x_spd_ddr2.c with
127	* board specific values.
128	*/
129	u32 ddr_wrdtr(u32 default_val) {
130	return (SDRAM_WRDTR_LLWP_1_CYC \| SDRAM_WRDTR_WTR_180_DEG_ADV \| 0x823);
131	}
132
133	u32 ddr_clktr(u32 default_val) {
134	return (SDRAM_CLKTR_CLKP_90_DEG_ADV);
135	}
136
137	#if defined(CFG_DRAM_TEST)
138	int testdram(void)
139	{
140	unsigned long mem = (unsigned long )0;
141	const unsigned long kend = (1024 / sizeof(unsigned long));
142	unsigned long k, n;
143
144	mtmsr(0);
145
146	for (k = 0; k < CFG_KBYTES_SDRAM;
147	++k, mem += (1024 / sizeof(unsigned long))) {
148	if ((k & 1023) == 0) {
149	printf("%3d MB\r", k / 1024);
150	}
151
152	memset(mem, 0xaaaaaaaa, 1024);
153	for (n = 0; n < kend; ++n) {
154	if (mem[n] != 0xaaaaaaaa) {
155	printf("SDRAM test fails at: %08x\n",
156	(uint) & mem[n]);
157	return 1;
158	}
159	}
160
161	memset(mem, 0x55555555, 1024);
162	for (n = 0; n < kend; ++n) {
163	if (mem[n] != 0x55555555) {
164	printf("SDRAM test fails at: %08x\n",
165	(uint) & mem[n]);
166	return 1;
167	}
168	}
169	}
170	printf("SDRAM test passes\n");
171	return 0;
172	}
173	#endif
174
175	/*************************************************************************
176	* pci_target_init
177	*
178	* The bootstrap configuration provides default settings for the pci
179	* inbound map (PIM). But the bootstrap config choices are limited and
180	* may not be sufficient for a given board.
181	*
182	************************************************************************/
183	#if defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT)
184	void pci_target_init(struct pci_controller * hose )
185	{
186	/*-------------------------------------------------------------------+
187	* Disable everything
188	-------------------------------------------------------------------/
189	out_le32((void )PCIX0_PIM0SA, 0); / disable */
190	out_le32((void )PCIX0_PIM1SA, 0); / disable */
191	out_le32((void )PCIX0_PIM2SA, 0); / disable */
192	out_le32((void )PCIX0_EROMBA, 0); / disable expansion rom */
193
194	/*-------------------------------------------------------------------+
195	* Map all of SDRAM to PCI address 0x0000_0000. Note that the 440
196	* strapping options to not support sizes such as 128/256 MB.
197	-------------------------------------------------------------------/
198	out_le32((void *)PCIX0_PIM0LAL, CFG_SDRAM_BASE);
199	out_le32((void *)PCIX0_PIM0LAH, 0);
200	out_le32((void *)PCIX0_PIM0SA, ~(gd->ram_size - 1) \| 1);
201	out_le32((void *)PCIX0_BAR0, 0);
202
203	/*-------------------------------------------------------------------+
204	* Program the board's subsystem id/vendor id
205	-------------------------------------------------------------------/
206	out_le16((void *)PCIX0_SBSYSVID, CFG_PCI_SUBSYS_VENDORID);
207	out_le16((void *)PCIX0_SBSYSID, CFG_PCI_SUBSYS_DEVICEID);
208
209	out_le16((void *)PCIX0_CMD, in16r(PCIX0_CMD) \| PCI_COMMAND_MEMORY);
210	}
211	#endif /* defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT) */
212
213	#if defined(CONFIG_PCI)
214	/*
215	* is_pci_host
216	*
217	* This routine is called to determine if a pci scan should be
218	* performed. With various hardware environments (especially cPCI and
219	* PPMC) it's insufficient to depend on the state of the arbiter enable
220	* bit in the strap register, or generic host/adapter assumptions.
221	*
222	* Rather than hard-code a bad assumption in the general 440 code, the
223	* 440 pci code requires the board to decide at runtime.
224	*
225	* Return 0 for adapter mode, non-zero for host (monarch) mode.
226	*/
227	int is_pci_host(struct pci_controller *hose)
228	{
229	/* Board is always configured as host. */
230	return (1);
231	}
232
233	static struct pci_controller pcie_hose[2] = {{0},{0}};
234
235	void pcie_setup_hoses(int busno)
236	{
237	struct pci_controller *hose;
238	int i, bus;
239	int ret = 0;
240	char *env;
241	unsigned int delay;
242
243	/*
244	* assume we're called after the PCIX hose is initialized, which takes
245	* bus ID 0 and therefore start numbering PCIe's from 1.
246	*/
247	bus = busno;
248	for (i = 0; i <= 1; i++) {
249
250	if (is_end_point(i))
251	ret = ppc4xx_init_pcie_endport(i);
252	else
253	ret = ppc4xx_init_pcie_rootport(i);
254	if (ret) {
255	printf("PCIE%d: initialization as %s failed\n", i,
256	is_end_point(i) ? "endpoint" : "root-complex");
257	continue;
258	}
259
260	hose = &pcie_hose[i];
261	hose->first_busno = bus;
262	hose->last_busno = bus;
263	hose->current_busno = bus;
264
265	/* setup mem resource */
266	pci_set_region(hose->regions + 0,
267	CFG_PCIE_MEMBASE + i * CFG_PCIE_MEMSIZE,
268	CFG_PCIE_MEMBASE + i * CFG_PCIE_MEMSIZE,
269	CFG_PCIE_MEMSIZE,
270	PCI_REGION_MEM);
271	hose->region_count = 1;
272	pci_register_hose(hose);
273
274	if (is_end_point(i)) {
275	ppc4xx_setup_pcie_endpoint(hose, i);
276	/*
277	* Reson for no scanning is endpoint can not generate
278	* upstream configuration accesses.
279	*/
280	} else {
281	ppc4xx_setup_pcie_rootpoint(hose, i);
282	env = getenv ("pciscandelay");
283	if (env != NULL) {
284	delay = simple_strtoul(env, NULL, 10);
285	if (delay > 5)
286	printf("Warning, expect noticable delay before "
287	"PCIe scan due to 'pciscandelay' value!\n");
288	mdelay(delay * 1000);
289	}
290
291	/*
292	* Config access can only go down stream
293	*/
294	hose->last_busno = pci_hose_scan(hose);
295	bus = hose->last_busno + 1;
296	}
297	}
298	}
299	#endif /* CONFIG_PCI */
300
301	int board_early_init_r (void)
302	{
303	/*
304	* Canyonlands has 64MBytes of NOR FLASH (Spansion 29GL512), but the
305	* boot EBC mapping only supports a maximum of 16MBytes
306	* (4.ff00.0000 - 4.ffff.ffff).
307	* To solve this problem, the FLASH has to get remapped to another
308	* EBC address which accepts bigger regions:
309	*
310	* 0xfc00.0000 -> 4.cc00.0000
311	*
312	* For this we have to remap the CS0 and re-relocate the envrironment,
313	* since the original FLASH location which was needed upon startup is
314	* now not correct anymore.
315	*/
316
317	/* Remap the NOR FLASH to 0xcc00.0000 ... 0xcfff.ffff */
318	mtebc(pb0cr, CFG_FLASH_BASE_PHYS_L \| 0xda000);
319
320	/* Remove TLB entry of boot EBC mapping */
321	remove_tlb(CFG_BOOT_BASE_ADDR, 16 << 20);
322
323	/* Add TLB entry for 0xfc00.0000 -> 0x4.cc00.0000 */
324	program_tlb(CFG_FLASH_BASE_PHYS, CFG_FLASH_BASE, CFG_FLASH_SIZE,
325	TLB_WORD2_I_ENABLE);
326
327	/*
328	* Now accessing of the whole 64Mbytes of NOR FLASH at virtual address
329	* 0xfc00.0000 is possible
330	*/
331
332	return 0;
333	}
334
335	int misc_init_r(void)
336	{
337	u32 sdr0_srst1 = 0;
338	u32 eth_cfg;
339
340	/*
341	* Set EMAC mode/configuration (GMII, SGMII, RGMII...).
342	* This is board specific, so let's do it here.
343	*/
344	mfsdr(SDR0_ETH_CFG, eth_cfg);
345	/* disable SGMII mode */
346	eth_cfg &= ~(SDR0_ETH_CFG_SGMII2_ENABLE \|
347	SDR0_ETH_CFG_SGMII1_ENABLE \|
348	SDR0_ETH_CFG_SGMII0_ENABLE);
349	/* Set the for 2 RGMII mode */
350	/* GMC0 EMAC4_0, GMC0 EMAC4_1, RGMII Bridge 0 */
351	eth_cfg &= ~SDR0_ETH_CFG_GMC0_BRIDGE_SEL;
352	eth_cfg \|= SDR0_ETH_CFG_GMC1_BRIDGE_SEL;
353	mtsdr(SDR0_ETH_CFG, eth_cfg);
354
355	/*
356	* The AHB Bridge core is held in reset after power-on or reset
357	* so enable it now
358	*/
359	mfsdr(SDR0_SRST1, sdr0_srst1);
360	sdr0_srst1 &= ~SDR0_SRST1_AHB;
361	mtsdr(SDR0_SRST1, sdr0_srst1);
362
363	return 0;
364	}
365
366	#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
367	void ft_board_setup(void blob, bd_t bd)
368	{
369	u32 val[4];
370	int rc;
371
372	ft_cpu_setup(blob, bd);
373
374	/* Fixup NOR mapping */
375	val[0] = 0; /* chip select number */
376	val[1] = 0; /* always 0 */
377	val[2] = gd->bd->bi_flashstart;
378	val[3] = gd->bd->bi_flashsize;
379	rc = fdt_find_and_setprop(blob, "/plb/opb/ebc", "ranges",
380	val, sizeof(val), 1);
381	if (rc)
382	printf("Unable to update property NOR mapping, err=%s\n",
383	fdt_strerror(rc));
384	}
385	#endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */