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8e1a3fe5 SR |
1 | /* |
2 | * (C) Copyright 2008 | |
3 | * Stefan Roese, DENX Software Engineering, sr@denx.de. | |
4 | * | |
5 | * This program is free software; you can redistribute it and/or | |
6 | * modify it under the terms of the GNU General Public License as | |
7 | * published by the Free Software Foundation; either version 2 of | |
8 | * the License, or (at your option) any later version. | |
9 | * | |
10 | * This program is distributed in the hope that it will be useful, | |
11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
13 | * GNU General Public License for more details. | |
14 | * | |
15 | * You should have received a copy of the GNU General Public License | |
16 | * along with this program; if not, write to the Free Software | |
17 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
18 | * MA 02111-1307 USA | |
19 | */ | |
20 | ||
21 | #include <common.h> | |
22 | #include <ppc440.h> | |
23 | #include <libfdt.h> | |
24 | #include <fdt_support.h> | |
212ed906 | 25 | #include <i2c.h> |
8e1a3fe5 SR |
26 | #include <asm/processor.h> |
27 | #include <asm/io.h> | |
28 | #include <asm/mmu.h> | |
29 | #include <asm/4xx_pcie.h> | |
41712b4e | 30 | #include <asm/gpio.h> |
8e1a3fe5 | 31 | |
6d0f6bcf | 32 | extern flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */ |
8e1a3fe5 SR |
33 | |
34 | DECLARE_GLOBAL_DATA_PTR; | |
35 | ||
6d0f6bcf | 36 | #define CONFIG_SYS_BCSR3_PCIE 0x10 |
cc8e839a SR |
37 | |
38 | #define BOARD_CANYONLANDS_PCIE 1 | |
39 | #define BOARD_CANYONLANDS_SATA 2 | |
40 | #define BOARD_GLACIER 3 | |
41 | ||
8e1a3fe5 SR |
42 | int board_early_init_f(void) |
43 | { | |
44 | u32 sdr0_cust0; | |
4c9e8557 | 45 | u32 pvr = get_pvr(); |
8e1a3fe5 | 46 | |
1c2926ab | 47 | /* |
8e1a3fe5 | 48 | * Setup the interrupt controller polarities, triggers, etc. |
1c2926ab | 49 | */ |
8e1a3fe5 SR |
50 | mtdcr(uic0sr, 0xffffffff); /* clear all */ |
51 | mtdcr(uic0er, 0x00000000); /* disable all */ | |
52 | mtdcr(uic0cr, 0x00000005); /* ATI & UIC1 crit are critical */ | |
53 | mtdcr(uic0pr, 0xffffffff); /* per ref-board manual */ | |
54 | mtdcr(uic0tr, 0x00000000); /* per ref-board manual */ | |
55 | mtdcr(uic0vr, 0x00000000); /* int31 highest, base=0x000 */ | |
56 | mtdcr(uic0sr, 0xffffffff); /* clear all */ | |
57 | ||
58 | mtdcr(uic1sr, 0xffffffff); /* clear all */ | |
59 | mtdcr(uic1er, 0x00000000); /* disable all */ | |
60 | mtdcr(uic1cr, 0x00000000); /* all non-critical */ | |
61 | mtdcr(uic1pr, 0xffffffff); /* per ref-board manual */ | |
62 | mtdcr(uic1tr, 0x00000000); /* per ref-board manual */ | |
63 | mtdcr(uic1vr, 0x00000000); /* int31 highest, base=0x000 */ | |
64 | mtdcr(uic1sr, 0xffffffff); /* clear all */ | |
65 | ||
66 | mtdcr(uic2sr, 0xffffffff); /* clear all */ | |
67 | mtdcr(uic2er, 0x00000000); /* disable all */ | |
68 | mtdcr(uic2cr, 0x00000000); /* all non-critical */ | |
69 | mtdcr(uic2pr, 0xffffffff); /* per ref-board manual */ | |
70 | mtdcr(uic2tr, 0x00000000); /* per ref-board manual */ | |
71 | mtdcr(uic2vr, 0x00000000); /* int31 highest, base=0x000 */ | |
72 | mtdcr(uic2sr, 0xffffffff); /* clear all */ | |
73 | ||
74 | mtdcr(uic3sr, 0xffffffff); /* clear all */ | |
75 | mtdcr(uic3er, 0x00000000); /* disable all */ | |
76 | mtdcr(uic3cr, 0x00000000); /* all non-critical */ | |
77 | mtdcr(uic3pr, 0xffffffff); /* per ref-board manual */ | |
78 | mtdcr(uic3tr, 0x00000000); /* per ref-board manual */ | |
79 | mtdcr(uic3vr, 0x00000000); /* int31 highest, base=0x000 */ | |
80 | mtdcr(uic3sr, 0xffffffff); /* clear all */ | |
81 | ||
82 | /* SDR Setting - enable NDFC */ | |
83 | mfsdr(SDR0_CUST0, sdr0_cust0); | |
84 | sdr0_cust0 = SDR0_CUST0_MUX_NDFC_SEL | | |
85 | SDR0_CUST0_NDFC_ENABLE | | |
86 | SDR0_CUST0_NDFC_BW_8_BIT | | |
87 | SDR0_CUST0_NDFC_ARE_MASK | | |
88 | SDR0_CUST0_NDFC_BAC_ENCODE(3) | | |
6d0f6bcf | 89 | (0x80000000 >> (28 + CONFIG_SYS_NAND_CS)); |
8e1a3fe5 SR |
90 | mtsdr(SDR0_CUST0, sdr0_cust0); |
91 | ||
92 | /* | |
93 | * Configure PFC (Pin Function Control) registers | |
94 | * UART0: 4 pins | |
95 | */ | |
96 | mtsdr(SDR0_PFC1, 0x00040000); | |
97 | ||
98 | /* Enable PCI host functionality in SDR0_PCI0 */ | |
99 | mtsdr(SDR0_PCI0, 0xe0000000); | |
100 | ||
101 | /* Enable ethernet and take out of reset */ | |
6d0f6bcf | 102 | out_8((void *)CONFIG_SYS_BCSR_BASE + 6, 0); |
8e1a3fe5 SR |
103 | |
104 | /* Remove NOR-FLASH, NAND-FLASH & EEPROM hardware write protection */ | |
6d0f6bcf | 105 | out_8((void *)CONFIG_SYS_BCSR_BASE + 5, 0); |
8e1a3fe5 SR |
106 | |
107 | /* Enable USB host & USB-OTG */ | |
6d0f6bcf | 108 | out_8((void *)CONFIG_SYS_BCSR_BASE + 7, 0); |
8e1a3fe5 SR |
109 | |
110 | mtsdr(SDR0_SRST1, 0); /* Pull AHB out of reset default=1 */ | |
111 | ||
41712b4e SR |
112 | /* Setup PLB4-AHB bridge based on the system address map */ |
113 | mtdcr(AHB_TOP, 0x8000004B); | |
114 | mtdcr(AHB_BOT, 0x8000004B); | |
115 | ||
4c9e8557 SR |
116 | if ((pvr == PVR_460EX_RA) || (pvr == PVR_460EX_SE_RA)) { |
117 | /* | |
118 | * Configure USB-STP pins as alternate and not GPIO | |
119 | * It seems to be neccessary to configure the STP pins as GPIO | |
120 | * input at powerup (perhaps while USB reset is asserted). So | |
121 | * we configure those pins to their "real" function now. | |
122 | */ | |
123 | gpio_config(16, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1); | |
124 | gpio_config(19, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1); | |
125 | } | |
41712b4e | 126 | |
8e1a3fe5 SR |
127 | return 0; |
128 | } | |
129 | ||
1c2926ab SR |
130 | static void canyonlands_sata_init(int board_type) |
131 | { | |
132 | u32 reg; | |
133 | ||
134 | if (board_type == BOARD_CANYONLANDS_SATA) { | |
135 | /* Put SATA in reset */ | |
136 | SDR_WRITE(SDR0_SRST1, 0x00020001); | |
137 | ||
138 | /* Set the phy for SATA, not PCI-E port 0 */ | |
139 | reg = SDR_READ(PESDR0_PHY_CTL_RST); | |
140 | SDR_WRITE(PESDR0_PHY_CTL_RST, (reg & 0xeffffffc) | 0x00000001); | |
141 | reg = SDR_READ(PESDR0_L0CLK); | |
142 | SDR_WRITE(PESDR0_L0CLK, (reg & 0xfffffff8) | 0x00000007); | |
143 | SDR_WRITE(PESDR0_L0CDRCTL, 0x00003111); | |
144 | SDR_WRITE(PESDR0_L0DRV, 0x00000104); | |
145 | ||
146 | /* Bring SATA out of reset */ | |
147 | SDR_WRITE(SDR0_SRST1, 0x00000000); | |
148 | } | |
149 | } | |
150 | ||
151 | int checkboard(void) | |
8e1a3fe5 SR |
152 | { |
153 | char *s = getenv("serial#"); | |
154 | u32 pvr = get_pvr(); | |
155 | ||
cc8e839a | 156 | if ((pvr == PVR_460GT_RA) || (pvr == PVR_460GT_SE_RA)) { |
8e1a3fe5 | 157 | printf("Board: Glacier - AMCC PPC460GT Evaluation Board"); |
cc8e839a SR |
158 | gd->board_type = BOARD_GLACIER; |
159 | } else { | |
8e1a3fe5 | 160 | printf("Board: Canyonlands - AMCC PPC460EX Evaluation Board"); |
6d0f6bcf | 161 | if (in_8((void *)(CONFIG_SYS_BCSR_BASE + 3)) & CONFIG_SYS_BCSR3_PCIE) |
cc8e839a SR |
162 | gd->board_type = BOARD_CANYONLANDS_PCIE; |
163 | else | |
164 | gd->board_type = BOARD_CANYONLANDS_SATA; | |
165 | } | |
166 | ||
167 | switch (gd->board_type) { | |
168 | case BOARD_CANYONLANDS_PCIE: | |
169 | case BOARD_GLACIER: | |
170 | puts(", 2*PCIe"); | |
171 | break; | |
172 | ||
173 | case BOARD_CANYONLANDS_SATA: | |
174 | puts(", 1*PCIe/1*SATA"); | |
175 | break; | |
176 | } | |
177 | ||
6d0f6bcf | 178 | printf(", Rev. %X", in_8((void *)(CONFIG_SYS_BCSR_BASE + 0))); |
8e1a3fe5 SR |
179 | |
180 | if (s != NULL) { | |
181 | puts(", serial# "); | |
182 | puts(s); | |
183 | } | |
184 | putc('\n'); | |
185 | ||
1c2926ab SR |
186 | canyonlands_sata_init(gd->board_type); |
187 | ||
8e1a3fe5 SR |
188 | return (0); |
189 | } | |
190 | ||
191 | /* | |
192 | * Override the default functions in cpu/ppc4xx/44x_spd_ddr2.c with | |
193 | * board specific values. | |
194 | */ | |
195 | u32 ddr_wrdtr(u32 default_val) { | |
196 | return (SDRAM_WRDTR_LLWP_1_CYC | SDRAM_WRDTR_WTR_180_DEG_ADV | 0x823); | |
197 | } | |
198 | ||
199 | u32 ddr_clktr(u32 default_val) { | |
200 | return (SDRAM_CLKTR_CLKP_90_DEG_ADV); | |
201 | } | |
202 | ||
71665ebf SR |
203 | #if defined(CONFIG_NAND_U_BOOT) |
204 | /* | |
205 | * NAND booting U-Boot version uses a fixed initialization, since the whole | |
206 | * I2C SPD DIMM autodetection/calibration doesn't fit into the 4k of boot | |
207 | * code. | |
208 | */ | |
9973e3c6 | 209 | phys_size_t initdram(int board_type) |
71665ebf | 210 | { |
6d0f6bcf | 211 | return CONFIG_SYS_MBYTES_SDRAM << 20; |
71665ebf SR |
212 | } |
213 | #endif | |
214 | ||
1c2926ab | 215 | /* |
8e1a3fe5 SR |
216 | * pci_target_init |
217 | * | |
218 | * The bootstrap configuration provides default settings for the pci | |
219 | * inbound map (PIM). But the bootstrap config choices are limited and | |
220 | * may not be sufficient for a given board. | |
1c2926ab | 221 | */ |
6d0f6bcf | 222 | #if defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT) |
8e1a3fe5 SR |
223 | void pci_target_init(struct pci_controller * hose ) |
224 | { | |
1c2926ab | 225 | /* |
8e1a3fe5 | 226 | * Disable everything |
1c2926ab | 227 | */ |
8e1a3fe5 SR |
228 | out_le32((void *)PCIX0_PIM0SA, 0); /* disable */ |
229 | out_le32((void *)PCIX0_PIM1SA, 0); /* disable */ | |
230 | out_le32((void *)PCIX0_PIM2SA, 0); /* disable */ | |
231 | out_le32((void *)PCIX0_EROMBA, 0); /* disable expansion rom */ | |
232 | ||
1c2926ab | 233 | /* |
8e1a3fe5 SR |
234 | * Map all of SDRAM to PCI address 0x0000_0000. Note that the 440 |
235 | * strapping options to not support sizes such as 128/256 MB. | |
1c2926ab | 236 | */ |
6d0f6bcf | 237 | out_le32((void *)PCIX0_PIM0LAL, CONFIG_SYS_SDRAM_BASE); |
8e1a3fe5 SR |
238 | out_le32((void *)PCIX0_PIM0LAH, 0); |
239 | out_le32((void *)PCIX0_PIM0SA, ~(gd->ram_size - 1) | 1); | |
240 | out_le32((void *)PCIX0_BAR0, 0); | |
241 | ||
1c2926ab | 242 | /* |
8e1a3fe5 | 243 | * Program the board's subsystem id/vendor id |
1c2926ab | 244 | */ |
6d0f6bcf JCPV |
245 | out_le16((void *)PCIX0_SBSYSVID, CONFIG_SYS_PCI_SUBSYS_VENDORID); |
246 | out_le16((void *)PCIX0_SBSYSID, CONFIG_SYS_PCI_SUBSYS_DEVICEID); | |
8e1a3fe5 SR |
247 | |
248 | out_le16((void *)PCIX0_CMD, in16r(PCIX0_CMD) | PCI_COMMAND_MEMORY); | |
249 | } | |
6d0f6bcf | 250 | #endif /* defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT) */ |
8e1a3fe5 SR |
251 | |
252 | #if defined(CONFIG_PCI) | |
253 | /* | |
254 | * is_pci_host | |
255 | * | |
256 | * This routine is called to determine if a pci scan should be | |
257 | * performed. With various hardware environments (especially cPCI and | |
258 | * PPMC) it's insufficient to depend on the state of the arbiter enable | |
259 | * bit in the strap register, or generic host/adapter assumptions. | |
260 | * | |
261 | * Rather than hard-code a bad assumption in the general 440 code, the | |
262 | * 440 pci code requires the board to decide at runtime. | |
263 | * | |
264 | * Return 0 for adapter mode, non-zero for host (monarch) mode. | |
265 | */ | |
266 | int is_pci_host(struct pci_controller *hose) | |
267 | { | |
268 | /* Board is always configured as host. */ | |
269 | return (1); | |
270 | } | |
271 | ||
272 | static struct pci_controller pcie_hose[2] = {{0},{0}}; | |
273 | ||
274 | void pcie_setup_hoses(int busno) | |
275 | { | |
276 | struct pci_controller *hose; | |
277 | int i, bus; | |
278 | int ret = 0; | |
279 | char *env; | |
280 | unsigned int delay; | |
cc8e839a | 281 | int start; |
8e1a3fe5 SR |
282 | |
283 | /* | |
284 | * assume we're called after the PCIX hose is initialized, which takes | |
285 | * bus ID 0 and therefore start numbering PCIe's from 1. | |
286 | */ | |
287 | bus = busno; | |
cc8e839a SR |
288 | |
289 | /* | |
290 | * Canyonlands with SATA enabled has only one PCIe slot | |
291 | * (2nd one). | |
292 | */ | |
293 | if (gd->board_type == BOARD_CANYONLANDS_SATA) | |
294 | start = 1; | |
295 | else | |
296 | start = 0; | |
297 | ||
298 | for (i = start; i <= 1; i++) { | |
8e1a3fe5 SR |
299 | |
300 | if (is_end_point(i)) | |
301 | ret = ppc4xx_init_pcie_endport(i); | |
302 | else | |
303 | ret = ppc4xx_init_pcie_rootport(i); | |
304 | if (ret) { | |
305 | printf("PCIE%d: initialization as %s failed\n", i, | |
306 | is_end_point(i) ? "endpoint" : "root-complex"); | |
307 | continue; | |
308 | } | |
309 | ||
310 | hose = &pcie_hose[i]; | |
311 | hose->first_busno = bus; | |
312 | hose->last_busno = bus; | |
313 | hose->current_busno = bus; | |
314 | ||
315 | /* setup mem resource */ | |
316 | pci_set_region(hose->regions + 0, | |
6d0f6bcf JCPV |
317 | CONFIG_SYS_PCIE_MEMBASE + i * CONFIG_SYS_PCIE_MEMSIZE, |
318 | CONFIG_SYS_PCIE_MEMBASE + i * CONFIG_SYS_PCIE_MEMSIZE, | |
319 | CONFIG_SYS_PCIE_MEMSIZE, | |
8e1a3fe5 SR |
320 | PCI_REGION_MEM); |
321 | hose->region_count = 1; | |
322 | pci_register_hose(hose); | |
323 | ||
324 | if (is_end_point(i)) { | |
325 | ppc4xx_setup_pcie_endpoint(hose, i); | |
326 | /* | |
327 | * Reson for no scanning is endpoint can not generate | |
328 | * upstream configuration accesses. | |
329 | */ | |
330 | } else { | |
331 | ppc4xx_setup_pcie_rootpoint(hose, i); | |
332 | env = getenv ("pciscandelay"); | |
333 | if (env != NULL) { | |
334 | delay = simple_strtoul(env, NULL, 10); | |
335 | if (delay > 5) | |
336 | printf("Warning, expect noticable delay before " | |
337 | "PCIe scan due to 'pciscandelay' value!\n"); | |
338 | mdelay(delay * 1000); | |
339 | } | |
340 | ||
341 | /* | |
342 | * Config access can only go down stream | |
343 | */ | |
344 | hose->last_busno = pci_hose_scan(hose); | |
345 | bus = hose->last_busno + 1; | |
346 | } | |
347 | } | |
348 | } | |
349 | #endif /* CONFIG_PCI */ | |
350 | ||
351 | int board_early_init_r (void) | |
352 | { | |
353 | /* | |
354 | * Canyonlands has 64MBytes of NOR FLASH (Spansion 29GL512), but the | |
355 | * boot EBC mapping only supports a maximum of 16MBytes | |
356 | * (4.ff00.0000 - 4.ffff.ffff). | |
357 | * To solve this problem, the FLASH has to get remapped to another | |
358 | * EBC address which accepts bigger regions: | |
359 | * | |
360 | * 0xfc00.0000 -> 4.cc00.0000 | |
8e1a3fe5 SR |
361 | */ |
362 | ||
363 | /* Remap the NOR FLASH to 0xcc00.0000 ... 0xcfff.ffff */ | |
71665ebf | 364 | #if defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL) |
6d0f6bcf | 365 | mtebc(pb3cr, CONFIG_SYS_FLASH_BASE_PHYS_L | 0xda000); |
71665ebf | 366 | #else |
6d0f6bcf | 367 | mtebc(pb0cr, CONFIG_SYS_FLASH_BASE_PHYS_L | 0xda000); |
71665ebf | 368 | #endif |
8e1a3fe5 SR |
369 | |
370 | /* Remove TLB entry of boot EBC mapping */ | |
6d0f6bcf | 371 | remove_tlb(CONFIG_SYS_BOOT_BASE_ADDR, 16 << 20); |
8e1a3fe5 SR |
372 | |
373 | /* Add TLB entry for 0xfc00.0000 -> 0x4.cc00.0000 */ | |
6d0f6bcf | 374 | program_tlb(CONFIG_SYS_FLASH_BASE_PHYS, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_SIZE, |
8e1a3fe5 SR |
375 | TLB_WORD2_I_ENABLE); |
376 | ||
377 | /* | |
378 | * Now accessing of the whole 64Mbytes of NOR FLASH at virtual address | |
379 | * 0xfc00.0000 is possible | |
380 | */ | |
381 | ||
71665ebf SR |
382 | /* |
383 | * Clear potential errors resulting from auto-calibration. | |
384 | * If not done, then we could get an interrupt later on when | |
385 | * exceptions are enabled. | |
386 | */ | |
387 | set_mcsr(get_mcsr()); | |
388 | ||
8e1a3fe5 SR |
389 | return 0; |
390 | } | |
391 | ||
392 | int misc_init_r(void) | |
393 | { | |
394 | u32 sdr0_srst1 = 0; | |
395 | u32 eth_cfg; | |
4c9e8557 | 396 | u32 pvr = get_pvr(); |
212ed906 | 397 | u8 val; |
8e1a3fe5 SR |
398 | |
399 | /* | |
400 | * Set EMAC mode/configuration (GMII, SGMII, RGMII...). | |
401 | * This is board specific, so let's do it here. | |
402 | */ | |
403 | mfsdr(SDR0_ETH_CFG, eth_cfg); | |
404 | /* disable SGMII mode */ | |
405 | eth_cfg &= ~(SDR0_ETH_CFG_SGMII2_ENABLE | | |
406 | SDR0_ETH_CFG_SGMII1_ENABLE | | |
407 | SDR0_ETH_CFG_SGMII0_ENABLE); | |
408 | /* Set the for 2 RGMII mode */ | |
409 | /* GMC0 EMAC4_0, GMC0 EMAC4_1, RGMII Bridge 0 */ | |
410 | eth_cfg &= ~SDR0_ETH_CFG_GMC0_BRIDGE_SEL; | |
4c9e8557 SR |
411 | if ((pvr == PVR_460EX_RA) || (pvr == PVR_460EX_SE_RA)) |
412 | eth_cfg |= SDR0_ETH_CFG_GMC1_BRIDGE_SEL; | |
413 | else | |
414 | eth_cfg &= ~SDR0_ETH_CFG_GMC1_BRIDGE_SEL; | |
8e1a3fe5 SR |
415 | mtsdr(SDR0_ETH_CFG, eth_cfg); |
416 | ||
417 | /* | |
418 | * The AHB Bridge core is held in reset after power-on or reset | |
419 | * so enable it now | |
420 | */ | |
421 | mfsdr(SDR0_SRST1, sdr0_srst1); | |
422 | sdr0_srst1 &= ~SDR0_SRST1_AHB; | |
423 | mtsdr(SDR0_SRST1, sdr0_srst1); | |
424 | ||
212ed906 SR |
425 | /* |
426 | * RTC/M41T62: | |
427 | * Disable square wave output: Batterie will be drained | |
428 | * quickly, when this output is not disabled | |
429 | */ | |
6d0f6bcf | 430 | val = i2c_reg_read(CONFIG_SYS_I2C_RTC_ADDR, 0xa); |
212ed906 | 431 | val &= ~0x40; |
6d0f6bcf | 432 | i2c_reg_write(CONFIG_SYS_I2C_RTC_ADDR, 0xa, val); |
212ed906 | 433 | |
8e1a3fe5 SR |
434 | return 0; |
435 | } | |
436 | ||
437 | #if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) | |
438 | void ft_board_setup(void *blob, bd_t *bd) | |
439 | { | |
440 | u32 val[4]; | |
441 | int rc; | |
442 | ||
443 | ft_cpu_setup(blob, bd); | |
444 | ||
445 | /* Fixup NOR mapping */ | |
446 | val[0] = 0; /* chip select number */ | |
447 | val[1] = 0; /* always 0 */ | |
6d0f6bcf | 448 | val[2] = CONFIG_SYS_FLASH_BASE_PHYS_L; /* we fixed up this address */ |
8e1a3fe5 SR |
449 | val[3] = gd->bd->bi_flashsize; |
450 | rc = fdt_find_and_setprop(blob, "/plb/opb/ebc", "ranges", | |
451 | val, sizeof(val), 1); | |
16bedc66 | 452 | if (rc) { |
8e1a3fe5 SR |
453 | printf("Unable to update property NOR mapping, err=%s\n", |
454 | fdt_strerror(rc)); | |
16bedc66 SR |
455 | } |
456 | ||
457 | if (gd->board_type == BOARD_CANYONLANDS_SATA) { | |
458 | /* | |
459 | * When SATA is selected we need to disable the first PCIe | |
460 | * node in the device tree, so that Linux doesn't initialize | |
461 | * it. | |
462 | */ | |
8fd4166c SR |
463 | fdt_find_and_setprop(blob, "/plb/pciex@d00000000", "status", |
464 | "disabled", sizeof("disabled"), 1); | |
16bedc66 SR |
465 | } |
466 | ||
467 | if (gd->board_type == BOARD_CANYONLANDS_PCIE) { | |
468 | /* | |
469 | * When PCIe is selected we need to disable the SATA | |
470 | * node in the device tree, so that Linux doesn't initialize | |
471 | * it. | |
472 | */ | |
8fd4166c SR |
473 | fdt_find_and_setprop(blob, "/plb/sata@bffd1000", "status", |
474 | "disabled", sizeof("disabled"), 1); | |
16bedc66 | 475 | } |
8e1a3fe5 SR |
476 | } |
477 | #endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */ |