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Commit | Line | Data |
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6c5879f3 | 1 | /* |
2f5df473 SR |
2 | * (C) Copyright 2007 |
3 | * Stefan Roese, DENX Software Engineering, sr@denx.de. | |
4 | * | |
6c5879f3 MB |
5 | * Copyright (C) 2002 Scott McNutt <smcnutt@artesyncp.com> |
6 | * | |
3765b3e7 | 7 | * SPDX-License-Identifier: GPL-2.0+ |
6c5879f3 | 8 | */ |
6c5879f3 MB |
9 | |
10 | #include <ppc_asm.tmpl> | |
11 | #include <config.h> | |
61f2b38a | 12 | #include <asm/mmu.h> |
550650dd | 13 | #include <asm/ppc4xx.h> |
6c5879f3 MB |
14 | |
15 | /************************************************************************** | |
16 | * TLB TABLE | |
17 | * | |
18 | * This table is used by the cpu boot code to setup the initial tlb | |
19 | * entries. Rather than make broad assumptions in the cpu source tree, | |
20 | * this table lets each board set things up however they like. | |
21 | * | |
22 | * Pointer to the table is returned in r1 | |
23 | * | |
24 | *************************************************************************/ | |
25 | ||
26 | .section .bootpg,"ax" | |
6c5879f3 | 27 | |
692519b1 RJ |
28 | /************************************************************************** |
29 | * TLB table for revA | |
30 | *************************************************************************/ | |
31 | .globl tlbtabA | |
32 | tlbtabA: | |
6c5879f3 | 33 | tlbtab_start |
6c5879f3 | 34 | |
2f5df473 SR |
35 | /* |
36 | * BOOT_CS (FLASH) must be first. Before relocation SA_I can be off to use the | |
37 | * speed up boot process. It is patched after relocation to enable SA_I | |
38 | */ | |
cf6eb6da | 39 | tlbentry(0xff000000, SZ_16M, 0xff000000, 4, AC_RWX | SA_G) |
2f5df473 SR |
40 | |
41 | /* | |
42 | * TLB entries for SDRAM are not needed on this platform. | |
43 | * They are dynamically generated in the SPD DDR(2) detection | |
44 | * routine. | |
45 | */ | |
6c5879f3 | 46 | |
cf6eb6da SR |
47 | tlbentry(CONFIG_SYS_ISRAM_BASE, SZ_256K, 0x00000000, 4, AC_RWX | SA_I) |
48 | tlbentry(CONFIG_SYS_FPGA_BASE, SZ_1K, 0xE2000000, 4,AC_RW | SA_I) | |
6d0f6bcf | 49 | |
cf6eb6da SR |
50 | tlbentry(CONFIG_SYS_OPER_FLASH, SZ_16M, 0xE7000000, 4,AC_RWX | SA_IG) |
51 | tlbentry(CONFIG_SYS_PERIPHERAL_BASE, SZ_4K, 0xF0000000, 4, AC_RW | SA_IG) | |
6d0f6bcf | 52 | |
cf6eb6da SR |
53 | tlbentry(CONFIG_SYS_PCI_BASE, SZ_256M, 0x00000000, 0xC, AC_RW | SA_IG) |
54 | tlbentry(CONFIG_SYS_PCI_MEMBASE, SZ_256M, 0x10000000, 0xC, AC_RW | SA_IG) | |
55 | tlbentry(CONFIG_SYS_PCIE_MEMBASE, SZ_256M, 0xB0000000, 0xD, AC_RW | SA_IG) | |
56 | tlbentry(CONFIG_SYS_PCIE_BASE, SZ_16K, 0x20000000, 0xC, AC_RW | SA_IG) | |
6d0f6bcf | 57 | |
cf6eb6da SR |
58 | tlbentry(CONFIG_SYS_PCIE0_CFGBASE, SZ_16M, 0x40000000, 0xC, AC_RW | SA_IG) |
59 | tlbentry(CONFIG_SYS_PCIE1_CFGBASE, SZ_16M, 0x80000000, 0xC, AC_RW | SA_IG) | |
60 | tlbentry(CONFIG_SYS_PCIE2_CFGBASE, SZ_16M, 0xC0000000, 0xC, AC_RW | SA_IG) | |
61 | tlbentry(CONFIG_SYS_PCIE0_XCFGBASE, SZ_1K, 0x50000000, 0xC, AC_RW | SA_IG) | |
62 | tlbentry(CONFIG_SYS_PCIE1_XCFGBASE, SZ_1K, 0x90000000, 0xC, AC_RW | SA_IG) | |
63 | tlbentry(CONFIG_SYS_PCIE2_XCFGBASE, SZ_1K, 0xD0000000, 0xC, AC_RW | SA_IG) | |
6c5879f3 MB |
64 | tlbtab_end |
65 | ||
692519b1 RJ |
66 | /************************************************************************** |
67 | * TLB table for revB | |
68 | * | |
d10afb39 | 69 | * Notice: revB of the 440SPe chip is very strict about PLB real addresses |
692519b1 RJ |
70 | * and ranges to be mapped for config space: it seems to only work with |
71 | * d_nnnn_nnnn range (hangs the core upon config transaction attempts when | |
72 | * set otherwise) while revA uses c_nnnn_nnnn. | |
73 | *************************************************************************/ | |
74 | .globl tlbtabB | |
75 | tlbtabB: | |
6c5879f3 | 76 | tlbtab_start |
6c5879f3 | 77 | |
2f5df473 SR |
78 | /* |
79 | * BOOT_CS (FLASH) must be first. Before relocation SA_I can be off to use the | |
80 | * speed up boot process. It is patched after relocation to enable SA_I | |
81 | */ | |
cf6eb6da | 82 | tlbentry(0xff000000, SZ_16M, 0xff000000, 4, AC_RWX | SA_G) |
2f5df473 SR |
83 | |
84 | /* | |
85 | * TLB entries for SDRAM are not needed on this platform. | |
86 | * They are dynamically generated in the SPD DDR(2) detection | |
87 | * routine. | |
88 | */ | |
6c5879f3 | 89 | |
cf6eb6da SR |
90 | tlbentry(CONFIG_SYS_ISRAM_BASE, SZ_256K, 0x00000000, 4, AC_RWX | SA_I) |
91 | tlbentry(CONFIG_SYS_FPGA_BASE, SZ_1K, 0xE2000000, 4,AC_RW | SA_I) | |
6c5879f3 | 92 | |
cf6eb6da SR |
93 | tlbentry(CONFIG_SYS_OPER_FLASH, SZ_16M, 0xE7000000, 4,AC_RWX | SA_IG) |
94 | tlbentry(CONFIG_SYS_PERIPHERAL_BASE, SZ_4K, 0xF0000000, 4, AC_RW | SA_IG) | |
6c5879f3 | 95 | |
cf6eb6da SR |
96 | tlbentry(CONFIG_SYS_PCI_BASE, SZ_256M, 0x00000000, 0xC, AC_RW | SA_IG) |
97 | tlbentry(CONFIG_SYS_PCI_MEMBASE, SZ_256M, 0x10000000, 0xC, AC_RW | SA_IG) | |
98 | tlbentry(CONFIG_SYS_PCIE_MEMBASE, SZ_256M, 0xB0000000, 0xD, AC_RW | SA_IG) | |
692519b1 | 99 | |
cf6eb6da SR |
100 | tlbentry(CONFIG_SYS_PCIE0_CFGBASE, SZ_16M, 0x00000000, 0xD, AC_RW | SA_IG) |
101 | tlbentry(CONFIG_SYS_PCIE1_CFGBASE, SZ_16M, 0x20000000, 0xD, AC_RW | SA_IG) | |
102 | tlbentry(CONFIG_SYS_PCIE2_CFGBASE, SZ_16M, 0x40000000, 0xD, AC_RW | SA_IG) | |
103 | tlbentry(CONFIG_SYS_PCIE0_XCFGBASE, SZ_1K, 0x10000000, 0xD, AC_RW | SA_IG) | |
104 | tlbentry(CONFIG_SYS_PCIE1_XCFGBASE, SZ_1K, 0x30000000, 0xD, AC_RW | SA_IG) | |
105 | tlbentry(CONFIG_SYS_PCIE2_XCFGBASE, SZ_1K, 0x50000000, 0xD, AC_RW | SA_IG) | |
6c5879f3 | 106 | tlbtab_end |