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7644f16f SR |
1 | /* |
2 | * (C) Copyright 2005 | |
3 | * Matthias Fuchs, esd gmbh germany, matthias.fuchs@esd-electronics.com | |
4 | * | |
5 | * See file CREDITS for list of people who contributed to this | |
6 | * project. | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or | |
9 | * modify it under the terms of the GNU General Public License as | |
10 | * published by the Free Software Foundation; either version 2 of | |
11 | * the License, or (at your option) any later version. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, | |
14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
f013dacf | 15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
7644f16f SR |
16 | * GNU General Public License for more details. |
17 | * | |
18 | * You should have received a copy of the GNU General Public License | |
19 | * along with this program; if not, write to the Free Software | |
20 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
21 | * MA 02111-1307 USA | |
22 | */ | |
23 | ||
24 | #include <common.h> | |
25 | #include <asm/processor.h> | |
26 | #include <command.h> | |
27 | #include <malloc.h> | |
28 | ||
d87080b7 WD |
29 | DECLARE_GLOBAL_DATA_PTR; |
30 | ||
7644f16f SR |
31 | int board_early_init_f (void) |
32 | { | |
33 | unsigned long cntrl0Reg; | |
34 | ||
35 | /* | |
2076d0a1 | 36 | * Setup GPIO pins |
7644f16f SR |
37 | */ |
38 | cntrl0Reg = mfdcr(cntrl0); | |
2076d0a1 | 39 | mtdcr(cntrl0, cntrl0Reg | ((CFG_EEPROM_WP | CFG_PB_LED | CFG_SELF_RST | CFG_INTA_FAKE) << 5)); |
7644f16f | 40 | |
bfc81252 | 41 | /* set output pins to high */ |
2076d0a1 | 42 | out32(GPIO0_OR, CFG_EEPROM_WP); |
bfc81252 | 43 | /* setup for output (LED=off) */ |
2076d0a1 | 44 | out32(GPIO0_TCR, CFG_EEPROM_WP | CFG_PB_LED); |
7644f16f SR |
45 | |
46 | /* | |
47 | * IRQ 0-15 405GP internally generated; active high; level sensitive | |
48 | * IRQ 16 405GP internally generated; active low; level sensitive | |
49 | * IRQ 17-24 RESERVED | |
50 | * IRQ 25 (EXT IRQ 0) PB0; active low; level sensitive | |
51 | * IRQ 26 (EXT IRQ 1) PB1; active low; level sensitive | |
52 | * IRQ 27 (EXT IRQ 2) PCI SLOT 0; active low; level sensitive | |
53 | * IRQ 28 (EXT IRQ 3) PCI SLOT 1; active low; level sensitive | |
54 | * IRQ 29 (EXT IRQ 4) PCI SLOT 2; active low; level sensitive | |
55 | * IRQ 30 (EXT IRQ 5) PCI SLOT 3; active low; level sensitive | |
56 | * IRQ 31 (EXT IRQ 6) unused | |
57 | */ | |
f013dacf WD |
58 | mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */ |
59 | mtdcr(uicer, 0x00000000); /* disable all ints */ | |
60 | mtdcr(uiccr, 0x00000000); /* set all to be non-critical*/ | |
61 | mtdcr(uicpr, 0xFFFFFF81); /* set int polarities */ | |
7644f16f | 62 | |
f013dacf WD |
63 | mtdcr(uictr, 0x10000000); /* set int trigger levels */ |
64 | mtdcr(uicvcr, 0x00000001); /* set vect base=0,INT0 highest priority*/ | |
65 | mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */ | |
7644f16f SR |
66 | |
67 | return 0; | |
68 | } | |
69 | ||
70 | ||
71 | int misc_init_f (void) | |
72 | { | |
73 | return 0; /* dummy implementation */ | |
74 | } | |
75 | ||
76 | ||
77 | int misc_init_r (void) | |
78 | { | |
7644f16f SR |
79 | unsigned long cntrl0Reg; |
80 | ||
81 | /* adjust flash start and offset */ | |
82 | gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize; | |
83 | gd->bd->bi_flashoffset = 0; | |
84 | ||
85 | /* | |
86 | * Select cts (and not dsr) on uart1 | |
87 | */ | |
88 | cntrl0Reg = mfdcr(cntrl0); | |
89 | mtdcr(cntrl0, cntrl0Reg | 0x00001000); | |
90 | ||
91 | return (0); | |
92 | } | |
93 | ||
94 | ||
95 | /* | |
96 | * Check Board Identity: | |
97 | */ | |
98 | int checkboard (void) | |
99 | { | |
77ddac94 | 100 | char str[64]; |
7644f16f SR |
101 | int i = getenv_r ("serial#", str, sizeof(str)); |
102 | ||
103 | puts ("Board: "); | |
104 | ||
105 | if (i == -1) { | |
106 | puts ("### No HW ID - assuming CPCI2DP"); | |
107 | } else { | |
108 | puts(str); | |
109 | } | |
110 | ||
111 | printf(" (Ver 1.0)"); | |
112 | ||
113 | putc ('\n'); | |
114 | ||
115 | return 0; | |
116 | } | |
117 | ||
118 | /* ------------------------------------------------------------------------- */ | |
119 | ||
9973e3c6 | 120 | phys_size_t initdram (int board_type) |
7644f16f SR |
121 | { |
122 | unsigned long val; | |
123 | ||
124 | mtdcr(memcfga, mem_mb0cf); | |
125 | val = mfdcr(memcfgd); | |
126 | ||
127 | return (4*1024*1024 << ((val & 0x000e0000) >> 17)); | |
128 | } | |
129 | ||
130 | /* ------------------------------------------------------------------------- */ | |
131 | ||
7644f16f SR |
132 | #if defined(CFG_EEPROM_WREN) |
133 | /* Input: <dev_addr> I2C address of EEPROM device to enable. | |
f013dacf WD |
134 | * <state> -1: deliver current state |
135 | * 0: disable write | |
7644f16f | 136 | * 1: enable write |
f013dacf WD |
137 | * Returns: -1: wrong device address |
138 | * 0: dis-/en- able done | |
7644f16f SR |
139 | * 0/1: current state if <state> was -1. |
140 | */ | |
141 | int eeprom_write_enable (unsigned dev_addr, int state) { | |
142 | if (CFG_I2C_EEPROM_ADDR != dev_addr) { | |
143 | return -1; | |
f013dacf | 144 | } else { |
7644f16f SR |
145 | switch (state) { |
146 | case 1: | |
147 | /* Enable write access, clear bit GPIO_SINT2. */ | |
148 | out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_EEPROM_WP); | |
149 | state = 0; | |
150 | break; | |
151 | case 0: | |
152 | /* Disable write access, set bit GPIO_SINT2. */ | |
153 | out32(GPIO0_OR, in32(GPIO0_OR) | CFG_EEPROM_WP); | |
154 | state = 0; | |
155 | break; | |
156 | default: | |
157 | /* Read current status back. */ | |
158 | state = (0 == (in32(GPIO0_OR) & CFG_EEPROM_WP)); | |
159 | break; | |
160 | } | |
161 | } | |
162 | return state; | |
163 | } | |
164 | #endif | |
165 | ||
166 | #if defined(CFG_EEPROM_WREN) | |
167 | int do_eep_wren (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) | |
168 | { | |
169 | int query = argc == 1; | |
170 | int state = 0; | |
171 | ||
172 | if (query) { | |
173 | /* Query write access state. */ | |
174 | state = eeprom_write_enable (CFG_I2C_EEPROM_ADDR, -1); | |
175 | if (state < 0) { | |
176 | puts ("Query of write access state failed.\n"); | |
f013dacf | 177 | } else { |
7644f16f SR |
178 | printf ("Write access for device 0x%0x is %sabled.\n", |
179 | CFG_I2C_EEPROM_ADDR, state ? "en" : "dis"); | |
180 | state = 0; | |
181 | } | |
f013dacf | 182 | } else { |
7644f16f SR |
183 | if ('0' == argv[1][0]) { |
184 | /* Disable write access. */ | |
185 | state = eeprom_write_enable (CFG_I2C_EEPROM_ADDR, 0); | |
f013dacf | 186 | } else { |
7644f16f SR |
187 | /* Enable write access. */ |
188 | state = eeprom_write_enable (CFG_I2C_EEPROM_ADDR, 1); | |
189 | } | |
190 | if (state < 0) { | |
191 | puts ("Setup of write access state failed.\n"); | |
192 | } | |
193 | } | |
194 | ||
195 | return state; | |
196 | } | |
197 | ||
198 | U_BOOT_CMD( | |
2076d0a1 SR |
199 | eepwren, 2, 0, do_eep_wren, |
200 | "eepwren - Enable / disable / query EEPROM write access\n", | |
201 | NULL | |
202 | ); | |
7644f16f | 203 | #endif /* #if defined(CFG_EEPROM_WREN) */ |