[people/ms/u-boot.git] / board / freescale / bsc9131rdb / README

Overview
--------
- BSC9131 is integrated device that targets Femto base station market.
 It combines Power Architecture e500v2 and DSP StarCore SC3850 core
 technologies with MAPLE-B2F baseband acceleration processing elements.
- It's MAPLE disabled personality is called 9231.

The BSC9131 SoC includes the following function and features:
. Power Architecture subsystem including a e500 processor with 256-Kbyte shared
  L2 cache
. StarCore SC3850 DSP subsystem with a 512-Kbyte private L2 cache
. The Multi Accelerator Platform Engine for Femto BaseStation Baseband
  Processing (MAPLE-B2F)
. A multi-standard baseband algorithm accelerator for Channel Decoding/Encoding,
 Fourier Transforms, UMTS chip rate processing, LTE UP/DL Channel processing,
 and CRC algorithms
. Consists of accelerators for Convolution, Filtering, Turbo Encoding,
 Turbo Decoding, Viterbi decoding, Chiprate processing, and Matrix Inversion
 operations
. DDR3/3L memory interface with 32-bit data width without ECC and 16-bit with
 ECC, up to 400-MHz clock/800 MHz data rate
. Dedicated security engine featuring trusted boot
. DMA controller
. OCNDMA with four bidirectional channels
. Interfaces
. Two triple-speed Gigabit Ethernet controllers featuring network acceleration
  including IEEE 1588. v2 hardware support and virtualization (eTSEC)
. eTSEC 1 supports RGMII/RMII
. eTSEC 2 supports RGMII
. High-speed USB 2.0 host and device controller with ULPI interface
. Enhanced secure digital (SD/MMC) host controller (eSDHC)
. Antenna interface controller (AIC), supporting three industry standard
  JESD207/three custom ADI RF interfaces (two dual port and one single port)
  and three MAXIM's MaxPHY serial interfaces
. ADI lanes support both full duplex FDD support and half duplex TDD support
. Universal Subscriber Identity Module (USIM) interface that facilitates
  communication to SIM cards or Eurochip pre-paid phone cards
. TDM with one TDM port
. Two DUART, four eSPI, and two I2C controllers
. Integrated Flash memory controller (IFC)
. TDM with 256 channels
. GPIO
. Sixteen 32-bit timers

The e500 core subsystem within the Power Architecture consists of the following:
. 32-Kbyte L1 instruction cache
. 32-Kbyte L1 data cache
. 256-Kbyte L2 cache/L2 memory/L2 stash
. programmable interrupt controller (PIC)
. Debug support
. Timers

The SC3850 core subsystem consists of the following:
. 32 Kbyte 8-way level 1 instruction cache (L1 ICache)
. 32 Kbyte 8-way level 1 data cache (L1 DCache)
. 512 Kbyte 8-way level 2 unified instruction/data cache (M2 memory)
. Memory management unit (MMU)
. Enhanced programmable interrupt controller (EPIC)
. Debug and profiling unit (DPU)
. Two 32-bit timers

BSC9131RDB board Overview
-------------------------
 1Gbyte DDR3 (on board DDR)
 128Mbyte 2K page size NAND Flash
 256 Kbit M24256 I2C EEPROM
 128 Mbit SPI Flash memory
 USB-ULPI
 eTSEC1: Connected to RGMII PHY
 eTSEC2: Connected to RGMII PHY
 DUART interface: supports one UARTs up to 115200 bps for console display
 USIM connector

Frequency Combinations Supported
--------------------------------
Core MHz/CCB MHz/DDR(MT/s)
1. 1000/500/800
2. 800/400/667

Boot Methods Supported
-----------------------
1. NAND Flash
2. SPI Flash

Default Boot Method
--------------------
NAND boot

Building U-Boot
--------------
To build the U-Boot for BSC9131RDB:
1. NAND Flash with sysclk 66MHz(J16 on RDB closed, default)
	make BSC9131RDB_NAND
2. NAND Flash with sysclk 100MHz(J16 on RDB open)
	make BSC9131RDB_NAND_SYSCLK100
3. SPI Flash with sysclk 66MHz(J16 on RDB closed, default)
	make BSC9131RDB_SPIFLASH
4. SPI Flash with sysclk 100MHz(J16 on RDB open)
	make BSC9131RDB_SPIFLASH_SYSCLK100

Memory map
-----------
 0x0000_0000	0x7FFF_FFFF	DDR			1G cacheable
 0xA0000000	0xBFFFFFFF	Shared DSP core L2/M2 space	512M
 0xC100_0000	0xC13F_FFFF	MAPLE-2F		4M
 0xC1F0_0000	0xC1F3_FFFF	PA SRAM Region 0	256K
 0xC1F8_0000	0xC1F9_FFFF	PA SRAM Region 1	128K
 0xFED0_0000	0xFED0_3FFF	SEC Secured RAM		16K
 0xFEE0_0000	0xFEE0_0FFF	DSP Boot ROM		4K
 0xFF60_0000	0xFF6F_FFFF 	DSP CCSR		1M
 0xFF70_0000	0xFF7F_FFFF	PA CCSR			1M
 0xFF80_0000	0xFFFF_FFFF	Boot Page & NAND Buffer 8M

DDR Memory map
---------------
 0x0000_0000	0x36FF_FFFF	Memory passed onto Linux
 0x3700_0000	0x37FF_FFFF	PowerPC-DSP shared control area
 0x3800_0000	0x4FFF_FFFF	DSP Private area

 Out of 880M, passed onto Linux, 1hugetlb page of 256M is reserved for
 data communcation between PowerPC and DSP core.
 Rest is PowerPC private area.

Flashing Images
---------------
To place a new U-Boot image in the NAND flash and then boot
with that new image temporarily, use this:
	tftp 1000000 u-boot-nand.bin
	nand erase 0 100000
	nand write 1000000 0 100000
	reset

Using the Device Tree Source File
---------------------------------
To create the DTB (Device Tree Binary) image file,
use a command similar to this:

	dtc -b 0 -f -I dts -O dtb bsc9131rdb.dts > bsc9131rdb.dtb

Likely, that .dts file will come from here;

	linux-2.6/arch/powerpc/boot/dts/bsc9131rdb.dts

Booting Linux
-------------
Place a linux uImage in the TFTP disk area.

	tftp 1000000 uImage
	tftp 2000000 rootfs.ext2.gz.uboot
	tftp c00000 bsc9131rdb.dtb
	bootm 1000000 2000000 c00000
Commit	Line	Data
7530d341 PK	1	Overview
	2	--------
	3	- BSC9131 is integrated device that targets Femto base station market.
	4	It combines Power Architecture e500v2 and DSP StarCore SC3850 core
	5	technologies with MAPLE-B2F baseband acceleration processing elements.
	6	- It's MAPLE disabled personality is called 9231.
	7
	8	The BSC9131 SoC includes the following function and features:
	9	. Power Architecture subsystem including a e500 processor with 256-Kbyte shared
	10	L2 cache
	11	. StarCore SC3850 DSP subsystem with a 512-Kbyte private L2 cache
	12	. The Multi Accelerator Platform Engine for Femto BaseStation Baseband
	13	Processing (MAPLE-B2F)
	14	. A multi-standard baseband algorithm accelerator for Channel Decoding/Encoding,
	15	Fourier Transforms, UMTS chip rate processing, LTE UP/DL Channel processing,
	16	and CRC algorithms
	17	. Consists of accelerators for Convolution, Filtering, Turbo Encoding,
	18	Turbo Decoding, Viterbi decoding, Chiprate processing, and Matrix Inversion
	19	operations
	20	. DDR3/3L memory interface with 32-bit data width without ECC and 16-bit with
	21	ECC, up to 400-MHz clock/800 MHz data rate
	22	. Dedicated security engine featuring trusted boot
	23	. DMA controller
	24	. OCNDMA with four bidirectional channels
	25	. Interfaces
	26	. Two triple-speed Gigabit Ethernet controllers featuring network acceleration
	27	including IEEE 1588. v2 hardware support and virtualization (eTSEC)
	28	. eTSEC 1 supports RGMII/RMII
	29	. eTSEC 2 supports RGMII
	30	. High-speed USB 2.0 host and device controller with ULPI interface
	31	. Enhanced secure digital (SD/MMC) host controller (eSDHC)
	32	. Antenna interface controller (AIC), supporting three industry standard
	33	JESD207/three custom ADI RF interfaces (two dual port and one single port)
	34	and three MAXIM's MaxPHY serial interfaces
	35	. ADI lanes support both full duplex FDD support and half duplex TDD support
	36	. Universal Subscriber Identity Module (USIM) interface that facilitates
	37	communication to SIM cards or Eurochip pre-paid phone cards
	38	. TDM with one TDM port
	39	. Two DUART, four eSPI, and two I2C controllers
	40	. Integrated Flash memory controller (IFC)
	41	. TDM with 256 channels
	42	. GPIO
	43	. Sixteen 32-bit timers
	44
	45	The e500 core subsystem within the Power Architecture consists of the following:
	46	. 32-Kbyte L1 instruction cache
	47	. 32-Kbyte L1 data cache
	48	. 256-Kbyte L2 cache/L2 memory/L2 stash
	49	. programmable interrupt controller (PIC)
	50	. Debug support
	51	. Timers
	52
	53	The SC3850 core subsystem consists of the following:
	54	. 32 Kbyte 8-way level 1 instruction cache (L1 ICache)
	55	. 32 Kbyte 8-way level 1 data cache (L1 DCache)
	56	. 512 Kbyte 8-way level 2 unified instruction/data cache (M2 memory)
	57	. Memory management unit (MMU)
	58	. Enhanced programmable interrupt controller (EPIC)
	59	. Debug and profiling unit (DPU)
	60	. Two 32-bit timers
	61
	62	BSC9131RDB board Overview
	63	-------------------------
	64	1Gbyte DDR3 (on board DDR)
65	128Mbyte 2K page size NAND Flash
66	256 Kbit M24256 I2C EEPROM
67	128 Mbit SPI Flash memory
68	USB-ULPI
69	eTSEC1: Connected to RGMII PHY
70	eTSEC2: Connected to RGMII PHY
71	DUART interface: supports one UARTs up to 115200 bps for console display
72	USIM connector
73
74	Frequency Combinations Supported
75	--------------------------------
76	Core MHz/CCB MHz/DDR(MT/s)
77	1. 1000/500/800
78	2. 800/400/667
79
80	Boot Methods Supported
81	-----------------------
82	1. NAND Flash
83	2. SPI Flash
84
85	Default Boot Method
86	--------------------
87	NAND boot
88
a187559e	89	Building U-Boot
7530d341	90	--------------
a187559e	91	To build the U-Boot for BSC9131RDB:
087cf44f	92	1. NAND Flash with sysclk 66MHz(J16 on RDB closed, default)
7530d341	93	make BSC9131RDB_NAND
087cf44f PJ	94	2. NAND Flash with sysclk 100MHz(J16 on RDB open)
	95	make BSC9131RDB_NAND_SYSCLK100
	96	3. SPI Flash with sysclk 66MHz(J16 on RDB closed, default)
7530d341	97	make BSC9131RDB_SPIFLASH
087cf44f PJ	98	4. SPI Flash with sysclk 100MHz(J16 on RDB open)
087cf44f PJ	99	make BSC9131RDB_SPIFLASH_SYSCLK100
7530d341 PK	100
	101	Memory map
	102	-----------
	103	0x0000_0000 0x7FFF_FFFF DDR 1G cacheable
	104	0xA0000000 0xBFFFFFFF Shared DSP core L2/M2 space 512M
	105	0xC100_0000 0xC13F_FFFF MAPLE-2F 4M
	106	0xC1F0_0000 0xC1F3_FFFF PA SRAM Region 0 256K
	107	0xC1F8_0000 0xC1F9_FFFF PA SRAM Region 1 128K
	108	0xFED0_0000 0xFED0_3FFF SEC Secured RAM 16K
	109	0xFEE0_0000 0xFEE0_0FFF DSP Boot ROM 4K
	110	0xFF60_0000 0xFF6F_FFFF DSP CCSR 1M
	111	0xFF70_0000 0xFF7F_FFFF PA CCSR 1M
	112	0xFF80_0000 0xFFFF_FFFF Boot Page & NAND Buffer 8M
	113
1d2949ae PJ	114	DDR Memory map
	115	---------------
	116	0x0000_0000 0x36FF_FFFF Memory passed onto Linux
	117	0x3700_0000 0x37FF_FFFF PowerPC-DSP shared control area
	118	0x3800_0000 0x4FFF_FFFF DSP Private area
	119
	120	Out of 880M, passed onto Linux, 1hugetlb page of 256M is reserved for
	121	data communcation between PowerPC and DSP core.
	122	Rest is PowerPC private area.
	123
7530d341 PK	124	Flashing Images
7530d341 PK	125	---------------
a187559e	126	To place a new U-Boot image in the NAND flash and then boot
7530d341 PK	127	with that new image temporarily, use this:
	128	tftp 1000000 u-boot-nand.bin
	129	nand erase 0 100000
	130	nand write 1000000 0 100000
	131	reset
	132
	133	Using the Device Tree Source File
	134	---------------------------------
	135	To create the DTB (Device Tree Binary) image file,
	136	use a command similar to this:
	137
	138	dtc -b 0 -f -I dts -O dtb bsc9131rdb.dts > bsc9131rdb.dtb
	139
	140	Likely, that .dts file will come from here;
	141
	142	linux-2.6/arch/powerpc/boot/dts/bsc9131rdb.dts
	143
	144	Booting Linux
	145	-------------
	146	Place a linux uImage in the TFTP disk area.
	147
	148	tftp 1000000 uImage
	149	tftp 2000000 rootfs.ext2.gz.uboot
	150	tftp c00000 bsc9131rdb.dtb
	151	bootm 1000000 2000000 c00000