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7530d341 PK |
1 | /* |
2 | * Copyright 2011-2012 Freescale Semiconductor, Inc. | |
3 | * | |
1a459660 | 4 | * SPDX-License-Identifier: GPL-2.0+ |
7530d341 PK |
5 | */ |
6 | ||
7 | #include <common.h> | |
8 | #include <asm/mmu.h> | |
9 | ||
10 | struct fsl_e_tlb_entry tlb_table[] = { | |
11 | /* TLB 0 - for temp stack in cache */ | |
12 | SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, CONFIG_SYS_INIT_RAM_ADDR, | |
13 | MAS3_SX|MAS3_SW|MAS3_SR, 0, | |
14 | 0, 0, BOOKE_PAGESZ_4K, 0), | |
15 | SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024 , | |
16 | CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024, | |
17 | MAS3_SX|MAS3_SW|MAS3_SR, 0, | |
18 | 0, 0, BOOKE_PAGESZ_4K, 0), | |
19 | SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024 , | |
20 | CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024, | |
21 | MAS3_SX|MAS3_SW|MAS3_SR, 0, | |
22 | 0, 0, BOOKE_PAGESZ_4K, 0), | |
23 | SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024 , | |
24 | CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024, | |
25 | MAS3_SX|MAS3_SW|MAS3_SR, 0, | |
26 | 0, 0, BOOKE_PAGESZ_4K, 0), | |
27 | ||
28 | /* TLB 1 */ | |
29 | /* *I*** - Covers boot page */ | |
f64bd7c0 PK |
30 | SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000, |
31 | MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, | |
32 | 0, 0, BOOKE_PAGESZ_4K, 1), | |
fbe76ae4 | 33 | #ifdef CONFIG_SPL_NAND_BOOT |
f64bd7c0 PK |
34 | SET_TLB_ENTRY(1, 0xffffe000, 0xffffe000, |
35 | MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, | |
36 | 0, 10, BOOKE_PAGESZ_4K, 1), | |
37 | #endif | |
7530d341 PK |
38 | |
39 | /* *I*G* - CCSRBAR (PA) */ | |
40 | SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS, | |
41 | MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, | |
42 | 0, 1, BOOKE_PAGESZ_1M, 1), | |
43 | ||
765b0bdb PJ |
44 | /* CCSRBAR (DSP) */ |
45 | SET_TLB_ENTRY(1, CONFIG_SYS_FSL_DSP_CCSRBAR, | |
46 | CONFIG_SYS_FSL_DSP_CCSRBAR_PHYS, | |
47 | MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, | |
48 | 0, 2, BOOKE_PAGESZ_1M, 1), | |
49 | ||
f1593269 | 50 | #if defined(CONFIG_SYS_RAMBOOT) || defined(CONFIG_SPL) |
7530d341 PK |
51 | SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE, |
52 | MAS3_SX|MAS3_SW|MAS3_SR, 0, | |
53 | 0, 8, BOOKE_PAGESZ_1G, 1), | |
54 | #endif | |
55 | ||
56 | SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS, | |
57 | MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, | |
58 | 0, 3, BOOKE_PAGESZ_1M, 1) | |
59 | ||
60 | }; | |
61 | ||
62 | int num_tlb_entries = ARRAY_SIZE(tlb_table); |