[people/ms/u-boot.git] / board / freescale / ls1043aqds / ls1043aqds.c

/*
 * Copyright 2015 Freescale Semiconductor, Inc.
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#include <common.h>
#include <i2c.h>
#include <fdt_support.h>
#include <fsl_ddr_sdram.h>
#include <asm/io.h>
#include <asm/arch/clock.h>
#include <asm/arch/fsl_serdes.h>
#include <asm/arch/fdt.h>
#include <asm/arch/mmu.h>
#include <asm/arch/soc.h>
#include <ahci.h>
#include <hwconfig.h>
#include <mmc.h>
#include <scsi.h>
#include <fm_eth.h>
#include <fsl_esdhc.h>
#include <fsl_ifc.h>
#include <spl.h>

#include "../common/qixis.h"
#include "ls1043aqds_qixis.h"

DECLARE_GLOBAL_DATA_PTR;

enum {
	MUX_TYPE_GPIO,
};

/* LS1043AQDS serdes mux */
#define CFG_SD_MUX1_SLOT2	0x0 /* SLOT2 TX/RX0 */
#define CFG_SD_MUX1_SLOT1	0x1 /* SLOT1 TX/RX1 */
#define CFG_SD_MUX2_SLOT3	0x0 /* SLOT3 TX/RX0 */
#define CFG_SD_MUX2_SLOT1	0x1 /* SLOT1 TX/RX2 */
#define CFG_SD_MUX3_SLOT4	0x0 /* SLOT4 TX/RX0 */
#define CFG_SD_MUX3_MUX4	0x1 /* MUX4 */
#define CFG_SD_MUX4_SLOT3	0x0 /* SLOT3 TX/RX1 */
#define CFG_SD_MUX4_SLOT1	0x1 /* SLOT1 TX/RX3 */
#define CFG_UART_MUX_MASK	0x6
#define CFG_UART_MUX_SHIFT	1
#define CFG_LPUART_EN		0x1

int checkboard(void)
{
	char buf[64];
#ifndef CONFIG_SD_BOOT
	u8 sw;
#endif

	puts("Board: LS1043AQDS, boot from ");

#ifdef CONFIG_SD_BOOT
	puts("SD\n");
#else
	sw = QIXIS_READ(brdcfg[0]);
	sw = (sw & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT;

	if (sw < 0x8)
		printf("vBank: %d\n", sw);
	else if (sw == 0x8)
		puts("PromJet\n");
	else if (sw == 0x9)
		puts("NAND\n");
	else if (sw == 0xF)
		printf("QSPI\n");
	else
		printf("invalid setting of SW%u\n", QIXIS_LBMAP_SWITCH);
#endif

	printf("Sys ID: 0x%02x, Sys Ver: 0x%02x\n",
	       QIXIS_READ(id), QIXIS_READ(arch));

	printf("FPGA:  v%d (%s), build %d\n",
	       (int)QIXIS_READ(scver), qixis_read_tag(buf),
	       (int)qixis_read_minor());

	return 0;
}

bool if_board_diff_clk(void)
{
	u8 diff_conf = QIXIS_READ(brdcfg[11]);

	return diff_conf & 0x40;
}

unsigned long get_board_sys_clk(void)
{
	u8 sysclk_conf = QIXIS_READ(brdcfg[1]);

	switch (sysclk_conf & 0x0f) {
	case QIXIS_SYSCLK_64:
		return 64000000;
	case QIXIS_SYSCLK_83:
		return 83333333;
	case QIXIS_SYSCLK_100:
		return 100000000;
	case QIXIS_SYSCLK_125:
		return 125000000;
	case QIXIS_SYSCLK_133:
		return 133333333;
	case QIXIS_SYSCLK_150:
		return 150000000;
	case QIXIS_SYSCLK_160:
		return 160000000;
	case QIXIS_SYSCLK_166:
		return 166666666;
	}

	return 66666666;
}

unsigned long get_board_ddr_clk(void)
{
	u8 ddrclk_conf = QIXIS_READ(brdcfg[1]);

	if (if_board_diff_clk())
		return get_board_sys_clk();
	switch ((ddrclk_conf & 0x30) >> 4) {
	case QIXIS_DDRCLK_100:
		return 100000000;
	case QIXIS_DDRCLK_125:
		return 125000000;
	case QIXIS_DDRCLK_133:
		return 133333333;
	}

	return 66666666;
}

int select_i2c_ch_pca9547(u8 ch)
{
	int ret;

	ret = i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &ch, 1);
	if (ret) {
		puts("PCA: failed to select proper channel\n");
		return ret;
	}

	return 0;
}

int dram_init(void)
{
	/*
	 * When resuming from deep sleep, the I2C channel may not be
	 * in the default channel. So, switch to the default channel
	 * before accessing DDR SPD.
	 */
	select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
	fsl_initdram();
#if !defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD)
	/* This will break-before-make MMU for DDR */
	update_early_mmu_table();
#endif

	return 0;
}

int i2c_multiplexer_select_vid_channel(u8 channel)
{
	return select_i2c_ch_pca9547(channel);
}

void board_retimer_init(void)
{
	u8 reg;

	/* Retimer is connected to I2C1_CH7_CH5 */
	select_i2c_ch_pca9547(I2C_MUX_CH7);
	reg = I2C_MUX_CH5;
	i2c_write(I2C_MUX_PCA_ADDR_SEC, 0, 1, &reg, 1);

	/* Access to Control/Shared register */
	reg = 0x0;
	i2c_write(I2C_RETIMER_ADDR, 0xff, 1, &reg, 1);

	/* Read device revision and ID */
	i2c_read(I2C_RETIMER_ADDR, 1, 1, &reg, 1);
	debug("Retimer version id = 0x%x\n", reg);

	/* Enable Broadcast. All writes target all channel register sets */
	reg = 0x0c;
	i2c_write(I2C_RETIMER_ADDR, 0xff, 1, &reg, 1);

	/* Reset Channel Registers */
	i2c_read(I2C_RETIMER_ADDR, 0, 1, &reg, 1);
	reg |= 0x4;
	i2c_write(I2C_RETIMER_ADDR, 0, 1, &reg, 1);

	/* Enable override divider select and Enable Override Output Mux */
	i2c_read(I2C_RETIMER_ADDR, 9, 1, &reg, 1);
	reg |= 0x24;
	i2c_write(I2C_RETIMER_ADDR, 9, 1, &reg, 1);

	/* Select VCO Divider to full rate (000) */
	i2c_read(I2C_RETIMER_ADDR, 0x18, 1, &reg, 1);
	reg &= 0x8f;
	i2c_write(I2C_RETIMER_ADDR, 0x18, 1, &reg, 1);

	/* Selects active PFD MUX Input as Re-timed Data (001) */
	i2c_read(I2C_RETIMER_ADDR, 0x1e, 1, &reg, 1);
	reg &= 0x3f;
	reg |= 0x20;
	i2c_write(I2C_RETIMER_ADDR, 0x1e, 1, &reg, 1);

	/* Set data rate as 10.3125 Gbps */
	reg = 0x0;
	i2c_write(I2C_RETIMER_ADDR, 0x60, 1, &reg, 1);
	reg = 0xb2;
	i2c_write(I2C_RETIMER_ADDR, 0x61, 1, &reg, 1);
	reg = 0x90;
	i2c_write(I2C_RETIMER_ADDR, 0x62, 1, &reg, 1);
	reg = 0xb3;
	i2c_write(I2C_RETIMER_ADDR, 0x63, 1, &reg, 1);
	reg = 0xcd;
	i2c_write(I2C_RETIMER_ADDR, 0x64, 1, &reg, 1);

	/* Return the default channel */
	select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
}

int board_early_init_f(void)
{
#ifdef CONFIG_HAS_FSL_XHCI_USB
	struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
	u32 usb_pwrfault;
#endif
#ifdef CONFIG_LPUART
	u8 uart;
#endif

#ifdef CONFIG_SYS_I2C_EARLY_INIT
	i2c_early_init_f();
#endif
	fsl_lsch2_early_init_f();

#ifdef CONFIG_HAS_FSL_XHCI_USB
	out_be32(&scfg->rcwpmuxcr0, 0x3333);
	out_be32(&scfg->usbdrvvbus_selcr, SCFG_USBDRVVBUS_SELCR_USB1);
	usb_pwrfault =
		(SCFG_USBPWRFAULT_DEDICATED << SCFG_USBPWRFAULT_USB3_SHIFT) |
		(SCFG_USBPWRFAULT_DEDICATED << SCFG_USBPWRFAULT_USB2_SHIFT) |
		(SCFG_USBPWRFAULT_SHARED << SCFG_USBPWRFAULT_USB1_SHIFT);
	out_be32(&scfg->usbpwrfault_selcr, usb_pwrfault);
#endif

#ifdef CONFIG_LPUART
	/* We use lpuart0 as system console */
	uart = QIXIS_READ(brdcfg[14]);
	uart &= ~CFG_UART_MUX_MASK;
	uart |= CFG_LPUART_EN << CFG_UART_MUX_SHIFT;
	QIXIS_WRITE(brdcfg[14], uart);
#endif

	return 0;
}

#ifdef CONFIG_FSL_DEEP_SLEEP
/* determine if it is a warm boot */
bool is_warm_boot(void)
{
#define DCFG_CCSR_CRSTSR_WDRFR	(1 << 3)
	struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;

	if (in_be32(&gur->crstsr) & DCFG_CCSR_CRSTSR_WDRFR)
		return 1;

	return 0;
}
#endif

int config_board_mux(int ctrl_type)
{
	u8 reg14;

	reg14 = QIXIS_READ(brdcfg[14]);

	switch (ctrl_type) {
	case MUX_TYPE_GPIO:
		reg14 = (reg14 & (~0x30)) | 0x20;
		break;
	default:
		puts("Unsupported mux interface type\n");
		return -1;
	}

	QIXIS_WRITE(brdcfg[14], reg14);

	return 0;
}

int config_serdes_mux(void)
{
	return 0;
}


#ifdef CONFIG_MISC_INIT_R
int misc_init_r(void)
{
	if (hwconfig("gpio"))
		config_board_mux(MUX_TYPE_GPIO);

	return 0;
}
#endif

int board_init(void)
{
#ifdef CONFIG_SYS_FSL_ERRATUM_A010315
	erratum_a010315();
#endif

	select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
	board_retimer_init();

#ifdef CONFIG_SYS_FSL_SERDES
	config_serdes_mux();
#endif

	return 0;
}

#ifdef CONFIG_OF_BOARD_SETUP
int ft_board_setup(void *blob, bd_t *bd)
{
	u64 base[CONFIG_NR_DRAM_BANKS];
	u64 size[CONFIG_NR_DRAM_BANKS];
	u8 reg;

	/* fixup DT for the two DDR banks */
	base[0] = gd->bd->bi_dram[0].start;
	size[0] = gd->bd->bi_dram[0].size;
	base[1] = gd->bd->bi_dram[1].start;
	size[1] = gd->bd->bi_dram[1].size;

	fdt_fixup_memory_banks(blob, base, size, 2);
	ft_cpu_setup(blob, bd);

#ifdef CONFIG_SYS_DPAA_FMAN
	fdt_fixup_fman_ethernet(blob);
	fdt_fixup_board_enet(blob);
#endif

	reg = QIXIS_READ(brdcfg[0]);
	reg = (reg & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT;

	/* Disable IFC if QSPI is enabled */
	if (reg == 0xF)
		do_fixup_by_compat(blob, "fsl,ifc",
				   "status", "disabled", 8 + 1, 1);

	return 0;
}
#endif

u8 flash_read8(void *addr)
{
	return __raw_readb(addr + 1);
}

void flash_write16(u16 val, void *addr)
{
	u16 shftval = (((val >> 8) & 0xff) | ((val << 8) & 0xff00));

	__raw_writew(shftval, addr);
}

u16 flash_read16(void *addr)
{
	u16 val = __raw_readw(addr);

	return (((val) >> 8) & 0x00ff) | (((val) << 8) & 0xff00);
}
Commit	Line	Data
02b5d2ed SX	1	/*
	2	* Copyright 2015 Freescale Semiconductor, Inc.
	3	*
	4	* SPDX-License-Identifier: GPL-2.0+
	5	*/
	6
	7	#include <common.h>
	8	#include <i2c.h>
	9	#include <fdt_support.h>
3eace37e	10	#include <fsl_ddr_sdram.h>
02b5d2ed SX	11	#include <asm/io.h>
	12	#include <asm/arch/clock.h>
	13	#include <asm/arch/fsl_serdes.h>
	14	#include <asm/arch/fdt.h>
4961eafc	15	#include <asm/arch/mmu.h>
02b5d2ed SX	16	#include <asm/arch/soc.h>
	17	#include <ahci.h>
	18	#include <hwconfig.h>
	19	#include <mmc.h>
	20	#include <scsi.h>
	21	#include <fm_eth.h>
02b5d2ed SX	22	#include <fsl_esdhc.h>
	23	#include <fsl_ifc.h>
	24	#include <spl.h>
	25
	26	#include "../common/qixis.h"
	27	#include "ls1043aqds_qixis.h"
	28
	29	DECLARE_GLOBAL_DATA_PTR;
	30
	31	enum {
	32	MUX_TYPE_GPIO,
	33	};
	34
	35	/* LS1043AQDS serdes mux */
	36	#define CFG_SD_MUX1_SLOT2 0x0 /* SLOT2 TX/RX0 */
	37	#define CFG_SD_MUX1_SLOT1 0x1 /* SLOT1 TX/RX1 */
	38	#define CFG_SD_MUX2_SLOT3 0x0 /* SLOT3 TX/RX0 */
	39	#define CFG_SD_MUX2_SLOT1 0x1 /* SLOT1 TX/RX2 */
	40	#define CFG_SD_MUX3_SLOT4 0x0 /* SLOT4 TX/RX0 */
	41	#define CFG_SD_MUX3_MUX4 0x1 /* MUX4 */
	42	#define CFG_SD_MUX4_SLOT3 0x0 /* SLOT3 TX/RX1 */
	43	#define CFG_SD_MUX4_SLOT1 0x1 /* SLOT1 TX/RX3 */
8c35cc3b SX	44	#define CFG_UART_MUX_MASK 0x6
	45	#define CFG_UART_MUX_SHIFT 1
	46	#define CFG_LPUART_EN 0x1
02b5d2ed SX	47
	48	int checkboard(void)
	49	{
	50	char buf[64];
a2fd238e	51	#ifndef CONFIG_SD_BOOT
02b5d2ed SX	52	u8 sw;
	53	#endif
	54
	55	puts("Board: LS1043AQDS, boot from ");
	56
	57	#ifdef CONFIG_SD_BOOT
	58	puts("SD\n");
	59	#else
	60	sw = QIXIS_READ(brdcfg[0]);
	61	sw = (sw & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT;
	62
	63	if (sw < 0x8)
	64	printf("vBank: %d\n", sw);
	65	else if (sw == 0x8)
	66	puts("PromJet\n");
	67	else if (sw == 0x9)
	68	puts("NAND\n");
a2fd238e QG	69	else if (sw == 0xF)
a2fd238e QG	70	printf("QSPI\n");
02b5d2ed SX	71	else
	72	printf("invalid setting of SW%u\n", QIXIS_LBMAP_SWITCH);
	73	#endif
	74
	75	printf("Sys ID: 0x%02x, Sys Ver: 0x%02x\n",
	76	QIXIS_READ(id), QIXIS_READ(arch));
	77
	78	printf("FPGA: v%d (%s), build %d\n",
	79	(int)QIXIS_READ(scver), qixis_read_tag(buf),
	80	(int)qixis_read_minor());
	81
	82	return 0;
	83	}
	84
	85	bool if_board_diff_clk(void)
	86	{
	87	u8 diff_conf = QIXIS_READ(brdcfg[11]);
	88
	89	return diff_conf & 0x40;
	90	}
	91
	92	unsigned long get_board_sys_clk(void)
	93	{
	94	u8 sysclk_conf = QIXIS_READ(brdcfg[1]);
	95
	96	switch (sysclk_conf & 0x0f) {
	97	case QIXIS_SYSCLK_64:
	98	return 64000000;
	99	case QIXIS_SYSCLK_83:
	100	return 83333333;
	101	case QIXIS_SYSCLK_100:
	102	return 100000000;
	103	case QIXIS_SYSCLK_125:
	104	return 125000000;
	105	case QIXIS_SYSCLK_133:
	106	return 133333333;
	107	case QIXIS_SYSCLK_150:
	108	return 150000000;
	109	case QIXIS_SYSCLK_160:
	110	return 160000000;
	111	case QIXIS_SYSCLK_166:
	112	return 166666666;
	113	}
	114
	115	return 66666666;
	116	}
	117
	118	unsigned long get_board_ddr_clk(void)
	119	{
	120	u8 ddrclk_conf = QIXIS_READ(brdcfg[1]);
	121
	122	if (if_board_diff_clk())
	123	return get_board_sys_clk();
	124	switch ((ddrclk_conf & 0x30) >> 4) {
	125	case QIXIS_DDRCLK_100:
	126	return 100000000;
	127	case QIXIS_DDRCLK_125:
	128	return 125000000;
	129	case QIXIS_DDRCLK_133:
	130	return 133333333;
	131	}
	132
	133	return 66666666;
	134	}
135
136	int select_i2c_ch_pca9547(u8 ch)
137	{
138	int ret;
139
140	ret = i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &ch, 1);
141	if (ret) {
142	puts("PCA: failed to select proper channel\n");
143	return ret;
144	}
145
146	return 0;
147	}
148
149	int dram_init(void)
150	{
151	/*
152	* When resuming from deep sleep, the I2C channel may not be
153	* in the default channel. So, switch to the default channel
154	* before accessing DDR SPD.
155	*/
156	select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
3eace37e	157	fsl_initdram();
4961eafc YS	158	#if !defined(CONFIG_SPL) \|\| defined(CONFIG_SPL_BUILD)
	159	/* This will break-before-make MMU for DDR */
	160	update_early_mmu_table();
	161	#endif
02b5d2ed SX	162
	163	return 0;
	164	}
	165
	166	int i2c_multiplexer_select_vid_channel(u8 channel)
	167	{
	168	return select_i2c_ch_pca9547(channel);
	169	}
	170
	171	void board_retimer_init(void)
	172	{
	173	u8 reg;
	174
	175	/* Retimer is connected to I2C1_CH7_CH5 */
ec44289d	176	select_i2c_ch_pca9547(I2C_MUX_CH7);
02b5d2ed SX	177	reg = I2C_MUX_CH5;
	178	i2c_write(I2C_MUX_PCA_ADDR_SEC, 0, 1, &reg, 1);
	179
	180	/* Access to Control/Shared register */
	181	reg = 0x0;
	182	i2c_write(I2C_RETIMER_ADDR, 0xff, 1, &reg, 1);
	183
	184	/* Read device revision and ID */
	185	i2c_read(I2C_RETIMER_ADDR, 1, 1, &reg, 1);
	186	debug("Retimer version id = 0x%x\n", reg);
	187
	188	/* Enable Broadcast. All writes target all channel register sets */
	189	reg = 0x0c;
	190	i2c_write(I2C_RETIMER_ADDR, 0xff, 1, &reg, 1);
	191
	192	/* Reset Channel Registers */
	193	i2c_read(I2C_RETIMER_ADDR, 0, 1, &reg, 1);
	194	reg \|= 0x4;
	195	i2c_write(I2C_RETIMER_ADDR, 0, 1, &reg, 1);
	196
	197	/* Enable override divider select and Enable Override Output Mux */
	198	i2c_read(I2C_RETIMER_ADDR, 9, 1, &reg, 1);
	199	reg \|= 0x24;
	200	i2c_write(I2C_RETIMER_ADDR, 9, 1, &reg, 1);
	201
	202	/* Select VCO Divider to full rate (000) */
	203	i2c_read(I2C_RETIMER_ADDR, 0x18, 1, &reg, 1);
	204	reg &= 0x8f;
	205	i2c_write(I2C_RETIMER_ADDR, 0x18, 1, &reg, 1);
	206
	207	/* Selects active PFD MUX Input as Re-timed Data (001) */
	208	i2c_read(I2C_RETIMER_ADDR, 0x1e, 1, &reg, 1);
	209	reg &= 0x3f;
	210	reg \|= 0x20;
	211	i2c_write(I2C_RETIMER_ADDR, 0x1e, 1, &reg, 1);
	212
	213	/* Set data rate as 10.3125 Gbps */
	214	reg = 0x0;
	215	i2c_write(I2C_RETIMER_ADDR, 0x60, 1, &reg, 1);
	216	reg = 0xb2;
	217	i2c_write(I2C_RETIMER_ADDR, 0x61, 1, &reg, 1);
	218	reg = 0x90;
	219	i2c_write(I2C_RETIMER_ADDR, 0x62, 1, &reg, 1);
	220	reg = 0xb3;
	221	i2c_write(I2C_RETIMER_ADDR, 0x63, 1, &reg, 1);
	222	reg = 0xcd;
	223	i2c_write(I2C_RETIMER_ADDR, 0x64, 1, &reg, 1);
ec44289d WS	224
	225	/* Return the default channel */
	226	select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
02b5d2ed SX	227	}
	228
	229	int board_early_init_f(void)
	230	{
5a7c40be QG	231	#ifdef CONFIG_HAS_FSL_XHCI_USB
	232	struct ccsr_scfg scfg = (struct ccsr_scfg )CONFIG_SYS_FSL_SCFG_ADDR;
	233	u32 usb_pwrfault;
	234	#endif
8c35cc3b SX	235	#ifdef CONFIG_LPUART
	236	u8 uart;
	237	#endif
581ff00b QG	238
	239	#ifdef CONFIG_SYS_I2C_EARLY_INIT
	240	i2c_early_init_f();
	241	#endif
02b5d2ed	242	fsl_lsch2_early_init_f();
5a7c40be QG	243
	244	#ifdef CONFIG_HAS_FSL_XHCI_USB
	245	out_be32(&scfg->rcwpmuxcr0, 0x3333);
	246	out_be32(&scfg->usbdrvvbus_selcr, SCFG_USBDRVVBUS_SELCR_USB1);
	247	usb_pwrfault =
3e06ba8f SX	248	(SCFG_USBPWRFAULT_DEDICATED << SCFG_USBPWRFAULT_USB3_SHIFT) \|
3e06ba8f SX	249	(SCFG_USBPWRFAULT_DEDICATED << SCFG_USBPWRFAULT_USB2_SHIFT) \|
5a7c40be QG	250	(SCFG_USBPWRFAULT_SHARED << SCFG_USBPWRFAULT_USB1_SHIFT);
	251	out_be32(&scfg->usbpwrfault_selcr, usb_pwrfault);
	252	#endif
	253
8c35cc3b SX	254	#ifdef CONFIG_LPUART
	255	/* We use lpuart0 as system console */
	256	uart = QIXIS_READ(brdcfg[14]);
	257	uart &= ~CFG_UART_MUX_MASK;
	258	uart \|= CFG_LPUART_EN << CFG_UART_MUX_SHIFT;
	259	QIXIS_WRITE(brdcfg[14], uart);
	260	#endif
02b5d2ed SX	261
	262	return 0;
	263	}
	264
	265	#ifdef CONFIG_FSL_DEEP_SLEEP
	266	/* determine if it is a warm boot */
	267	bool is_warm_boot(void)
	268	{
	269	#define DCFG_CCSR_CRSTSR_WDRFR (1 << 3)
	270	struct ccsr_gur __iomem gur = (void )CONFIG_SYS_FSL_GUTS_ADDR;
	271
	272	if (in_be32(&gur->crstsr) & DCFG_CCSR_CRSTSR_WDRFR)
	273	return 1;
	274
	275	return 0;
	276	}
	277	#endif
	278
	279	int config_board_mux(int ctrl_type)
	280	{
	281	u8 reg14;
	282
	283	reg14 = QIXIS_READ(brdcfg[14]);
	284
	285	switch (ctrl_type) {
	286	case MUX_TYPE_GPIO:
	287	reg14 = (reg14 & (~0x30)) \| 0x20;
	288	break;
	289	default:
	290	puts("Unsupported mux interface type\n");
	291	return -1;
	292	}
	293
	294	QIXIS_WRITE(brdcfg[14], reg14);
	295
	296	return 0;
	297	}
	298
	299	int config_serdes_mux(void)
	300	{
	301	return 0;
	302	}
	303
	304
	305	#ifdef CONFIG_MISC_INIT_R
	306	int misc_init_r(void)
	307	{
	308	if (hwconfig("gpio"))
	309	config_board_mux(MUX_TYPE_GPIO);
	310
	311	return 0;
	312	}
	313	#endif
	314
	315	int board_init(void)
	316	{
b392a6d4 HZ	317	#ifdef CONFIG_SYS_FSL_ERRATUM_A010315
	318	erratum_a010315();
	319	#endif
	320
02b5d2ed SX	321	select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
	322	board_retimer_init();
	323
	324	#ifdef CONFIG_SYS_FSL_SERDES
	325	config_serdes_mux();
	326	#endif
	327
02b5d2ed SX	328	return 0;
	329	}
	330
	331	#ifdef CONFIG_OF_BOARD_SETUP
	332	int ft_board_setup(void blob, bd_t bd)
	333	{
58e4ad1d SX	334	u64 base[CONFIG_NR_DRAM_BANKS];
58e4ad1d SX	335	u64 size[CONFIG_NR_DRAM_BANKS];
8401c710	336	u8 reg;
58e4ad1d SX	337
	338	/* fixup DT for the two DDR banks */
	339	base[0] = gd->bd->bi_dram[0].start;
	340	size[0] = gd->bd->bi_dram[0].size;
	341	base[1] = gd->bd->bi_dram[1].start;
	342	size[1] = gd->bd->bi_dram[1].size;
	343
	344	fdt_fixup_memory_banks(blob, base, size, 2);
02b5d2ed SX	345	ft_cpu_setup(blob, bd);
	346
	347	#ifdef CONFIG_SYS_DPAA_FMAN
	348	fdt_fixup_fman_ethernet(blob);
	349	fdt_fixup_board_enet(blob);
	350	#endif
8401c710 QG	351
	352	reg = QIXIS_READ(brdcfg[0]);
	353	reg = (reg & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT;
	354
	355	/* Disable IFC if QSPI is enabled */
	356	if (reg == 0xF)
	357	do_fixup_by_compat(blob, "fsl,ifc",
	358	"status", "disabled", 8 + 1, 1);
	359
02b5d2ed SX	360	return 0;
	361	}
	362	#endif
	363
	364	u8 flash_read8(void *addr)
	365	{
	366	return __raw_readb(addr + 1);
	367	}
	368
	369	void flash_write16(u16 val, void *addr)
	370	{
	371	u16 shftval = (((val >> 8) & 0xff) \| ((val << 8) & 0xff00));
	372
	373	__raw_writew(shftval, addr);
	374	}
	375
	376	u16 flash_read16(void *addr)
	377	{
	378	u16 val = __raw_readw(addr);
	379
	380	return (((val) >> 8) & 0x00ff) \| (((val) << 8) & 0xff00);
	381	}