[people/ms/u-boot.git] / board / freescale / mpc8544ds / mpc8544ds.c

/*
 * Copyright 2007 Freescale Semiconductor, Inc.
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

#include <common.h>
#include <command.h>
#include <pci.h>
#include <asm/processor.h>
#include <asm/mmu.h>
#include <asm/immap_85xx.h>
#include <asm/fsl_pci.h>
#include <asm/fsl_ddr_sdram.h>
#include <asm/io.h>
#include <miiphy.h>
#include <libfdt.h>
#include <fdt_support.h>
#include <tsec.h>
#include <netdev.h>

#include "../common/pixis.h"
#include "../common/sgmii_riser.h"

int checkboard (void)
{
	volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
	volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR);
	volatile ccsr_local_ecm_t *ecm = (void *)(CONFIG_SYS_MPC85xx_ECM_ADDR);
	u8 vboot;
	u8 *pixis_base = (u8 *)PIXIS_BASE;

	if ((uint)&gur->porpllsr != 0xe00e0000) {
		printf("immap size error %lx\n",(ulong)&gur->porpllsr);
	}
	printf ("Board: MPC8544DS, Sys ID: 0x%02x, "
		"Sys Ver: 0x%02x, FPGA Ver: 0x%02x, ",
		in_8(pixis_base + PIXIS_ID), in_8(pixis_base + PIXIS_VER),
		in_8(pixis_base + PIXIS_PVER));

	vboot = in_8(pixis_base + PIXIS_VBOOT);
	if (vboot & PIXIS_VBOOT_FMAP)
		printf ("vBank: %d\n", ((vboot & PIXIS_VBOOT_FBANK) >> 6));
	else
		puts ("Promjet\n");

	lbc->ltesr = 0xffffffff;	/* Clear LBC error interrupts */
	lbc->lteir = 0xffffffff;	/* Enable LBC error interrupts */
	ecm->eedr = 0xffffffff;		/* Clear ecm errors */
	ecm->eeer = 0xffffffff;		/* Enable ecm errors */

	return 0;
}

phys_size_t
initdram(int board_type)
{
	long dram_size = 0;

	puts("Initializing\n");

	dram_size = fsl_ddr_sdram();

	dram_size = setup_ddr_tlbs(dram_size / 0x100000);

	dram_size *= 0x100000;

	puts("    DDR: ");
	return dram_size;
}

#ifdef CONFIG_PCI1
static struct pci_controller pci1_hose;
#endif

#ifdef CONFIG_PCIE1
static struct pci_controller pcie1_hose;
#endif

#ifdef CONFIG_PCIE2
static struct pci_controller pcie2_hose;
#endif

#ifdef CONFIG_PCIE3
static struct pci_controller pcie3_hose;
#endif

int first_free_busno=0;

void
pci_init_board(void)
{
	volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
	uint devdisr = gur->devdisr;
	uint io_sel = (gur->pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> 19;
	uint host_agent = (gur->porbmsr & MPC85xx_PORBMSR_HA) >> 16;

	debug ("   pci_init_board: devdisr=%x, io_sel=%x, host_agent=%x\n",
		devdisr, io_sel, host_agent);

	if (io_sel & 1) {
		if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII1_DIS))
			printf ("    eTSEC1 is in sgmii mode.\n");
		if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII3_DIS))
			printf ("    eTSEC3 is in sgmii mode.\n");
	}

#ifdef CONFIG_PCIE3
{
	volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE3_ADDR;
	struct pci_controller *hose = &pcie3_hose;
	int pcie_ep = is_fsl_pci_agent(LAW_TRGT_IF_PCIE_3, host_agent);
	int pcie_configured = is_fsl_pci_cfg(LAW_TRGT_IF_PCIE_3, io_sel);
	struct pci_region *r = hose->regions;

	if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){
		printf ("\n    PCIE3 connected to ULI as %s (base address %x)",
			pcie_ep ? "End Point" : "Root Complex",
			(uint)pci);
		if (pci->pme_msg_det) {
			pci->pme_msg_det = 0xffffffff;
			debug (" with errors.  Clearing.  Now 0x%08x",pci->pme_msg_det);
		}
		printf ("\n");

		/* outbound memory */
		pci_set_region(r++,
			       CONFIG_SYS_PCIE3_MEM_BUS,
			       CONFIG_SYS_PCIE3_MEM_PHYS,
			       CONFIG_SYS_PCIE3_MEM_SIZE,
			       PCI_REGION_MEM);

		/* outbound io */
		pci_set_region(r++,
			       CONFIG_SYS_PCIE3_IO_BUS,
			       CONFIG_SYS_PCIE3_IO_PHYS,
			       CONFIG_SYS_PCIE3_IO_SIZE,
			       PCI_REGION_IO);

#ifdef CONFIG_SYS_PCIE3_MEM_BUS2
		/* outbound memory */
		pci_set_region(r++,
			       CONFIG_SYS_PCIE3_MEM_BUS2,
			       CONFIG_SYS_PCIE3_MEM_PHYS2,
			       CONFIG_SYS_PCIE3_MEM_SIZE2,
			       PCI_REGION_MEM);
#endif
		hose->region_count = r - hose->regions;
		hose->first_busno=first_free_busno;

		fsl_pci_init(hose, (u32)&pci->cfg_addr, (u32)&pci->cfg_data);

		first_free_busno=hose->last_busno+1;
		printf ("    PCIE3 on bus %02x - %02x\n",
			hose->first_busno,hose->last_busno);

		/*
		 * Activate ULI1575 legacy chip by performing a fake
		 * memory access.  Needed to make ULI RTC work.
		 */
		in_be32((u32 *)CONFIG_SYS_PCIE3_MEM_BUS);
	} else {
		printf ("    PCIE3: disabled\n");
	}

 }
#else
	gur->devdisr |= MPC85xx_DEVDISR_PCIE3; /* disable */
#endif

#ifdef CONFIG_PCIE1
 {
	volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE1_ADDR;
	struct pci_controller *hose = &pcie1_hose;
	int pcie_ep = is_fsl_pci_agent(LAW_TRGT_IF_PCIE_1, host_agent);
	int pcie_configured = is_fsl_pci_cfg(LAW_TRGT_IF_PCIE_1, io_sel);
	struct pci_region *r = hose->regions;

	if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){
		printf ("\n    PCIE1 connected to Slot2 as %s (base address %x)",
			pcie_ep ? "End Point" : "Root Complex",
			(uint)pci);
		if (pci->pme_msg_det) {
			pci->pme_msg_det = 0xffffffff;
			debug (" with errors.  Clearing.  Now 0x%08x",pci->pme_msg_det);
		}
		printf ("\n");

		/* outbound memory */
		pci_set_region(r++,
			       CONFIG_SYS_PCIE1_MEM_BUS,
			       CONFIG_SYS_PCIE1_MEM_PHYS,
			       CONFIG_SYS_PCIE1_MEM_SIZE,
			       PCI_REGION_MEM);

		/* outbound io */
		pci_set_region(r++,
			       CONFIG_SYS_PCIE1_IO_BUS,
			       CONFIG_SYS_PCIE1_IO_PHYS,
			       CONFIG_SYS_PCIE1_IO_SIZE,
			       PCI_REGION_IO);

#ifdef CONFIG_SYS_PCIE1_MEM_BUS2
		/* outbound memory */
		pci_set_region(r++,
			       CONFIG_SYS_PCIE1_MEM_BUS2,
			       CONFIG_SYS_PCIE1_MEM_PHYS2,
			       CONFIG_SYS_PCIE1_MEM_SIZE2,
			       PCI_REGION_MEM);
#endif
		hose->region_count = r - hose->regions;
		hose->first_busno=first_free_busno;

		fsl_pci_init(hose, (u32)&pci->cfg_addr, (u32)&pci->cfg_data);

		first_free_busno=hose->last_busno+1;
		printf("    PCIE1 on bus %02x - %02x\n",
		       hose->first_busno,hose->last_busno);

	} else {
		printf ("    PCIE1: disabled\n");
	}

 }
#else
	gur->devdisr |= MPC85xx_DEVDISR_PCIE; /* disable */
#endif

#ifdef CONFIG_PCIE2
 {
	volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE2_ADDR;
	struct pci_controller *hose = &pcie2_hose;
	int pcie_ep = is_fsl_pci_agent(LAW_TRGT_IF_PCIE_2, host_agent);
	int pcie_configured = is_fsl_pci_cfg(LAW_TRGT_IF_PCIE_2, io_sel);
	struct pci_region *r = hose->regions;

	if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){
		printf ("\n    PCIE2 connected to Slot 1 as %s (base address %x)",
			pcie_ep ? "End Point" : "Root Complex",
			(uint)pci);
		if (pci->pme_msg_det) {
			pci->pme_msg_det = 0xffffffff;
			debug (" with errors.  Clearing.  Now 0x%08x",pci->pme_msg_det);
		}
		printf ("\n");

		/* outbound memory */
		pci_set_region(r++,
			       CONFIG_SYS_PCIE2_MEM_BUS,
			       CONFIG_SYS_PCIE2_MEM_PHYS,
			       CONFIG_SYS_PCIE2_MEM_SIZE,
			       PCI_REGION_MEM);

		/* outbound io */
		pci_set_region(r++,
			       CONFIG_SYS_PCIE2_IO_BUS,
			       CONFIG_SYS_PCIE2_IO_PHYS,
			       CONFIG_SYS_PCIE2_IO_SIZE,
			       PCI_REGION_IO);

#ifdef CONFIG_SYS_PCIE2_MEM_BUS2
		/* outbound memory */
		pci_set_region(r++,
			       CONFIG_SYS_PCIE2_MEM_BUS2,
			       CONFIG_SYS_PCIE2_MEM_PHYS2,
			       CONFIG_SYS_PCIE2_MEM_SIZE2,
			       PCI_REGION_MEM);
#endif
		hose->region_count = r - hose->regions;
		hose->first_busno=first_free_busno;

		fsl_pci_init(hose, (u32)&pci->cfg_addr, (u32)&pci->cfg_data);
		first_free_busno=hose->last_busno+1;
		printf ("    PCIE2 on bus %02x - %02x\n",
			hose->first_busno,hose->last_busno);

	} else {
		printf ("    PCIE2: disabled\n");
	}

 }
#else
	gur->devdisr |= MPC85xx_DEVDISR_PCIE2; /* disable */
#endif


#ifdef CONFIG_PCI1
{
	volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCI1_ADDR;
	struct pci_controller *hose = &pci1_hose;
	struct pci_region *r = hose->regions;

	uint pci_agent = is_fsl_pci_agent(LAW_TRGT_IF_PCI, host_agent);
	uint pci_speed = 66666000; /*get_clock_freq (); PCI PSPEED in [4:5] */
	uint pci_32 = 1;
	uint pci_arb = gur->pordevsr & MPC85xx_PORDEVSR_PCI1_ARB;	/* PORDEVSR[14] */
	uint pci_clk_sel = gur->porpllsr & MPC85xx_PORDEVSR_PCI1_SPD;	/* PORPLLSR[16] */


	if (!(devdisr & MPC85xx_DEVDISR_PCI1)) {
		printf ("\n    PCI: %d bit, %s MHz, %s, %s, %s (base address %x)\n",
			(pci_32) ? 32 : 64,
			(pci_speed == 33333000) ? "33" :
			(pci_speed == 66666000) ? "66" : "unknown",
			pci_clk_sel ? "sync" : "async",
			pci_agent ? "agent" : "host",
			pci_arb ? "arbiter" : "external-arbiter",
			(uint)pci
			);

		/* outbound memory */
		pci_set_region(r++,
			       CONFIG_SYS_PCI1_MEM_BUS,
			       CONFIG_SYS_PCI1_MEM_PHYS,
			       CONFIG_SYS_PCI1_MEM_SIZE,
			       PCI_REGION_MEM);

		/* outbound io */
		pci_set_region(r++,
			       CONFIG_SYS_PCI1_IO_BUS,
			       CONFIG_SYS_PCI1_IO_PHYS,
			       CONFIG_SYS_PCI1_IO_SIZE,
			       PCI_REGION_IO);

#ifdef CONFIG_SYS_PCIE3_MEM_BUS2
		/* outbound memory */
		pci_set_region(r++,
			       CONFIG_SYS_PCIE3_MEM_BUS2,
			       CONFIG_SYS_PCIE3_MEM_PHYS2,
			       CONFIG_SYS_PCIE3_MEM_SIZE2,
			       PCI_REGION_MEM);
#endif
		hose->region_count = r - hose->regions;
		hose->first_busno=first_free_busno;

		fsl_pci_init(hose, (u32)&pci->cfg_addr, (u32)&pci->cfg_data);
		first_free_busno=hose->last_busno+1;
		printf ("PCI on bus %02x - %02x\n",
			hose->first_busno,hose->last_busno);
	} else {
		printf ("    PCI: disabled\n");
	}
}
#else
	gur->devdisr |= MPC85xx_DEVDISR_PCI1; /* disable */
#endif
}


int last_stage_init(void)
{
	return 0;
}


unsigned long
get_board_sys_clk(ulong dummy)
{
	u8 i, go_bit, rd_clks;
	ulong val = 0;
	u8 *pixis_base = (u8 *)PIXIS_BASE;

	go_bit = in_8(pixis_base + PIXIS_VCTL);
	go_bit &= 0x01;

	rd_clks = in_8(pixis_base + PIXIS_VCFGEN0);
	rd_clks &= 0x1C;

	/*
	 * Only if both go bit and the SCLK bit in VCFGEN0 are set
	 * should we be using the AUX register. Remember, we also set the
	 * GO bit to boot from the alternate bank on the on-board flash
	 */

	if (go_bit) {
		if (rd_clks == 0x1c)
			i = in_8(pixis_base + PIXIS_AUX);
		else
			i = in_8(pixis_base + PIXIS_SPD);
	} else {
		i = in_8(pixis_base + PIXIS_SPD);
	}

	i &= 0x07;

	switch (i) {
	case 0:
		val = 33333333;
		break;
	case 1:
		val = 40000000;
		break;
	case 2:
		val = 50000000;
		break;
	case 3:
		val = 66666666;
		break;
	case 4:
		val = 83000000;
		break;
	case 5:
		val = 100000000;
		break;
	case 6:
		val = 133333333;
		break;
	case 7:
		val = 166666666;
		break;
	}

	return val;
}

int board_eth_init(bd_t *bis)
{
#ifdef CONFIG_TSEC_ENET
	struct tsec_info_struct tsec_info[2];
	volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
	uint io_sel = (gur->pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> 19;
	int num = 0;

#ifdef CONFIG_TSEC1
	SET_STD_TSEC_INFO(tsec_info[num], 1);
	if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII1_DIS))
		tsec_info[num].flags |= TSEC_SGMII;
	num++;
#endif
#ifdef CONFIG_TSEC3
	SET_STD_TSEC_INFO(tsec_info[num], 3);
	if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII3_DIS))
		tsec_info[num].flags |= TSEC_SGMII;
	num++;
#endif

	if (!num) {
		printf("No TSECs initialized\n");

		return 0;
	}

	if (io_sel & 1)
		fsl_sgmii_riser_init(tsec_info, num);


	tsec_eth_init(bis, tsec_info, num);
#endif
	return pci_eth_init(bis);
}

#if defined(CONFIG_OF_BOARD_SETUP)
void ft_board_setup(void *blob, bd_t *bd)
{
	ft_cpu_setup(blob, bd);


#ifdef CONFIG_PCI1
	ft_fsl_pci_setup(blob, "pci0", &pci1_hose);
#endif
#ifdef CONFIG_PCIE2
	ft_fsl_pci_setup(blob, "pci1", &pcie1_hose);
#endif
#ifdef CONFIG_PCIE1
	ft_fsl_pci_setup(blob, "pci2", &pcie3_hose);
#endif
#ifdef CONFIG_PCIE3
	ft_fsl_pci_setup(blob, "pci3", &pcie2_hose);
#endif
#ifdef CONFIG_FSL_SGMII_RISER
	fsl_sgmii_riser_fdt_fixup(blob);
#endif
}
#endif
Commit	Line	Data
25d83d7f JL	1	/*
	2	* Copyright 2007 Freescale Semiconductor, Inc.
	3	*
	4	* See file CREDITS for list of people who contributed to this
	5	* project.
	6	*
	7	* This program is free software; you can redistribute it and/or
	8	* modify it under the terms of the GNU General Public License as
	9	* published by the Free Software Foundation; either version 2 of
	10	* the License, or (at your option) any later version.
	11	*
	12	* This program is distributed in the hope that it will be useful,
	13	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	14	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	15	* GNU General Public License for more details.
	16	*
	17	* You should have received a copy of the GNU General Public License
	18	* along with this program; if not, write to the Free Software
	19	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	20	* MA 02111-1307 USA
	21	*/
	22
	23	#include <common.h>
	24	#include <command.h>
837f1ba0	25	#include <pci.h>
25d83d7f	26	#include <asm/processor.h>
1167a2fd	27	#include <asm/mmu.h>
25d83d7f	28	#include <asm/immap_85xx.h>
c8514622	29	#include <asm/fsl_pci.h>
1167a2fd	30	#include <asm/fsl_ddr_sdram.h>
56a92705	31	#include <asm/io.h>
25d83d7f	32	#include <miiphy.h>
addce57e KG	33	#include <libfdt.h>
addce57e KG	34	#include <fdt_support.h>
216f2a71	35	#include <tsec.h>
0b252f50	36	#include <netdev.h>
25d83d7f JL	37
25d83d7f JL	38	#include "../common/pixis.h"
216f2a71	39	#include "../common/sgmii_riser.h"
25d83d7f	40
25d83d7f JL	41	int checkboard (void)
25d83d7f JL	42	{
6d0f6bcf JCPV	43	volatile ccsr_gur_t gur = (void )(CONFIG_SYS_MPC85xx_GUTS_ADDR);
	44	volatile ccsr_lbc_t lbc = (void )(CONFIG_SYS_MPC85xx_LBC_ADDR);
	45	volatile ccsr_local_ecm_t ecm = (void )(CONFIG_SYS_MPC85xx_ECM_ADDR);
6bb5b412 KG	46	u8 vboot;
6bb5b412 KG	47	u8 pixis_base = (u8 )PIXIS_BASE;
25d83d7f	48
2f15278c	49	if ((uint)&gur->porpllsr != 0xe00e0000) {
9b55a253	50	printf("immap size error %lx\n",(ulong)&gur->porpllsr);
25d83d7f	51	}
6bb5b412 KG	52	printf ("Board: MPC8544DS, Sys ID: 0x%02x, "
	53	"Sys Ver: 0x%02x, FPGA Ver: 0x%02x, ",
	54	in_8(pixis_base + PIXIS_ID), in_8(pixis_base + PIXIS_VER),
	55	in_8(pixis_base + PIXIS_PVER));
	56
	57	vboot = in_8(pixis_base + PIXIS_VBOOT);
	58	if (vboot & PIXIS_VBOOT_FMAP)
	59	printf ("vBank: %d\n", ((vboot & PIXIS_VBOOT_FBANK) >> 6));
	60	else
	61	puts ("Promjet\n");
25d83d7f	62
837f1ba0 ES	63	lbc->ltesr = 0xffffffff; /* Clear LBC error interrupts */
	64	lbc->lteir = 0xffffffff; /* Enable LBC error interrupts */
	65	ecm->eedr = 0xffffffff; /* Clear ecm errors */
	66	ecm->eeer = 0xffffffff; /* Enable ecm errors */
	67
25d83d7f JL	68	return 0;
	69	}
	70
9973e3c6	71	phys_size_t
25d83d7f JL	72	initdram(int board_type)
	73	{
	74	long dram_size = 0;
	75
	76	puts("Initializing\n");
	77
1167a2fd KG	78	dram_size = fsl_ddr_sdram();
	79
	80	dram_size = setup_ddr_tlbs(dram_size / 0x100000);
	81
	82	dram_size *= 0x100000;
25d83d7f	83
25d83d7f JL	84	puts(" DDR: ");
	85	return dram_size;
	86	}
	87
837f1ba0 ES	88	#ifdef CONFIG_PCI1
	89	static struct pci_controller pci1_hose;
	90	#endif
	91
	92	#ifdef CONFIG_PCIE1
	93	static struct pci_controller pcie1_hose;
	94	#endif
	95
	96	#ifdef CONFIG_PCIE2
	97	static struct pci_controller pcie2_hose;
	98	#endif
	99
	100	#ifdef CONFIG_PCIE3
	101	static struct pci_controller pcie3_hose;
	102	#endif
	103
	104	int first_free_busno=0;
	105
	106	void
	107	pci_init_board(void)
	108	{
6d0f6bcf	109	volatile ccsr_gur_t gur = (void )(CONFIG_SYS_MPC85xx_GUTS_ADDR);
837f1ba0 ES	110	uint devdisr = gur->devdisr;
	111	uint io_sel = (gur->pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> 19;
	112	uint host_agent = (gur->porbmsr & MPC85xx_PORBMSR_HA) >> 16;
	113
	114	debug (" pci_init_board: devdisr=%x, io_sel=%x, host_agent=%x\n",
	115	devdisr, io_sel, host_agent);
	116
	117	if (io_sel & 1) {
	118	if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII1_DIS))
	119	printf (" eTSEC1 is in sgmii mode.\n");
	120	if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII3_DIS))
	121	printf (" eTSEC3 is in sgmii mode.\n");
	122	}
	123
	124	#ifdef CONFIG_PCIE3
	125	{
6d0f6bcf	126	volatile ccsr_fsl_pci_t pci = (ccsr_fsl_pci_t ) CONFIG_SYS_PCIE3_ADDR;
837f1ba0	127	struct pci_controller *hose = &pcie3_hose;
865f24dc KG	128	int pcie_ep = is_fsl_pci_agent(LAW_TRGT_IF_PCIE_3, host_agent);
865f24dc KG	129	int pcie_configured = is_fsl_pci_cfg(LAW_TRGT_IF_PCIE_3, io_sel);
2dba0dea	130	struct pci_region *r = hose->regions;
837f1ba0 ES	131
	132	if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){
	133	printf ("\n PCIE3 connected to ULI as %s (base address %x)",
	134	pcie_ep ? "End Point" : "Root Complex",
	135	(uint)pci);
	136	if (pci->pme_msg_det) {
	137	pci->pme_msg_det = 0xffffffff;
	138	debug (" with errors. Clearing. Now 0x%08x",pci->pme_msg_det);
	139	}
	140	printf ("\n");
	141
837f1ba0	142	/* outbound memory */
2dba0dea	143	pci_set_region(r++,
10795f42	144	CONFIG_SYS_PCIE3_MEM_BUS,
6d0f6bcf JCPV	145	CONFIG_SYS_PCIE3_MEM_PHYS,
6d0f6bcf JCPV	146	CONFIG_SYS_PCIE3_MEM_SIZE,
837f1ba0 ES	147	PCI_REGION_MEM);
	148
	149	/* outbound io */
2dba0dea	150	pci_set_region(r++,
5f91ef6a	151	CONFIG_SYS_PCIE3_IO_BUS,
6d0f6bcf JCPV	152	CONFIG_SYS_PCIE3_IO_PHYS,
6d0f6bcf JCPV	153	CONFIG_SYS_PCIE3_IO_SIZE,
837f1ba0 ES	154	PCI_REGION_IO);
837f1ba0 ES	155
10795f42	156	#ifdef CONFIG_SYS_PCIE3_MEM_BUS2
837f1ba0	157	/* outbound memory */
2dba0dea	158	pci_set_region(r++,
10795f42	159	CONFIG_SYS_PCIE3_MEM_BUS2,
6d0f6bcf JCPV	160	CONFIG_SYS_PCIE3_MEM_PHYS2,
6d0f6bcf JCPV	161	CONFIG_SYS_PCIE3_MEM_SIZE2,
837f1ba0	162	PCI_REGION_MEM);
837f1ba0	163	#endif
2dba0dea	164	hose->region_count = r - hose->regions;
837f1ba0	165	hose->first_busno=first_free_busno;
837f1ba0	166
fb3143b3	167	fsl_pci_init(hose, (u32)&pci->cfg_addr, (u32)&pci->cfg_data);
837f1ba0 ES	168
	169	first_free_busno=hose->last_busno+1;
	170	printf (" PCIE3 on bus %02x - %02x\n",
	171	hose->first_busno,hose->last_busno);
	172
56a92705 KG	173	/*
	174	* Activate ULI1575 legacy chip by performing a fake
	175	* memory access. Needed to make ULI RTC work.
	176	*/
10795f42	177	in_be32((u32 *)CONFIG_SYS_PCIE3_MEM_BUS);
837f1ba0 ES	178	} else {
	179	printf (" PCIE3: disabled\n");
	180	}
	181
	182	}
	183	#else
	184	gur->devdisr \|= MPC85xx_DEVDISR_PCIE3; /* disable */
	185	#endif
	186
	187	#ifdef CONFIG_PCIE1
	188	{
6d0f6bcf	189	volatile ccsr_fsl_pci_t pci = (ccsr_fsl_pci_t ) CONFIG_SYS_PCIE1_ADDR;
837f1ba0	190	struct pci_controller *hose = &pcie1_hose;
865f24dc KG	191	int pcie_ep = is_fsl_pci_agent(LAW_TRGT_IF_PCIE_1, host_agent);
865f24dc KG	192	int pcie_configured = is_fsl_pci_cfg(LAW_TRGT_IF_PCIE_1, io_sel);
2dba0dea	193	struct pci_region *r = hose->regions;
837f1ba0 ES	194
	195	if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){
	196	printf ("\n PCIE1 connected to Slot2 as %s (base address %x)",
	197	pcie_ep ? "End Point" : "Root Complex",
	198	(uint)pci);
	199	if (pci->pme_msg_det) {
	200	pci->pme_msg_det = 0xffffffff;
	201	debug (" with errors. Clearing. Now 0x%08x",pci->pme_msg_det);
	202	}
	203	printf ("\n");
	204
837f1ba0	205	/* outbound memory */
2dba0dea	206	pci_set_region(r++,
10795f42	207	CONFIG_SYS_PCIE1_MEM_BUS,
6d0f6bcf JCPV	208	CONFIG_SYS_PCIE1_MEM_PHYS,
6d0f6bcf JCPV	209	CONFIG_SYS_PCIE1_MEM_SIZE,
837f1ba0 ES	210	PCI_REGION_MEM);
	211
	212	/* outbound io */
2dba0dea	213	pci_set_region(r++,
5f91ef6a	214	CONFIG_SYS_PCIE1_IO_BUS,
6d0f6bcf JCPV	215	CONFIG_SYS_PCIE1_IO_PHYS,
6d0f6bcf JCPV	216	CONFIG_SYS_PCIE1_IO_SIZE,
837f1ba0 ES	217	PCI_REGION_IO);
837f1ba0 ES	218
10795f42	219	#ifdef CONFIG_SYS_PCIE1_MEM_BUS2
837f1ba0	220	/* outbound memory */
2dba0dea	221	pci_set_region(r++,
10795f42	222	CONFIG_SYS_PCIE1_MEM_BUS2,
6d0f6bcf JCPV	223	CONFIG_SYS_PCIE1_MEM_PHYS2,
6d0f6bcf JCPV	224	CONFIG_SYS_PCIE1_MEM_SIZE2,
837f1ba0	225	PCI_REGION_MEM);
837f1ba0	226	#endif
2dba0dea	227	hose->region_count = r - hose->regions;
837f1ba0 ES	228	hose->first_busno=first_free_busno;
837f1ba0 ES	229
fb3143b3	230	fsl_pci_init(hose, (u32)&pci->cfg_addr, (u32)&pci->cfg_data);
837f1ba0 ES	231
	232	first_free_busno=hose->last_busno+1;
	233	printf(" PCIE1 on bus %02x - %02x\n",
	234	hose->first_busno,hose->last_busno);
	235
	236	} else {
	237	printf (" PCIE1: disabled\n");
	238	}
	239
	240	}
	241	#else
	242	gur->devdisr \|= MPC85xx_DEVDISR_PCIE; /* disable */
	243	#endif
	244
	245	#ifdef CONFIG_PCIE2
	246	{
6d0f6bcf	247	volatile ccsr_fsl_pci_t pci = (ccsr_fsl_pci_t ) CONFIG_SYS_PCIE2_ADDR;
837f1ba0	248	struct pci_controller *hose = &pcie2_hose;
865f24dc KG	249	int pcie_ep = is_fsl_pci_agent(LAW_TRGT_IF_PCIE_2, host_agent);
865f24dc KG	250	int pcie_configured = is_fsl_pci_cfg(LAW_TRGT_IF_PCIE_2, io_sel);
2dba0dea	251	struct pci_region *r = hose->regions;
837f1ba0 ES	252
	253	if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){
	254	printf ("\n PCIE2 connected to Slot 1 as %s (base address %x)",
	255	pcie_ep ? "End Point" : "Root Complex",
	256	(uint)pci);
	257	if (pci->pme_msg_det) {
	258	pci->pme_msg_det = 0xffffffff;
	259	debug (" with errors. Clearing. Now 0x%08x",pci->pme_msg_det);
	260	}
	261	printf ("\n");
	262
837f1ba0	263	/* outbound memory */
2dba0dea	264	pci_set_region(r++,
10795f42	265	CONFIG_SYS_PCIE2_MEM_BUS,
6d0f6bcf JCPV	266	CONFIG_SYS_PCIE2_MEM_PHYS,
6d0f6bcf JCPV	267	CONFIG_SYS_PCIE2_MEM_SIZE,
837f1ba0 ES	268	PCI_REGION_MEM);
	269
	270	/* outbound io */
2dba0dea	271	pci_set_region(r++,
5f91ef6a	272	CONFIG_SYS_PCIE2_IO_BUS,
6d0f6bcf JCPV	273	CONFIG_SYS_PCIE2_IO_PHYS,
6d0f6bcf JCPV	274	CONFIG_SYS_PCIE2_IO_SIZE,
837f1ba0 ES	275	PCI_REGION_IO);
837f1ba0 ES	276
10795f42	277	#ifdef CONFIG_SYS_PCIE2_MEM_BUS2
837f1ba0	278	/* outbound memory */
2dba0dea	279	pci_set_region(r++,
10795f42	280	CONFIG_SYS_PCIE2_MEM_BUS2,
6d0f6bcf JCPV	281	CONFIG_SYS_PCIE2_MEM_PHYS2,
6d0f6bcf JCPV	282	CONFIG_SYS_PCIE2_MEM_SIZE2,
837f1ba0	283	PCI_REGION_MEM);
837f1ba0	284	#endif
2dba0dea	285	hose->region_count = r - hose->regions;
837f1ba0	286	hose->first_busno=first_free_busno;
837f1ba0	287
fb3143b3	288	fsl_pci_init(hose, (u32)&pci->cfg_addr, (u32)&pci->cfg_data);
837f1ba0 ES	289	first_free_busno=hose->last_busno+1;
	290	printf (" PCIE2 on bus %02x - %02x\n",
	291	hose->first_busno,hose->last_busno);
	292
	293	} else {
	294	printf (" PCIE2: disabled\n");
	295	}
	296
	297	}
	298	#else
	299	gur->devdisr \|= MPC85xx_DEVDISR_PCIE2; /* disable */
	300	#endif
	301
	302
	303	#ifdef CONFIG_PCI1
	304	{
6d0f6bcf	305	volatile ccsr_fsl_pci_t pci = (ccsr_fsl_pci_t ) CONFIG_SYS_PCI1_ADDR;
837f1ba0	306	struct pci_controller *hose = &pci1_hose;
2dba0dea	307	struct pci_region *r = hose->regions;
837f1ba0	308
865f24dc	309	uint pci_agent = is_fsl_pci_agent(LAW_TRGT_IF_PCI, host_agent);
837f1ba0 ES	310	uint pci_speed = 66666000; /get_clock_freq (); PCI PSPEED in [4:5] /
	311	uint pci_32 = 1;
	312	uint pci_arb = gur->pordevsr & MPC85xx_PORDEVSR_PCI1_ARB; /* PORDEVSR[14] */
	313	uint pci_clk_sel = gur->porpllsr & MPC85xx_PORDEVSR_PCI1_SPD; /* PORPLLSR[16] */
	314
	315
	316	if (!(devdisr & MPC85xx_DEVDISR_PCI1)) {
	317	printf ("\n PCI: %d bit, %s MHz, %s, %s, %s (base address %x)\n",
	318	(pci_32) ? 32 : 64,
	319	(pci_speed == 33333000) ? "33" :
	320	(pci_speed == 66666000) ? "66" : "unknown",
	321	pci_clk_sel ? "sync" : "async",
	322	pci_agent ? "agent" : "host",
	323	pci_arb ? "arbiter" : "external-arbiter",
	324	(uint)pci
	325	);
	326
837f1ba0	327	/* outbound memory */
2dba0dea	328	pci_set_region(r++,
10795f42	329	CONFIG_SYS_PCI1_MEM_BUS,
6d0f6bcf JCPV	330	CONFIG_SYS_PCI1_MEM_PHYS,
6d0f6bcf JCPV	331	CONFIG_SYS_PCI1_MEM_SIZE,
837f1ba0 ES	332	PCI_REGION_MEM);
	333
	334	/* outbound io */
2dba0dea	335	pci_set_region(r++,
5f91ef6a	336	CONFIG_SYS_PCI1_IO_BUS,
6d0f6bcf JCPV	337	CONFIG_SYS_PCI1_IO_PHYS,
6d0f6bcf JCPV	338	CONFIG_SYS_PCI1_IO_SIZE,
837f1ba0	339	PCI_REGION_IO);
2dba0dea	340
10795f42	341	#ifdef CONFIG_SYS_PCIE3_MEM_BUS2
837f1ba0	342	/* outbound memory */
2dba0dea	343	pci_set_region(r++,
10795f42	344	CONFIG_SYS_PCIE3_MEM_BUS2,
6d0f6bcf JCPV	345	CONFIG_SYS_PCIE3_MEM_PHYS2,
6d0f6bcf JCPV	346	CONFIG_SYS_PCIE3_MEM_SIZE2,
837f1ba0	347	PCI_REGION_MEM);
837f1ba0	348	#endif
2dba0dea	349	hose->region_count = r - hose->regions;
837f1ba0	350	hose->first_busno=first_free_busno;
837f1ba0	351
fb3143b3	352	fsl_pci_init(hose, (u32)&pci->cfg_addr, (u32)&pci->cfg_data);
837f1ba0 ES	353	first_free_busno=hose->last_busno+1;
	354	printf ("PCI on bus %02x - %02x\n",
	355	hose->first_busno,hose->last_busno);
	356	} else {
	357	printf (" PCI: disabled\n");
	358	}
	359	}
	360	#else
	361	gur->devdisr \|= MPC85xx_DEVDISR_PCI1; /* disable */
	362	#endif
	363	}
	364
	365
25d83d7f JL	366	int last_stage_init(void)
	367	{
	368	return 0;
	369	}
	370
	371
	372	unsigned long
	373	get_board_sys_clk(ulong dummy)
	374	{
	375	u8 i, go_bit, rd_clks;
	376	ulong val = 0;
048e7efe	377	u8 pixis_base = (u8 )PIXIS_BASE;
25d83d7f	378
048e7efe	379	go_bit = in_8(pixis_base + PIXIS_VCTL);
25d83d7f JL	380	go_bit &= 0x01;
25d83d7f JL	381
048e7efe	382	rd_clks = in_8(pixis_base + PIXIS_VCFGEN0);
25d83d7f JL	383	rd_clks &= 0x1C;
	384
	385	/*
	386	* Only if both go bit and the SCLK bit in VCFGEN0 are set
	387	* should we be using the AUX register. Remember, we also set the
	388	* GO bit to boot from the alternate bank on the on-board flash
	389	*/
	390
	391	if (go_bit) {
	392	if (rd_clks == 0x1c)
048e7efe	393	i = in_8(pixis_base + PIXIS_AUX);
25d83d7f	394	else
048e7efe	395	i = in_8(pixis_base + PIXIS_SPD);
25d83d7f	396	} else {
048e7efe	397	i = in_8(pixis_base + PIXIS_SPD);
25d83d7f JL	398	}
	399
	400	i &= 0x07;
	401
	402	switch (i) {
	403	case 0:
	404	val = 33333333;
	405	break;
	406	case 1:
	407	val = 40000000;
	408	break;
	409	case 2:
	410	val = 50000000;
	411	break;
	412	case 3:
	413	val = 66666666;
	414	break;
	415	case 4:
	416	val = 83000000;
	417	break;
	418	case 5:
	419	val = 100000000;
	420	break;
	421	case 6:
	422	val = 133333333;
	423	break;
	424	case 7:
	425	val = 166666666;
	426	break;
	427	}
	428
	429	return val;
	430	}
	431
216f2a71 AF	432	int board_eth_init(bd_t *bis)
216f2a71 AF	433	{
0b252f50	434	#ifdef CONFIG_TSEC_ENET
216f2a71	435	struct tsec_info_struct tsec_info[2];
6d0f6bcf	436	volatile ccsr_gur_t gur = (void )(CONFIG_SYS_MPC85xx_GUTS_ADDR);
216f2a71 AF	437	uint io_sel = (gur->pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> 19;
	438	int num = 0;
	439
	440	#ifdef CONFIG_TSEC1
	441	SET_STD_TSEC_INFO(tsec_info[num], 1);
	442	if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII1_DIS))
	443	tsec_info[num].flags \|= TSEC_SGMII;
	444	num++;
	445	#endif
	446	#ifdef CONFIG_TSEC3
	447	SET_STD_TSEC_INFO(tsec_info[num], 3);
	448	if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII3_DIS))
	449	tsec_info[num].flags \|= TSEC_SGMII;
	450	num++;
	451	#endif
	452
	453	if (!num) {
	454	printf("No TSECs initialized\n");
	455
	456	return 0;
	457	}
	458
	459	if (io_sel & 1)
	460	fsl_sgmii_riser_init(tsec_info, num);
	461
	462
	463	tsec_eth_init(bis, tsec_info, num);
216f2a71	464	#endif
0b252f50 BW	465	return pci_eth_init(bis);
0b252f50 BW	466	}
216f2a71	467
addce57e	468	#if defined(CONFIG_OF_BOARD_SETUP)
2dba0dea	469	void ft_board_setup(void blob, bd_t bd)
25d83d7f	470	{
2f15278c	471	ft_cpu_setup(blob, bd);
25d83d7f	472
2dba0dea	473
f75e89e9	474	#ifdef CONFIG_PCI1
2dba0dea	475	ft_fsl_pci_setup(blob, "pci0", &pci1_hose);
837f1ba0 ES	476	#endif
837f1ba0 ES	477	#ifdef CONFIG_PCIE2
2dba0dea	478	ft_fsl_pci_setup(blob, "pci1", &pcie1_hose);
addce57e KG	479	#endif
addce57e KG	480	#ifdef CONFIG_PCIE1
2dba0dea	481	ft_fsl_pci_setup(blob, "pci2", &pcie3_hose);
837f1ba0 ES	482	#endif
837f1ba0 ES	483	#ifdef CONFIG_PCIE3
2dba0dea	484	ft_fsl_pci_setup(blob, "pci3", &pcie2_hose);
837f1ba0	485	#endif
feede8b0 AF	486	#ifdef CONFIG_FSL_SGMII_RISER
	487	fsl_sgmii_riser_fdt_fixup(blob);
	488	#endif
25d83d7f JL	489	}
25d83d7f JL	490	#endif