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3dd2db53 | 1 | /* |
d5c784ed | 2 | * Copyright 2007,2009-2011 Freescale Semiconductor, Inc. |
3dd2db53 | 3 | * |
3765b3e7 | 4 | * SPDX-License-Identifier: GPL-2.0+ |
3dd2db53 | 5 | */ |
c9974ab0 | 6 | |
3dd2db53 JL |
7 | #include <common.h> |
8 | #include <command.h> | |
9 | #include <pci.h> | |
10 | #include <asm/processor.h> | |
11 | #include <asm/immap_86xx.h> | |
c8514622 | 12 | #include <asm/fsl_pci.h> |
39aa1a73 | 13 | #include <asm/fsl_ddr_sdram.h> |
5d27e02c | 14 | #include <asm/fsl_serdes.h> |
c9974ab0 | 15 | #include <i2c.h> |
3dd2db53 | 16 | #include <asm/io.h> |
1df170f8 JL |
17 | #include <libfdt.h> |
18 | #include <fdt_support.h> | |
a30a549a | 19 | #include <spd_sdram.h> |
89973f8a | 20 | #include <netdev.h> |
3dd2db53 | 21 | |
3dd2db53 | 22 | void sdram_init(void); |
4c77de3f | 23 | phys_size_t fixed_sdram(void); |
e69e520f | 24 | int mpc8610hpcd_diu_init(void); |
c9974ab0 | 25 | |
3dd2db53 JL |
26 | |
27 | /* called before any console output */ | |
28 | int board_early_init_f(void) | |
29 | { | |
6d0f6bcf | 30 | volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR; |
3dd2db53 JL |
31 | volatile ccsr_gur_t *gur = &immap->im_gur; |
32 | ||
a877880c YS |
33 | gur->gpiocr |= 0x88aa5500; /* DIU16, IR1, UART0, UART2 */ |
34 | ||
35 | return 0; | |
36 | } | |
37 | ||
38 | int misc_init_r(void) | |
39 | { | |
40 | u8 tmp_val, version; | |
048e7efe | 41 | u8 *pixis_base = (u8 *)PIXIS_BASE; |
a877880c YS |
42 | |
43 | /*Do not use 8259PIC*/ | |
048e7efe KG |
44 | tmp_val = in_8(pixis_base + PIXIS_BRDCFG0); |
45 | out_8(pixis_base + PIXIS_BRDCFG0, tmp_val | 0x80); | |
a877880c YS |
46 | |
47 | /*For FPGA V7 or higher, set the IRQMAPSEL to 0 to use MAP0 interrupt*/ | |
048e7efe | 48 | version = in_8(pixis_base + PIXIS_PVER); |
a877880c | 49 | if(version >= 0x07) { |
048e7efe KG |
50 | tmp_val = in_8(pixis_base + PIXIS_BRDCFG0); |
51 | out_8(pixis_base + PIXIS_BRDCFG0, tmp_val & 0xbf); | |
a877880c YS |
52 | } |
53 | ||
54 | /* Using this for DIU init before the driver in linux takes over | |
55 | * Enable the TFP410 Encoder (I2C address 0x38) | |
56 | */ | |
57 | ||
58 | tmp_val = 0xBF; | |
59 | i2c_write(0x38, 0x08, 1, &tmp_val, sizeof(tmp_val)); | |
60 | /* Verify if enabled */ | |
61 | tmp_val = 0; | |
62 | i2c_read(0x38, 0x08, 1, &tmp_val, sizeof(tmp_val)); | |
7315ab22 | 63 | debug("DVI Encoder Read: 0x%02x\n", tmp_val); |
a877880c YS |
64 | |
65 | tmp_val = 0x10; | |
66 | i2c_write(0x38, 0x0A, 1, &tmp_val, sizeof(tmp_val)); | |
67 | /* Verify if enabled */ | |
68 | tmp_val = 0; | |
69 | i2c_read(0x38, 0x0A, 1, &tmp_val, sizeof(tmp_val)); | |
7315ab22 | 70 | debug("DVI Encoder Read: 0x%02x\n", tmp_val); |
a877880c | 71 | |
3dd2db53 JL |
72 | return 0; |
73 | } | |
74 | ||
75 | int checkboard(void) | |
76 | { | |
6d0f6bcf | 77 | volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR; |
3dd2db53 | 78 | volatile ccsr_local_mcm_t *mcm = &immap->im_local_mcm; |
048e7efe | 79 | u8 *pixis_base = (u8 *)PIXIS_BASE; |
3dd2db53 | 80 | |
26fd33b9 TT |
81 | printf ("Board: MPC8610HPCD, Sys ID: 0x%02x, " |
82 | "Sys Ver: 0x%02x, FPGA Ver: 0x%02x, ", | |
048e7efe KG |
83 | in_8(pixis_base + PIXIS_ID), in_8(pixis_base + PIXIS_VER), |
84 | in_8(pixis_base + PIXIS_PVER)); | |
3dd2db53 | 85 | |
26fd33b9 TT |
86 | /* |
87 | * The MPC8610 HPCD workbook says that LBMAP=11 is the "normal" boot | |
88 | * bank and LBMAP=00 is the alternate bank. However, the pixis | |
89 | * altbank code can only set bits, not clear them, so we treat 00 as | |
90 | * the normal bank and 11 as the alternate. | |
91 | */ | |
92 | switch (in_8(pixis_base + PIXIS_VBOOT) & 0xC0) { | |
93 | case 0: | |
94 | puts("vBank: Standard\n"); | |
95 | break; | |
96 | case 0x40: | |
97 | puts("Promjet\n"); | |
98 | break; | |
99 | case 0x80: | |
100 | puts("NAND\n"); | |
101 | break; | |
102 | case 0xC0: | |
103 | puts("vBank: Alternate\n"); | |
104 | break; | |
105 | } | |
106 | ||
3dd2db53 JL |
107 | mcm->abcr |= 0x00010000; /* 0 */ |
108 | mcm->hpmr3 = 0x80000008; /* 4c */ | |
109 | mcm->hpmr0 = 0; | |
110 | mcm->hpmr1 = 0; | |
111 | mcm->hpmr2 = 0; | |
112 | mcm->hpmr4 = 0; | |
113 | mcm->hpmr5 = 0; | |
114 | ||
115 | return 0; | |
116 | } | |
117 | ||
118 | ||
9973e3c6 | 119 | phys_size_t |
3dd2db53 JL |
120 | initdram(int board_type) |
121 | { | |
4c77de3f | 122 | phys_size_t dram_size = 0; |
3dd2db53 JL |
123 | |
124 | #if defined(CONFIG_SPD_EEPROM) | |
39aa1a73 | 125 | dram_size = fsl_ddr_sdram(); |
3dd2db53 JL |
126 | #else |
127 | dram_size = fixed_sdram(); | |
128 | #endif | |
129 | ||
9ff32d8c TT |
130 | setup_ddr_bat(dram_size); |
131 | ||
21cd5815 | 132 | debug(" DDR: "); |
3dd2db53 JL |
133 | return dram_size; |
134 | } | |
135 | ||
136 | ||
3dd2db53 JL |
137 | #if !defined(CONFIG_SPD_EEPROM) |
138 | /* | |
139 | * Fixed sdram init -- doesn't use serial presence detect. | |
140 | */ | |
141 | ||
4c77de3f | 142 | phys_size_t fixed_sdram(void) |
3dd2db53 | 143 | { |
6d0f6bcf JCPV |
144 | #if !defined(CONFIG_SYS_RAMBOOT) |
145 | volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR; | |
3dd2db53 JL |
146 | volatile ccsr_ddr_t *ddr = &immap->im_ddr1; |
147 | uint d_init; | |
148 | ||
149 | ddr->cs0_bnds = 0x0000001f; | |
150 | ddr->cs0_config = 0x80010202; | |
151 | ||
45239cf4 | 152 | ddr->timing_cfg_3 = 0x00000000; |
3dd2db53 JL |
153 | ddr->timing_cfg_0 = 0x00260802; |
154 | ddr->timing_cfg_1 = 0x3935d322; | |
155 | ddr->timing_cfg_2 = 0x14904cc8; | |
e7ee23ec | 156 | ddr->sdram_mode = 0x00480432; |
3dd2db53 JL |
157 | ddr->sdram_mode_2 = 0x00000000; |
158 | ddr->sdram_interval = 0x06180fff; /* 0x06180100; */ | |
159 | ddr->sdram_data_init = 0xDEADBEEF; | |
160 | ddr->sdram_clk_cntl = 0x03800000; | |
161 | ddr->sdram_cfg_2 = 0x04400010; | |
162 | ||
163 | #if defined(CONFIG_DDR_ECC) | |
164 | ddr->err_int_en = 0x0000000d; | |
165 | ddr->err_disable = 0x00000000; | |
166 | ddr->err_sbe = 0x00010000; | |
167 | #endif | |
168 | asm("sync;isync"); | |
169 | ||
170 | udelay(500); | |
171 | ||
e7ee23ec | 172 | ddr->sdram_cfg = 0xc3000000; /* 0xe3008000;*/ |
3dd2db53 JL |
173 | |
174 | ||
175 | #if defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) | |
176 | d_init = 1; | |
177 | debug("DDR - 1st controller: memory initializing\n"); | |
178 | /* | |
179 | * Poll until memory is initialized. | |
180 | * 512 Meg at 400 might hit this 200 times or so. | |
181 | */ | |
182 | while ((ddr->sdram_cfg_2 & (d_init << 4)) != 0) | |
183 | udelay(1000); | |
184 | ||
185 | debug("DDR: memory initialized\n\n"); | |
186 | asm("sync; isync"); | |
187 | udelay(500); | |
188 | #endif | |
189 | ||
190 | return 512 * 1024 * 1024; | |
191 | #endif | |
6d0f6bcf | 192 | return CONFIG_SYS_SDRAM_SIZE * 1024 * 1024; |
3dd2db53 JL |
193 | } |
194 | ||
195 | #endif | |
196 | ||
197 | #if defined(CONFIG_PCI) | |
198 | /* | |
199 | * Initialize PCI Devices, report devices found. | |
200 | */ | |
201 | ||
202 | #ifndef CONFIG_PCI_PNP | |
203 | static struct pci_config_table pci_fsl86xxads_config_table[] = { | |
204 | {PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, | |
205 | PCI_IDSEL_NUMBER, PCI_ANY_ID, | |
206 | pci_cfgfunc_config_device, {PCI_ENET0_IOADDR, | |
207 | PCI_ENET0_MEMADDR, | |
208 | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER} }, | |
209 | {} | |
210 | }; | |
211 | #endif | |
212 | ||
213 | ||
d5c784ed | 214 | static struct pci_controller pci1_hose; |
3dd2db53 JL |
215 | #endif /* CONFIG_PCI */ |
216 | ||
3dd2db53 JL |
217 | void pci_init_board(void) |
218 | { | |
6d0f6bcf | 219 | volatile immap_t *immap = (immap_t *) CONFIG_SYS_CCSRBAR; |
3dd2db53 | 220 | volatile ccsr_gur_t *gur = &immap->im_gur; |
b8526212 | 221 | struct fsl_pci_info pci_info; |
e38cc2c7 | 222 | u32 devdisr; |
b8526212 KG |
223 | int first_free_busno; |
224 | int pci_agent; | |
5e3d7050 KG |
225 | |
226 | devdisr = in_be32(&gur->devdisr); | |
3dd2db53 | 227 | |
b8526212 | 228 | first_free_busno = fsl_pcie_init_board(0); |
3dd2db53 JL |
229 | |
230 | #ifdef CONFIG_PCI1 | |
5e3d7050 | 231 | if (!(devdisr & MPC86xx_DEVDISR_PCI1)) { |
b8526212 KG |
232 | SET_STD_PCI_INFO(pci_info, 1); |
233 | set_next_law(pci_info.mem_phys, | |
234 | law_size_bits(pci_info.mem_size), pci_info.law); | |
235 | set_next_law(pci_info.io_phys, | |
236 | law_size_bits(pci_info.io_size), pci_info.law); | |
237 | ||
238 | pci_agent = fsl_setup_hose(&pci1_hose, pci_info.regs); | |
8ca78f2c | 239 | printf("PCI: connected to PCI slots as %s" \ |
5e3d7050 | 240 | " (base address %lx)\n", |
3dd2db53 | 241 | pci_agent ? "Agent" : "Host", |
b8526212 | 242 | pci_info.regs); |
d5c784ed ZC |
243 | #ifndef CONFIG_PCI_PNP |
244 | pci1_hose.config_table = pci_mpc86xxcts_config_table; | |
245 | #endif | |
b8526212 | 246 | first_free_busno = fsl_pci_init_port(&pci_info, |
5e3d7050 KG |
247 | &pci1_hose, first_free_busno); |
248 | } else { | |
8ca78f2c | 249 | printf("PCI: disabled\n"); |
5e3d7050 | 250 | } |
3dd2db53 | 251 | |
5e3d7050 KG |
252 | puts("\n"); |
253 | #else | |
254 | setbits_be32(&gur->devdisr, MPC86xx_DEVDISR_PCI1); /* disable */ | |
255 | #endif | |
b8526212 KG |
256 | |
257 | fsl_pcie_init_board(first_free_busno); | |
3dd2db53 JL |
258 | } |
259 | ||
1df170f8 | 260 | #if defined(CONFIG_OF_BOARD_SETUP) |
3dd2db53 JL |
261 | void |
262 | ft_board_setup(void *blob, bd_t *bd) | |
263 | { | |
8439f05c | 264 | ft_cpu_setup(blob, bd); |
1df170f8 | 265 | |
6525d51f | 266 | FT_FSL_PCI_SETUP; |
3dd2db53 JL |
267 | } |
268 | #endif | |
269 | ||
270 | /* | |
271 | * get_board_sys_clk | |
272 | * Reads the FPGA on board for CONFIG_SYS_CLK_FREQ | |
273 | */ | |
274 | ||
275 | unsigned long | |
276 | get_board_sys_clk(ulong dummy) | |
277 | { | |
a877880c | 278 | u8 i; |
3dd2db53 | 279 | ulong val = 0; |
048e7efe | 280 | u8 *pixis_base = (u8 *)PIXIS_BASE; |
3dd2db53 | 281 | |
048e7efe | 282 | i = in_8(pixis_base + PIXIS_SPD); |
3dd2db53 JL |
283 | i &= 0x07; |
284 | ||
285 | switch (i) { | |
286 | case 0: | |
287 | val = 33333000; | |
288 | break; | |
289 | case 1: | |
290 | val = 39999600; | |
291 | break; | |
292 | case 2: | |
293 | val = 49999500; | |
294 | break; | |
295 | case 3: | |
296 | val = 66666000; | |
297 | break; | |
298 | case 4: | |
299 | val = 83332500; | |
300 | break; | |
301 | case 5: | |
302 | val = 99999000; | |
303 | break; | |
304 | case 6: | |
305 | val = 133332000; | |
306 | break; | |
307 | case 7: | |
308 | val = 166665000; | |
309 | break; | |
310 | } | |
311 | ||
312 | return val; | |
313 | } | |
65d3d99c | 314 | |
65d3d99c BW |
315 | int board_eth_init(bd_t *bis) |
316 | { | |
89973f8a | 317 | return pci_eth_init(bis); |
65d3d99c | 318 | } |
4ef630df PT |
319 | |
320 | void board_reset(void) | |
321 | { | |
048e7efe KG |
322 | u8 *pixis_base = (u8 *)PIXIS_BASE; |
323 | ||
324 | out_8(pixis_base + PIXIS_RST, 0); | |
4ef630df PT |
325 | |
326 | while (1) | |
327 | ; | |
328 | } |