[people/ms/u-boot.git] / board / gateworks / gw_ventana / gw_ventana_spl.c

/*
 * Copyright (C) 2014 Gateworks Corporation
 * Author: Tim Harvey <tharvey@gateworks.com>
 *
 * SPDX-License-Identifier:     GPL-2.0+
 */

#include <common.h>
#include <asm/io.h>
#include <asm/arch/crm_regs.h>
#include <asm/arch/mx6-ddr.h>
#include <asm/arch/mx6-pins.h>
#include <asm/arch/sys_proto.h>
#include <asm/imx-common/boot_mode.h>
#include <asm/imx-common/iomux-v3.h>
#include <asm/imx-common/mxc_i2c.h>
#include <environment.h>
#include <spl.h>

#include "gsc.h"
#include "common.h"

DECLARE_GLOBAL_DATA_PTR;

#define RTT_NOM_120OHM /* use 120ohm Rtt_nom vs 60ohm (lower power) */
#define GSC_EEPROM_DDR_SIZE	0x2B	/* enum (512,1024,2048) MB */
#define GSC_EEPROM_DDR_WIDTH	0x2D	/* enum (32,64) bit */

/* configure MX6Q/DUAL mmdc DDR io registers */
struct mx6dq_iomux_ddr_regs mx6dq_ddr_ioregs = {
	/* SDCLK[0:1], CAS, RAS, Reset: Differential input, 40ohm */
	.dram_sdclk_0 = 0x00020030,
	.dram_sdclk_1 = 0x00020030,
	.dram_cas = 0x00020030,
	.dram_ras = 0x00020030,
	.dram_reset = 0x00020030,
	/* SDCKE[0:1]: 100k pull-up */
	.dram_sdcke0 = 0x00003000,
	.dram_sdcke1 = 0x00003000,
	/* SDBA2: pull-up disabled */
	.dram_sdba2 = 0x00000000,
	/* SDODT[0:1]: 100k pull-up, 40 ohm */
	.dram_sdodt0 = 0x00003030,
	.dram_sdodt1 = 0x00003030,
	/* SDQS[0:7]: Differential input, 40 ohm */
	.dram_sdqs0 = 0x00000030,
	.dram_sdqs1 = 0x00000030,
	.dram_sdqs2 = 0x00000030,
	.dram_sdqs3 = 0x00000030,
	.dram_sdqs4 = 0x00000030,
	.dram_sdqs5 = 0x00000030,
	.dram_sdqs6 = 0x00000030,
	.dram_sdqs7 = 0x00000030,

	/* DQM[0:7]: Differential input, 40 ohm */
	.dram_dqm0 = 0x00020030,
	.dram_dqm1 = 0x00020030,
	.dram_dqm2 = 0x00020030,
	.dram_dqm3 = 0x00020030,
	.dram_dqm4 = 0x00020030,
	.dram_dqm5 = 0x00020030,
	.dram_dqm6 = 0x00020030,
	.dram_dqm7 = 0x00020030,
};

/* configure MX6Q/DUAL mmdc GRP io registers */
struct mx6dq_iomux_grp_regs mx6dq_grp_ioregs = {
	/* DDR3 */
	.grp_ddr_type = 0x000c0000,
	.grp_ddrmode_ctl = 0x00020000,
	/* disable DDR pullups */
	.grp_ddrpke = 0x00000000,
	/* ADDR[00:16], SDBA[0:1]: 40 ohm */
	.grp_addds = 0x00000030,
	/* CS0/CS1/SDBA2/CKE0/CKE1/SDWE: 40 ohm */
	.grp_ctlds = 0x00000030,
	/* DATA[00:63]: Differential input, 40 ohm */
	.grp_ddrmode = 0x00020000,
	.grp_b0ds = 0x00000030,
	.grp_b1ds = 0x00000030,
	.grp_b2ds = 0x00000030,
	.grp_b3ds = 0x00000030,
	.grp_b4ds = 0x00000030,
	.grp_b5ds = 0x00000030,
	.grp_b6ds = 0x00000030,
	.grp_b7ds = 0x00000030,
};

/* configure MX6SOLO/DUALLITE mmdc DDR io registers */
struct mx6sdl_iomux_ddr_regs mx6sdl_ddr_ioregs = {
	/* SDCLK[0:1], CAS, RAS, Reset: Differential input, 40ohm */
	.dram_sdclk_0 = 0x00020030,
	.dram_sdclk_1 = 0x00020030,
	.dram_cas = 0x00020030,
	.dram_ras = 0x00020030,
	.dram_reset = 0x00020030,
	/* SDCKE[0:1]: 100k pull-up */
	.dram_sdcke0 = 0x00003000,
	.dram_sdcke1 = 0x00003000,
	/* SDBA2: pull-up disabled */
	.dram_sdba2 = 0x00000000,
	/* SDODT[0:1]: 100k pull-up, 40 ohm */
	.dram_sdodt0 = 0x00003030,
	.dram_sdodt1 = 0x00003030,
	/* SDQS[0:7]: Differential input, 40 ohm */
	.dram_sdqs0 = 0x00000030,
	.dram_sdqs1 = 0x00000030,
	.dram_sdqs2 = 0x00000030,
	.dram_sdqs3 = 0x00000030,
	.dram_sdqs4 = 0x00000030,
	.dram_sdqs5 = 0x00000030,
	.dram_sdqs6 = 0x00000030,
	.dram_sdqs7 = 0x00000030,

	/* DQM[0:7]: Differential input, 40 ohm */
	.dram_dqm0 = 0x00020030,
	.dram_dqm1 = 0x00020030,
	.dram_dqm2 = 0x00020030,
	.dram_dqm3 = 0x00020030,
	.dram_dqm4 = 0x00020030,
	.dram_dqm5 = 0x00020030,
	.dram_dqm6 = 0x00020030,
	.dram_dqm7 = 0x00020030,
};

/* configure MX6SOLO/DUALLITE mmdc GRP io registers */
struct mx6sdl_iomux_grp_regs mx6sdl_grp_ioregs = {
	/* DDR3 */
	.grp_ddr_type = 0x000c0000,
	/* SDQS[0:7]: Differential input, 40 ohm */
	.grp_ddrmode_ctl = 0x00020000,
	/* disable DDR pullups */
	.grp_ddrpke = 0x00000000,
	/* ADDR[00:16], SDBA[0:1]: 40 ohm */
	.grp_addds = 0x00000030,
	/* CS0/CS1/SDBA2/CKE0/CKE1/SDWE: 40 ohm */
	.grp_ctlds = 0x00000030,
	/* DATA[00:63]: Differential input, 40 ohm */
	.grp_ddrmode = 0x00020000,
	.grp_b0ds = 0x00000030,
	.grp_b1ds = 0x00000030,
	.grp_b2ds = 0x00000030,
	.grp_b3ds = 0x00000030,
	.grp_b4ds = 0x00000030,
	.grp_b5ds = 0x00000030,
	.grp_b6ds = 0x00000030,
	.grp_b7ds = 0x00000030,
};

/* MT41K64M16JT-125 (1Gb density) */
static struct mx6_ddr3_cfg mt41k64m16jt_125 = {
	.mem_speed = 1600,
	.density = 1,
	.width = 16,
	.banks = 8,
	.rowaddr = 13,
	.coladdr = 10,
	.pagesz = 2,
	.trcd = 1375,
	.trcmin = 4875,
	.trasmin = 3500,
};

/* MT41K128M16JT-125 (2Gb density) */
static struct mx6_ddr3_cfg mt41k128m16jt_125 = {
	.mem_speed = 1600,
	.density = 2,
	.width = 16,
	.banks = 8,
	.rowaddr = 14,
	.coladdr = 10,
	.pagesz = 2,
	.trcd = 1375,
	.trcmin = 4875,
	.trasmin = 3500,
};

/* MT41K256M16HA-125 (4Gb density) */
static struct mx6_ddr3_cfg mt41k256m16ha_125 = {
	.mem_speed = 1600,
	.density = 4,
	.width = 16,
	.banks = 8,
	.rowaddr = 15,
	.coladdr = 10,
	.pagesz = 2,
	.trcd = 1375,
	.trcmin = 4875,
	.trasmin = 3500,
};

/*
 * calibration - these are the various CPU/DDR3 combinations we support
 */
static struct mx6_mmdc_calibration mx6sdl_64x16_mmdc_calib = {
	/* write leveling calibration determine */
	.p0_mpwldectrl0 = 0x004C004E,
	.p0_mpwldectrl1 = 0x00440044,
	/* Read DQS Gating calibration */
	.p0_mpdgctrl0 = 0x42440247,
	.p0_mpdgctrl1 = 0x02310232,
	/* Read Calibration: DQS delay relative to DQ read access */
	.p0_mprddlctl = 0x45424746,
	/* Write Calibration: DQ/DM delay relative to DQS write access */
	.p0_mpwrdlctl = 0x33382C31,
};

static struct mx6_mmdc_calibration mx6dq_256x16_mmdc_calib = {
	/* write leveling calibration determine */
	.p0_mpwldectrl0 = 0x001B0016,
	.p0_mpwldectrl1 = 0x000C000E,
	/* Read DQS Gating calibration */
	.p0_mpdgctrl0 = 0x4324033A,
	.p0_mpdgctrl1 = 0x00000000,
	/* Read Calibration: DQS delay relative to DQ read access */
	.p0_mprddlctl = 0x40403438,
	/* Write Calibration: DQ/DM delay relative to DQS write access */
	.p0_mpwrdlctl = 0x40403D36,
};

static struct mx6_mmdc_calibration mx6sdl_256x16_mmdc_calib = {
	/* write leveling calibration determine */
	.p0_mpwldectrl0 = 0x00420043,
	.p0_mpwldectrl1 = 0x0016001A,
	/* Read DQS Gating calibration */
	.p0_mpdgctrl0 = 0x4238023B,
	.p0_mpdgctrl1 = 0x00000000,
	/* Read Calibration: DQS delay relative to DQ read access */
	.p0_mprddlctl = 0x40404849,
	/* Write Calibration: DQ/DM delay relative to DQS write access */
	.p0_mpwrdlctl = 0x40402E2F,
};

static struct mx6_mmdc_calibration mx6dq_128x32_mmdc_calib = {
	/* write leveling calibration determine */
	.p0_mpwldectrl0 = 0x00190017,
	.p0_mpwldectrl1 = 0x00140026,
	/* Read DQS Gating calibration */
	.p0_mpdgctrl0 = 0x43380347,
	.p0_mpdgctrl1 = 0x433C034D,
	/* Read Calibration: DQS delay relative to DQ read access */
	.p0_mprddlctl = 0x3C313539,
	/* Write Calibration: DQ/DM delay relative to DQS write access */
	.p0_mpwrdlctl = 0x36393C39,
};

static struct mx6_mmdc_calibration mx6sdl_128x32_mmdc_calib = {
	/* write leveling calibration determine */
	.p0_mpwldectrl0 = 0x003C003C,
	.p0_mpwldectrl1 = 0x001F002A,
	/* Read DQS Gating calibration */
	.p0_mpdgctrl0 = 0x42410244,
	.p0_mpdgctrl1 = 0x4234023A,
	/* Read Calibration: DQS delay relative to DQ read access */
	.p0_mprddlctl = 0x484A4C4B,
	/* Write Calibration: DQ/DM delay relative to DQS write access */
	.p0_mpwrdlctl = 0x33342B32,
};

static struct mx6_mmdc_calibration mx6dq_128x64_mmdc_calib = {
	/* write leveling calibration determine */
	.p0_mpwldectrl0 = 0x00190017,
	.p0_mpwldectrl1 = 0x00140026,
	.p1_mpwldectrl0 = 0x0021001C,
	.p1_mpwldectrl1 = 0x0011001D,
	/* Read DQS Gating calibration */
	.p0_mpdgctrl0 = 0x43380347,
	.p0_mpdgctrl1 = 0x433C034D,
	.p1_mpdgctrl0 = 0x032C0324,
	.p1_mpdgctrl1 = 0x03310232,
	/* Read Calibration: DQS delay relative to DQ read access */
	.p0_mprddlctl = 0x3C313539,
	.p1_mprddlctl = 0x37343141,
	/* Write Calibration: DQ/DM delay relative to DQS write access */
	.p0_mpwrdlctl = 0x36393C39,
	.p1_mpwrdlctl = 0x42344438,
};

static struct mx6_mmdc_calibration mx6sdl_128x64_mmdc_calib = {
	/* write leveling calibration determine */
	.p0_mpwldectrl0 = 0x003C003C,
	.p0_mpwldectrl1 = 0x001F002A,
	.p1_mpwldectrl0 = 0x00330038,
	.p1_mpwldectrl1 = 0x0022003F,
	/* Read DQS Gating calibration */
	.p0_mpdgctrl0 = 0x42410244,
	.p0_mpdgctrl1 = 0x4234023A,
	.p1_mpdgctrl0 = 0x022D022D,
	.p1_mpdgctrl1 = 0x021C0228,
	/* Read Calibration: DQS delay relative to DQ read access */
	.p0_mprddlctl = 0x484A4C4B,
	.p1_mprddlctl = 0x4B4D4E4B,
	/* Write Calibration: DQ/DM delay relative to DQS write access */
	.p0_mpwrdlctl = 0x33342B32,
	.p1_mpwrdlctl = 0x3933332B,
};

static struct mx6_mmdc_calibration mx6dq_256x32_mmdc_calib = {
	/* write leveling calibration determine */
	.p0_mpwldectrl0 = 0x001E001A,
	.p0_mpwldectrl1 = 0x0026001F,
	/* Read DQS Gating calibration */
	.p0_mpdgctrl0 = 0x43370349,
	.p0_mpdgctrl1 = 0x032D0327,
	/* Read Calibration: DQS delay relative to DQ read access */
	.p0_mprddlctl = 0x3D303639,
	/* Write Calibration: DQ/DM delay relative to DQS write access */
	.p0_mpwrdlctl = 0x32363934,
};

static struct mx6_mmdc_calibration mx6sdl_256x32_mmdc_calib = {
	/* write leveling calibration determine */
	.p0_mpwldectrl0 = 0X00480047,
	.p0_mpwldectrl1 = 0X003D003F,
	/* Read DQS Gating calibration */
	.p0_mpdgctrl0 = 0X423E0241,
	.p0_mpdgctrl1 = 0X022B022C,
	/* Read Calibration: DQS delay relative to DQ read access */
	.p0_mprddlctl = 0X49454A4A,
	/* Write Calibration: DQ/DM delay relative to DQS write access */
	.p0_mpwrdlctl = 0X2E372C32,
};

static struct mx6_mmdc_calibration mx6dq_256x64_mmdc_calib = {
	/* write leveling calibration determine */
	.p0_mpwldectrl0 = 0X00220021,
	.p0_mpwldectrl1 = 0X00200030,
	.p1_mpwldectrl0 = 0X002D0027,
	.p1_mpwldectrl1 = 0X00150026,
	/* Read DQS Gating calibration */
	.p0_mpdgctrl0 = 0x43330342,
	.p0_mpdgctrl1 = 0x0339034A,
	.p1_mpdgctrl0 = 0x032F0325,
	.p1_mpdgctrl1 = 0x032F022E,
	/* Read Calibration: DQS delay relative to DQ read access */
	.p0_mprddlctl = 0X3A2E3437,
	.p1_mprddlctl = 0X35312F3F,
	/* Write Calibration: DQ/DM delay relative to DQS write access */
	.p0_mpwrdlctl = 0X33363B37,
	.p1_mpwrdlctl = 0X40304239,
};

static void spl_dram_init(int width, int size_mb, int board_model)
{
	struct mx6_ddr3_cfg *mem = NULL;
	struct mx6_mmdc_calibration *calib = NULL;
	struct mx6_ddr_sysinfo sysinfo = {
		/* width of data bus:0=16,1=32,2=64 */
		.dsize = width/32,
		/* config for full 4GB range so that get_mem_size() works */
		.cs_density = 32, /* 32Gb per CS */
		/* single chip select */
		.ncs = 1,
		.cs1_mirror = 0,
		.rtt_wr = 1 /*DDR3_RTT_60_OHM*/,	/* RTT_Wr = RZQ/4 */
#ifdef RTT_NOM_120OHM
		.rtt_nom = 2 /*DDR3_RTT_120_OHM*/,	/* RTT_Nom = RZQ/2 */
#else
		.rtt_nom = 1 /*DDR3_RTT_60_OHM*/,	/* RTT_Nom = RZQ/4 */
#endif
		.walat = 1,	/* Write additional latency */
		.ralat = 5,	/* Read additional latency */
		.mif3_mode = 3,	/* Command prediction working mode */
		.bi_on = 1,	/* Bank interleaving enabled */
		.sde_to_rst = 0x10,	/* 14 cycles, 200us (JEDEC default) */
		.rst_to_cke = 0x23,	/* 33 cycles, 500us (JEDEC default) */
		.pd_fast_exit = 1, /* enable precharge power-down fast exit */
	};

	/*
	 * MMDC Calibration requires the following data:
	 *   mx6_mmdc_calibration - board-specific calibration (routing delays)
	 *      these calibration values depend on board routing, SoC, and DDR
	 *   mx6_ddr_sysinfo - board-specific memory architecture (width/cs/etc)
	 *   mx6_ddr_cfg - chip specific timing/layout details
	 */
	if (width == 16 && size_mb == 128) {
		mem = &mt41k64m16jt_125;
		if (is_cpu_type(MXC_CPU_MX6Q))
			;
		else
			calib = &mx6sdl_64x16_mmdc_calib;
		debug("1gB density\n");
	} else if (width == 16 && size_mb == 256) {
		/* 1x 2Gb density chip - same calib as 2x 2Gb */
		mem = &mt41k128m16jt_125;
		if (is_cpu_type(MXC_CPU_MX6Q))
			calib = &mx6dq_128x32_mmdc_calib;
		else
			calib = &mx6sdl_128x32_mmdc_calib;
		debug("2gB density\n");
	} else if (width == 16 && size_mb == 512) {
		mem = &mt41k256m16ha_125;
		if (is_cpu_type(MXC_CPU_MX6Q))
			calib = &mx6dq_256x16_mmdc_calib;
		else
			calib = &mx6sdl_256x16_mmdc_calib;
		debug("4gB density\n");
	} else if (width == 32 && size_mb == 256) {
		/* Same calib as width==16, size==128 */
		mem = &mt41k64m16jt_125;
		if (is_cpu_type(MXC_CPU_MX6Q))
			;
		else
			calib = &mx6sdl_64x16_mmdc_calib;
		debug("1gB density\n");
	} else if (width == 32 && size_mb == 512) {
		mem = &mt41k128m16jt_125;
		if (is_cpu_type(MXC_CPU_MX6Q))
			calib = &mx6dq_128x32_mmdc_calib;
		else
			calib = &mx6sdl_128x32_mmdc_calib;
		debug("2gB density\n");
	}  else if (width == 32 && size_mb == 1024) {
		mem = &mt41k256m16ha_125;
		if (is_cpu_type(MXC_CPU_MX6Q))
			calib = &mx6dq_256x32_mmdc_calib;
		else
			calib = &mx6sdl_256x32_mmdc_calib;
		debug("4gB density\n");
	} else if (width == 64 && size_mb == 512) {
		mem = &mt41k64m16jt_125;
		debug("1gB density\n");
	} else if (width == 64 && size_mb == 1024) {
		mem = &mt41k128m16jt_125;
		if (is_cpu_type(MXC_CPU_MX6Q))
			calib = &mx6dq_128x64_mmdc_calib;
		else
			calib = &mx6sdl_128x64_mmdc_calib;
		debug("2gB density\n");
	} else if (width == 64 && size_mb == 2048) {
		mem = &mt41k256m16ha_125;
		if (is_cpu_type(MXC_CPU_MX6Q))
			calib = &mx6dq_256x64_mmdc_calib;
		debug("4gB density\n");
	}

	if (!(mem && calib)) {
		puts("Error: Invalid Calibration/Board Configuration\n");
		printf("MEM    : %s\n", mem ? "OKAY" : "NULL");
		printf("CALIB  : %s\n", calib ? "OKAY" : "NULL");
		printf("CPUTYPE: %s\n",
		       is_cpu_type(MXC_CPU_MX6Q) ? "IMX6Q" : "IMX6DL");
		printf("SIZE_MB: %d\n", size_mb);
		printf("WIDTH  : %d\n", width);
		hang();
	}

	if (is_cpu_type(MXC_CPU_MX6Q))
		mx6dq_dram_iocfg(width, &mx6dq_ddr_ioregs,
				 &mx6dq_grp_ioregs);
	else
		mx6sdl_dram_iocfg(width, &mx6sdl_ddr_ioregs,
				  &mx6sdl_grp_ioregs);
	mx6_dram_cfg(&sysinfo, calib, mem);
}

static void ccgr_init(void)
{
	struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;

	writel(0x00C03F3F, &ccm->CCGR0);
	writel(0x0030FC03, &ccm->CCGR1);
	writel(0x0FFFC000, &ccm->CCGR2);
	writel(0x3FF00000, &ccm->CCGR3);
	writel(0xFFFFF300, &ccm->CCGR4);	/* enable NAND/GPMI/BCH clks */
	writel(0x0F0000C3, &ccm->CCGR5);
	writel(0x000003FF, &ccm->CCGR6);
}

static void gpr_init(void)
{
	struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;

	/* enable AXI cache for VDOA/VPU/IPU */
	writel(0xF00000CF, &iomux->gpr[4]);
	/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */
	writel(0x007F007F, &iomux->gpr[6]);
	writel(0x007F007F, &iomux->gpr[7]);
}

/*
 * called from C runtime startup code (arch/arm/lib/crt0.S:_main)
 * - we have a stack and a place to store GD, both in SRAM
 * - no variable global data is available
 */
void board_init_f(ulong dummy)
{
	struct ventana_board_info ventana_info;
	int board_model;

	/* setup clock gating */
	ccgr_init();

	/* setup AIPS and disable watchdog */
	arch_cpu_init();

	/* setup AXI */
	gpr_init();

	/* iomux and setup of i2c */
	setup_iomux_uart();
	setup_ventana_i2c();

	/* setup GP timer */
	timer_init();

	/* UART clocks enabled and gd valid - init serial console */
	preloader_console_init();

	/* read/validate EEPROM info to determine board model and SDRAM cfg */
	board_model = read_eeprom(CONFIG_I2C_GSC, &ventana_info);

	/* configure model-specific gpio */
	setup_iomux_gpio(board_model, &ventana_info);

	/* provide some some default: 32bit 128MB */
	if (GW_UNKNOWN == board_model) {
		ventana_info.sdram_width = 2;
		ventana_info.sdram_size = 3;
	}

	/* configure MMDC for SDRAM width/size and per-model calibration */
	spl_dram_init(8 << ventana_info.sdram_width,
		      16 << ventana_info.sdram_size,
		      board_model);

	/* Clear the BSS. */
	memset(__bss_start, 0, __bss_end - __bss_start);

	/* disable boot watchdog */
	gsc_boot_wd_disable();
}

/* called from board_init_r after gd setup if CONFIG_SPL_BOARD_INIT defined */
/* its our chance to print info about boot device */
void spl_board_init(void)
{
	/* determine boot device from SRC_SBMR1 (BOOT_CFG[4:1]) or SRC_GPR9 */
	u32 boot_device = spl_boot_device();

	switch (boot_device) {
	case BOOT_DEVICE_MMC1:
		puts("Booting from MMC\n");
		break;
	case BOOT_DEVICE_NAND:
		puts("Booting from NAND\n");
		break;
	case BOOT_DEVICE_SATA:
		puts("Booting from SATA\n");
		break;
	default:
		puts("Unknown boot device\n");
	}

	/* PMIC init */
	setup_pmic();
}

#ifdef CONFIG_SPL_OS_BOOT
/* return 1 if we wish to boot to uboot vs os (falcon mode) */
int spl_start_uboot(void)
{
	int ret = 1;

	debug("%s\n", __func__);
#ifdef CONFIG_SPL_ENV_SUPPORT
	env_init();
	env_relocate_spec();
	debug("boot_os=%s\n", getenv("boot_os"));
	if (getenv_yesno("boot_os") == 1)
		ret = 0;
#endif
	debug("%s booting %s\n", __func__, ret ? "uboot" : "linux");
	return ret;
}
#endif

void reset_cpu(ulong addr)
{
}
Commit	Line	Data
0cc11dea TH	1	/*
	2	* Copyright (C) 2014 Gateworks Corporation
	3	* Author: Tim Harvey <tharvey@gateworks.com>
	4	*
	5	* SPDX-License-Identifier: GPL-2.0+
	6	*/
	7
	8	#include <common.h>
0cc11dea	9	#include <asm/io.h>
e25fbe3f	10	#include <asm/arch/crm_regs.h>
0cc11dea TH	11	#include <asm/arch/mx6-ddr.h>
	12	#include <asm/arch/mx6-pins.h>
	13	#include <asm/arch/sys_proto.h>
	14	#include <asm/imx-common/boot_mode.h>
	15	#include <asm/imx-common/iomux-v3.h>
	16	#include <asm/imx-common/mxc_i2c.h>
53940a50	17	#include <environment.h>
0cc11dea TH	18	#include <spl.h>
0cc11dea TH	19
2089b7be TH	20	#include "gsc.h"
2089b7be TH	21	#include "common.h"
0cc11dea TH	22
	23	DECLARE_GLOBAL_DATA_PTR;
	24
	25	#define RTT_NOM_120OHM /* use 120ohm Rtt_nom vs 60ohm (lower power) */
0cc11dea TH	26	#define GSC_EEPROM_DDR_SIZE 0x2B /* enum (512,1024,2048) MB */
0cc11dea TH	27	#define GSC_EEPROM_DDR_WIDTH 0x2D /* enum (32,64) bit */
0cc11dea TH	28
	29	/* configure MX6Q/DUAL mmdc DDR io registers */
	30	struct mx6dq_iomux_ddr_regs mx6dq_ddr_ioregs = {
	31	/* SDCLK[0:1], CAS, RAS, Reset: Differential input, 40ohm */
	32	.dram_sdclk_0 = 0x00020030,
	33	.dram_sdclk_1 = 0x00020030,
	34	.dram_cas = 0x00020030,
	35	.dram_ras = 0x00020030,
	36	.dram_reset = 0x00020030,
	37	/* SDCKE[0:1]: 100k pull-up */
	38	.dram_sdcke0 = 0x00003000,
	39	.dram_sdcke1 = 0x00003000,
	40	/* SDBA2: pull-up disabled */
	41	.dram_sdba2 = 0x00000000,
	42	/* SDODT[0:1]: 100k pull-up, 40 ohm */
	43	.dram_sdodt0 = 0x00003030,
	44	.dram_sdodt1 = 0x00003030,
	45	/* SDQS[0:7]: Differential input, 40 ohm */
	46	.dram_sdqs0 = 0x00000030,
	47	.dram_sdqs1 = 0x00000030,
	48	.dram_sdqs2 = 0x00000030,
	49	.dram_sdqs3 = 0x00000030,
	50	.dram_sdqs4 = 0x00000030,
	51	.dram_sdqs5 = 0x00000030,
	52	.dram_sdqs6 = 0x00000030,
	53	.dram_sdqs7 = 0x00000030,
	54
	55	/* DQM[0:7]: Differential input, 40 ohm */
	56	.dram_dqm0 = 0x00020030,
	57	.dram_dqm1 = 0x00020030,
	58	.dram_dqm2 = 0x00020030,
	59	.dram_dqm3 = 0x00020030,
	60	.dram_dqm4 = 0x00020030,
	61	.dram_dqm5 = 0x00020030,
	62	.dram_dqm6 = 0x00020030,
	63	.dram_dqm7 = 0x00020030,
	64	};
	65
	66	/* configure MX6Q/DUAL mmdc GRP io registers */
	67	struct mx6dq_iomux_grp_regs mx6dq_grp_ioregs = {
	68	/* DDR3 */
	69	.grp_ddr_type = 0x000c0000,
	70	.grp_ddrmode_ctl = 0x00020000,
	71	/* disable DDR pullups */
	72	.grp_ddrpke = 0x00000000,
	73	/* ADDR[00:16], SDBA[0:1]: 40 ohm */
	74	.grp_addds = 0x00000030,
	75	/* CS0/CS1/SDBA2/CKE0/CKE1/SDWE: 40 ohm */
	76	.grp_ctlds = 0x00000030,
	77	/* DATA[00:63]: Differential input, 40 ohm */
	78	.grp_ddrmode = 0x00020000,
	79	.grp_b0ds = 0x00000030,
	80	.grp_b1ds = 0x00000030,
	81	.grp_b2ds = 0x00000030,
	82	.grp_b3ds = 0x00000030,
	83	.grp_b4ds = 0x00000030,
	84	.grp_b5ds = 0x00000030,
	85	.grp_b6ds = 0x00000030,
	86	.grp_b7ds = 0x00000030,
	87	};
	88
	89	/* configure MX6SOLO/DUALLITE mmdc DDR io registers */
	90	struct mx6sdl_iomux_ddr_regs mx6sdl_ddr_ioregs = {
	91	/* SDCLK[0:1], CAS, RAS, Reset: Differential input, 40ohm */
92	.dram_sdclk_0 = 0x00020030,
93	.dram_sdclk_1 = 0x00020030,
94	.dram_cas = 0x00020030,
95	.dram_ras = 0x00020030,
96	.dram_reset = 0x00020030,
97	/* SDCKE[0:1]: 100k pull-up */
98	.dram_sdcke0 = 0x00003000,
99	.dram_sdcke1 = 0x00003000,
100	/* SDBA2: pull-up disabled */
101	.dram_sdba2 = 0x00000000,
102	/* SDODT[0:1]: 100k pull-up, 40 ohm */
103	.dram_sdodt0 = 0x00003030,
104	.dram_sdodt1 = 0x00003030,
105	/* SDQS[0:7]: Differential input, 40 ohm */
106	.dram_sdqs0 = 0x00000030,
107	.dram_sdqs1 = 0x00000030,
108	.dram_sdqs2 = 0x00000030,
109	.dram_sdqs3 = 0x00000030,
110	.dram_sdqs4 = 0x00000030,
111	.dram_sdqs5 = 0x00000030,
112	.dram_sdqs6 = 0x00000030,
113	.dram_sdqs7 = 0x00000030,
114
115	/* DQM[0:7]: Differential input, 40 ohm */
116	.dram_dqm0 = 0x00020030,
117	.dram_dqm1 = 0x00020030,
118	.dram_dqm2 = 0x00020030,
119	.dram_dqm3 = 0x00020030,
120	.dram_dqm4 = 0x00020030,
121	.dram_dqm5 = 0x00020030,
122	.dram_dqm6 = 0x00020030,
123	.dram_dqm7 = 0x00020030,
124	};
125
126	/* configure MX6SOLO/DUALLITE mmdc GRP io registers */
127	struct mx6sdl_iomux_grp_regs mx6sdl_grp_ioregs = {
128	/* DDR3 */
129	.grp_ddr_type = 0x000c0000,
130	/* SDQS[0:7]: Differential input, 40 ohm */
131	.grp_ddrmode_ctl = 0x00020000,
132	/* disable DDR pullups */
133	.grp_ddrpke = 0x00000000,
134	/* ADDR[00:16], SDBA[0:1]: 40 ohm */
135	.grp_addds = 0x00000030,
136	/* CS0/CS1/SDBA2/CKE0/CKE1/SDWE: 40 ohm */
137	.grp_ctlds = 0x00000030,
138	/* DATA[00:63]: Differential input, 40 ohm */
139	.grp_ddrmode = 0x00020000,
140	.grp_b0ds = 0x00000030,
141	.grp_b1ds = 0x00000030,
142	.grp_b2ds = 0x00000030,
143	.grp_b3ds = 0x00000030,
144	.grp_b4ds = 0x00000030,
145	.grp_b5ds = 0x00000030,
146	.grp_b6ds = 0x00000030,
147	.grp_b7ds = 0x00000030,
148	};
149
767d88b0 PS	150	/* MT41K64M16JT-125 (1Gb density) */
	151	static struct mx6_ddr3_cfg mt41k64m16jt_125 = {
	152	.mem_speed = 1600,
	153	.density = 1,
	154	.width = 16,
	155	.banks = 8,
	156	.rowaddr = 13,
	157	.coladdr = 10,
	158	.pagesz = 2,
	159	.trcd = 1375,
	160	.trcmin = 4875,
	161	.trasmin = 3500,
	162	};
	163
b0b83347	164	/* MT41K128M16JT-125 (2Gb density) */
0cc11dea TH	165	static struct mx6_ddr3_cfg mt41k128m16jt_125 = {
	166	.mem_speed = 1600,
	167	.density = 2,
	168	.width = 16,
	169	.banks = 8,
	170	.rowaddr = 14,
	171	.coladdr = 10,
	172	.pagesz = 2,
	173	.trcd = 1375,
	174	.trcmin = 4875,
	175	.trasmin = 3500,
	176	};
	177
b0b83347	178	/* MT41K256M16HA-125 (4Gb density) */
c91e4b8b TH	179	static struct mx6_ddr3_cfg mt41k256m16ha_125 = {
	180	.mem_speed = 1600,
	181	.density = 4,
	182	.width = 16,
	183	.banks = 8,
	184	.rowaddr = 15,
	185	.coladdr = 10,
	186	.pagesz = 2,
	187	.trcd = 1375,
	188	.trcmin = 4875,
	189	.trasmin = 3500,
	190	};
	191
	192	/*
	193	* calibration - these are the various CPU/DDR3 combinations we support
	194	*/
767d88b0 PS	195	static struct mx6_mmdc_calibration mx6sdl_64x16_mmdc_calib = {
	196	/* write leveling calibration determine */
	197	.p0_mpwldectrl0 = 0x004C004E,
	198	.p0_mpwldectrl1 = 0x00440044,
	199	/* Read DQS Gating calibration */
	200	.p0_mpdgctrl0 = 0x42440247,
	201	.p0_mpdgctrl1 = 0x02310232,
	202	/* Read Calibration: DQS delay relative to DQ read access */
	203	.p0_mprddlctl = 0x45424746,
	204	/* Write Calibration: DQ/DM delay relative to DQS write access */
	205	.p0_mpwrdlctl = 0x33382C31,
	206	};
c91e4b8b	207
75f21e31 TH	208	static struct mx6_mmdc_calibration mx6dq_256x16_mmdc_calib = {
75f21e31 TH	209	/* write leveling calibration determine */
06edcb9d TH	210	.p0_mpwldectrl0 = 0x001B0016,
06edcb9d TH	211	.p0_mpwldectrl1 = 0x000C000E,
75f21e31	212	/* Read DQS Gating calibration */
06edcb9d TH	213	.p0_mpdgctrl0 = 0x4324033A,
06edcb9d TH	214	.p0_mpdgctrl1 = 0x00000000,
75f21e31	215	/* Read Calibration: DQS delay relative to DQ read access */
06edcb9d	216	.p0_mprddlctl = 0x40403438,
75f21e31	217	/* Write Calibration: DQ/DM delay relative to DQS write access */
06edcb9d	218	.p0_mpwrdlctl = 0x40403D36,
75f21e31 TH	219	};
75f21e31 TH	220
75f21e31 TH	221	static struct mx6_mmdc_calibration mx6sdl_256x16_mmdc_calib = {
75f21e31 TH	222	/* write leveling calibration determine */
06edcb9d TH	223	.p0_mpwldectrl0 = 0x00420043,
06edcb9d TH	224	.p0_mpwldectrl1 = 0x0016001A,
75f21e31	225	/* Read DQS Gating calibration */
06edcb9d TH	226	.p0_mpdgctrl0 = 0x4238023B,
06edcb9d TH	227	.p0_mpdgctrl1 = 0x00000000,
75f21e31	228	/* Read Calibration: DQS delay relative to DQ read access */
06edcb9d	229	.p0_mprddlctl = 0x40404849,
75f21e31	230	/* Write Calibration: DQ/DM delay relative to DQS write access */
06edcb9d	231	.p0_mpwrdlctl = 0x40402E2F,
75f21e31 TH	232	};
75f21e31 TH	233
c91e4b8b	234	static struct mx6_mmdc_calibration mx6dq_128x32_mmdc_calib = {
0cc11dea	235	/* write leveling calibration determine */
c91e4b8b TH	236	.p0_mpwldectrl0 = 0x00190017,
c91e4b8b TH	237	.p0_mpwldectrl1 = 0x00140026,
0cc11dea	238	/* Read DQS Gating calibration */
c91e4b8b TH	239	.p0_mpdgctrl0 = 0x43380347,
c91e4b8b TH	240	.p0_mpdgctrl1 = 0x433C034D,
0cc11dea TH	241	/* Read Calibration: DQS delay relative to DQ read access */
0cc11dea TH	242	.p0_mprddlctl = 0x3C313539,
0cc11dea	243	/* Write Calibration: DQ/DM delay relative to DQS write access */
c91e4b8b TH	244	.p0_mpwrdlctl = 0x36393C39,
	245	};
	246
	247	static struct mx6_mmdc_calibration mx6sdl_128x32_mmdc_calib = {
	248	/* write leveling calibration determine */
	249	.p0_mpwldectrl0 = 0x003C003C,
	250	.p0_mpwldectrl1 = 0x001F002A,
	251	/* Read DQS Gating calibration */
	252	.p0_mpdgctrl0 = 0x42410244,
	253	.p0_mpdgctrl1 = 0x4234023A,
	254	/* Read Calibration: DQS delay relative to DQ read access */
	255	.p0_mprddlctl = 0x484A4C4B,
	256	/* Write Calibration: DQ/DM delay relative to DQS write access */
	257	.p0_mpwrdlctl = 0x33342B32,
0cc11dea TH	258	};
0cc11dea TH	259
c91e4b8b	260	static struct mx6_mmdc_calibration mx6dq_128x64_mmdc_calib = {
0cc11dea	261	/* write leveling calibration determine */
c91e4b8b TH	262	.p0_mpwldectrl0 = 0x00190017,
	263	.p0_mpwldectrl1 = 0x00140026,
	264	.p1_mpwldectrl0 = 0x0021001C,
	265	.p1_mpwldectrl1 = 0x0011001D,
0cc11dea	266	/* Read DQS Gating calibration */
c91e4b8b TH	267	.p0_mpdgctrl0 = 0x43380347,
	268	.p0_mpdgctrl1 = 0x433C034D,
	269	.p1_mpdgctrl0 = 0x032C0324,
	270	.p1_mpdgctrl1 = 0x03310232,
0cc11dea	271	/* Read Calibration: DQS delay relative to DQ read access */
c91e4b8b TH	272	.p0_mprddlctl = 0x3C313539,
c91e4b8b TH	273	.p1_mprddlctl = 0x37343141,
0cc11dea	274	/* Write Calibration: DQ/DM delay relative to DQS write access */
c91e4b8b TH	275	.p0_mpwrdlctl = 0x36393C39,
c91e4b8b TH	276	.p1_mpwrdlctl = 0x42344438,
0cc11dea	277	};
c91e4b8b TH	278
c91e4b8b TH	279	static struct mx6_mmdc_calibration mx6sdl_128x64_mmdc_calib = {
0cc11dea TH	280	/* write leveling calibration determine */
0cc11dea TH	281	.p0_mpwldectrl0 = 0x003C003C,
c91e4b8b TH	282	.p0_mpwldectrl1 = 0x001F002A,
c91e4b8b TH	283	.p1_mpwldectrl0 = 0x00330038,
0cc11dea TH	284	.p1_mpwldectrl1 = 0x0022003F,
	285	/* Read DQS Gating calibration */
	286	.p0_mpdgctrl0 = 0x42410244,
c91e4b8b TH	287	.p0_mpdgctrl1 = 0x4234023A,
c91e4b8b TH	288	.p1_mpdgctrl0 = 0x022D022D,
0cc11dea TH	289	.p1_mpdgctrl1 = 0x021C0228,
	290	/* Read Calibration: DQS delay relative to DQ read access */
	291	.p0_mprddlctl = 0x484A4C4B,
	292	.p1_mprddlctl = 0x4B4D4E4B,
	293	/* Write Calibration: DQ/DM delay relative to DQS write access */
	294	.p0_mpwrdlctl = 0x33342B32,
	295	.p1_mpwrdlctl = 0x3933332B,
	296	};
	297
c91e4b8b	298	static struct mx6_mmdc_calibration mx6dq_256x32_mmdc_calib = {
0cc11dea	299	/* write leveling calibration determine */
c91e4b8b TH	300	.p0_mpwldectrl0 = 0x001E001A,
c91e4b8b TH	301	.p0_mpwldectrl1 = 0x0026001F,
0cc11dea	302	/* Read DQS Gating calibration */
c91e4b8b TH	303	.p0_mpdgctrl0 = 0x43370349,
c91e4b8b TH	304	.p0_mpdgctrl1 = 0x032D0327,
0cc11dea	305	/* Read Calibration: DQS delay relative to DQ read access */
c91e4b8b	306	.p0_mprddlctl = 0x3D303639,
0cc11dea	307	/* Write Calibration: DQ/DM delay relative to DQS write access */
c91e4b8b	308	.p0_mpwrdlctl = 0x32363934,
0cc11dea TH	309	};
0cc11dea TH	310
b0b83347 TH	311	static struct mx6_mmdc_calibration mx6sdl_256x32_mmdc_calib = {
	312	/* write leveling calibration determine */
	313	.p0_mpwldectrl0 = 0X00480047,
	314	.p0_mpwldectrl1 = 0X003D003F,
	315	/* Read DQS Gating calibration */
	316	.p0_mpdgctrl0 = 0X423E0241,
	317	.p0_mpdgctrl1 = 0X022B022C,
	318	/* Read Calibration: DQS delay relative to DQ read access */
	319	.p0_mprddlctl = 0X49454A4A,
	320	/* Write Calibration: DQ/DM delay relative to DQS write access */
	321	.p0_mpwrdlctl = 0X2E372C32,
	322	};
	323
c91e4b8b	324	static struct mx6_mmdc_calibration mx6dq_256x64_mmdc_calib = {
0cc11dea	325	/* write leveling calibration determine */
c91e4b8b TH	326	.p0_mpwldectrl0 = 0X00220021,
	327	.p0_mpwldectrl1 = 0X00200030,
	328	.p1_mpwldectrl0 = 0X002D0027,
	329	.p1_mpwldectrl1 = 0X00150026,
0cc11dea	330	/* Read DQS Gating calibration */
c91e4b8b TH	331	.p0_mpdgctrl0 = 0x43330342,
	332	.p0_mpdgctrl1 = 0x0339034A,
	333	.p1_mpdgctrl0 = 0x032F0325,
	334	.p1_mpdgctrl1 = 0x032F022E,
0cc11dea	335	/* Read Calibration: DQS delay relative to DQ read access */
c91e4b8b TH	336	.p0_mprddlctl = 0X3A2E3437,
c91e4b8b TH	337	.p1_mprddlctl = 0X35312F3F,
0cc11dea	338	/* Write Calibration: DQ/DM delay relative to DQS write access */
c91e4b8b TH	339	.p0_mpwrdlctl = 0X33363B37,
c91e4b8b TH	340	.p1_mpwrdlctl = 0X40304239,
0cc11dea TH	341	};
0cc11dea TH	342
c91e4b8b	343	static void spl_dram_init(int width, int size_mb, int board_model)
0cc11dea	344	{
c91e4b8b TH	345	struct mx6_ddr3_cfg *mem = NULL;
c91e4b8b TH	346	struct mx6_mmdc_calibration *calib = NULL;
0cc11dea TH	347	struct mx6_ddr_sysinfo sysinfo = {
	348	/* width of data bus:0=16,1=32,2=64 */
	349	.dsize = width/32,
	350	/* config for full 4GB range so that get_mem_size() works */
	351	.cs_density = 32, /* 32Gb per CS */
	352	/* single chip select */
	353	.ncs = 1,
	354	.cs1_mirror = 0,
	355	.rtt_wr = 1 /DDR3_RTT_60_OHM/, /* RTT_Wr = RZQ/4 */
	356	#ifdef RTT_NOM_120OHM
	357	.rtt_nom = 2 /DDR3_RTT_120_OHM/, /* RTT_Nom = RZQ/2 */
	358	#else
	359	.rtt_nom = 1 /DDR3_RTT_60_OHM/, /* RTT_Nom = RZQ/4 */
	360	#endif
	361	.walat = 1, /* Write additional latency */
	362	.ralat = 5, /* Read additional latency */
	363	.mif3_mode = 3, /* Command prediction working mode */
	364	.bi_on = 1, /* Bank interleaving enabled */
	365	.sde_to_rst = 0x10, /* 14 cycles, 200us (JEDEC default) */
	366	.rst_to_cke = 0x23, /* 33 cycles, 500us (JEDEC default) */
29f0d6b1	367	.pd_fast_exit = 1, /* enable precharge power-down fast exit */
0cc11dea TH	368	};
	369
	370	/*
	371	* MMDC Calibration requires the following data:
	372	* mx6_mmdc_calibration - board-specific calibration (routing delays)
c91e4b8b	373	* these calibration values depend on board routing, SoC, and DDR
0cc11dea TH	374	* mx6_ddr_sysinfo - board-specific memory architecture (width/cs/etc)
	375	* mx6_ddr_cfg - chip specific timing/layout details
	376	*/
767d88b0 PS	377	if (width == 16 && size_mb == 128) {
	378	mem = &mt41k64m16jt_125;
	379	if (is_cpu_type(MXC_CPU_MX6Q))
	380	;
	381	else
	382	calib = &mx6sdl_64x16_mmdc_calib;
	383	debug("1gB density\n");
	384	} else if (width == 16 && size_mb == 256) {
7f14c31b	385	/* 1x 2Gb density chip - same calib as 2x 2Gb */
75f21e31 TH	386	mem = &mt41k128m16jt_125;
75f21e31 TH	387	if (is_cpu_type(MXC_CPU_MX6Q))
7f14c31b	388	calib = &mx6dq_128x32_mmdc_calib;
75f21e31	389	else
7f14c31b	390	calib = &mx6sdl_128x32_mmdc_calib;
75f21e31 TH	391	debug("2gB density\n");
	392	} else if (width == 16 && size_mb == 512) {
	393	mem = &mt41k256m16ha_125;
	394	if (is_cpu_type(MXC_CPU_MX6Q))
	395	calib = &mx6dq_256x16_mmdc_calib;
	396	else
	397	calib = &mx6sdl_256x16_mmdc_calib;
	398	debug("4gB density\n");
767d88b0 PS	399	} else if (width == 32 && size_mb == 256) {
	400	/* Same calib as width==16, size==128 */
	401	mem = &mt41k64m16jt_125;
	402	if (is_cpu_type(MXC_CPU_MX6Q))
	403	;
	404	else
	405	calib = &mx6sdl_64x16_mmdc_calib;
	406	debug("1gB density\n");
75f21e31	407	} else if (width == 32 && size_mb == 512) {
c91e4b8b	408	mem = &mt41k128m16jt_125;
0cc11dea	409	if (is_cpu_type(MXC_CPU_MX6Q))
c91e4b8b	410	calib = &mx6dq_128x32_mmdc_calib;
0cc11dea	411	else
c91e4b8b TH	412	calib = &mx6sdl_128x32_mmdc_calib;
c91e4b8b TH	413	debug("2gB density\n");
767d88b0 PS	414	} else if (width == 32 && size_mb == 1024) {
	415	mem = &mt41k256m16ha_125;
	416	if (is_cpu_type(MXC_CPU_MX6Q))
	417	calib = &mx6dq_256x32_mmdc_calib;
	418	else
	419	calib = &mx6sdl_256x32_mmdc_calib;
	420	debug("4gB density\n");
	421	} else if (width == 64 && size_mb == 512) {
	422	mem = &mt41k64m16jt_125;
	423	debug("1gB density\n");
c91e4b8b TH	424	} else if (width == 64 && size_mb == 1024) {
c91e4b8b TH	425	mem = &mt41k128m16jt_125;
0cc11dea	426	if (is_cpu_type(MXC_CPU_MX6Q))
c91e4b8b	427	calib = &mx6dq_128x64_mmdc_calib;
0cc11dea	428	else
c91e4b8b TH	429	calib = &mx6sdl_128x64_mmdc_calib;
c91e4b8b TH	430	debug("2gB density\n");
c91e4b8b TH	431	} else if (width == 64 && size_mb == 2048) {
	432	mem = &mt41k256m16ha_125;
	433	if (is_cpu_type(MXC_CPU_MX6Q))
	434	calib = &mx6dq_256x64_mmdc_calib;
	435	debug("4gB density\n");
	436	}
	437
9e2b0c2d PS	438	if (!(mem && calib)) {
	439	puts("Error: Invalid Calibration/Board Configuration\n");
	440	printf("MEM : %s\n", mem ? "OKAY" : "NULL");
	441	printf("CALIB : %s\n", calib ? "OKAY" : "NULL");
	442	printf("CPUTYPE: %s\n",
	443	is_cpu_type(MXC_CPU_MX6Q) ? "IMX6Q" : "IMX6DL");
	444	printf("SIZE_MB: %d\n", size_mb);
	445	printf("WIDTH : %d\n", width);
c91e4b8b	446	hang();
0cc11dea TH	447	}
	448
	449	if (is_cpu_type(MXC_CPU_MX6Q))
	450	mx6dq_dram_iocfg(width, &mx6dq_ddr_ioregs,
	451	&mx6dq_grp_ioregs);
	452	else
	453	mx6sdl_dram_iocfg(width, &mx6sdl_ddr_ioregs,
	454	&mx6sdl_grp_ioregs);
	455	mx6_dram_cfg(&sysinfo, calib, mem);
	456	}
	457
e25fbe3f FE	458	static void ccgr_init(void)
	459	{
	460	struct mxc_ccm_reg ccm = (struct mxc_ccm_reg )CCM_BASE_ADDR;
	461
	462	writel(0x00C03F3F, &ccm->CCGR0);
	463	writel(0x0030FC03, &ccm->CCGR1);
	464	writel(0x0FFFC000, &ccm->CCGR2);
	465	writel(0x3FF00000, &ccm->CCGR3);
576cd6b3	466	writel(0xFFFFF300, &ccm->CCGR4); /* enable NAND/GPMI/BCH clks */
e25fbe3f FE	467	writel(0x0F0000C3, &ccm->CCGR5);
	468	writel(0x000003FF, &ccm->CCGR6);
	469	}
	470
	471	static void gpr_init(void)
	472	{
	473	struct iomuxc iomux = (struct iomuxc )IOMUXC_BASE_ADDR;
	474
	475	/* enable AXI cache for VDOA/VPU/IPU */
	476	writel(0xF00000CF, &iomux->gpr[4]);
	477	/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */
	478	writel(0x007F007F, &iomux->gpr[6]);
	479	writel(0x007F007F, &iomux->gpr[7]);
	480	}
	481
0cc11dea TH	482	/*
	483	* called from C runtime startup code (arch/arm/lib/crt0.S:_main)
	484	* - we have a stack and a place to store GD, both in SRAM
	485	* - no variable global data is available
	486	*/
	487	void board_init_f(ulong dummy)
	488	{
	489	struct ventana_board_info ventana_info;
	490	int board_model;
	491
d783c274 TH	492	/* setup clock gating */
	493	ccgr_init();
	494
0cc11dea TH	495	/* setup AIPS and disable watchdog */
	496	arch_cpu_init();
	497
d783c274	498	/* setup AXI */
e25fbe3f FE	499	gpr_init();
e25fbe3f FE	500
0cc11dea	501	/* iomux and setup of i2c */
2089b7be TH	502	setup_iomux_uart();
2089b7be TH	503	setup_ventana_i2c();
0cc11dea TH	504
	505	/* setup GP timer */
	506	timer_init();
	507
	508	/* UART clocks enabled and gd valid - init serial console */
	509	preloader_console_init();
	510
	511	/* read/validate EEPROM info to determine board model and SDRAM cfg */
2089b7be	512	board_model = read_eeprom(CONFIG_I2C_GSC, &ventana_info);
0cc11dea	513
c4b44d76 TH	514	/* configure model-specific gpio */
	515	setup_iomux_gpio(board_model, &ventana_info);
	516
0cc11dea TH	517	/* provide some some default: 32bit 128MB */
	518	if (GW_UNKNOWN == board_model) {
	519	ventana_info.sdram_width = 2;
	520	ventana_info.sdram_size = 3;
	521	}
	522
	523	/* configure MMDC for SDRAM width/size and per-model calibration */
	524	spl_dram_init(8 << ventana_info.sdram_width,
	525	16 << ventana_info.sdram_size,
	526	board_model);
	527
	528	/* Clear the BSS. */
	529	memset(__bss_start, 0, __bss_end - __bss_start);
	530
ea7a3c44 TH	531	/* disable boot watchdog */
ea7a3c44 TH	532	gsc_boot_wd_disable();
0cc11dea TH	533	}
0cc11dea TH	534
06c3564d TH	535	/* called from board_init_r after gd setup if CONFIG_SPL_BOARD_INIT defined */
	536	/* its our chance to print info about boot device */
	537	void spl_board_init(void)
	538	{
	539	/* determine boot device from SRC_SBMR1 (BOOT_CFG[4:1]) or SRC_GPR9 */
	540	u32 boot_device = spl_boot_device();
	541
	542	switch (boot_device) {
	543	case BOOT_DEVICE_MMC1:
	544	puts("Booting from MMC\n");
	545	break;
	546	case BOOT_DEVICE_NAND:
	547	puts("Booting from NAND\n");
	548	break;
	549	case BOOT_DEVICE_SATA:
	550	puts("Booting from SATA\n");
	551	break;
	552	default:
	553	puts("Unknown boot device\n");
	554	}
e06a0362 TH	555
	556	/* PMIC init */
	557	setup_pmic();
06c3564d TH	558	}
06c3564d TH	559
53940a50 TH	560	#ifdef CONFIG_SPL_OS_BOOT
	561	/* return 1 if we wish to boot to uboot vs os (falcon mode) */
	562	int spl_start_uboot(void)
	563	{
	564	int ret = 1;
	565
	566	debug("%s\n", __func__);
	567	#ifdef CONFIG_SPL_ENV_SUPPORT
	568	env_init();
	569	env_relocate_spec();
	570	debug("boot_os=%s\n", getenv("boot_os"));
	571	if (getenv_yesno("boot_os") == 1)
	572	ret = 0;
	573	#endif
	574	debug("%s booting %s\n", __func__, ret ? "uboot" : "linux");
	575	return ret;
	576	}
	577	#endif
	578
0cc11dea TH	579	void reset_cpu(ulong addr)
	580	{
	581	}