[people/ms/u-boot.git] / board / inka4x0 / inka4x0.c

/*
 * (C) Copyright 2008-2009
 * Andreas Pfefferle, DENX Software Engineering, ap@denx.de.
 *
 * (C) Copyright 2009
 * Detlev Zundel, DENX Software Engineering, dzu@denx.de.
 *
 * (C) Copyright 2004
 * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com.
 *
 * (C) Copyright 2004
 * Martin Krause, TQ-Systems GmbH, martin.krause@tqs.de
 *
 * (C) Copyright 2003-2004
 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#include <asm/io.h>
#include <common.h>
#include <mpc5xxx.h>
#include <pci.h>

#if defined(CONFIG_DDR_MT46V16M16)
#include "mt46v16m16-75.h"
#elif defined(CONFIG_SDR_MT48LC16M16A2)
#include "mt48lc16m16a2-75.h"
#elif defined(CONFIG_DDR_MT46V32M16)
#include "mt46v32m16.h"
#elif defined(CONFIG_DDR_HYB25D512160BF)
#include "hyb25d512160bf.h"
#elif defined(CONFIG_DDR_K4H511638C)
#include "k4h511638c.h"
#else
#error "INKA4x0 SDRAM: invalid chip type specified!"
#endif

DECLARE_GLOBAL_DATA_PTR;

#ifndef CONFIG_SYS_RAMBOOT
static void sdram_start (int hi_addr)
{
	volatile struct mpc5xxx_sdram *sdram =
		(struct mpc5xxx_sdram *)MPC5XXX_SDRAM;
	long hi_addr_bit = hi_addr ? 0x01000000 : 0;

	/* unlock mode register */
	out_be32(&sdram->ctrl, SDRAM_CONTROL | 0x80000000 | hi_addr_bit);

	/* precharge all banks */
	out_be32(&sdram->ctrl, SDRAM_CONTROL | 0x80000002 | hi_addr_bit);

#if SDRAM_DDR
	/* set mode register: extended mode */
	out_be32(&sdram->mode, SDRAM_EMODE);

	/* set mode register: reset DLL */
	out_be32(&sdram->mode, SDRAM_MODE | 0x04000000);
#endif

	/* precharge all banks */
	out_be32(&sdram->ctrl, SDRAM_CONTROL | 0x80000002 | hi_addr_bit);

	/* auto refresh */
	out_be32(&sdram->ctrl, SDRAM_CONTROL | 0x80000004 | hi_addr_bit);

	/* set mode register */
	out_be32(&sdram->mode, SDRAM_MODE);

	/* normal operation */
	out_be32(&sdram->ctrl, SDRAM_CONTROL | hi_addr_bit);
}
#endif

/*
 * ATTENTION: Although partially referenced initdram does NOT make real use
 *	      use of CONFIG_SYS_SDRAM_BASE. The code does not work if CONFIG_SYS_SDRAM_BASE
 *	      is something else than 0x00000000.
 */

int initdram(void)
{
	volatile struct mpc5xxx_mmap_ctl *mm =
		(struct mpc5xxx_mmap_ctl *) CONFIG_SYS_MBAR;
	volatile struct mpc5xxx_cdm     *cdm =
		(struct mpc5xxx_cdm *)      MPC5XXX_CDM;
	volatile struct mpc5xxx_sdram *sdram =
		(struct mpc5xxx_sdram *)    MPC5XXX_SDRAM;
	ulong dramsize = 0;
#ifndef CONFIG_SYS_RAMBOOT
	long test1, test2;

	/* setup SDRAM chip selects */
	out_be32(&mm->sdram0, 0x0000001c);	/* 512MB at 0x0 */
	out_be32(&mm->sdram1, 0x40000000);	/* disabled */

	/* setup config registers */
	out_be32(&sdram->config1, SDRAM_CONFIG1);
	out_be32(&sdram->config2, SDRAM_CONFIG2);

#if SDRAM_DDR
	/* set tap delay */
	out_be32(&cdm->porcfg, SDRAM_TAPDELAY);
#endif

	/* find RAM size using SDRAM CS0 only */
	sdram_start(0);
	test1 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x20000000);
	sdram_start(1);
	test2 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x20000000);
	if (test1 > test2) {
		sdram_start(0);
		dramsize = test1;
	} else {
		dramsize = test2;
	}

	/* memory smaller than 1MB is impossible */
	if (dramsize < (1 << 20)) {
		dramsize = 0;
	}

	/* set SDRAM CS0 size according to the amount of RAM found */
	if (dramsize > 0) {
		out_be32(&mm->sdram0, 0x13 +
			 __builtin_ffs(dramsize >> 20) - 1);
	} else {
		out_be32(&mm->sdram0, 0); /* disabled */
	}

	out_be32(&mm->sdram1, dramsize); /* disabled */
#else /* CONFIG_SYS_RAMBOOT */

	/* retrieve size of memory connected to SDRAM CS0 */
	dramsize = in_be32(&mm->sdram0) & 0xFF;
	if (dramsize >= 0x13) {
		dramsize = (1 << (dramsize - 0x13)) << 20;
	} else {
		dramsize = 0;
	}
#endif /* CONFIG_SYS_RAMBOOT */

	gd->ram_size = dramsize;

	return 0;
}

int checkboard (void)
{
	puts ("Board: INKA 4X0\n");
	return 0;
}

void flash_preinit(void)
{
	volatile struct mpc5xxx_lpb *lpb = (struct mpc5xxx_lpb *)MPC5XXX_LPB;

	/*
	 * Now, when we are in RAM, enable flash write
	 * access for detection process.
	 * Note that CS_BOOT (CS0) cannot be cleared when
	 * executing in flash.
	 */
	clrbits_be32(&lpb->cs0_cfg, 0x1); /* clear RO */
}

int misc_init_f (void)
{
	volatile struct mpc5xxx_gpio	*gpio    =
		(struct mpc5xxx_gpio *)   MPC5XXX_GPIO;
	volatile struct mpc5xxx_wu_gpio	*wu_gpio =
		(struct mpc5xxx_wu_gpio *)MPC5XXX_WU_GPIO;
	volatile struct mpc5xxx_gpt	*gpt;
	char tmp[10];
	int i, br;

	i = getenv_f("brightness", tmp, sizeof(tmp));
	br = (i > 0)
		? (int) simple_strtoul (tmp, NULL, 10)
		: CONFIG_SYS_BRIGHTNESS;
	if (br > 255)
		br = 255;

	/* Initialize GPIO output pins.
	 */
	/* Configure GPT as GPIO output (and set them as they control low-active LEDs */
	for (i = 0; i <= 5; i++) {
		gpt = (struct mpc5xxx_gpt *)(MPC5XXX_GPT + (i * 0x10));
		out_be32(&gpt->emsr, 0x34);
	}

	/* Configure GPT7 as PWM timer, 1kHz, no ints. */
	gpt = (struct mpc5xxx_gpt *)(MPC5XXX_GPT + (7 * 0x10));
	out_be32(&gpt->emsr,  0);		/* Disable */
	out_be32(&gpt->cir,   0x020000fe);
	out_be32(&gpt->pwmcr, (br << 16));
	out_be32(&gpt->emsr,  0x3);		/* Enable PWM mode and start */

	/* Configure PSC3_6,7 as GPIO output */
	setbits_be32(&gpio->simple_gpioe, MPC5XXX_GPIO_SIMPLE_PSC3_6 |
					  MPC5XXX_GPIO_SIMPLE_PSC3_7);
	setbits_be32(&gpio->simple_ddr,   MPC5XXX_GPIO_SIMPLE_PSC3_6 |
					  MPC5XXX_GPIO_SIMPLE_PSC3_7);

	/* Configure PSC3_9 and GPIO_WKUP6,7 as GPIO output */
	setbits_8(&wu_gpio->enable,  MPC5XXX_GPIO_WKUP_6 |
				     MPC5XXX_GPIO_WKUP_7 |
				     MPC5XXX_GPIO_WKUP_PSC3_9);
	setbits_8(&wu_gpio->ddr,     MPC5XXX_GPIO_WKUP_6 |
				     MPC5XXX_GPIO_WKUP_7 |
				     MPC5XXX_GPIO_WKUP_PSC3_9);

	/* Set LR mirror bit because it is low-active */
	setbits_8(&wu_gpio->dvo,     MPC5XXX_GPIO_WKUP_7);

	/* Reset Coral-P graphics controller */
	setbits_8(&wu_gpio->dvo,     MPC5XXX_GPIO_WKUP_PSC3_9);

	/* Enable display backlight */
	clrbits_8(&gpio->sint_inten, MPC5XXX_GPIO_SINT_PSC3_8);
	setbits_8(&gpio->sint_gpioe, MPC5XXX_GPIO_SINT_PSC3_8);
	setbits_8(&gpio->sint_ddr,   MPC5XXX_GPIO_SINT_PSC3_8);
	setbits_8(&gpio->sint_dvo,   MPC5XXX_GPIO_SINT_PSC3_8);

	/*
	 * Configure three wire serial interface to RTC (PSC1_4,
	 * PSC2_4, PSC3_4, PSC3_5)
	 */
	setbits_8(&wu_gpio->enable,  MPC5XXX_GPIO_WKUP_PSC1_4 |
				     MPC5XXX_GPIO_WKUP_PSC2_4);
	setbits_8(&wu_gpio->ddr,     MPC5XXX_GPIO_WKUP_PSC1_4 |
				     MPC5XXX_GPIO_WKUP_PSC2_4);
	clrbits_8(&wu_gpio->dvo,     MPC5XXX_GPIO_WKUP_PSC1_4);
	clrbits_8(&gpio->sint_inten, MPC5XXX_GPIO_SINT_PSC3_4 |
				     MPC5XXX_GPIO_SINT_PSC3_5);
	setbits_8(&gpio->sint_gpioe, MPC5XXX_GPIO_SINT_PSC3_4 |
				     MPC5XXX_GPIO_SINT_PSC3_5);
	setbits_8(&gpio->sint_ddr,   MPC5XXX_GPIO_SINT_PSC3_5);
	clrbits_8(&gpio->sint_dvo,   MPC5XXX_GPIO_SINT_PSC3_5);

	return 0;
}

#ifdef	CONFIG_PCI
static struct pci_controller hose;

extern void pci_mpc5xxx_init(struct pci_controller *);

void pci_init_board(void)
{
	pci_mpc5xxx_init(&hose);
}
#endif
Commit	Line	Data
138ff60c	1	/*
7b5611cd DZ	2	* (C) Copyright 2008-2009
	3	* Andreas Pfefferle, DENX Software Engineering, ap@denx.de.
	4	*
	5	* (C) Copyright 2009
	6	* Detlev Zundel, DENX Software Engineering, dzu@denx.de.
138ff60c WD	7	*
	8	* (C) Copyright 2004
	9	* Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com.
	10	*
	11	* (C) Copyright 2004
	12	* Martin Krause, TQ-Systems GmbH, martin.krause@tqs.de
	13	*
7b5611cd DZ	14	* (C) Copyright 2003-2004
	15	* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
	16	*
3765b3e7	17	* SPDX-License-Identifier: GPL-2.0+
138ff60c WD	18	*/
138ff60c WD	19
e979e85f	20	#include <asm/io.h>
138ff60c WD	21	#include <common.h>
	22	#include <mpc5xxx.h>
	23	#include <pci.h>
	24
5fb6d719	25	#if defined(CONFIG_DDR_MT46V16M16)
138ff60c	26	#include "mt46v16m16-75.h"
5fb6d719	27	#elif defined(CONFIG_SDR_MT48LC16M16A2)
138ff60c	28	#include "mt48lc16m16a2-75.h"
5fb6d719 MB	29	#elif defined(CONFIG_DDR_MT46V32M16)
	30	#include "mt46v32m16.h"
	31	#elif defined(CONFIG_DDR_HYB25D512160BF)
	32	#include "hyb25d512160bf.h"
	33	#elif defined(CONFIG_DDR_K4H511638C)
	34	#include "k4h511638c.h"
	35	#else
	36	#error "INKA4x0 SDRAM: invalid chip type specified!"
138ff60c WD	37	#endif
138ff60c WD	38
088454cd SG	39	DECLARE_GLOBAL_DATA_PTR;
088454cd SG	40
6d0f6bcf	41	#ifndef CONFIG_SYS_RAMBOOT
138ff60c WD	42	static void sdram_start (int hi_addr)
138ff60c WD	43	{
2344bb8d DZ	44	volatile struct mpc5xxx_sdram *sdram =
2344bb8d DZ	45	(struct mpc5xxx_sdram *)MPC5XXX_SDRAM;
138ff60c WD	46	long hi_addr_bit = hi_addr ? 0x01000000 : 0;
	47
	48	/* unlock mode register */
2344bb8d	49	out_be32(&sdram->ctrl, SDRAM_CONTROL \| 0x80000000 \| hi_addr_bit);
138ff60c WD	50
138ff60c WD	51	/* precharge all banks */
2344bb8d	52	out_be32(&sdram->ctrl, SDRAM_CONTROL \| 0x80000002 \| hi_addr_bit);
138ff60c WD	53
	54	#if SDRAM_DDR
	55	/* set mode register: extended mode */
2344bb8d	56	out_be32(&sdram->mode, SDRAM_EMODE);
138ff60c WD	57
138ff60c WD	58	/* set mode register: reset DLL */
2344bb8d	59	out_be32(&sdram->mode, SDRAM_MODE \| 0x04000000);
138ff60c WD	60	#endif
	61
	62	/* precharge all banks */
2344bb8d	63	out_be32(&sdram->ctrl, SDRAM_CONTROL \| 0x80000002 \| hi_addr_bit);
138ff60c WD	64
138ff60c WD	65	/* auto refresh */
2344bb8d	66	out_be32(&sdram->ctrl, SDRAM_CONTROL \| 0x80000004 \| hi_addr_bit);
138ff60c WD	67
138ff60c WD	68	/* set mode register */
2344bb8d	69	out_be32(&sdram->mode, SDRAM_MODE);
138ff60c WD	70
138ff60c WD	71	/* normal operation */
2344bb8d	72	out_be32(&sdram->ctrl, SDRAM_CONTROL \| hi_addr_bit);
138ff60c WD	73	}
	74	#endif
	75
	76	/*
	77	* ATTENTION: Although partially referenced initdram does NOT make real use
6d0f6bcf	78	* use of CONFIG_SYS_SDRAM_BASE. The code does not work if CONFIG_SYS_SDRAM_BASE
138ff60c WD	79	* is something else than 0x00000000.
	80	*/
	81
088454cd	82	int initdram(void)
138ff60c	83	{
2344bb8d DZ	84	volatile struct mpc5xxx_mmap_ctl *mm =
	85	(struct mpc5xxx_mmap_ctl *) CONFIG_SYS_MBAR;
	86	volatile struct mpc5xxx_cdm *cdm =
	87	(struct mpc5xxx_cdm *) MPC5XXX_CDM;
	88	volatile struct mpc5xxx_sdram *sdram =
	89	(struct mpc5xxx_sdram *) MPC5XXX_SDRAM;
138ff60c	90	ulong dramsize = 0;
6d0f6bcf	91	#ifndef CONFIG_SYS_RAMBOOT
f23cb34c	92	long test1, test2;
138ff60c WD	93
138ff60c WD	94	/* setup SDRAM chip selects */
2344bb8d DZ	95	out_be32(&mm->sdram0, 0x0000001c); /* 512MB at 0x0 */
2344bb8d DZ	96	out_be32(&mm->sdram1, 0x40000000); /* disabled */
138ff60c WD	97
138ff60c WD	98	/* setup config registers */
2344bb8d DZ	99	out_be32(&sdram->config1, SDRAM_CONFIG1);
2344bb8d DZ	100	out_be32(&sdram->config2, SDRAM_CONFIG2);
138ff60c WD	101
	102	#if SDRAM_DDR
	103	/* set tap delay */
2344bb8d	104	out_be32(&cdm->porcfg, SDRAM_TAPDELAY);
138ff60c WD	105	#endif
	106
	107	/* find RAM size using SDRAM CS0 only */
	108	sdram_start(0);
6d0f6bcf	109	test1 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x20000000);
138ff60c	110	sdram_start(1);
6d0f6bcf	111	test2 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x20000000);
138ff60c WD	112	if (test1 > test2) {
	113	sdram_start(0);
	114	dramsize = test1;
	115	} else {
	116	dramsize = test2;
	117	}
	118
	119	/* memory smaller than 1MB is impossible */
	120	if (dramsize < (1 << 20)) {
	121	dramsize = 0;
	122	}
	123
	124	/* set SDRAM CS0 size according to the amount of RAM found */
	125	if (dramsize > 0) {
2344bb8d DZ	126	out_be32(&mm->sdram0, 0x13 +
2344bb8d DZ	127	__builtin_ffs(dramsize >> 20) - 1);
138ff60c	128	} else {
2344bb8d	129	out_be32(&mm->sdram0, 0); /* disabled */
138ff60c WD	130	}
138ff60c WD	131
2344bb8d	132	out_be32(&mm->sdram1, dramsize); /* disabled */
6d0f6bcf	133	#else /* CONFIG_SYS_RAMBOOT */
138ff60c WD	134
138ff60c WD	135	/* retrieve size of memory connected to SDRAM CS0 */
2344bb8d	136	dramsize = in_be32(&mm->sdram0) & 0xFF;
138ff60c WD	137	if (dramsize >= 0x13) {
	138	dramsize = (1 << (dramsize - 0x13)) << 20;
	139	} else {
	140	dramsize = 0;
	141	}
6d0f6bcf	142	#endif /* CONFIG_SYS_RAMBOOT */
138ff60c	143
088454cd SG	144	gd->ram_size = dramsize;
	145
	146	return 0;
138ff60c WD	147	}
	148
	149	int checkboard (void)
	150	{
08f27278	151	puts ("Board: INKA 4X0\n");
138ff60c WD	152	return 0;
	153	}
	154
	155	void flash_preinit(void)
	156	{
2344bb8d DZ	157	volatile struct mpc5xxx_lpb lpb = (struct mpc5xxx_lpb )MPC5XXX_LPB;
2344bb8d DZ	158
138ff60c WD	159	/*
	160	* Now, when we are in RAM, enable flash write
	161	* access for detection process.
2344bb8d	162	* Note that CS_BOOT (CS0) cannot be cleared when
138ff60c WD	163	* executing in flash.
138ff60c WD	164	*/
2344bb8d	165	clrbits_be32(&lpb->cs0_cfg, 0x1); /* clear RO */
138ff60c	166	}
436be29c	167
151ab83a WD	168	int misc_init_f (void)
151ab83a WD	169	{
2344bb8d DZ	170	volatile struct mpc5xxx_gpio *gpio =
	171	(struct mpc5xxx_gpio *) MPC5XXX_GPIO;
	172	volatile struct mpc5xxx_wu_gpio *wu_gpio =
	173	(struct mpc5xxx_wu_gpio *)MPC5XXX_WU_GPIO;
	174	volatile struct mpc5xxx_gpt *gpt;
f23cb34c	175	char tmp[10];
a0bdf49e WD	176	int i, br;
a0bdf49e WD	177
cdb74977	178	i = getenv_f("brightness", tmp, sizeof(tmp));
a0bdf49e WD	179	br = (i > 0)
a0bdf49e WD	180	? (int) simple_strtoul (tmp, NULL, 10)
6d0f6bcf	181	: CONFIG_SYS_BRIGHTNESS;
a0bdf49e WD	182	if (br > 255)
	183	br = 255;
	184
f4733a07 WD	185	/* Initialize GPIO output pins.
f4733a07 WD	186	*/
342717f7	187	/* Configure GPT as GPIO output (and set them as they control low-active LEDs */
2344bb8d DZ	188	for (i = 0; i <= 5; i++) {
	189	gpt = (struct mpc5xxx_gpt )(MPC5XXX_GPT + (i 0x10));
	190	out_be32(&gpt->emsr, 0x34);
	191	}
f4733a07	192
a0bdf49e	193	/* Configure GPT7 as PWM timer, 1kHz, no ints. */
2344bb8d DZ	194	gpt = (struct mpc5xxx_gpt )(MPC5XXX_GPT + (7 0x10));
	195	out_be32(&gpt->emsr, 0); /* Disable */
	196	out_be32(&gpt->cir, 0x020000fe);
	197	out_be32(&gpt->pwmcr, (br << 16));
	198	out_be32(&gpt->emsr, 0x3); /* Enable PWM mode and start */
f4733a07 WD	199
f4733a07 WD	200	/* Configure PSC3_6,7 as GPIO output */
2344bb8d DZ	201	setbits_be32(&gpio->simple_gpioe, MPC5XXX_GPIO_SIMPLE_PSC3_6 \|
	202	MPC5XXX_GPIO_SIMPLE_PSC3_7);
	203	setbits_be32(&gpio->simple_ddr, MPC5XXX_GPIO_SIMPLE_PSC3_6 \|
	204	MPC5XXX_GPIO_SIMPLE_PSC3_7);
f4733a07 WD	205
f4733a07 WD	206	/* Configure PSC3_9 and GPIO_WKUP6,7 as GPIO output */
2344bb8d DZ	207	setbits_8(&wu_gpio->enable, MPC5XXX_GPIO_WKUP_6 \|
	208	MPC5XXX_GPIO_WKUP_7 \|
	209	MPC5XXX_GPIO_WKUP_PSC3_9);
	210	setbits_8(&wu_gpio->ddr, MPC5XXX_GPIO_WKUP_6 \|
	211	MPC5XXX_GPIO_WKUP_7 \|
	212	MPC5XXX_GPIO_WKUP_PSC3_9);
f4733a07	213
342717f7	214	/* Set LR mirror bit because it is low-active */
2344bb8d DZ	215	setbits_8(&wu_gpio->dvo, MPC5XXX_GPIO_WKUP_7);
	216
	217	/* Reset Coral-P graphics controller */
	218	setbits_8(&wu_gpio->dvo, MPC5XXX_GPIO_WKUP_PSC3_9);
	219
	220	/* Enable display backlight */
	221	clrbits_8(&gpio->sint_inten, MPC5XXX_GPIO_SINT_PSC3_8);
	222	setbits_8(&gpio->sint_gpioe, MPC5XXX_GPIO_SINT_PSC3_8);
	223	setbits_8(&gpio->sint_ddr, MPC5XXX_GPIO_SINT_PSC3_8);
	224	setbits_8(&gpio->sint_dvo, MPC5XXX_GPIO_SINT_PSC3_8);
e979e85f DZ	225
	226	/*
	227	* Configure three wire serial interface to RTC (PSC1_4,
	228	* PSC2_4, PSC3_4, PSC3_5)
	229	*/
	230	setbits_8(&wu_gpio->enable, MPC5XXX_GPIO_WKUP_PSC1_4 \|
	231	MPC5XXX_GPIO_WKUP_PSC2_4);
	232	setbits_8(&wu_gpio->ddr, MPC5XXX_GPIO_WKUP_PSC1_4 \|
	233	MPC5XXX_GPIO_WKUP_PSC2_4);
	234	clrbits_8(&wu_gpio->dvo, MPC5XXX_GPIO_WKUP_PSC1_4);
	235	clrbits_8(&gpio->sint_inten, MPC5XXX_GPIO_SINT_PSC3_4 \|
	236	MPC5XXX_GPIO_SINT_PSC3_5);
	237	setbits_8(&gpio->sint_gpioe, MPC5XXX_GPIO_SINT_PSC3_4 \|
	238	MPC5XXX_GPIO_SINT_PSC3_5);
	239	setbits_8(&gpio->sint_ddr, MPC5XXX_GPIO_SINT_PSC3_5);
	240	clrbits_8(&gpio->sint_dvo, MPC5XXX_GPIO_SINT_PSC3_5);
	241
f4733a07	242	return 0;
151ab83a WD	243	}
151ab83a WD	244
f4733a07	245	#ifdef CONFIG_PCI
436be29c WD	246	static struct pci_controller hose;
	247
	248	extern void pci_mpc5xxx_init(struct pci_controller *);
	249
	250	void pci_init_board(void)
	251	{
f4733a07	252	pci_mpc5xxx_init(&hose);
436be29c WD	253	}
436be29c WD	254	#endif